TPA3122D2_14 [TI]
15-W STEREO CLASS-D AUDIO POWER AMPLIFIER;
| 型号： | TPA3122D2_14 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 15-W STEREO CLASS-D AUDIO POWER AMPLIFIER 放大器 功率放大器 |
| 文件： | 总20页 (文件大小：417K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPA3122D2
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SLOS527A–DECEMBER 2007–REVISED DECEMBER 2007
15-W STEREO CLASS-D AUDIO POWER AMPLIFIER
1
FEATURES
APPLICATIONS
•
Televisions
•
10-W/ch into an 4-Ω Load From a 17-V Supply
15-W/ch into an 8-Ω Load From a 28-V Supply
Operates from 10 V to 30 V
•
•
•
•
•
DESCRIPTION
The TPA3122D2 is a 15-W (per channel) efficient,
Class-D audio power amplifier for driving stereo
single ended speakers or mono bridge tied load. The
TPA3122D2 can drive stereo speakers as low as 4Ω.
The efficiency of the TPA3122D2 eliminates the need
for an external heat sink when playing music.
Efficient Class-D Operation
Four Selectable, Fixed Gain Settings
Internal Oscillator (No External Components
Required)
•
•
Single Ended Analog Inputs
The gain of the amplifier is controlled by two gain
select pins. The gain selections are 20, 26, 32, and
36 dB.
Thermal and Short-Circuit Protection with
Auto Recovery Feature
•
20-pin DIP Package
SIMPLIFIED APPLICATION CIRCUIT
TPA3122D2
1 mF
0.22 mF
Left Channel
LIN
RIN
BSR
22 mH 470 mF
Right Channel
ROUT
0.68 mF
1 mF
PGNDR
PGNDL
LOUT
BSL
0.68 mF
1 mF
BYPASS
AGND
22 mH
470 mF
0.22 mF
PVCCL
PVCCR
10 V to 30 V
10 V to 30 V
AVCC
VCLAMP
Shutdown
Control
SD
1 mF
MUTE
Mute Control
GAIN0
GAIN1
4-Step Gain
Control
}
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2007, Texas Instruments Incorporated
TPA3122D2
www.ti.com
SLOS527A–DECEMBER 2007–REVISED DECEMBER 2007
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
N (DIP) PACKAGE
(TOP VIEW)
1
20
19
18
PVCCL
PGNDL
LOUT
BSL
2
SD
MUTE
LIN
3
4
17 AVCC
5
16
15
14
13
12
11
RIN
AVCC
6
BYPASS
AGND
GAIN0
GAIN1
BSR
7
8
AGND
9
VCLAMP
ROUT
10
PVCCR
PGNDR
TERMINAL FUNCTIONS
TERMINAL
I/O
DESCRIPTION
20-PIN
(DIP)
NAME
Shutdown signal for IC (low = disabled, high = operational). TTL logic levels with compliance to
AVCC.
SD
2
I
RIN
LIN
5
4
I
I
I
I
Audio input for right channel.
Audio input for left channel.
GAIN0
GAIN1
15
14
Gain select least significant bit. TTL logic levels with compliance to AVCC.
Gain select most significant bit. TTL logic levels with compliance to AVCC.
Mute signal for quick disable/enable of outputs (high = outputs switch at 50% duty cycle; low =
outputs enabled). TTL logic levels with compliance to AVCC.
MUTE
3
I
BSL
18
1
I/O
Bootstrap I/O for left channel.
PVCCL
LOUT
Power supply for left channel H-bridge, not internally connected to PVCCR or AVCC.
Class-D ꢀ -H-bridge positive output for left channel.
Power ground for left channel H-bridge.
19
20
9
O
PGNDL
VCLAMP
BSR
Internally generated voltage supply for bootstrap capacitors.
Bootstrap I/O for right channel.
13
12
11
10
8
I/O
O
ROUT
PGNDR
PVCCR
AGND
AGND
Class-D ꢀ -H-bridge negative output for right channel.
Power ground for right channel H-bridge.
Power supply for right channel H-bridge, not connected to PVCCL or AVCC.
Analog ground for digital/analog cells in core.
7
Analog Ground for analog cells in core.
Reference for pre-amplifier inputs. Nominally equal to AVCC/8. Also controls start-up time via
external capacitor sizing.
BYPASS
AVCC
6
O
16, 17
High-voltage analog power supply. Not internally connected to PVCCR or PVCCL
2
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SLOS527A–DECEMBER 2007–REVISED DECEMBER 2007
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)(1)
VALUE
UNIT
VCC
VI
Supply voltage, AVCC, PVCC
–0.3 to 36
V
V
V
Logic input voltage
Analog input voltage
SD, MUTE, GAIN0, GAIN1
RIN, LIN
–0.3 to VCC +0.3 –0.3 to VCC +0.3
VIN
–0.3 to 7
Continuous total power dissipation
Operating free-air temperature range
Operating junction temperature range
Storage temperature range
See Dissipation Rating Table
TA
TJ
–40 to 85
–40 to 150
-65 to 150
3.2
°C
°C
°C
kV
kV
V
Tstg
RL
Load resistance (Minimum value)
Human body model (all pins)
Charged-device model (all pins)
±2
ESD
Electrostatic Discharge
±500
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operations of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
DISSIPATION RATINGS
PACKAGE(1)
TA ≤ 25°C
DERATING FACTOR
TA = 70°C
TA = 85°C
20-pin DIP
1.87 W
15 mW/°C
1.20 W
0.97 W
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
Web site at www.ti.com.
RECOMMENDED OPERATING CONDITIONS
MIN
10
2
MAX
UNIT
VCC
VIH
VIL
Supply voltage
PVCC, AVCC
30
V
V
V
High-level input voltage
Low-level input voltage
SD, MUTE, GAIN0, GAIN1
SD, MUTE, GAIN0, GAIN1
SD, VI = VCC, VCC = 30 V
MUTE, VI = VCC, VCC = 30 V
GAIN0, GAIN1, VI = VCC, VCC = 24 V
SD, VI = 0, VCC = 30 V
0.8
125
125
125
1
IIH
High-level input current
µA
IIL
Low-level input current
MUTE, VI = 0 V, VCC = 30 V
GAIN0, GAIN1, VI = 0 V, VCC = 24 V
1
µA
°C
1
TA
Operating free-air temperature
–40
85
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SLOS527A–DECEMBER 2007–REVISED DECEMBER 2007
DC CHARACTERISTICS
TA = 25°C, VCC = 24 V, RL = 4Ω (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VI = 0 V, AV = 36 dB
MIN
TYP
7.5
MAX UNIT
Class-D output offset voltage
(measured differentially)
| VOS
|
50
mV
V(BYPASS) Bypass output voltage
No load
AVCC/8
23
V
ICC(q)
ICC(q)
ICC(q)
Quiescent supply current
SD = 2 V, MUTE = 0 V, No load
MUTE = 2 V, No load
37
1
mA
mA
Quiescent supply current in mute mode
23
Quiescent supply current in shutdown
mode
SD = 0.8 V , No load
0.39
mA
rDS(on)
Drain-source on-state resistance
200
20
mΩ
Gain0 = 0.8 V
18
24
30
34
22
28
34
38
Gain1 = 0.8 V
Gain0 = 2 V
Gain0 = 0.8 V
Gain0 = 2 V
26
G
Gain
dB
32
Gain1 = 2 V
VI = 1Vrms
36
Mute Attenuation
–82
AC CHARACTERISTICS
TA = 25°C, VCC = 24V, RL = 4Ω (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC = 12 V, Vripple = 200 mVPP
Gain = 20 dB
MIN
TYP
–30
-48
4
MAX UNIT
100 Hz
1 kHz
dB
dB
KSVR
Supply ripple rejection
VCC = 12 V, RL = 4 Ω, f = 1 kHz
VCC = 24 V, RL = 8 Ω, f = 1 kHz
VCC = 12 V, RL = 4 Ω, f = 1 kHz
VCC = 24 V, RL = 8 Ω, f = 1 kHz
RL = 4 Ω, f = 1 kHz, PO = 1 W
RL = 8 Ω, f = 1 kHz, PO = 1 W
Output Power at 1% THD+N
8
PO
W
5
Output Power at 10%
THD+N
10
0.1%
0.06%
85
Total harmonic distortion +
noise
THD+N
Vn
µV
dB
dB
dB
°C
°C
Output integrated noise floor 20 Hz to 22 kHz, A-weighted filter, Gain = 20 dB
–80
–60
99
Crosstalk
PO = 1 W, f = 1kHz; Gain = 20 dB
SNR
Signal-to-noise ratio
Thermal trip point
Thermal hysteresis
Oscillator frequency
mute delay
Max Output at THD+N < 1%, f = 1 kHz, Gain = 20 dB
150
30
fOSC
10 V ≤ VCC
230
250
120
120
270
kHz
time from mute input switches high until outputs muted
time from mute input switches low until outputs unmuted
msec
msec
Δt
unmute delay
4
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SLOS527A–DECEMBER 2007–REVISED DECEMBER 2007
FUNCTIONAL BLOCK DIAGRAM
BSL
AVCC
PVCCL
AVDD
REGULATOR
HS
+
-
LOUT
VCLAMP
LS
AVDD
AVDD
PGNDL
LIN
SC
DETECT
AVDD/2
AGND
CONTROL
SD
BIAS
VCLAMP
THERMAL
MUTE
MUTE
CONTROL
OSC/RAMP
BYPASS
BYPASS
AV
GAIN1
GAIN0
CONTROL
SC
DETECT
BSR
PVCCR
HS
ROUT
-
VCLAMP
LS
+
PGNDR
AVDD
AVDD
RIN
AVDD/2
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SLOS527A–DECEMBER 2007–REVISED DECEMBER 2007
TYPICAL CHARACTERISTICS
TOTAL HARMONIC DISTORTION + NOISE
TOTAL HARMONIC DISTORTION + NOISE
vs
vs
FREQUENCY (SE)
FREQUENCY (SE)
10
1
10
1
Gain = 20 dB
Gain = 20 dB
R
L
= 4 Ω (SE)
R
L
= 4 Ω (SE)
V
CC
= 12 V
V
CC
= 18 V
P
O
= 5 W
P
O
= 2 W
0.1
0.01
0.1
0.01
P
O
= 1 W
P
O
= 1 W
P
O
= 0.5 W
P
O
= 2.5 W
20
100
1k
10k 20k
20
100
1k
10k 20k
f − Frequency − Hz
f − Frequency − Hz
G002
G001
Figure 1.
Figure 2.
TOTAL HARMONIC DISTORTION + NOISE
TOTAL HARMONIC DISTORTION + NOISE
vs
vs
FREQUENCY (SE)
FREQUENCY (SE)
10
1
10
1
Gain = 20 dB
Gain = 20 dB
R
L
= 4 Ω (SE)
R
L
= 8 Ω (SE)
V
CC
= 24 V
V
CC
= 24 V
P
O
= 5 W
P
O
= 5 W
P
O
= 2.5 W
0.1
0.01
0.1
0.01
P
O
= 1 W
P
O
= 2.5 W
P
O
= 1 W
20
100
1k
10k 20k
20
100
1k
10k 20k
f − Frequency − Hz
f − Frequency − Hz
G003
G004
Figure 3.
Figure 4.
TOTAL HARMONIC DISTORTION + NOISE
TOTAL HARMONIC DISTORTION + NOISE
vs
vs
OUTPUT POWER (SE)
OUTPUT POWER (SE)
10
1
10
1
Gain = 20 dB
= 4 Ω (SE)
Gain = 20 dB
R = 8 Ω (SE)
L
R
L
V
CC
= 12 V
V
CC
= 12 V
V
CC
= 18 V
0.1
0.01
0.1
0.01
V
CC
= 24 V
10
V
CC
= 24 V
V
CC
= 18 V
0.01
0.1
1
40
0.01
0.1
1
10
40
P
O
− Output Power − W
P
O
− Output Power − W
G005
G006
Figure 5.
Figure 6.
6
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SLOS527A–DECEMBER 2007–REVISED DECEMBER 2007
TYPICAL CHARACTERISTICS (continued)
CROSSTALK
vs
FREQUENCY (SE)
CROSSTALK
vs
FREQUENCY (SE)
0
0
−20
Gain = 20 dB
Gain = 20 dB
P
O
= 0.25 W
P
= 0.125 W
= 8 Ω (SE)
O
−20
−40
R
L
= 4 Ω (SE)
R
L
V
CC
= 18 V
V
CC
= 18 V
−40
Left to Right
Left to Right
−60
−60
−80
−80
Right to Left
Right to Left
100
−100
−100
20
100
1k
f − Frequency − Hz
Figure 7.
10k 20k
20
1k
f − Frequency − Hz
Figure 8.
10k 20k
G007
G008
GAIN/PHASE
vs
FREQUENCY (SE)
GAIN/PHASE
vs
FREQUENCY (SE)
400
200
0
200
100
0
30
Gain
20
25
20
15
10
5
Gain
0
−20
−40
Phase
Phase
−100
−200
−300
Gain = 20 dB
L
= 22 mH
L
= 47 mH
Gain = 20 dB
filt
filt
P
= 0.125 W
= 4 Ω (SE)
= 0.68 mF
= 470 mF
P
= 0.125 W
= 8 Ω (SE)
= 0.22 mF
= 470 mF
C
C
O
O
filt
filt
R
C
R
C
dc
L
dc
L
V
CC
= 24 V
V
CC
= 18 V
0
−200
100
1k
10k
100k
20
100
1k
10k
200k
f − Frequency − Hz
f − Frequency − Hz
G009
G010
Figure 9.
Figure 10.
OUTPUT POWER
vs
SUPPLY VOLTAGE (SE)
OUTPUT POWER
vs
SUPPLY VOLTAGE (SE)
15
10
5
18
Gain = 20 dB
= 8 Ω (SE)
Gain = 20 dB
= 4 W (SE)
16
14
12
10
8
R
L
R
L
THD+N = 10%
THD+N = 10%
6
THD+N = 1%
THD+N = 1%
4
2
0
0
10
12
14
16
18
20
10
12
14
16
18
20
22
24
26
28
30
PV − Supply Voltage − V
CC
PV − Supply Voltage − V
CC
G011
G012
Figure 12.
NOTE: Dashed line = Thermally limited
Figure 11.
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SLOS527A–DECEMBER 2007–REVISED DECEMBER 2007
TYPICAL CHARACTERISTICS (continued)
EFFICIENCY
vs
OUTPUT POWER (SE)
EFFICIENCY
vs
OUTPUT POWER (SE)
100
80
60
40
20
0
100
80
60
40
20
0
V
CC
= 24 V
V
= 12 V
CC
V
CC
= 18 V
Gain = 20 dB
Gain = 20 dB
R
V
= 4 Ω (SE)
= 12 V
L
R
L
= 8 Ω (SE)
CC
0
1
2
3
4
5
6
7
0
2
4
6
8
10
12
14
P
O
− Output Power − W
P
O
− Output Power − W
G013
G014
Figure 13.
Figure 14.
SUPPLY CURRENT
vs
TOTAL OUTPUT POWER (SE)
SUPPLY CURRENT
vs
TOTAL OUTPUT POWER (SE)
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
Gain = 20 dB
Gain = 20 dB
R
L
= 4 Ω (SE)
R
L
= 8 Ω (SE)
V
CC
= 12 V
V
= 24 V
CC
V
CC
= 18 V
V
= 12 V
6
CC
0
2
4
6
8
10
12
14
0
2
4
8
10
12
14
P
O
− Total Output Power − W
P
O
− Total Output Power − W
G015
G016
Figure 15.
Figure 16.
POWER SUPPLY REJECTION RATIO
TOTAL HARMONIC DISTORTION + NOISE
vs
vs
FREQUENCY (SE)
FREQUENCY (BTL)
0
−20
10
1
Gain = 20 dB
R
L
= 8 Ω (BTL)
V
CC
= 24 V
P
O
= 20 W
−40
P
O
= 1 W
0.1
−60
−80
Gain = 20 dB
P
O
= 5 W
0.01
0.001
R
= 4 Ω (SE)
= 12 V
L
−100
V
CC
V
ripple
= 200 mV
p-p
−120
20
100
1k
10k 20k
20
100
1k
10k 20k
f − Frequency − Hz
f − Frequency − Hz
G017
G018
Figure 17.
Figure 18.
8
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SLOS527A–DECEMBER 2007–REVISED DECEMBER 2007
TYPICAL CHARACTERISTICS (continued)
TOTAL HARMONIC DISTORTION + NOISE
GAIN/PHASE
vs
FREQUENCY (BTL)
vs
OUTPUT POWER (BTL)
10
1
30
20
Phase
Gain = 20 dB
−200
−300
−400
−500
−600
R
L
= 8 Ω (BTL)
Gain
V
= 12 V
CC
10
0.1
0
−10
−20
−30
Gain = 20 dB
= 0.125 W
L
= 33 mH
= 1 mF
filt
0.01
0.001
P
C
V
CC
= 18 V
O
filt
V
= 24 V
CC
R
= 8 Ω (BTL)
L
V
CC
= 24 V
−700
20
100
1k
10k
200k
0.01
0.1
1
10
50
f − Frequency − Hz
P
O
− Output Power − W
G020
G019
Figure 19.
Figure 20.
OUTPUT POWER
vs
SUPPLY VOLTAGE (BTL)
EFFICIENCY
vs
OUTPUT POWER (BTL)
70
60
50
40
30
20
10
0
100
80
60
40
20
0
Gain = 20 dB
= 8 Ω (BTL)
R
L
V
CC
= 24 V
V
= 12 V
THD+N = 10%
CC
V
CC
= 18 V
THD+N = 1%
Gain = 20 dB
R
L
= 8 Ω (BTL)
10
12
14
16
18
20
22
24
26
28
30
0
4
8
12
16
20
24
28
PV − Supply Voltage − V
CC
P
O
− Output Power − W
G021
G022
Figure 21.
Figure 22.
SUPPLY CURRENT
vs
TOTAL OUTPUT POWER (BTL)
POWER SUPPLY REJECTION RATIO
vs
FREQUENCY (BTL)
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
0
−20
Gain = 20 dB
= 8 Ω (BTL)
Gain = 20 dB
R
L
R
L
= 8 Ω (BTL)
V
CC
= 18 V
V
V
= 24 V
CC
= 200 mV
ripple
p-p
−40
V
CC
= 12 V
−60
−80
V
CC
= 24 V
−100
−120
0
4
8
12
16
20
24
28
20
100
1k
10k 20k
f − Frequency − Hz
P
O
− Total Output Power − W
G024
G023
Figure 23.
Figure 24.
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APPLICATION INFORMATION
CLASS-D OPERATION
This section focuses on the class-D operation of the TPA3122D2.
Traditional Class-D Modulation Scheme
The TPA3122D2 operates in AD mode. There are two main configurations that may be used. For stereo
operation, the TPA3122D2 should be configured in a single-ended (SE) half bridge amplifier. For mono
applications, TPA3122D2 may be used as a bridge tied load (BTL) amplifier. The traditional class-D modulation
scheme, which is used in the TPA3122D2 BTL configuration, has a differential output where each output is 180
degrees out of phase and changes from ground to the supply voltage, VCC. Therefore, the differential pre-filtered
output varies between positive and negative VCC
,
where filtered 50% duty cycle yields
0 V across the load. The traditional class-D modulation scheme with voltage and current waveforms is shown in
Figure 25.
+12 V
OUTP
0 V
-12 V
OUTN
0 V
+12 V
Differential Voltage
0 V
Across Load
-12 V
Current
Figure 25. Traditional Class-D Modulation Scheme's Output Voltage and Current Waveforms into an
Inductive Load With No Input
Supply Pumping
One issue encountered in single-ended (SE) class-D amplifier designs is supply pumping. Power-supply pumping
is a rise in the local supply voltage due to energy being driven back to the supply by operation of the class-D
amplifier. This phenomenon is most evident at low audio frequencies and when both channels are operating at
the same frequency and phase. At low levels, power-supply pumping results in distortion in the audio output due
to fluctuations in supply voltage. At higher levels, pumping can cause the overvoltage protection to operate,
which temporarily shuts down the audio output.
Several things can be done to relieve power-supply pumping. The lowest impact is to operate the two inputs out
of phase 180° and reverse the speaker connections. Because most audio is highly correlated, this causes the
supply pumping to be out of phase and not as severe. If this is not enough, the amount of bulk capacitance on
the supply must be increased. Also, improvement is realized by hooking other supplies to this node, thereby,
sinking some of the excess current. Power-supply pumping should be tested by operating the amplifier at low
frequencies and high output levels.
Gain setting via GAIN0 and GAIN1 inputs
The gain of the TPA3122D2 is set by two input terminals, GAIN0 and GAIN1.
The gains listed in Table 1 are realized by changing the taps on the input resistors and feedback resistors inside
the amplifier. This causes the input impedance (ZI) to be dependent on the gain setting. The actual gain settings
are controlled by ratios of resistors, so the gain variation from part-to-part is small. However, the input impedance
from part-to-part at the same gain may shift by ±20% due to shifts in the actual resistance of the input resistors.
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For design purposes, the input network (discussed in the next section) should be designed assuming an input
impedance of 8 kΩ, which is the absolute minimum input impedance of the TPA3122D2. At the higher gain
settings, the input impedance could increase as high as 72 kΩ
Table 1. Gain Setting
AMPLIFIER GAIN (dB)
INPUT IMPEDANCE (kΩ)
GAIN1
GAIN0
TYPICAL
TYPICAL
0
0
1
1
0
1
0
1
20
26
32
36
60
30
15
9
INPUT RESISTANCE
Changing the gain setting can vary the input resistance of the amplifier from its smallest value, 10 kΩ ±20%, to
the largest value, 60 kΩ ±20%. As a result, if a single capacitor is used in the input high-pass filter, the -3 dB or
cutoff frequency may change when changing gain steps.
Z
f
C
i
Z
i
IN
Input
Signal
The -3-dB frequency can be calculated using Equation 1. Use the ZI values given in Table 1.
1
f =
2p Zi Ci
(1)
INPUT CAPACITOR, CI
In the typical application, an input capacitorꢀ I) is required to allow the amplifier to bias the input signal to the
proper dc level for optimum operation. In this case, CI and the input impedance of the amplifier (ZI) form a
high-pass filter with the corner frequency determined in Equation 2.
–3 dB
1
2p Zi Ci
fc
=
f
c
(2)
The value of CI is important, as it directly affects the bass (low-frequency) performance of the circuit. Consider
the example where ZI is 20 kΩ and the specification calls for a flat bass response down to 20 Hz. Equation 2 is
reconfigured as Equation 3.
1
Ci =
2p Zi fc
(3)
In this example, CI is 0.4 µF; so, one would likely choose a value of 0.47 µF as this value is commonly used. If
the gain is known and is constant, use ZI from Table 1 to calculate CI. A further consideration for this capacitor is
the leakage path from the input source through the input networkꢀ I) and the feedback network to the load. This
leakage current creates a dc offset voltage at the input to the amplifier that reduces useful headroom, especially
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in high gain applications. For this reason, a low-leakage tantalum or ceramic capacitor is the best choice. When
polarized capacitors are used, the positive side of the capacitor should face the amplifier input in most
applications as the dc level there is held at 2 V, which is likely higher than the source dc level. Note that it is
important to confirm the capacitor polarity in the application. Additionally, lead-free solder can create dc offset
voltages and it is important to ensure that boards are cleaned properly.
Single Ended Output Capacitor, Co
In single ended (SE) applications, the DC blocking capacitor forms a high pass filter with speaker impedance.
The frequency response rolls of with decreasing frequency at a rate of 20dB/decade. The cutoff frequency is
determined by
fc = 1/2×πCoZL
Table 2 shows some common component values and the associated cutoff frequencies:
Table 2. Common Filter Responses
CSE – DC Blocking Capacitor (µF)
Speaker Impedance (Ω)
fc = 60 Hz
680
fc = 40 Hz
1000
fc = 20 Hz
2200
4
8
330
470
1000
Output Filter and Frequency Response
For the best frequency response, a flat passband output filter (second order Butterworth) may be used. The
output filter components consist of the series inductor and capacitor to ground at the LOUT and ROUT pins.
There are several possible configurations depending on the speaker impedance and whether the output
configuration is Single Ended (SE) or Bridge Tied Load (BTL). Table 3 list several possible arrangements.
Table 3. Recommended Filter Output Components
Output Configuration
Speaker Impedance (Ω)
Filter Inductor (µH)
Filter Capacitor (nF)
4
8
4
8
22
47
10
22
680
390
Single Ended (SE)
1500
680
Bridge Tied Load
L
L
filter
LOUT / ROUT
filter
LOUT
C
C
filter
filter
L
ROUT
filter
C
filter
Figure 26. BTL Filter Configuration
Figure 27. SE Filter Configuration
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Power Supply Decoupling, CS
The TPA3122D2 is a high-performance CMOS audio amplifier that requires adequate power supply decoupling
to ensure that the output total harmonic distortion (THD) is as low as possible. Power supply decoupling also
prevents oscillations for long lead lengths between the amplifier and the speaker. The optimum decoupling is
achieved by using two capacitors of different types that target different types of noise on the power supply leads.
For higher frequency transients, spikes, or digital hash on the line, a good low equivalent-series-resistance (ESR)
ceramic capacitor, typically 0.1 µF to 1 µF placed as close as possible to the device VCC lead works best. For
filtering lower frequency noise signals, a larger aluminum electrolytic capacitor of 220 µF or greater placed near
the audio power amplifier is recommended. The 220-µF capacitor also serves as local storage capacitor for
supplying current during large signal transients on the amplifier outputs. The PVCC terminals provide the power
to the output transistors, so a 220-µF or larger capacitor should be placed on each PVCC terminal. A 10-µF
capacitor on the AVCC terminal is adequate.
BSN and BSP Capacitors
The half H-bridge output stages use only NMOS transistors. Therefore, they require bootstrap capacitors for the
high side of each output to turn on correctly. A 220-nF ceramic capacitor, rated for at least 25 V, must be
connected from each output to its corresponding bootstrap input. Specifically, one 220-nF capacitor must be
connected from LOUT to BSL, and one 220-nF capacitor must be connected from ROUT to BSR.
The bootstrap capacitors connected between the BSx pins and corresponding output function as a floating power
supply for the high-side N-channel power MOSFET gate drive circuitry. During each high-side switching cycle,
the bootstrap capacitors hold the gate-to-source voltage high enough to keep the high-side MOSFETs turned on.
VCLAMP Capacitor
To ensure that the maximum gate-to-source voltage for the NMOS output transistors is not exceeded, one
internal regulator clamps the gate voltage. One 1-µF capacitor must be connected from VCLAMP (pin 11 for
PWP and pin 9 for DIP package) to ground and must be rated for at least 16 V. The voltages at the VCLAMP
terminal may vary with VCC and may not be used for powering any other circuitry.
VBYP Capacitor Selection
The scaled supply reference (VBYP) nominally provides an AVcc/8 internal bias for the preamplifier stages. The
external capacitor for this reference CBYP) is a critical component and serves several important functions. During
start-up or recovery from shutdown mode, CBSP determines the rate at which the amplifier starts up. The second
function is to reduce noise produced by the power supply caused by coupling with the output drive signal. This
noise could result in degraded PSRR and THD + N.
The circuit is designed for a CBSP value of 1 µF for best pop performance. The inputs caps should be the same
value. A ceramic or tantalum low-ESR capacitor is recommended.
SHUTDOWN OPERATION
The TPA3122D2 employs a shutdown mode of operation designed to reduce supply current (ICC) to the absolute
minimum level during periods of non-use for power conservation. The SHUTDOWN input terminal should be held
high (see specification table for trip point) during normal operation when the amplifier is in use. Pulling
SHUTDOWN low causes the outputs to mute and the amplifier to enter a low-current state. Never leave
SHUTDOWN unconnected, because amplifier operation would be unpredictable.
For the best power-up pop performance, place the amplifier in the shutdown or mute mode prior to applying the
power supply voltage.
MUTE Operation
The MUTE pin is an input for controlling the output state of the TPA3122D2. A logic high on this terminal causes
the outputs to run at a constant 50% duty cycle. A logic low on this pin enables the outputs. This terminal may be
used as a quick disable/enable of outputs when changing channels on a television or switching between different
audio sources.
The MUTE terminal should never be left floating. For power conservation, the SHUTDOWN terminal should be
used to reduce the quiescent current to the absolute minimum level.
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USING LOW-ESR CAPACITORS
Low-ESR capacitors are recommended throughout this application section. A real (as opposed to ideal) capacitor
can be modeled simply as a resistor in series with an ideal capacitor. The voltage drop across this resistor
minimizes the beneficial effects of the capacitor in the circuit. The lower the equivalent value of this resistance,
the more the real capacitor behaves like an ideal capacitor.
SHORT-CIRCUIT PROTECTION
The TPA3122D2 has short-circuit protection circuitry on the outputs that prevents damage to the device during
output-to-output shorts and output-to-GND shorts. When a short circuit is detected on the outputs, the part
immediately disables the output drive. This is an unlatched fault. Normal operation is restored when the fault is
removed.
THERMAL PROTECTION
Thermal protection on the TPA3122D2 prevents damage to the device when the internal die temperature
exceeds 150°C. There is a ±15°C tolerance on this trip point from device to device. Once the die temperature
exceeds the thermal set point, the device enters into the shutdown state and the outputs are disabled. This is not
a latched fault. The thermal fault is cleared once the temperature of the die is reduced by 30°C. The device
begins normal operation at this point with no external system interaction.
PRINTED-CIRCUIT BOARD (PCB) LAYOUT
Because the TPA3122D2 is a class-D amplifier that switches at a high frequency, the layout of the printed-circuit
board (PCB) should be optimized according to the following guidelines for the best possible performance.
•
•
•
Decoupling capacitors—The high-frequency 0.1µF decoupling capacitors should be placed as close to the
PVCC (pins 1 and 10) and AVCC (pins 16 and 17) terminals as possible. The VBYP (pin 6) capacitor and
VCLAMP (pin 9) capacitor should also be placed as close to the device as possible. Large (220 µF or
greater) bulk power supply decoupling capacitors should be placed near the TPA3122D2 on the PVCCL and
PVCCR terminals.
Grounding—The AVCC (pins 16 and 17) decoupling capacitor and VBYP (pin 6) capacitor should each be
grounded to analog ground (AGND, pins 7 and 8). The PVCCx decoupling capacitors and VCLAMP
capacitors should each be grounded to power ground (PGND, pins 11 and 20). Analog ground and power
ground should be connected at the thermal pad, which should be used as a central ground connection or star
ground for the TPA3122D2.
Output filter—The EMI filter (L1, L2, C9, and C16) should be placed as close to the output terminals as
possible for the best EMI performance. The capacitors should be grounded to power ground.
For an example layout, see the TPA3122D2 Evaluation Module (TPA3122D2EVM) User Manual, (SLOU214).
Both the EVM user manual and the thermal pad application note are available on the TI Web site at
http://www.ti.com.
VCC
22uH
Shutdown Control
Mute Control
0.1uF
470uF
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
PVCCL
SD
MUTE
LIN
RIN
BYPASS
AGND1
AGND2
VCLAMP
PVCCR
PGNDL
LOUT
BSL
AVCC1
AVCC2
GAIN0
GAIN1
BSR
1.0uF
LEFT_OUT
4.7K
0.68uF
Left Input
0.22uF
0.22uF
Right Input
1.0uF
1.0uF
RIGHT_OUT
ROUT
PGNDR
TPA3122_PDIP
0.1uF
4.7K
22uH
0.68uF
470uF
1.0uF
470uF
470uF
0.1uF
10uF
Figure 28. SE 4-Ω Application Schematic
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VCC
22uH
Shutdown Control
Mute Control
0.1uF
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
PVCCL
SD
MUTE
LIN
RIN
BYPASS
AGND1
AGND2
VCLAMP
PVCCR
PGNDL
LOUT
BSL
AVCC1
AVCC2
GAIN0
GAIN1
BSR
1.0uF
LEFT_OUT
4.7K
0.68uF
Plus Input
0.22uF
0.22uF
Minus Input
1.0uF
1.0uF
RIGHT_OUT
ROUT
PGNDR
TPA3122_PDIP
0.1uF
4.7K
22uH
0.68uF
1.0uF
470uF
470uF
0.1uF
10uF
Figure 29. BTL 8-Ω Application Schematic
BASIC MEASUREMENT SYSTEM
This application note focuses on methods that use the basic equipment listed below:
•
•
•
•
•
•
•
•
•
Audio analyzer or spectrum analyzer
Digital multimeter (DMM)
Oscilloscope
Twisted-pair wires
Signal generator
Power resistor(s)
Linear regulated power supply
Filter components
EVM or other complete audio circuit
Figure 30 shows the block diagrams of basic measurement systems for class-AB and class-D amplifiers. A sine
wave is normally used as the input signal because it consists of the fundamental frequency only (no other
harmonics are present). An analyzer is then connected to the APA output to measure the voltage output. The
analyzer must be capable of measuring the entire audio bandwidth. A regulated dc power supply is used to
reduce the noise and distortion injected into the APA through the power pins. A System Two audio measurement
system (AP-II) (Reference 1) by Audio Precision includes the signal generator and analyzer in one package.
The generator output and amplifier input must be ac-coupled. However, the EVMs already have the ac-coupling
capacitors, CIN), so no additional coupling is required. The generator output impedance should be low to avoid
attenuating the test signal, and is important because the input resistance of APAs is not high. Conversely, the
analyzer-input impedance should be high. The output resistance, ROUT, of the APA is normally in the hundreds of
milliohms and can be ignored for all but the power-related calculations.
Figure 30(a) shows a class-AB amplifier system. It takes an analog signal input and produces an analog signal
output. This amplifier circuit can be directly connected to the AP-II or other analyzer input.
This is not true of the class-D amplifier system shown in Figure 30(b), which requires low-pass filters in most
cases in order to measure the audio output waveforms. This is because it takes an analog input signal and
converts it into a pulse-width modulated (PWM) output signal that is not accurately processed by some
analyzers.
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Power Supply
Analyzer
20 Hz - 20 kHz
Signal
Generator
APA
RL
(a) Basic Class-AB
Power Supply
Lfilt
Analyzer
20 Hz - 20 kHz
Signal
Generator
Cfilt
Class-D APA
RL
(b) Traditional Class-D
Figure 30. Audio Measurement Systems
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SE Input and SE Output (TPA3122D2 Stereo Configuration)
The SE input and output configuration is used with class-AB amplifiers. A block diagram of a fully SE
measurement circuit is shown in Figure 31. SE inputs normally have one input pin per channel. In some cases,
two pins are present; one is the signal and the other is ground. SE outputs have one pin driving a load through
an output ac coupling capacitor and the other end of the load is tied to ground. SE inputs and outputs are
considered to be unbalanced, meaning one end is tied to ground and the other to an amplifier input/output.
The generator should have unbalanced outputs, and the signal should be referenced to the generator ground for
best results. Unbalanced or balanced outputs can be used when floating, but they may create a ground loop that
will effect the measurement accuracy. The analyzer should have balanced inputs to cancel out any
common-mode noise in the measurement.
Evaluation Module
Audio Power
Amplifier
Analyzer
Generator
C
IN
L
filt
C
R
L
R
IN
GEN
V
GEN
R
R
C
ANA
ANA
ANA
C
R
filt
L
C
ANA
Twisted-Pair Wire
Twisted-Pair Wire
Figure 31. SE Input—SE Output Measurement Circuit
The following general rules should be followed when connecting to APAs with SE inputs and outputs:
•
•
•
•
•
Use an unbalanced source to supply the input signal.
Use an analyzer with balanced inputs.
Use twisted pair wire for all connections.
Use shielding when the system environment is noisy.
Ensure the cables from the power supply to the APA, and from the APA to the load, can handle the large
currents (see Table 4)
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DIFFERENTIAL INPUT AND BTL OUTPUT (TPA3122D2 Mono Configuration)
Many of the class-D APAs and many class-AB APAs have differential inputs and bridge-tied load (BTL) outputs.
Differential inputs have two input pins per channel and amplify the difference in voltage between the pins.
Differential inputs reduce the common-mode noise and distortion of the input circuit. BTL is a term commonly
used in audio to describe differential outputs. BTL outputs have two output pins providing voltages that are 180
degrees out of phase. The load is connected between these pins. This has the added benefits of quadrupling the
output power to the load and eliminating a dc blocking capacitor.
A block diagram of the measurement circuit is shown in Figure 32. The differential input is a balanced input,
meaning the positive (+) and negative (-) pins have the same impedance to ground. Similarly, the SE output
equates to a balanced output.
Evaluation Module
Audio Power
Generator
Analyzer
Amplifier
CIN
L
filt
RGEN
RIN
RIN
C
C
RANA
CANA
filt
RL
VGEN
CIN
L
filt
RGEN
RANA
CANA
filt
Twisted-Pair Wire
Twisted-Pair Wire
Figure 32. Differential Input, BTL Output Measurement Circuit
The generator should have balanced outputs, and the signal should be balanced for best results. An unbalanced
output can be used, but it may create a ground loop that affects the measurement accuracy. The analyzer must
also have balanced inputs for the system to be fully balanced, thereby cancelling out any common-mode noise in
the circuit and providing the most accurate measurement.
The following general rules should be followed when connecting to APAs with differential inputs and BTL outputs:
•
•
•
•
•
Use a balanced source to supply the input signal.
Use an analyzer with balanced inputs.
Use twisted-pair wire for all connections.
Use shielding when the system environment is noisy.
Ensure that the cables from the power supply to the APA, and from the APA to the load, can handle the large
currents (see Table 4).
Table 4 shows the recommended wire size for the power supply and load cables of the APA system. The real
concern is the dc or ac power loss that occurs as the current flows through the cable. These recommendations
are based on 12-inch long wire with a 20-kHz sine-wave signal at 25°C.
Table 4. Recommended Minimum Wire Size for Power Cables
DC POWER LOSS
(MW)
AC POWER LOSS
(MW)
POUT (W)
RL(Ω)
AWG Size
10
4
4
8
8
18
18
22
22
22
22
28
28
16
3.2
2
40
8
18
3.7
2.1
1.6
42
8.5
8.1
6.2
2
1
8
< 0.75
1.5
6.1
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Apr-2008
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
TPA3122D2N
ACTIVE
PDIP
N
20
20
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
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