TPA3156D2DAD [TI]
70W 立体声、140W 单声道、4.5V 至 26V、模拟输入 D 类音频放大器，低空闲电流 | DAD | 32 | -40 to 85;
| 型号： | TPA3156D2DAD |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 70W 立体声、140W 单声道、4.5V 至 26V、模拟输入 D 类音频放大器，低空闲电流 | DAD | 32 | -40 to 85 放大器 光电二极管 商用集成电路 音频放大器 |
| 文件： | 总41页 (文件大小：3347K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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TPA3156D2
SLOS992 –DECEMBER 2017
TPA3156D2 2 x 70-W, Analog Input, Stereo, Class-D Audio Amplifier With Low Idle Power
Dissipation
1 Features
3 Description
The TPA3156D2 has low idle power loss and helps to
extend the battery life of Bluetooth/Wireless speakers
and other battery-powered audio systems. The high
efficiency of the TPA3156D2 device allows it to do 2
× 70 W with external heat sink on a dual layer PCB.
This device integrates an efficiency boost mode,
which dynamically reduces the current ripple of the
external LC filter and the idle current .
1
•
•
•
2 × 70 W Into a 4-Ω BTL Load at 24 V
Wide Voltage Range: 4.5 V to 26 V
Efficient Class-D Operation
–
Very Low Idle Current: <23 mA for
recommended LC filter configurations
–
–
Greater than 90% Power Efficiency
Adaptive Modulation Schemes based on
Output Power
The TPA3156D2 advanced oscillator/PLL circuit
employs a multiple switching frequency option to
avoid AM interferences, which is achieved together
with an option of either master or slave option,
making it possible to synchronize multiple devices.
•
•
Multiple Switching Frequencies
–
–
–
AM Avoidance
Master and Slave Synchronization
300-KHz to 1.2-MHz Switching Frequency
The TPA3156D2 devices are fully protected against
faults with short-circuit protection and thermal
protection as well as overvoltage, undervoltage, and
DC protection. Faults are reported back to the
processor to prevent devices from being damaged
during overload conditions.
Feedback Power-Stage Architecture With High
PSRR Reduces PSU Requirements
•
•
Programmable Power Limit
Parallel BTL Mode and Mono-Channel Mode
Support
Device Information(1)
•
•
Supports Both Single and Dual Power Supply
Modes
PART NUMBER
PACKAGE
BODY SIZE (NOM)
TPA3156D2
DAD (32)
11.00 mm × 6.20 mm
Integrated Self-Protection Circuits Including
Overvoltage, Undervoltage, Overtemperature, DC-
Detect, and Short Circuit With Error Reporting
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
•
•
Thermally Enhanced Packages
Simplified Application Circuit
–
DAD (32-Pin HTSSOP Pad Up)
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An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPA3156D2
SLOS992 –DECEMBER 2017
www.ti.com
Table of Contents
7.4 Device Functional Modes........................................ 21
Applications and Implementation ...................... 23
8.1 Application Information............................................ 23
8.2 Typical Application .................................................. 23
Power Supply Recommendations...................... 25
9.1 Power Supply Mode................................................ 25
1
2
3
4
5
6
Features.................................................................. 1
8
9
Applications ........................................................... 1
Description ............................................................. 1
Revision History..................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 5
6.1 Absolute Maximum Ratings ...................................... 5
6.2 ESD Ratings ............................................................ 5
6.3 Recommended Operating Conditions....................... 5
6.4 Thermal Information.................................................. 6
6.5 DC Electrical Characteristics .................................... 6
6.6 AC Electrical Characteristics..................................... 7
6.7 Typical Characteristics.............................................. 8
Detailed Description ............................................ 12
7.1 Overview ................................................................. 12
7.2 Functional Block Diagram ....................................... 12
7.3 Feature Description................................................. 13
10 Layout................................................................... 25
10.1 Layout Guidelines ................................................. 25
10.2 Layout Example .................................................... 27
10.3 Heat Sink Used on the EVM................................. 29
11 Device and Documentation Support ................. 30
11.1 Documentation Support ....................................... 30
11.2 Community Resources.......................................... 30
11.3 Trademarks........................................................... 30
11.4 Electrostatic Discharge Caution............................ 30
11.5 Glossary................................................................ 30
7
12 Mechanical, Packaging, and Orderable
Information ........................................................... 31
4 Revision History
DATE
REVISION
NOTES
December 2017
*
Initial release.
2
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SLOS992 –DECEMBER 2017
5 Pin Configuration and Functions
DAD Package
32-Pin HTSSOP With PowerPAD Up
TPA3156D2, Top View
1
2
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
PVCC
PVCC
BSPR
OUTPR
GND
MODSEL
SDZ
FAULTZ
RINP
3
4
RINN
5
PLIMIT
GVDD
GAIN/SLV
GND
6
OUTNR
BSNR
GND
7
8
Thermal
PAD
9
BSPL
OUTPL
GND
LINP
10
11
12
13
14
15
16
LINN
MUTE
AM2
OUTNL
BSNL
PVCC
PVCC
AVCC
AM1
AM0
SYNC
Pin Functions
PIN
NAME
TYPE(1)
DESCRIPTION
NO.
1
MODSEL
I
Mode selection logic input (LOW = Ultra Low Idle Loss Mode, HIGH = BD Mode). TTL logic levels with
compliance to AVCC.
2
3
SDZ
I
Shutdown logic input for audio amp (LOW = outputs Hi-Z, HIGH = outputs enabled). TTL logic levels with
compliance to AVCC.
FAULTZ
DO
General fault reporting including Over-temp, DC Detect. Open drain.
FAULTZ = High, normal operation
FAULTZ = Low, fault condition
4
5
6
RINP
RINN
I
I
I
Positive audio input for right channel. Connect to GND for MONO mode.
Negative audio input for right channel. Connect to GND for MONO mode.
PLIMIT
Power limit level adjust. Connect a resistor divider from GVDD to GND to set power limit. Connect directly
to GVDD for no power limit.
7
GVDD
PO
Internally generated gate voltage supply. Not to be used as a supply or connected to any component other
than a 1 µF X7R ceramic decoupling capacitor and the PLIMIT and GAIN/SLV resistor dividers.
8
GAIN/SLV
GND
I
G
I
Selects Gain and selects between Master and Slave mode depending on pin voltage divider.
Ground
9
10
11
12
LINP
Positive audio input for left channel. Connect to GND for PBTL mode.
Negative audio input for left channel. Connect to GND for PBTL mode.
LINN
I
MUTE
I
Mute signal for fast disable/enable of outputs (HIGH = outputs Hi-Z, LOW = outputs enabled). TTL logic
levels with compliance to AVCC.
13
14
15
16
17
AM2
AM1
I
AM Avoidance Frequency Selection
I
I
AM Avoidance Frequency Selection
AM0
AM Avoidance Frequency Selection
SYNC
AVCC
DIO
P
Clock input/output for synchronizing multiple class-D devices. Direction determined by GAIN/SLV terminal.
Analog Supply
(1) DO = Digital Output, I = Analog Input, G = General Ground, PO = Power Output, BST = Boot Strap.
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Pin Functions (continued)
PIN
TYPE(1)
DESCRIPTION
NO.
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
NAME
PVCC
PVCC
BSNL
P
P
Power supply
Power supply
BST
PO
G
Boot strap for negative left channel output, connect to 220 nF X5R, or better ceramic cap to OUTPL
OUTNL
GND
Negative left channel output
Ground
OUTPL
BSPL
PO
BST
G
Positive left channel output
Boot strap for positive left channel output, connect to 220 nF X5R, or better ceramic cap to OUTNL
GND
Ground
BSNR
OUTNR
GND
BST
PO
G
Boot strap for negative right channel output, connect to 220 nF X5R, or better ceramic cap to OUTNR
Negative right channel output
Ground
OUTPR
BSPR
PO
BST
P
Positive right channel output
Boot strap for positive right channel output, connect to 220 nF X5R or better ceramic cap to OUTPR
PVCC
PVCC
PowerPAD
Power supply
P
Power supply
G
Connect to GND for best system performance. If not connected to GND, leave floating.
4
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SLOS992 –DECEMBER 2017
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–0.3
–0.3
–0.3
–0.3
MAX
30
UNIT
V
Supply voltage, VCC
Input voltage, VI
PVCC, AVCC
INPL, INNL, INPR, INNR
6.3
V
PLIMIT, GAIN / SLV, SYNC
AM0, AM1, AM2, MUTE, SDZ, MODSEL
AM0, AM1, AM2, MUTE, SDZ, MODSEL
GVDD+0.3
PVCC+0.3
10
V
V
Slew rate, maximum(2)
V/ms
°C
°C
°C
Operating free-air temperature, TA
Operating junction temperature , TJ
Storage temperature, Tstg
–40
–40
–40
85
150
125
(1) Stresses beyond those listed under absolute maximum ratings can cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods can affect device reliability.
(2) 100-kΩ series resistor is required if maximum slew rate is exceeded.
6.2 ESD Ratings
VALUE
±2000
±500
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
V(ESD)
Electrostatic discharge
V
Charged-device model (CDM), per JEDEC specification JESD22-
C101(2)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. .
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
4.5
2
NOM
MAX
UNIT
VCC
VIH
VIL
Supply voltage
PVCC, AVCC
26
V
V
V
V
High-level input voltage
Low-level input voltage
Low-level output voltage
AM0, AM1, AM2, MUTE, SDZ, SYNC, MODSEL
AM0, AM1, AM2, MUTE, SDZ, SYNC, MODSEL
FAULTZ, RPULL-UP = 100 kΩ, PVCC = 26 V
0.8
0.8
VOL
AM0, AM1, AM2, MUTE, SDZ, MODSEL
(VI = 2 V, VCC = 18 V)
IIH
High-level input current
Minimum load Impedance
Output-filter Inductance
50
µA
Ω
RL(BTL)
Output filter: L = 10 µH, C = 680 nF
Output filter: L = 10 µH, C = 1 µF
3.2
1.6
4
2
RL(PBTL)
Minimum output filter inductance under short-
circuit condition
Lo
1
µH
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6.4 Thermal Information
TPA3156D2
DAD(2)
32 PINS
N/A
THERMAL METRIC(1)
UNIT
RθJA
RθJC(top)
ψJT
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-top characterization parameter
Junction-to-board characterization parameter
°C/W
°C/W
°C/W
°C/W
1.2
1.2
ψJB
21
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) For the PCB layout please see the TPA3156D2EVM user guide.
6.5 DC Electrical Characteristics
TA = 25°C, AVCC = PVCC = 12 V to 24 V, RL = 4 Ω, fs = 400 kHz, low idle-loss mode(unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
Class-D output offset voltage
(measured differentially)
| VOS
ICC
|
VI = 0 V
1.5
5
mV
mA
SDZ = 2 V, With load and filter, PVCC = 12 V
SDZ = 2 V, With load and filter, PVCC = 24 V
SDZ = 0.8 V, With load and filter, PVCC = 12 V
SDZ = 0.8 V, With load and filter, PVCC = 24 V
15
23
20
30
Quiescent supply current
Quiescent supply current in
shutdown mode
ICC(SD)
rDS(on)
µA
mΩ
dB
Drain-source on-state resistance,
measured pin to pin
PVCC = 21 V, Iout = 500 mA, TJ = 25°C
90
R1 = 5.6 kΩ, R2 = Open
R1 = 20 kΩ, R2 = 100 kΩ
R1 = 39 kΩ, R2 = 100 kΩ
R1 = 47 kΩ, R2 = 75 kΩ
R1 = 51 kΩ, R2 = 51 kΩ
R1 = 75 kΩ, R2 = 47 kΩ
R1 = 100 kΩ, R2 = 39 kΩ
R1 = 100 kΩ, R2 = 16 kΩ
SDZ = 2 V
19
25
31
35
19
25
31
35
20
26
32
36
20
26
32
36
40
2
21
27
33
37
21
27
33
37
G
G
Gain (BTL)
Gain (SLV)
dB
dB
dB
ton
Turn-on time
ms
µs
V
tOFF
GVDD
Turn-off time
SDZ = 0.8 V
Gate drive supply
IGVDD < 200 µA
5.1
5.6
6.3
Output voltage maximum under
PLIMIT control
VO
V(PLIMIT) = 2 V; VI = 1 Vrms
6.75
8.2
8.75
V
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6.6 AC Electrical Characteristics
TA = 25°C, AVCC = PVCC = 12 V to 24 V, RL = 4 Ω (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
200 mVPP ripple at 1 kHz, Gain = 26 dB,
Inputs
KSVR
Power supply ripple rejection
–70
dB
AC-coupled to GND
THD+N = 10%, f = 1 kHz, PVCC = 14.4 V,
Load = 4Ω
25
50
THD+N = 10%, f = 1 kHz, PVCC = 21 V,
Load = 8 Ω
PO
Continuous output power
W
THD+N = 10%, f = 1 kHz, PVCC = 24 V,
Load = 4 Ω
70
VCC = 21 V, f = 1 kHz, PO = 15 W (half-
power)
THD+N
Vn
Total harmonic distortion + noise
Output integrated noise
0.1%
65
–80
µV
dBV
dB
20 Hz to 22 kHz, A-weighted filter, Gain = 20
dB
Crosstalk
VO = 1 Vrms, Gain = 20 dB, f = 1 kHz
–100
Maximum output at THD+N < 1%, f = 1 kHz,
Gain = 20 dB, A-weighted
SNR
Signal-to-noise ratio
102
dB
AM2=0, AM1=0, AM0=0
AM2=0, AM1=0, AM0=1
AM2=0, AM1=1, AM0=0
AM2=0, AM1=1, AM0=1
AM2=1, AM1=0, AM0=0
AM2=1, AM1=0, AM0=1
376
470
564
940
1128
282
282
400
500
424
530
600
636
1000
1200
300
1060
1278
318
fOSC
Oscillator frequency
kHz
300
318
AM2=1, AM1=1, AM0=0
AM2=1, AM1=1, AM0=1
Modulation scheme Fixed in
1SPW Mode
Reserved
Thermal trip point
≥150
15
°C
°C
A
Thermal hysteresis
Over current trip point
10
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6.7 Typical Characteristics
fs = 400 kHz, Ultra Low Idle Loss Mode, TPA3156D2EVM Tested With AP2722. (unless otherwise noted)
30
20
10
0
10
Gain=26dB
TA=25èC
RL=4W
Gain=26dB
PVcc=12V
TA=25èC
RL=8W
P O=1W
PO =2.5W
PO=5W
1
0.1
0.01
FPWM = 400 kHz
20 25
0.001
5
10
15
20
100
1k
10k 20k
Supply Voltage (V)
Frequency (Hz)
D0021
D005
Figure 1. Idle Current vs PVCC
Figure 2. Total Harmonic Distortion + Noise (BTL) vs
Frequency
10
1
10
Gain=26dB
PVcc=24V
TA=25èC
RL=8W
P O=1W
PO =5W
PO=10W
Gain=26dB
PVCC=6V
TA=25èC
RL=4W
1
0.1
0.1
0.01
0.01
f= 20Hz
f= 1kHz
f= 6KHz
0.001
0.001
20
100
1k
10k 20k
0.01
0.1
Output Power (W)
1
10
Frequency (Hz)
D006
D007
Figure 3. Total Harmonic Distortion + Noise (BTL) vs
Frequency
Figure 4. Total Harmonic Distortion + Noise (BTL) vs Output
Power
10
10
Gain=26dB
PVCC=12V
TA=25èC
RL=4W
Gain=26dB
PVCC=24V
TA=25èC
RL=4W
1
0.1
1
0.1
0.01
0.01
f= 20Hz
f= 20Hz
f= 1kHz
f= 6KHz
f= 1kHz
f= 6KHz
0.001
0.001
0.01
0.1
1
10
40
0.01
0.1
1
10
100
Output Power (W)
Output Power (W)
D008
D009
Figure 5. Total Harmonic Distortion + Noise (BTL) vs Output
Power
Figure 6. Total Harmonic Distortion + Noise (BTL) vs Output
Power
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Typical Characteristics (continued)
fs = 400 kHz, Ultra Low Idle Loss Mode, TPA3156D2EVM Tested With AP2722. (unless otherwise noted)
10
10
Gain=26dB
PVCC=24V
TA=25èC
RL=8W
Gain=26dB
PVCC=12V
TA=25èC
RL=8W
1
1
0.1
0.1
0.01
0.01
f= 20Hz
f= 20Hz
f= 1kHz
f= 6KHz
f= 1kHz
f= 6KHz
0.001
0.001
0.01
0.1
1
10
50
0.01
0.1
1
10
50
Output Power (W)
Output Power (W)
D010
D011
Figure 7. Total Harmonic Distortion + Noise (BTL) vs Output
Power
Figure 8. Total Harmonic Distortion + Noise (BTL) vs Output
Power
50
30
300
200
100
0
Gain=26dB
TA=25èC
PVCC=24V
20
40
RL=4W
10
0
30
-10
-20
-30
-40
-50
-100
-200
-300
-400
-500
20
10
0
Gain=26dB
PVCC=12V
TA=25èC
RL=4W
Gain
Phase
1
2
3
4
5
20
100
1k
10k 20k
100k
PLIMIT Voltage(V)
Frequency (Hz)
D0012
D0225
Figure 9. Output Power (BTL) vs Plimit Voltage
Figure 10. Gain/Phase (BTL) vs Frequency
100
90
80
70
60
50
40
30
20
10
0
50
45
40
35
30
25
20
15
10
5
Gain=26dB
TA=25èC
RL=4W
Gain=26dB
TA=25èC
RL=8W
THD+N=1%
THD+N=10%
THD+N=1%
THD+N=10%
0
4
6
8
10 12 14 16 18 20 22 24 26
Supply Voltage (V)
4
6
8
10 12 14 16 18 20 22 24 26
Supply Voltage (V)
D014
D037
15
D037
Figure 11. Maximum Output Power (BTL) vs Supply Voltage
Figure 12. Maximum Output Power (BTL) vs Supply Voltage
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Typical Characteristics (continued)
fs = 400 kHz, Ultra Low Idle Loss Mode, TPA3156D2EVM Tested With AP2722. (unless otherwise noted)
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
Gain=26dB
TA=25èC
RL=8W
Gain=26dB
TA=25èC
RL=4W
PVCC = 6V
PVCC = 12 V
PVCC = 24 V
PVCC = 6V
PVCC = 12 V
PVCC = 24 V
0
5
10
15
20
25
30
35
40
45
50
0
5
10
15
20
25
30
35
40
45
50
Output Power (W)
Output Power (W)
D016
D017
Figure 13. Power Efficiency (BTL) vs Output Power
Figure 14. Power Efficiency (BTL) vs Output Power
0
0
-20
Gain=26dB
PVCC=24V
TA=25èC
RL=8W
Gain=26dB
PVCC=12V
TA=25èC
RL=4W
-20
-40
-60
-40
-60
-80
-80
-100
-120
-140
-100
-120
-140
Right to Left
Left to Right
Right to Left
Left to Right
20
100
1k
10k 20k
20
100
1k
10k 20k
Frequency (Hz)
Frequency (Hz)
D010318
D00139
Figure 15. Crosstalk vs Frequency
Figure 16. Crosstalk vs Frequency
0
-20
10
1
Gain=26dB
PVCC=12VDC+200mVP-P
TA=25èC
Gain=26dB
P O=1W
PO =5W
PO=10W
PVcc=12V
TA=25èC
RL=2W
RL=8W
-40
0.1
-60
0.01
-80
Left Channel
Right Channel
-100
0.001
20
100
1k
10k 20k
20
100
1k
10k 20k
Frequency (Hz)
Frequency (Hz)
D020
D021
Figure 17. Supply Ripple Rejection Ratio (BTL) vs
Frequency
Figure 18. Total Harmonic Distortion + Noise (PBTL) vs
Frequency
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Typical Characteristics (continued)
fs = 400 kHz, Ultra Low Idle Loss Mode, TPA3156D2EVM Tested With AP2722. (unless otherwise noted)
180
160
140
120
100
80
10
Gain=26dB
TA=25èC
RL=2W
Gain=26dB
PVCC=12V
TA=25èC
RL=2W
1
0.1
60
0.01
40
f= 20Hz
f= 1kHz
f= 6KHz
THD+N=1%
THD+N=10%
20
0.001
0
0.01
0.1
1
10
40
4
6
8
10
12
14
16
18
20
22
Output Power (W)
Supply Voltage (V)
D022
D023
Figure 19. Total Harmonic Distortion + Noise (PBTL) vs
Output Power
Figure 20. Maximum Output Power (PBTL) vs Supply
Voltage
100
0
Gain=26dB
PVCC=12VDC+200mVP-P
TA=25èC
90
80
70
60
50
40
30
20
10
0
-20
-40
RL=2W
-60
-80
Gain=26dB
TA=25èC
RL=2W
PVCC = 6V
PVCC = 12 V
PVCC = 24 V
-100
0
10
20
30
40
50
60
70
20
100
1k
10k 20k
Output Power (W)
Frequency (Hz)
D024
D025
Figure 21. Power Efficiency (PBTL) vs Output Power
Figure 22. Supply Ripple Rejection Ratio (PBTL) vs
Frequency
10
160 Gain=26dB
Gain=26dB
PVCC=24V
TA=25èC
RL=2W
5
TA=25èC
140
120
100
80
RL=2W
2
1
0.5
0.2
0.1
0.05
60
0.02
0.01
40
f= 20Hz
f= 1kHz
f= 6KHz
0.005
20
THD+N=1%
THD+N=10%
0.002
0.001
0
4
6
8
10 12 14 16 18 20 22 24 26
Supply Voltage (V)
0.01
0.1
1
10 20
100
Output Power (W)
D014
D03074
D0037
Figure 24. Maximum Output Power (PBTL) vs Supply
Voltage
Figure 23. Total Harmonic Distortion + Noise (PBTL) vs
Output Power
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7 Detailed Description
7.1 Overview
The TPA3156D2 device is a highly efficient Class D audio amplifier with extreme low idle power dissipation. It
can support as low as 23-mA idle loss current using standard LC filter configurations. It is integrated with 90-mΩ
MOSFET that allows output currents up to 10 A for TPA3156D2. The high efficiency allows the amplifier to
provide an excellent audio performance without the requirement for a bulky heat sink.
The device can be configured for either master or slave operation by using the SYNC pin. Configuring using the
SYNC pin helps to prevent audible beats noise.
7.2 Functional Block Diagram
GVDD
PVCC
BSPR
SDZ
PVCC
TTL
Buffer
Modulation and
PBTL Select
MUTE
Gain
Control
OUTPR_FB
Gate
Drive
OUTPR
GAIN
+
OUTPR_FB
–
–
–
–
GND
RINP
RINN
+
+
PWM
Logic
Gain
Control
PLIMIT
GVDD
–
PVCC
–
+
BSNR
+
PVCC
OUTPNR_FB
OUTNR_
FB
+
FAULTZ
Gate
Drive
OUTNR
GND
Input
Sense
MONO
Select
SC Detect
DC Detect
SYNC
GAIN/SLV
Ramp
Generator
Startup Protection
Logic
Biases and
References
Thermal
Detect
AM<2:0>
PLIMIT
Reference
PLIMIT
PVCC
UVLO/OVLO
PVCC
GVDD
PVCC
BSNL
AVDD
PVCC
LDO
Regulator
AVCC
GVDD
GVDD
Gate
Drive
OUTNL
–
OUTNL_FB
OUTNL_
FB
–
+
+
–
LINP
LINN
GND
+
+
Gain
Control
PWM
Logic
PLIMIT
–
GVDD
–
PVCC
+
+
BSPL
PVCC
OUTPL_FB
–
Gate
Drive
OUTPL
GND
Input
Sense
PBTL
Select
Modulation and
PBTL Select
OUTPL_FB
GND
Thermal
Pad
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7.3 Feature Description
7.3.1 Gain Setting and Master and Slave
The gain of the TPA3156D2 is set by the voltage divider connected to the GAIN/SLV control pin. Master or Slave
mode is also controlled by the same pin. An internal ADC is used to detect the 8 input states. The first four
stages sets the GAIN in Master mode in gains of 20, 26, 32, 36 dB respectively, while the next four stages sets
the GAIN in Slave mode in gains of 20, 26, 32, 36 dB respectively. The gain setting is latched during power-up
and cannot be changed while device is powered. Table 1 lists the recommended resistor values and the state
and gain:
Table 1. Gain and Master/Slave
MASTER / SLAVE
GAIN
R1 (to GND)(1)
R2 (to GVDD)(1)
INPUT IMPEDANCE
MODE
Master
Master
Master
Master
Slave
20 dB
26 dB
32 dB
36 dB
20 dB
26 dB
32 dB
36 dB
5.6 kΩ
20 kΩ
39 kΩ
47 kΩ
51 kΩ
75 kΩ
100 kΩ
100 kΩ
OPEN
100 kΩ
100 kΩ
75 kΩ
51 kΩ
47 kΩ
39 kΩ
16 kΩ
60 kΩ
30 kΩ
15 kΩ
9 kΩ
60 kΩ
30 kΩ
15 kΩ
9 kΩ
Slave
Slave
Slave
(1) Resistor tolerance should be 5% or better.
5
6
INNR
2
1
PLIMIT
GVDD
1
C5 1 µF
2
7
2
1
R2
8
51 k
GAIN/SLV
GND
9
R1 51 k
10
Figure 25. Gain, Master/Slave
In Master mode, SYNC terminal is an output, in Slave mode, SYNC terminal is an input for a clock input. TTL
logic levels with compliance to GVDD.
7.3.2 Input Impedance
The TPA3156D2 input stage is a fully differential input stage and the input impedance changes with the gain
setting from 7.3 kΩ at 36 dB gain to 50 kΩ at 20 dB gain. Table 1 lists the values from min to max gain. The
tolerance of the input resistor value is ±20% so the minimum value will be higher than 5.9 kΩ. The inputs must
be AC-coupled to minimize the output dc-offset and ensure correct ramping of the output voltages during power-
ON and power-OFF. The input ac-coupling capacitor together with the input impedance forms a high-pass filter
with the following cut-off frequency:
1
ƒ
=
2pZiCi
(1)
If a flat bass response is required down to 20 Hz the recommended cut-off frequency is a tenth of that, 2 Hz.
Table 2 lists the recommended ac-couplings capacitors for each gain step. If a –3-dB capacitor is accepted at 20
Hz 10 times lower capacitors can used – for example, a 1-µF capacitor can be used.
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Table 2. Recommended Input AC-Coupling Capacitors
GAIN
20 dB
26 dB
32 dB
36 dB
INPUT IMPEDANCE
50 kΩ
INPUT CAPACITANCE
HIGH-PASS FILTER
1.5 µF
3.3 µF
5.6 µF
10 µF
2.1 Hz
1.9 Hz
2.3 Hz
2.2 Hz
25 kΩ
12.5 kΩ
7.3 kΩ
Z
f
C
i
Z
i
IN
Input
Signal
Figure 26. Input Impedance
The input capacitors used should be a type with low leakage, such as quality electrolytic, tantalum, or ceramic
capacitors. If a polarized type is used the positive connection should face the input pins which are biased to 3
Vdc.
7.3.3 Startup and Shutdown Operation
The TPA3156D2 employs a shutdown mode of operation designed to reduce supply current (Icc) to the absolute
minimum level during periods of nonuse for power conservation. The SDZ input terminal should be held high
(see specification table for trip point) during normal operation when the amplifier is in use. Pulling SDZ low will
put the outputs to mute and the amplifier to enter a low-current state. Do not leave SDZ unconnected, because
amplifier operation would be unpredictable.
For the best power-off pop performance, place the amplifier in the shutdown mode prior to removing the power
supply. The gain setting is selected at the end of the start-up cycle. At the end of the start-up cycle, the gain is
selected and cannot be changed until the next power-up.
7.3.4 PLIMIT Operation
The TPA3156D2 has a built-in voltage limiter that can be used to limit the output voltage level below the supply
rail, the amplifier operates as if it was powered by a lower supply voltage, and thereby limits the output power.
Add a resistor divider from GVDD to ground to set the voltage at the PLIMIT pin. An external reference may also
be used if tighter tolerance is required. Add a 1-µF capacitor from pin PLIMIT to ground to ensure stability.
Figure 27. Power Limit Example
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The PLIMIT circuit sets a limit on the output peak-to-peak voltage. The limiting is done by limiting the duty cycle
to a fixed maximum value. The limit can be thought of as a "virtual" voltage rail which is lower than the supply
connected to PVCC. The "virtual" rail is approximately four times the voltage at the PLIMIT pin. The output
voltage can be used to calculate the maximum output power for a given maximum input voltage and speaker
impedance.
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æ
æ
ö2
ö
÷
ø
RL
´ V
ç
÷
ç
P
ç
÷
RL + 2 ´ RS
è
è
ø
POUT
=
for unclipped power
2 ´ RL
where
•
•
•
•
POUT (10%THD) = 1.25 × POUT (unclipped)
RL is the load resistance.
RS is the total series resistance including RDS(on), and output filter resistance.
VP is the peak amplitude, which is limited by "virtual" voltage rail.
(2)
Table 3. Power Limit Example
PVCC (V)
24 V
PLIMIT VOLTAGE (V)(1)
R to GND
Open
R to GVDD
Short
OUTPUT VOLTAGE (Vrms)
GVDD
3.3
17.9
12.67
9
24 V
45 kΩ
24 kΩ
Open
51 kΩ
24 V
2.25
GVDD
2.25
1.5
51 kΩ
12 V
Short
10.33
9
12 V
24 kΩ
18 kΩ
51 kΩ
12 V
68 kΩ
6.3
(1) PLIMIT measurements taken with EVM gain set to 26 dB and input voltage set to 1 Vrms
.
7.3.5 GVDD Supply
The GVDD Supply is used to power the gates of the output full bridge transistors. The GVDD Supply can also be
used to supply the PLIMIT and GAIN/SLV voltage dividers. Decouple GVDD with a X5R ceramic 1-µF capacitor
to GND. The GVDD supply is not intended to be used for external supply. The current consumption should be
limited by using resistor voltage dividers for GAIN/SLV and PLIMIT of 100 kΩ or more.
7.3.6 BSPx AND BSNx Capacitors
The full H-bridge output stages use only NMOS transistors. Therefore, they require bootstrap capacitors for the
high side of each output to turn on correctly. A 220-nF ceramic capacitor of quality X5R or better, rated for at
least 16 V, must be connected from each output to the corresponding bootstrap input. (See the application circuit
diagram in Figure 34.) The bootstrap capacitors connected between the BSxx pins and corresponding output
function as a floating power supply for the high-side N-channel power MOSFET gate drive circuitry. During each
high-side switching cycle, the bootstrap capacitors hold the gate-to-source voltage high enough to keep the high-
side MOSFETs turned on.
7.3.7 Differential Inputs
The differential input stage of the amplifier cancels any noise that appears on both input lines of the channel. To
use the TPA3156D2 with a differential source, connect the positive lead of the audio source to the RINP or LINP
input and the negative lead from the audio source to the RINN or LINN input. To use the TPA3156D2 with a
single-ended source, ac ground the negative input through a capacitor equal in value to the input capacitor on
positive and apply the audio source to either input. In a single-ended input application, the unused input should
be ac grounded at the audio source instead of at the device input for best noise performance. For good transient
performance, the impedance seen at each of the two differential inputs should be the same.
The impedance seen at the inputs should be limited to an RC time constant of 1 ms or less if possible to allow
the input dc blocking capacitors to become completely charged during the 40-ms power-up time. If the input
capacitors are not allowed to completely charge, there will be some additional sensitivity to component matching
which can result in pop if the input components are not well matched.
7.3.8 Device Protection System
The TPA3156D2 contains a complete set of protection circuits carefully designed to make system design efficient
as well as to protect the device against any kind of permanent failures due to short circuits, overload, over
temperature, and under-voltage. The FAULTZ pin will signal if an error is detected according to Table 4:
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Table 4. Fault Reporting
TRIGGERING CONDITION
LATCHED/SELF-
CLEARING
FAULT
FAULTZ
ACTION
(typical value)
Output short or short to PVCC or GND
Tj > 150°C
Over Current
Low
Low
Low
Output high impedance
Output high impedance
Output high impedance
Latched
Latched
Latched
Over Temperature
Too High DC Offset
DC output voltage
Under Voltage on
PVCC
PVCC < 4.5V
PVCC > 27V
–
–
Output high impedance
Output high impedance
Self-clearing
Self-clearing
Over Voltage on
PVCC
7.3.9 DC Detect Protection
The TPA3156D2 has circuitry which will protect the speakers from DC current which might occur due to defective
capacitors on the input or shorts on the printed circuit board at the inputs. A DC detect fault will be reported on
the FAULT pin as a low state. The DC Detect fault will also cause the amplifier to shutdown by changing the
state of the outputs to Hi-Z.
If automatic recovery from the short circuit protection latch is desired, connect the FAULTZ pin directly to the
SDZ pin. Connecting the FAULTZ and SDZ pins allows the FAULTZ pin function to automatically drive the SDZ
pin low which clears the DC Detect protection latch.
A DC Detect Fault is issued when the output differential voltage of either channel exceeds DC protection
threshold level for more than 640 ms at the same polarity. Table 5 below shows some examples of the typical
DC Detect Protection threshold for several values of the supply voltage. The Detect Protection Threshold feature
protects the speaker from large DC currents or AC currents less than 2 Hz. To avoid nuisance faults due to the
DC detect circuit, hold the SD pin low at power-up until the signals at the inputs are stable. Also, take care to
match the impedance seen at the positive and negative inputs to avoid nuisance DC detect faults.
Table 5 lists the minimum output offset voltages required to trigger the DC detect. The outputs must remain at or
above the voltage listed in the table for more than 640 ms to trigger the DC detect.
Table 5. DC Detect Threshold
PVCC (V)
VOS - OUTPUT OFFSET VOLTAGE (V)
4.5
6
1.35
1.8
12
18
3.6
5.4
7.3.10 Short-Circuit Protection and Automatic Recovery Feature
The TPA3156D2 has protection from over current conditions caused by a short circuit on the output stage. The
short circuit protection fault is reported on the FAULTZ pin as a low state. The amplifier outputs are switched to a
high impedance state when the short circuit protection latch is engaged. The latch can be cleared by cycling the
SDZ pin through the low state.
If automatic recovery from the short circuit protection latch is desired, connect the FAULTZ pin directly to the
SDZ pin. Connecting the FAULTZ and SDZ pins allows the FAULTZ pin function to automatically drive the SDZ
pin low which clears the short-circuit protection latch.
7.3.11 Thermal Protection
Thermal protection on the TPA3156D2 prevents damage to the device when the internal die temperature
exceeds 150°C. This trip point has a ±15°C tolerance from device to device. Once the die temperature exceeds
the thermal trip point, the device enters into the shutdown state and the outputs are disabled. This is a latched
fault.
Thermal protection faults are reported on the FAULTZ terminal as a low state.
If automatic recovery from the thermal protection latch is desired, connect the FAULTZ pin directly to the SDZ
pin. This allows the FAULTZ pin function to automatically drive the SDZ pin low which clears the thermal
protection latch.
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7.3.12 Device Modulation Scheme
The TPA3156D2 and have the option of running in either BD modulation or low idle-loss mode.
7.3.12.1 BD-Modulation
This is a modulation scheme that allows operation without the classic LC reconstruction filter when the amp is
driving an inductive load with short speaker wires. Each output is switching from 0 volts to the supply voltage.
The OUTPx and OUTNx are in phase with each other with no input so that there is little or no current in the
speaker. The duty cycle of OUTPx is greater than 50% and OUTNx is less than 50% for positive output voltages.
The duty cycle of OUTPx is less than 50% and OUTNx is greater than 50% for negative output voltages. The
voltage across the load sits at 0V throughout most of the switching period, reducing the switching current, which
reduces any I2R losses in the load.
OUTP
OUTN
No Output
0V
OUTP-OUTN
Speaker
Current
OUTP
OUTN
Positive Output
PVCC
-
OUTP OUTN
0V
Speaker
Current
0A
OUTP
Negative Output
OUTN
0V
OUTP-OUTN
-
PVCC
0A
Speaker
Current
Figure 28. BD Mode Modulation
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7.3.13 Efficiency: LC Filter Required with the Traditional Class-D Modulation Scheme
The main reason that the traditional class-D amplifier-based on AD modulation requires an output filter is that the
switching waveform results in maximum current flow. This causes more loss in the load, which causes lower
efficiency. The ripple current is large for the traditional modulation scheme, because the ripple current is
proportional to voltage multiplied by the time at that voltage. The differential voltage swing is 2 × VCC, and the
time at each voltage is half the period for the traditional modulation scheme. An ideal LC filter is required to store
the ripple current from each half cycle for the next half cycle, while any resistance causes power dissipation. The
speaker is both resistive and reactive, whereas an LC filter is almost purely reactive.
The TPA3156D2 and modulation schemes have little loss in the load without a filter because the pulses are short
and the change in voltage is VCC instead of 2 × VCC. As the output power increases, the pulses widen, making
the ripple current larger. Ripple current could be filtered with an LC filter for increased efficiency, but for most
applications the filter is not required.
An LC filter with a cutoff frequency less than the class-D switching frequency allows the switching current to flow
through the filter instead of the load. The filter has less resistance but higher impedance at the switching
frequency than the speaker, which results in less power dissipation, therefore increasing efficiency.
7.3.14 Ferrite Bead Filter Considerations
Using the Advanced Emissions Suppression Technology in the TPA3156D2 and amplifiers, a high efficiency
class-D audio amplifier can be designed while minimizing interference to surrounding circuits. Designing the
amplifier can also be accomplished with only a low-cost ferrite bead filter. In this case the user must carefully
select the ferrite bead used in the filter. One important aspect of the ferrite bead selection is the type of material
used in the ferrite bead. Not all ferrite material is alike, therefore the user must select a material that is effective
in the 10-MHz to 100-MHz range which is key to the operation of the class-D amplifier. Many of the specifications
regulating consumer electronics have emissions limits as low as 30 MHz. The ferrite bead filter should be used to
block radiation in the 30-MHz and above range from appearing on the speaker wires and the power supply lines
which are good antennas for these signals. The impedance of the ferrite bead can be used along with a small
capacitor with a value in the range of 1000 pF to reduce the frequency spectrum of the signal to an acceptable
level. For best performance, the resonant frequency of the ferrite bead/ capacitor filter should be less than 10
MHz.
Also, the ferrite bead must be large enough to maintain its impedance at the peak currents expected for the
amplifier. Some ferrite bead manufacturers specify the bead impedance at a variety of current levels. In this case
the user can make sure the ferrite bead maintains an adequate amount of impedance at the peak current the
amplifier will see. If these specifications are not available, the device can also estimate the bead current handling
capability by measuring the resonant frequency of the filter output at low power and at maximum power. A
change of resonant frequency of less than fifty percent under this condition is desirable. Examples of ferrite
beads which have been tested and work well with the TPA3136D2 can be seen in the TPA3136D2EVM user
guide SLOU444.
A high quality ceramic capacitor is also required for the ferrite bead filter. A low ESR capacitor with good
temperature and voltage characteristics will work best.
Additional EMC improvements may be obtained by adding snubber networks from each of the class-D outputs to
ground. Suggested values for a simple RC series snubber network would be 18 Ω in series with a 330 pF
capacitor although design of the snubber network is specific to every application and must be designed taking
into account the parasitic reactance of the printed circuit board as well as the audio amp. Take care to evaluate
the stress on the component in the snubber network especially if the amp is running at high PVCC. Also, make
sure the layout of the snubber network is tight and returns directly to the GND pins on the IC.
Figure 29 and Figure 30 are TPA3156D2 EN55022 Radiated Emissions results uses TPA3156D2EVM with 8-Ω
speakers.
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Figure 29. TPA3156D2 Radiated Emissions-Horizontal
Figure 30. TPA3156D2 Radiated Emissions-Vertical
(PVCC=19V, PO=1W)
(PVCC=19V, PO=1W)
7.3.15 When to Use an Output Filter for EMI Suppression
A complete LC reconstruction filter should be added in some circuit instances. These circumstances might occur
if there are nearby circuits which are sensitive to noise. In these cases a classic second order Butterworth filter
similar to those shown in the figures below can be used.
Some systems have little power supply decoupling from the AC line but are also subject to line conducted
interference (LCI) regulations. These include systems powered by "wall warts" and "power bricks." In these
cases, LC reconstruction filters can be the lowest cost means to pass LCI tests. Common mode chokes using
low frequency ferrite material can also be effective at preventing line conducted interference.
10 µH
OUTP
C2
L1
0.68 µF
4 W - 8 W
10 µH
OUTN
C3
L2
0.68 µF
Ferrite
Chip Bead
OUTP
1 nF
4 W - 8 W
Ferrite
Chip Bead
OUTN
1 nF
Figure 31. Output Filters
7.3.16 AM Avoidance EMI Reduction
Table 6. AM Frequencies
US
EUROPEAN
AM FREQUENCY (kHz)
522-540
SWITCHING FREQUENCY (kHz)
AM2
AM1
AM0
AM FREQUENCY (kHz)
540-917
917-1125
1125-1375
1375-1547
540-914
500
0
0
0
0
0
0
0
1
0
0
1
0
1
0
0
1
0
0
914-1122
1122-1373
1373-1548
600 (or 400)
500
600 (or 400)
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Table 6. AM Frequencies (continued)
US
EUROPEAN
SWITCHING FREQUENCY (kHz)
AM2
AM1
AM0
AM FREQUENCY (kHz)
AM FREQUENCY (kHz)
0
0
1
0
0
1
1547-1700
1548-1701
600 (or 500)
7.4 Device Functional Modes
7.4.1 PBTL Mode
The TPA3156D2 can be connected in PBTL mode enabling up to 100W output power. This is done by:
•
•
•
Connect INPL and INNL directly to Ground (without capacitors) this sets the device in Mono mode during
power up.
Connect OUTPR and OUTNR together for the positive speaker terminal and OUTNL and OUTPL together for
the negative pin.
Analog input signal is applied to INPR and INNR.
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4.5ë t 26ë
Çꢀ!3129ꢁ2
wLbb
wLDIÇ
hÜÇꢀw
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ꢀꢃÇ[
ꢁꢄÇꢄ/Ç
[/
Cilter
hÜÇꢀ[
hÜÇb[
Figure 32. PBTL Mode
7.4.2 Mono Mode (Single Channel Mode)
The TPA3156D2 and can be connected in MONO mode to cut the idle power-loss nearly by half. This is done by:
•
Connect INPR and INNR directly to Ground (without capacitors) this sets the device in Mono mode during
power up.
•
•
Connect OUTPL and OUTNL to speaker just like normal BTL mode.
Analog input signal is applied to INPL and INNL.
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Device Functional Modes (continued)
Çꢀ!3156ꢁ2
Çꢀ!3126ꢁ2
Çꢀ!3128ꢁ2
Çꢀ!312ꢂꢁ2
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Figure 33. MONO Mode
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8 Applications and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
This section describes a 2.1 Master and Slave application. The Master is configured as stereo outputs and the
Slave is configured as mono PBTL output.
8.2 Typical Application
A 2.1 solution, U1 TPA3156D2 in Master mode 400 kHz, BTL, gain if 26 dB, power limit not implemented. U2 in
Slave, PBTL mode gain of 26 dB. Inputs are connected for differential inputs.
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Figure 34. TPA3156D2 Schematic
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Typical Application (continued)
8.2.1 Design Requriements
DESIGN PARAMETERS
Input voltage range PVCC
PWM output frequencies
Maximum output power
EXAMPLE VALUE
4.5 V to 26 V
300kHz, 400 kHz, 500 kHz, 600 kHz, 1 MHz or 1.2 MHz
2 × 70 W
8.2.2 Detailed Design Procedure
The TPA3156D2 devices are very flexible and easy to use Class D amplifier; therefore the design process is
straightforward. Before beginning the design, gather the following information regarding the audio system.
•
•
•
•
PVCC rail planned for the design
Speaker or load impedance
Maximum output power requirement
Desired PWM frequency
8.2.2.1 Select the PWM Frequency
Set the PWM frequency by using AM0, AM1 and AM2 pins.
8.2.2.2 Select the Amplifier Gain and Master/Slave Mode
In order to select the amplifier gain setting, the designer must determine the maximum power target and the
speaker impedance. Once these parameters have been determined, calculate the required output voltage swing
which delivers the maximum output power.
Choose the lowest analog gain setting that corresponds to produce an output voltage swing greater than the
required output swing for maximum power. The analog gain and master/slave mode can be set by selecting the
voltage divider resistors (R1 and R2) on the Gain/SLV pin.
8.2.2.3 Select Input Capacitance
Select the bulk capacitors at the PVCC inputs for proper voltage margin and adequate capacitance to support the
power requirements. In practice, with a well-designed power supply, two 100-μF, 50-V capacitors should be
sufficient. One capacitor should be placed near the PVCC inputs at each side of the device. PVCC capacitors
should be a low ESR type because they are being used in a high-speed switching application.
8.2.2.4 Select Decoupling Capacitors
Good quality decoupling capacitors must be added at each of the PVCC inputs to provide good reliability, good
audio performance, and to meet regulatory requirements. X5R or better ratings should be used in this
application. Consider temperature, ripple current, and voltage overshoots when selecting decoupling capacitors.
Also, these decoupling capacitors should be located near the PVCC and GND connections to the device in order
to minimize series inductances.
8.2.2.5 Select Bootstrap Capacitors
Each of the outputs require bootstrap capacitors to provide gate drive for the high-side output FETs. For this
design, use 0.22-μF, 25-V capacitors of X5R quality or better.
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8.2.3 Application Curves
10
160 Gain=26dB
Gain=26dB
PVCC=24V
5
TA=25èC
140
120
100
80
RL=2W
2
1
T
A=25èC
RL=2W
0.5
0.2
0.1
0.05
60
0.02
0.01
40
f= 20Hz
f= 1kHz
f= 6KHz
0.005
20
THD+N=1%
THD+N=10%
0.002
0.001
0
4
6
8
10 12 14 16 18 20 22 24 26
Supply Voltage (V)
0.01
0.1
1
10 20
100
Output Power (W)
D014
D03074
D0037
Figure 36. Maximum Output Power (PBTL) vs Supply
Voltage
Figure 35. Total Harmonic Distortion + Noise (PBTL) vs
Output Power
9 Power Supply Recommendations
The power supply requirements for the TPA3156D2 consist of one higher-voltage supply to power the output
stage of the speaker amplifier. Several on-chip regulators are included on the TPA3156D2 to generate the
voltages necessary for the internal circuitry of the audio path. The voltage regulators which have been integrated
are sized only to provide the current necessary to power the internal circuitry. The external pins are provided only
as a connection point for off-chip bypass capacitors to filter the supply. Connecting external circuitry to these
regulator outputs may result in reduced performance and damage to the device. The high voltage supply,
between 4.5 V and 26 V, supplies the analog circuitry (AVCC) and the power stage (PVCC). The AVCC supply
feeds internal LDO including GVDD. This LDO output are connected to external pins for filtering purposes, but
should not be connected to external circuits. GVDD LDO output have been sized to provide current necessary for
internal functions but not for external loading.
9.1 Power Supply Mode
The TPA3156D2 and devices support both single and dual power supply modes. Dual power supply mode is
benefit for low PVCC power consumption. For dual power supply mode application, when AVCC is supplied with
4.5V power, PVCC is recommended to be lower than 20V. When PVCC is supplied with power greater than 20V,
AVCC is recommended to be higher than 6V.
10 Layout
10.1 Layout Guidelines
The TPA3156D2 can be used with a small, inexpensive ferrite bead output filter for most applications. However,
because the class-D switching edges are fast, the layout of the printed circuit board must be planned carefully.
The following suggestions will help to meet EMC requirements.
•
Decoupling capacitors — The high-frequency decoupling capacitors should be placed as close to the PVCC
and AVCC terminals as possible. Large (100 μF or greater) bulk power supply decoupling capacitors should
be placed near the TPA3156D2 on the PVCC supplies. Local, high-frequency bypass capacitors should be
placed as close to the PVCC pins as possible. These caps can be connected to the IC GND pad directly for
an excellent ground connection. Consider adding a small, good quality low ESR ceramic capacitor between
220 pF and 1 nF and a larger mid-frequency cap of value between 100 nF and 1 µF also of good quality to
the PVCC connections at each end of the chip.
•
•
•
Keep the current loop from each of the outputs through the ferrite bead and the small filter cap and back to
GND as small and tight as possible. The size of this current loop determines its effectiveness as an antenna.
Grounding — The PVCC decoupling capacitors should connect to GND. All ground should be connected at
the IC GND, which should be used as a central ground connection or star ground for the TPA3156D2.
Output filter — The ferrite EMI filter (see Figure 31) should be placed as close to the output terminals as
possible for the best EMI performance. The LC filter should be placed close to the outputs. The capacitors
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Layout Guidelines (continued)
used in both the ferrite and LC filters should be grounded.
For an example layout, see the TPA3156D2 Evaluation Module (TPA3156D2EVM) User Guide (SLOU449). Both
the EVM user manual and the thermal pad application reports, SLMA002 and SLMA004, are available on the TI
Web site at http://www.ti.com.
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10.2 Layout Example
Figure 37. Layout Example Top
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Layout Example (continued)
Figure 38. Layout Example Bottom
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10.3 Heat Sink Used on the EVM
The heat sink used on the EVM is a 25-mm × 50-mm × 25-mm extruded aluminum heat sink with five fins (see
Figure 39 )
Figure 39. EVM Heat Sink
This size heat sink has shown to be sufficient for continuous output power. The crest factor of music and having
airflow lowers the requirement of heat sinking, and smaller types of heat sinks can be used.
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11 Device and Documentation Support
11.1 Documentation Support
11.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.3 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
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12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
TPA3156D2DAD
TPA3156D2DADR
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
-40 to 85
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
ACTIVE
HTSSOP
HTSSOP
DAD
32
32
46
RoHS & Green
NIPDAU
Level-3-260C-168 HR
Level-3-260C-168 HR
TPA
3156
D2
ACTIVE
DAD
2000 RoHS & Green
NIPDAU
-40 to 85
TPA
3156
D2
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPA3156D2DADR
HTSSOP DAD
32
2000
330.0
24.4
8.6
11.5
1.6
12.0
24.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
*All dimensions are nominal
Device
Package Type Package Drawing Pins
HTSSOP DAD 32
SPQ
Length (mm) Width (mm) Height (mm)
350.0 350.0 43.0
TPA3156D2DADR
2000
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
TUBE
*All dimensions are nominal
Device
Package Name Package Type
DAD HTSSOP
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
TPA3156D2DAD
32
46
530
11.89
3600
4.9
Pack Materials-Page 3
PACKAGE OUTLINE
TM
DAD0032A
PowerPAD TSSOP - 1.15 mm max height
S
C
A
L
E
1
.
6
0
0
PLASTIC SMALL OUTLINE
C
8.3
7.9
SEATING PLANE
TYP
A
0.1 C
PIN 1 ID AREA
30X 0.65
32
1
EXPOSED
THERMAL PAD
11.1
10.9
NOTE 3
4.36
3.26
2X
9.75
16
17
0.30
32X
0.19
4.11
3.31
0.1
C A
B
6.2
6.0
B
(0.15) TYP
0.25
SEE DETAIL A
1.15
1.00
GAGE PLANE
0.75
0.50
0.15
0.05
0 - 8
DETAIL A
TYPICAL
4222646/B 02/2020
PowerPAD is a trademark of Texas Instruments.
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. Reference JEDEC registration MO-153.
www.ti.com
EXAMPLE BOARD LAYOUT
DAD0032A
PowerPAD TMTSSOP - 1.15 mm max height
PLASTIC SMALL OUTLINE
32X (1.5)
SEE DETAILS
SYMM
1
32
32X (0.45)
30X (0.65)
SYMM
(R0.05) TYP
17
16
(7.5)
LAND PATTERN EXAMPLE
SCALE:8X
METAL UNDER
SOLDER MASK
SOLDER MASK
SOLDER MASK
OPENING
METAL
OPENING
0.05 MIN
AROUND
0.05 MAX
AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
NOT TO SCALE
4222646/B 02/2020
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
TM
DAD0032A
PowerPAD TSSOP - 1.15 mm max height
PLASTIC SMALL OUTLINE
32X (1.5)
SYMM
1
32
32X (0.45)
30X (0.65)
SYMM
(R0.05) TYP
16
17
(7.5)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:8X
4222646/B 02/2020
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.
www.ti.com
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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, regulatory or other requirements.
These resources are subject to change without notice. TI grants you permission to use these resources only for development of an
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TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE
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Copyright © 2022, Texas Instruments Incorporated
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