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TPA6133A2_15 [TI]

138-mW DirectPath Stereo Headphone Amplifier;
TPA6133A2_15
型号： TPA6133A2_15
厂家： TEXAS INSTRUMENTS    TEXAS INSTRUMENTS
描述：

138-mW DirectPath Stereo Headphone Amplifier
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TPA6133A2  
www.ti.com  
SLOS821 –JUNE 2013  
138-mW DIRECTPATH™ STEREO HEADPHONE AMPLIFIER  
Check for Samples: TPA6133A2  
1
FEATURES  
DESCRIPTION  
The TPA6133A2 is a stereo DirectPath™ headphone  
amplifier with GPIO control. The TPA6133A2 has  
minimal quiescent current consumption, with a typical  
IDD of 4.2 mA, making it optimal for portable  
applications. The GPIO control allows the device to  
be put in a low power shutdown mode.  
2
•
DirectPath™ Ground-Referenced Outputs  
–
–
–
–
Eliminates Output DC Blocking Capacitors  
Reduces Board Area  
Reduces Component Height and Cost  
Full Bass Response Without Attenuation  
The TPA6133A2 is a high fidelity amplifier with an  
SNR of 93 dB. A PSRR greater than 100 dB enables  
direct-to-battery connections without compromising  
the listening experience. The output noise of 12  
μVrms (typical A-weighted) provides a minimal noise  
background during periods of silence. Configurable  
differential inputs and high CMRR allow for maximum  
noise rejection in the noisy environment of a mobile  
device.  
•
•
Power Supply Voltage Range: 2.5 V to 5.5 V  
High Power Supply Rejection Ratio  
(>100 dB PSRR)  
•
Differential Inputs for Maximum Noise  
Rejection (69 dB CMRR)  
•
•
High-Impedance Outputs When Disabled  
Advanced Pop and Click Suppression  
Circuitry  
TPA6133A2 is available in a 4 by 4 mm QFN  
package.  
•
•
GPIO Control for Shutdown  
20 Pin, 4 mm x 4 mm QFN Package  
APPLICATIONS  
•
•
•
•
Mobile Phones  
Audio Headsets  
Notebook Computers  
High Fidelity Applications  
SIMPLIFIED APPLICATION DIAGRAM  
GPIO  
VBAT  
2.2KQ  
Audio Source  
TEST1 TEST2  
SD  
0.47uF  
0.47uF  
LEFT_OUTM  
LEFTINM  
LEFTINP  
HPLEFT  
LEFT_OUTP  
HPRIGHT  
0.47uF  
0.47uF  
RIGHT_OUTM  
RIGHT_OUTP  
RIGHTINM  
RIGHTINP  
GND  
GND  
CPP  
CPN  
CPVSS  
VDD  
VDD  
VBAT  
1uF  
1uF  
1uF  
1uF  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
2
DirectPath is a trademark of Texas Instruments.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
Copyright © 2013, Texas Instruments Incorporated  
TPA6133A2  
SLOS821 –JUNE 2013  
www.ti.com  
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam  
during storage or handling to prevent electrostatic damage to the MOS gates.  
FUNCTIONAL BLOCK DIAGRAM  
TEST2  
TEST1  
LEFTINM  
LEFTINP  
HPLEFT  
LEFT  
INPUT  
STAGE  
DEPOP  
RIGHTINM  
RIGHTINP  
HPRIGHT  
RIGHT  
CURRENT  
LIMIT  
THERMAL  
CPP  
SD  
CHARGE  
PUMP  
POWER  
MANAGEMENT  
SHUTDOWN  
CONTROL  
CPN  
CPVSS  
VDD  
GND  
VDD  
GND  
Headphone channels and the charge pump are activated by toggling the SD pin to logic 1. The charge pump  
generates a negative supply voltage for the output amplifiers. This allows a 0 V bias at the outputs, eliminating  
the need for bulky output capacitors. The thermal block detects faults and shuts down the device before damage  
occurs. The current limit block prevents the output current from getting high enough to damage the device. The  
De-Pop block eliminates audible pops during power-up, power-down, and amplifier enable and disable events.  
2
Copyright © 2013, Texas Instruments Incorporated  
Product Folder Links: TPA6133A2  
TPA6133A2  
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SLOS821 –JUNE 2013  
RJT PACKAGE  
(Top VIEW)  
20  
19  
18  
17  
16  
1
2
3
4
5
15  
14  
13  
12  
11  
LEFTINM  
LEFTINP  
GND  
CPVSS  
HPLEFT  
GND  
Top View  
RIGHTINP  
RIGHTINM  
VDD  
HPRIGHT  
6
7
8
9
10  
Top View QFN Package (RTJ)  
PIN FUNCTIONS  
PIN  
INPUT,  
OUTPUT,  
POWER  
DESCRIPTION  
NAME  
PIN QFN  
Charge pump voltage supply. VDD must be connected to the common VDD voltage  
supply. Decouple to GND (pin 19 ) with its own 1 μF capacitor.  
VDD  
20  
P
Charge pump ground. GND must be connected to common supply GND. It is  
recommended that this pin be decoupled to the VDD of the charge pump pin (pin 20 on  
the QFN).  
GND  
19  
P
Charge pump flying capacitor positive terminal. Connect one side of the flying capacitor  
to CPP.  
CPP  
18  
17  
1
P
P
I
Charge pump flying capacitor negative terminal. Connect one side of the flying  
capacitor to CPN.  
CPN  
Left channel negative differential input. Impedance must be matched to LEFTINP.  
Connect the left input to LEFTINM when using single-ended inputs.  
LEFTINM  
Left channel positive differential input. Impedance must be matched to LEFTINM. AC  
ground LEFTINP near signal source while maintaining matched impedance to  
LEFTINM when using single-ended inputs.  
LEFTINP  
2
I
Negative supply generated by the charge pump. Decouple to pin 19 or a GND plane.  
Use a 1 μF capacitor.  
CPVSS  
15, 16  
14  
P
O
I
HPLEFT  
RIGHTINM  
Headphone left channel output. Connect to left terminal of headphone jack.  
Right channel negative differential input. Impedance must be matched to RIGHTINP.  
Connect the right input to RIGHTINM when using single-ended inputs.  
5
Right channel positive differential input. Impedance must be matched to RIGHTINM.  
AC ground RIGHTINP near signal source while maintaining matched impedance to  
RIGHTINM when using single-ended inputs.  
RIGHTINP  
GND  
4
I
Analog ground. Must be connected to common supply GND. It is recommended that  
this pin be used to decouple VDD for analog. Use pin 13 to decouple pin 12 on the QFN  
package.  
3, 9, 10, 13  
P
Analog VDD. VDD must be connected to common VDD supply. Decouple with its own 1-  
μF capacitor to analog ground (pin 13).  
VDD  
SD  
12  
6
P
I
Shutdown. Active low logic. 5V tolerant input.  
Copyright © 2013, Texas Instruments Incorporated  
3
Product Folder Links: TPA6133A2  
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SLOS821 –JUNE 2013  
www.ti.com  
PIN FUNCTIONS (continued)  
PIN  
INPUT,  
OUTPUT,  
POWER  
DESCRIPTION  
NAME  
PIN QFN  
TEST2  
7
8
I
I
Factory test pins. Pull up to VDD supply. See Applications Diagram.  
Factory test pins. Pull up to VDD supply. See Applications Diagram.  
TEST1  
HPRIGHT  
11  
O
Headphone light channel output. Connect to the right terminal of the headphone jack.  
Solder the thermal pad on the bottom of the QFN package to the GND plane of the  
PCB. It is required for mechanical stability and will enhance thermal performance.  
Thermal pad  
Die Pad  
P
ABSOLUTE MAXIMUM RATINGS(1)  
over operating free-air temperature range, TA = 25°C (unless otherwise noted)  
MIN  
MAX  
UNIT  
Supply voltage, VDD  
–0.3  
6
V
CPVSS-0.2 V to minimum of  
(3.6 V, VDD+0.2 V)  
RIGHTINx, LEFTINx  
Input voltage  
SD, TEST1, TEST2  
Output continuous total power dissipation  
Operating free-air temperature range, TA  
Operating junction temperature range, TJ  
Storage temperature range, Tstg  
–0.3  
7
V
See Dissipation Rating Table  
–40  
–40  
–65  
85  
150  
150  
3
°C  
°C  
°C  
kV  
ESD Protection  
HBM  
Minimum Load Impedance  
12.8 Ω  
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings  
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating  
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.  
DISSIPATION RATINGS TABLE  
T
A ≤ 25°C  
DERATING  
TA = 70°C  
POWER RATING  
TA = 85°C  
POWER RATING  
PACKAGE  
POWER RATING  
FACTOR(1) (2)  
RTJ  
4100 mW  
41 mW/°C  
2250 mW  
1640 mW  
(1) Derating factor measured with JEDEC High K board: 1S2P - One signal layer and two plane layers.  
(2) See JEDEC Standard 51-3 for Low-K board, JEDEC Standard 51-7 for High-K board, and JEDEC  
Standard 51-12 for using package thermal information. Please see JEDEC document page for  
downloadable copies: http://www.jedec.org/download/default.cfm.  
AVAILABLE OPTIONS  
TA  
PACKAGED DEVICES(1)  
PART NUMBER  
SYMBOL  
–40°C to 85°C  
20-pin, 4 mm × 4 mm QFN  
TPA6133A2RTJ(2)  
SIZ  
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI  
Web site at www.ti.com.  
(2) The RTJ package is only available taped and reeled. To order, add the suffix “R” to the end of the part number for a reel of 3000, or add  
the suffix “T” to the end of the part number for a reel of 250 (that is, TPA6133A2RTJR).  
RECOMMENDED OPERATING CONDITIONS  
MIN  
2.5  
MAX  
UNIT  
V
Supply voltage, VDD  
5.5  
VIH  
VIL  
TA  
High-level input voltage  
Low-level input voltage  
Operating free-air temperature  
TEST1, TEST2, SD  
SD  
1.3  
V
0.35  
85  
V
–40  
°C  
4
Copyright © 2013, Texas Instruments Incorporated  
Product Folder Links: TPA6133A2  
TPA6133A2  
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SLOS821 –JUNE 2013  
ELECTRICAL CHARACTERISTICS  
TA = 25°C (unless otherwise noted)  
PARAMETER  
TEST CONDITIONS  
VDD = 2.5 V to 5.5 V, inputs grounded  
DC Power supply rejection ratio VDD = 2.5 V to 5.5 V, inputs grounded  
MIN  
TYP MAX UNIT  
|VOS  
PSRR  
CMRR Common mode rejection ratio  
|
Output offset voltage  
135 400  
μV  
dB  
dB  
–101  
–69  
-85  
VDD = 2.5 V to 5.5 V  
TEST1, TEST2  
1
10  
1
|IIH  
|
High-level input current  
Low-level input current  
Supply current  
VDD = 5.5 V, VI = VDD  
µA  
SD  
SD  
|IIL|  
IDD  
VDD = 5.5 V, VI = 0 V  
µA  
mA  
µA  
VDD = 2.5 V to 5.5 V, SD = VDD  
4.2  
6
Shutdown mode, VDD = 2.5V to 5.5 V, SD = 0 V  
0.08  
1
OPERATING CHARACTERISTICS  
VDD = 3.6 V , TA = 25°C, RL = 16 Ω (unless otherwise noted)  
PARAMETER  
TEST CONDITIONS  
MIN  
TYP  
63  
MAX UNIT  
VDD = 2.5V  
VDD = 3.6V  
VDD = 5V  
Stereo, Outputs out of phase,  
THD = 1%, f = 1 kHz, Gain = +4 dB  
PO  
Output power  
133  
142  
mW  
f = 100 Hz  
f = 1 kHz  
0.0096%  
0.007%  
0.0021%  
-94.3  
-92  
Total harmonic distortion  
plus noise  
THD+N  
kSVR  
PO = 35 mW  
f = 20 kHz  
200 mVpp ripple, f = 217 Hz  
200 mVpp ripple, f = 1 kHz  
200 mVpp ripple, f = 20 kHz  
SD = VDD  
-85  
dB  
Supply ripple rejection ratio  
-77.1  
1.597  
0.1  
Av  
Channel DC Gain  
Gain matching  
Slew rate  
V/V  
%
ΔAv  
0.4  
V/µs  
µVRMS  
Vn  
Noise output voltage  
VDD = 3.6V, A-weighted, Gain = +4 dB  
12  
Charge pump switching  
frequency  
fosc  
300  
381  
500  
kHz  
Start-up time from shutdown  
Differential input impedance  
Signal-to-noise ratio  
4.8  
36.6  
93  
ms  
kΩ  
dB  
°C  
°C  
SNR  
Po = 35 mW  
Threshold  
Hysteresis  
180  
35  
Thermal shutdown  
HW Shutdown HP output  
impedance  
ZO  
CO  
SD = 0 V, measured output to ground.  
112  
80  
Ω
Output capacitance  
pF  
Copyright © 2013, Texas Instruments Incorporated  
5
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Table of Graphs  
FIGURE  
Total harmonic distortion + noise  
Total harmonic distortion + noise  
Supply voltage rejection ratio  
Common mode rejection ratio  
Crosstalk  
versus Output power  
versus Frequency  
versus Frequency  
versus Frequency  
versus Frequency  
1–4  
5–12  
13-14  
15-16  
17-18  
TYPICAL CHARACTERISTICS  
C(PUMP, DECOUPLE, ,BYPASS, CPVSS) = 1 μF, CI = 2.2µF.  
All THD + N graphs taken with outputs out of phase (unless otherwise noted).  
TOTAL HARMONIC DISTORTION +  
TOTAL HARMONIC DISTORTION +  
TOTAL HARMONIC DISTORTION +  
NOISE  
vs  
NOISE  
vs  
NOISE  
vs  
OUTPUT POWER  
OUTPUT POWER  
OUTPUT POWER  
10  
1
10  
1
10  
1
VDD = 3.6V  
f = 1kHz  
RL = 16Ω  
Stereo  
VDD = 3.6V  
f = 1kHz  
RL = 32Ω  
Stereo  
VDD = 2.5V  
f = 1kHz  
RL = 16Ω  
Stereo  
0.1  
0.1  
0.1  
VDD = 2.5V  
VDD = 3.0V  
VDD = 3.6V  
VDD = 5.0V  
0.01  
0.001  
0.01  
0.001  
0.01  
0.001  
Out of Phase  
In Phase  
Out of Phase  
In Phase  
0.01  
0.1  
1
0.01  
0.1  
1
0.001  
0.01  
0.1  
1
Output Power (W)  
Output Power (W)  
Output Power (W)  
C007  
C007  
C006  
Figure 1.  
Figure 2.  
Figure 3.  
TOTAL HARMONIC DISTORTION +  
TOTAL HARMONIC DISTORTION +  
TOTAL HARMONIC DISTORTION +  
NOISE  
vs  
NOISE  
vs  
NOISE  
vs  
OUTPUT POWER  
FREQUENCY  
FREQUENCY  
10  
1
1
1
VDD = 2.5V  
RL = 16Ω  
VDD = 3.0V  
RL = 16Ω  
VDD = 2.5V  
f = 1kHz  
RL = 32Ω  
Stereo  
0.1  
0.1  
0.1  
0.01  
0.01  
VDD = 2.5V  
VDD = 3.0V  
VDD = 3.6V  
VDD = 5.0V  
0.01  
0.001  
Po = 1mW  
Po = 4mW  
Po = 20mW  
Po = 5mW  
Po = 20mW  
Po = 40mW  
0.001  
0.001  
0.001  
0.01  
0.1  
1
20  
200  
2k  
20k  
20  
200  
2k  
20k  
Output Power (W)  
Frequency (Hz)  
Frequency (Hz)  
C006  
C004  
C004  
Figure 4.  
Figure 5.  
Figure 6.  
6
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Product Folder Links: TPA6133A2  
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SLOS821 –JUNE 2013  
TOTAL HARMONIC DISTORTION +  
TOTAL HARMONIC DISTORTION +  
TOTAL HARMONIC DISTORTION +  
NOISE  
vs  
NOISE  
vs  
NOISE  
vs  
FREQUENCY  
FREQUENCY  
FREQUENCY  
1
1
1
VDD = 3.6V  
VDD = 5.0V  
VDD = 2.5V  
RL = 16Ω  
RL = 16Ω  
RL = 32Ω  
0.1  
0.1  
0.1  
0.01  
0.01  
0.01  
Po = 5mW  
Po = 5mW  
Po = 50mW  
Po = 80mW  
Po = 1mW  
Po = 4mW  
Po = 20mW  
Po = 35mW  
Po = 70mW  
0.001  
0.001  
0.001  
20  
200  
2k  
20k  
20  
200  
2k  
20k  
20  
200  
2k  
20k  
Frequency (Hz)  
Frequency (Hz)  
Frequency (Hz)  
C004  
C004  
C004  
Figure 7.  
Figure 8.  
Figure 9.  
TOTAL HARMONIC DISTORTION +  
TOTAL HARMONIC DISTORTION +  
TOTAL HARMONIC DISTORTION +  
NOISE  
vs  
NOISE  
vs  
NOISE  
vs  
FREQUENCY  
FREQUENCY  
FREQUENCY  
1
1
1
VDD = 3.0V  
RL = 32Ω  
VDD = 3.6V  
RL = 32Ω  
VDD = 5.0V  
RL = 32Ω  
0.1  
0.1  
0.1  
0.01  
0.01  
0.01  
Po = 5mW  
Po = 20mW  
Po = 40mW  
Po = 5mW  
Po = 35mW  
Po = 70mW  
Po = 5mW  
Po = 50mW  
Po = 80mW  
0.001  
0.001  
0.001  
20  
200  
2k  
20k  
20  
200  
2k  
20k  
20  
200  
2k  
20k  
Frequency (Hz)  
Frequency (Hz)  
Frequency (Hz)  
C004  
C004  
C004  
Figure 10.  
Figure 11.  
Figure 12.  
SUPPLY VOLTAGE REJECTION  
SUPPLY VOLTAGE REJECTION  
RATIO  
vs  
RATIO  
vs  
COMMON MODE REJECTION RATIO  
vs  
FREQUENCY  
FREQUENCY  
FREQUENCY  
0
-20  
-40  
-60  
-80  
0
-20  
-40  
-60  
-80  
0
-10  
-20  
-30  
-40  
-50  
-60  
-70  
-80  
VDD = 2.5V  
VDD = 2.5V  
VDD = 2.5V  
Vo = 0.1Vrms  
Vrip = 0.1VPK  
Vrip = 0.1VPK  
RL = 16Ω  
Ci = 1µF  
Stereo  
RL = 32Ω  
Ci = 1µF  
Stereo  
RL = 16Ω  
Ci = 1µF  
VDD = 3.6V  
VDD = 5.0V  
VDD = 3.6V  
VDD = 5.0V  
VDD = 3.6V  
Stereo  
VDD = 5.0V  
-100  
-100  
-120  
-120  
20  
200  
2k  
20k  
20  
200  
2k  
20k  
20  
200  
2k  
20k  
Frequency (Hz)  
Frequency (Hz)  
Frequency (Hz)  
C010  
C010  
C010  
Figure 13.  
Figure 14.  
Figure 15.  
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COMMON MODE REJECTION RATIO  
CROSSTALK  
vs  
FREQUENCY  
CROSSTALK  
vs  
FREQUENCY  
vs  
FREQUENCY  
0
-10  
-20  
-30  
-40  
-50  
-60  
-70  
-80  
0
-10  
-20  
-30  
-40  
-50  
-60  
-70  
-80  
0
-10  
-20  
-30  
-40  
-50  
-60  
-70  
-80  
VDD = 2.5V  
VDD = 3.6V  
VDD = 5.0V  
VDD = 2.5V  
VDD = 3.6V  
VDD = 5.0V  
VDD = 2.5V  
VDD = 3.6V  
VDD = 5.0V  
Vo = 0.1Vrms  
RL = 32Ω  
Ci = 1µF  
Vo = 1Vrms  
RL = 16Ω  
Ci = 1µF  
Stereo  
Vo = 1Vrms  
RL = 32Ω  
Ci = 1µF  
Stereo  
Stereo  
20  
200  
2k  
20k  
20  
200  
2k  
20k  
20  
200  
2k  
20k  
Frequency (Hz)  
Frequency (Hz)  
Frequency (Hz)  
C010  
C010  
C010  
Figure 16.  
Figure 17.  
Figure 18.  
8
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APPLICATION INFORMATION  
SIMPLIFIED APPLICATIONS CIRCUIT  
1uF  
1uF  
20  
19  
18  
17  
16  
1
2
3
4
5
15  
14  
13  
12  
11  
LEFTINM  
LEFTINP  
GND  
CPVSS  
HPLEFT  
GND  
0.47uF  
0.47uF  
1uF  
Top View  
RIGHTINP  
RIGHTINM  
VDD  
0.47uF  
0.47uF  
1uF  
HPRIGHT  
6
7
8
9
10  
2.2KQ  
Headphone Amplifiers  
Single-supply headphone amplifiers typically require dc-blocking capacitors. The capacitors are required because  
most headphone amplifiers have a dc bias on the outputs pin. If the dc bias is not removed, the output signal is  
severely clipped, and large amounts of dc current rush through the headphones, potentially damaging them. The  
top drawing in Figure 19 illustrates the conventional headphone amplifier connection to the headphone jack and  
output signal.  
DC blocking capacitors are often large in value. The headphone speakers (typical resistive values of 16 Ω or 32  
Ω) combine with the dc blocking capacitors to form a high-pass filter. Equation 1 shows the relationship between  
the load impedance (RL), the capacitor (CO), and the cutoff frequency (fC).  
1
f +  
c
2pR C  
L
O
(1)  
CO can be determined using Equation 2, where the load impedance and the cutoff frequency are known.  
1
C
+
O
2pR f  
c
L
(2)  
If fc is low, the capacitor must then have a large value because the load resistance is small. Large capacitance  
values require large package sizes. Large package sizes consume PCB area, stand high above the PCB,  
increase cost of assembly, and can reduce the fidelity of the audio output signal.  
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Two different headphone amplifier applications are available that allow for the removal of the output dc blocking  
capacitors. The Capless amplifier architecture is implemented in the same manner as the conventional amplifier  
with the exception of the headphone jack shield pin. This amplifier provides a reference voltage, which is  
connected to the headphone jack shield pin. This is the voltage on which the audio output signals are centered.  
This voltage reference is half of the amplifier power supply to allow symmetrical swing of the output voltages. Do  
not connect the shield to any GND reference or large currents will result. The scenario can happen if, for  
example, an accessory other than a floating GND headphone is plugged into the headphone connector. See the  
second block diagram and waveform in Figure 19.  
Conventional  
VDD  
CO  
VOUT  
GND  
VDD/2  
CO  
Capless  
VDD  
VOUT  
GND  
VBIAS  
VBIAS  
DirectPathTM  
VDD  
GND  
VSS  
Figure 19. Amplifier Applications  
The DirectPath™ amplifier architecture operates from a single supply but makes use of an internal charge pump  
to provide a negative voltage rail. Combining the user provided positive rail and the negative rail generated by  
the IC, the device operates in what is effectively a split supply mode. The output voltages are now centered at  
zero volts with the capability to swing to the positive rail or negative rail. The DirectPath™ amplifier requires no  
output dc blocking capacitors, and does not place any voltage on the sleeve. The bottom block diagram and  
waveform of Figure 19 illustrate the ground-referenced headphone architecture. This is the architecture of the  
TPA6133A2.  
Input-Blocking Capacitors  
DC input-blocking capacitors block the dc portion of the audio source, and allow the inputs to properly bias.  
Maximum performance is achieved when the inputs of the TPA6133A2 are properly biased. Performance issues  
such as pop are optimized with proper input capacitors.  
The dc input-blocking capacitors may be removed provided the inputs are connected differentially and within the  
input common mode range of the amplifier, the audio signal does not exceed ±3 V, and pop performance is  
sufficient.  
10  
Copyright © 2013, Texas Instruments Incorporated  
Product Folder Links: TPA6133A2  
 
TPA6133A2  
www.ti.com  
SLOS821 –JUNE 2013  
CIN is a theoretical capacitor used for mathematical calculations only. Its value is the series combination of the dc  
input-blocking capacitors, C(DCINPUT-BLOCKING). Use Equation 3 to determine the value of C(DCINPUT-BLOCKING). For  
example, if CIN is equal to 0.22 μF, then C(DCINPUT-BLOCKING) is equal to about 0.47 μF.  
1
2
C
C
=
(DCINPUT-BLOCKING)  
IN  
(3)  
The two C(DCINPUT-BLOCKING) capacitors form a high-pass filter with the input impedance of the TPA6133A2. Use  
Equation 3 to calculate CIN, then calculate the cutoff frequency using CIN and the differential input impedance of  
the TPA6133A2, RIN, using Equation 4. Note that the differential input impedance changes with gain. See for  
input impedance values. The frequency and/or capacitance can be determined when one of the two values are  
given.  
1
1
fc  
+
C
+
or  
IN  
IN  
2p R  
C
2p fc  
R
IN IN  
IN IN  
(4)  
If a high pass filter with a -3 dB point of no more than 20 Hz is desired over all gain settings, the minimum  
impedance would be used in the above equation. shows this to be 37 kΩ. The capacitor value by the above  
equation would be 0.215 μF. However, this is CIN, and the desired value is for C(DCINPUT-BLOCKING). Multiplying CIN  
by 2 yields 0.43 μF, which is close to the standard capacitor value of 0.47 μF. Place 0.47 μF capacitors at each  
input terminal of the TPA6133A2 to complete the filter.  
Charge Pump Flying Capacitor and CPVSS Capacitor  
The charge pump flying capacitor serves to transfer charge during the generation of the negative supply voltage.  
The CPVSS capacitor must be at least equal to the flying capacitor in order to allow maximum charge transfer.  
Low ESR capacitors are an ideal selection, and a value of 1 µF is typical.  
Decoupling Capacitors  
The TPA6133A2 is a DirectPath™ headphone amplifier that requires adequate power supply decoupling to  
ensure that the noise and total harmonic distortion (THD) are low. Use good low equivalent-series-resistance  
(ESR) ceramic capacitors, typically 1.0 µF. Find the smallest package possible, and place as close as possible to  
the device VDD lead. Placing the decoupling capacitors close to the TPA6133A2 is important for the performance  
of the amplifier. Use a 10 μF or greater capacitor near the TPA6133A2 to filter lower frequency noise signals.  
The high PSRR of the TPA6133A2 will make the 10 μF capacitor unnecessary in most applications.  
Layout Recommendations  
Exposed Pad On TPA6133A2RTJ Package  
Solder the exposed metal pad on the TPA6133A2RTJ QFN package to the a pad on the PCB. The pad on the  
PCB may be grounded or may be allowed to float (not be connected to ground or power). If the pad is grounded,  
it must be connected to the same ground as the GND pins (3, 9, 10, 13, and 19). See the layout and mechanical  
drawings at the end of the datasheet for proper sizing. Soldering the thermal pad improves mechanical reliability,  
improves grounding of the device, and enhances thermal conductivity of the package.  
GND Connections  
The GND pin for charge pump should be decoupled to the charge pump VDD pin, and the GND pin adjacent to  
the Analog VDD pin should be separately decoupled to each other.  
Modes of Operation  
The TPA6133A2 supports two modes of operation. When the SD pin is driven to logic 0, the device is in low  
power mode where the charge pump is powered down, the headphone channel is disabled and the outputs are  
weakly pulled to ground. When the SD pin is driven to logic 1, the device enters an active mode with charge  
pump powered up and headphone channel enabled with channel gain of +4dB. The transition from inactive to  
active and active to inactive states is done softly to avoid audible artifacts.  
Copyright © 2013, Texas Instruments Incorporated  
11  
Product Folder Links: TPA6133A2  
 
 
PACKAGE OPTION ADDENDUM  
www.ti.com  
9-Aug-2013  
PACKAGING INFORMATION  
Orderable Device  
TPA6133A2RTJR  
TPA6133A2RTJT  
Status Package Type Package Pins Package  
Eco Plan Lead/Ball Finish  
MSL Peak Temp  
Op Temp (°C)  
-40 to 85  
Device Marking  
Samples  
Drawing  
Qty  
(1)  
(2)  
(3)  
(4/5)  
ACTIVE  
QFN  
QFN  
RTJ  
20  
20  
3000  
Green (RoHS  
& no Sb/Br)  
CU NIPDAU  
CU NIPDAU  
Level-2-260C-1 YEAR  
SIZ  
SIZ  
ACTIVE  
RTJ  
250  
Green (RoHS  
& no Sb/Br)  
Level-2-260C-1 YEAR  
-40 to 85  
(1) The marketing status values are defined as follows:  
ACTIVE: Product device recommended for new designs.  
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.  
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.  
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.  
OBSOLETE: TI has discontinued the production of the device.  
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability  
information and additional product content details.  
TBD: The Pb-Free/Green conversion plan has not been defined.  
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that  
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.  
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between  
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.  
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight  
in homogeneous material)  
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.  
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.  
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation  
of the previous line and the two combined represent the entire Device Marking for that device.  
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information  
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and  
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.  
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.  
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.  
Addendum-Page 1  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
12-Aug-2013  
TAPE AND REEL INFORMATION  
*All dimensions are nominal  
Device  
Package Package Pins  
Type Drawing  
SPQ  
Reel  
Reel  
A0  
B0  
K0  
P1  
W
Pin1  
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant  
(mm) W1 (mm)  
TPA6133A2RTJR  
TPA6133A2RTJT  
QFN  
QFN  
RTJ  
RTJ  
20  
20  
3000  
250  
330.0  
180.0  
12.4  
12.4  
4.25  
4.25  
4.25  
4.25  
1.15  
1.15  
8.0  
8.0  
12.0  
12.0  
Q2  
Q2  
Pack Materials-Page 1  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
12-Aug-2013  
*All dimensions are nominal  
Device  
Package Type Package Drawing Pins  
SPQ  
Length (mm) Width (mm) Height (mm)  
TPA6133A2RTJR  
TPA6133A2RTJT  
QFN  
QFN  
RTJ  
RTJ  
20  
20  
3000  
250  
367.0  
210.0  
367.0  
185.0  
35.0  
35.0  
Pack Materials-Page 2  
IMPORTANT NOTICE  
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