TPA6141A2YFFT [TI]
CLASS-G DIRECTPATH STEREO HEADPHONE AMPLIFIER; G类DirectPath立体声耳机放大器
| 型号： | TPA6141A2YFFT |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | CLASS-G DIRECTPATH STEREO HEADPHONE AMPLIFIER |
| 文件： | 总23页 (文件大小：970K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPA6141A2
www.ti.com.................................................................................................................................................... SLOS634A –MARCH 2009–REVISED AUGUST 2009
CLASS-G DIRECTPATH™ STEREO HEADPHONE AMPLIFIER
Check for Samples: TPA6141A2
1
FEATURES
DESCRIPTION
2
•
TI Class-G Technology Significantly Prolongs
Battery Life and Music Playback Time
The TPA6141A2 (also known as TPA6141) is a
Class-G DirectPath™ stereo headphone amplifier
with selectable gain. Class-G technology maximizes
battery life by adjusting the voltage supplies of the
headphone amplifier based on the audio signal level.
At low level audio signals, the internal supply voltage
is reduced to minimize power dissipation.
–
–
0.6 mA / Ch Quiescent Current
50% to 80% Lower Quiescent Current Than
Ground-Referenced Class-AB Headphone
Amplifiers
DirectPathTM
DC-blocking capacitors.
technology
eliminates
external
•
DirectPathTM Technology Eliminates Large
Output DC-Blocking Capacitors
–
–
Outputs Biased at 0 V
The device features fully differential inputs with an
integrated low pass filter to reduce system noise
pickup between the audio source and the headphone
amplifier and to reduce DAC out–of–band noise. The
high power supply noise rejection performance and
differential architecture provides increased RF noise
immunity. For single–ended input signals, connect
INL+ and INR+ to ground.
Improves Low Frequency Audio Fidelity
•
•
Active Click and Pop Suppression
Fully Differential Inputs Reduce System Noise
–
Also Configurable as Single-Ended Inputs
•
•
•
•
•
•
•
•
•
SGND Pin Eliminates Ground Loop Noise
Wide Power Supply Range: 2.5 V to 5.5 V
100 dB Power Supply Noise Rejection
Built-in Input Low Pass Filter
The device operates from a 2.5 V to 5.5 V supply
voltage. Class-G operation keeps total supply current
below 5.0 mA while delivering 500 μW per channel
into 32 Ω. Shutdown mode reduces the supply
current to less than 3 μA and is activated through the
EN pin.
Gain Settings: 0 dB and 6dB
Short-Circuit Current Limiter
Thermal-Overload Protection
The device has built-in pop suppression circuitry to
completely eliminate disturbing pop noise during
turn-on and turn-off. The amplifier outputs have
short-circuit and thermal-overload protection along
with ±8 kV HBM ESD protection, simplifying end
equipment compliance to the IEC 61000-4-2 ESD
standard.
±8 kV HBM ESD Protected Outputs
0,4 mm Pitch, 1,6 mm × 1,6 mm 16-Bump
WCSP (YFF) Package
APPLICATIONS
•
•
•
•
Cellular Phones / Music Phones
Smart Phones
Portable Media / MP3 Players
Portable CD / DVD Players
1 mF
OUTR+
OUTR-
OUTL+
OUTL-
INR+
INR-
INL+
OUTR
OUTL
CODEC
TPA6141A2
INL-
SGND
AGND
EN
EN
GAIN
Vbat
GAIN
AVDD
SW
HPVSS
CPN
2.2 mH
2.2 mF
HPVDD
2.2 mF
CPP
1 mF
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
Class-G DirectPath, DirectPath are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2009, Texas Instruments Incorporated
TPA6141A2
SLOS634A –MARCH 2009–REVISED AUGUST 2009.................................................................................................................................................... www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
FUNCTIONAL BLOCK DIAGRAM
AVDD
Ramp
Generator
SW
+
–
Gate
Drivers
Comparator
2.2 mH
AGND
Compensation
Network
+
–
HPVDD
2.2 mF
Audio
Level
Detector
AVDD
Optimizer
Thermal
Protection
HPVDD
–
INL-
+
OUTL
INL+
HPVSS
Short-Circuit
Protection
HPVDD
–
INR-
+
OUTR
INR+
HPVSS
HPVDD
HPVDD
CPP
CPN
EN
Charge
Pump
1 mF
Click-and-Pop
Suppression
Interface
GAIN
SGND
HPVSS
2.2 mF
2
Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s): TPA6141A2
TPA6141A2
www.ti.com.................................................................................................................................................... SLOS634A –MARCH 2009–REVISED AUGUST 2009
DEVICE PINOUT
WCSP PACKAGE
(TOP VIEW)
A1
SW
B1
A2
AVDD
B2
A3
OUTL
B3
A4
INL-
B4
AGND
C1
CPP
C2
HPVDD
C3
INL+
C4
CPN
D1
HPVSS SGND
INR+
D2
D3
D4
INR-
EN
GAIN
OUTR
TERMINAL FUNCTIONS
TERMINAL
INPUT /
OUTPUT /
POWER
BALL
DESCRIPTION
NAME
WCSP
(I/O/P)
INL–
A4
I
Inverting left input for differential signals. Connect to left input signal through 1 μF capacitor for
single-ended input applications.
INL+
INR+
INR-
B4
C4
D4
I
I
I
Non-inverting left input for differential signals. Connect to ground through 1 μF capacitor for
single-ended input applications.
Non-inverting right input for differential signals. Connect to ground through 1 μF capacitor for
single-ended input applications.
Inverting right input for differential signals. Connect to right input signal through 1 μF capacitor for
single-ended input applications.
SGND
EN
C3
D1
D2
I
I
I
Sense ground. Connect to shield terminal of headphone jack.
Amplifier enable. Connect to logic low to shutdown; connect to logic high to activate.
GAIN
Amplifier gain select pin. Connect to logic low to select a gain of 0 dB; connect to logic high to select
a gain of 6 dB.
OUTL
OUTR
CPP
A3
D3
B2
C1
A1
A2
B3
B1
C2
O
O
P
P
P
P
P
P
P
Left headphone amplifier output. Connect to left terminal of headphone jack.
Right headphone amplifier output. Connect to right terminal of headphone jack.
Charge pump positive flying cap. Connect to positive side of capacitor between CPP and CPN.
Charge pump negative flying cap. Connect to negative side of capacitor between CPP and CPN.
Buck converter switching node.
CPN
SW
AVDD
HPVDD
AGND
HPVSS
Primary power supply for device.
Power supply for headphone amplifier (DC/DC output node).
Main Ground for headphone amplifiers, DC/DC converter, and charge pump.
Charge pump output. Connect 2.2 μF capacitor to GND.
ORDERING INFORMATION
PACKAGED DEVICES
(1)
(2)
TA
–40°C to 85°C
PART NUMBER
SYMBOL
ASBI
16-ball, WCSP
TPA6141A2YFFR
TPA6141A2YFFT
16-ball, WCSP
ASBI
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
Web site at www.ti.com.
(2) YFF packages are only available taped and reeled. The suffix “R” indicates a reel of 3000, the suffix “T” indicates a reel of 250.
Copyright © 2009, Texas Instruments Incorporated
3
Product Folder Link(s): TPA6141A2
TPA6141A2
SLOS634A –MARCH 2009–REVISED AUGUST 2009.................................................................................................................................................... www.ti.com
ABSOLUTE MAXIMUM RATINGS(1)
over operating free-air temperature range, TA = 25°C (unless otherwise noted)
VALUE / UNIT
Supply voltage, AVDD
–0.3 V to 6.0 V
–0.3 V to 2.0 V
–0.3 V to HPVDD +0.3 V
–0.3 V to AVDD
See Dissipation Rating Table
–40°C to 85°C
–40°C to 150°C
–65°C to 85°C
12 Ω
Amplifier supply voltage, HPVDD
Input voltage (INR+, INR-, INL+, INL-)
Control input voltage (EN, GAIN)
Output continuous total power dissipation
Operating free-air temperature range
Operating junction temperature range
Storage temperature range
VI
TA
TJ
Tstg
RL
Minimum load resistance
OUTL, OUTR, SGND
All other pins
8 kV
ESD Protection – HBM
2 kV
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.
DISSIPATION RATINGS TABLE(1) (2)
OPERATING
FACTOR
ABOVE TA = 25°C
TA < 25°C
POWER RATING
TA = 70°C
POWER RATING
TA = 85°C
POWER RATING
PACKAGE
YFF (WCSP)
1.25 W
10 mW/°C
800 mW
650 mW
(1) Derating factor measured with JEDEC High K board: 1S0P – One signal layer and zero plane layers.
(2) See JEDEC Standard 51-3 for Low-K board, JEDEC Standard 51-7 for High-K board, and JEDEC
Standard 51-12 for using package thermal information. See JEDEC document page for downloadable
copies: http://www.jedec.org/download/default.cfm.
RECOMMENDED OPERATING CONDITIONS
MIN
2.5
MAX
UNIT
VDD Supply voltage, AVDD
5.5
V
V
V
VIH
VIL
High-level input voltage
Low-level input voltage
EN, GAIN
EN, GAIN
1.3
0.6
3.6
Voltage applied to Output; OUTR, OUTL (when EN = logic low)
Operating free-air temperature
–0.3
–40
TA
+85
°C
4
Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s): TPA6141A2
TPA6141A2
www.ti.com.................................................................................................................................................... SLOS634A –MARCH 2009–REVISED AUGUST 2009
ELECTRICAL CHARACTERISTICS
TA = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
AVDD = 2.5 V to 5.5 V, inputs grounded, GAIN = 0 dB
HPVDD = 1.3 V to 1.8 V, GAIN = 0 dB
MIN
TYP
105
68
MAX UNIT
PSRR
Power supply rejection ratio
90
dB
dB
CMRR Common mode rejection ratio
|IIH
|
High-level input current
Low-level input current
Shutdown current
AVDD = 2.5 V to 5.5 V, VI = AVDD
AVDD = 2.5 V to 5.5 V, VI = 0 V
EN = 0 V, AVDD = 2.5 V to 5.5 V
EN, GAIN
EN, GAIN
1
1
3
µA
µA
μA
|IIL|
ISD
1
AVDD = 3.6 V HPVDD = 1.3 V, Amplifiers active, no load, no
input signal
1.2
2.0
AVDD = 3.6 V, POUT = 100 μW into 32 Ω(1), fAUD = 1 kHz
AVDD = 3.6 V, POUT = 500 μW into 32 Ω(1), fAUD = 1 kHz
AVDD = 3.6 V, POUT = 1 mW into 32 Ω(1), fAUD = 1 kHz
2.5
4.0
6.8
IDD
Total supply current
mA
(1) Per channel output power assuming a 10 dB crest factor
OPERATING CHARACTERISTICS
AVDD = 3.6 V , TA = 25°C, GAIN = 0 dB, RL = 32 Ω (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
AVDD = 2.7 V, THD = 1%, f = 1 kHz
Output power(1) (Outputs in Phase) AVDD = 2.7 V, THD = 10%, f = 1 kHz
26
32
25
PO
mW
AVDD = 2.7 V, THD = 1%, f = 1 kHz, RL = 16Ω
PO = 10 mW into 16 Ω, f = 1 kHz
PO = 20 mW into 32 Ω, f = 1 kHz
200 mVpp ripple, f = 217 Hz
200 mVpp ripple, f = 4 kHz
GAIN = logic low
0.02%
0.01%
100
90
Total harmonic distortion plus
noise(2)
THD+N
kSVR
AV
80
AC-Power supply rejection ratio
dB
0
dB
dB
Closed–loop voltage gain (OUT /
IN–)
GAIN = logic high
6
ΔAV
VOS
EN
Gain matching
Between left and right channels
AVDD = 2.5 V to 5.5 V, inputs grounded
A-weighted
1%
0
Output offset voltage
Noise output voltage
0.5
0.5
mV
µVRMS
kHz
5.3
600
315
1260
5
fBUCK
Buck converter switching frequency PO = 0.5 mW, f = 1 kHz
PO = 0.5 mW, f = 1 kHz
Charge pump switching frequency
fPUMP
kHz
PO = 15 mW, f = 1 kHz
Start-up time from shutdown
ms
kΩ
kΩ
dB
RIN,SE
RIN,DF
SNR
Single Ended Input impedance
Differential input impedance
Signal-to-noise ratio
Gain = 6 dB, per input node
Gain = 6 dB, per input node
VOUT = 1 VRMS, GAIN = 6 dB, no load
Threshold
13.2
26.4
105
165
35
Thermal shutdown
°C
Hysteresis
ZO,SD
Output impedance in shutdown
EN = logic low, DC value
8
kΩ
Input to Output attenuation in
shutdown
EN = logic low, f = 1 kHz, VOUT = 1 VRMS
PO = 15 mW, f = 1 kHz
90
dB
Crosstalk
–80
dB
V
VCM
Input common-mode voltage range
0
1.4
(1) Per channel output power
(2) A-weighted
Copyright © 2009, Texas Instruments Incorporated
5
Product Folder Link(s): TPA6141A2
TPA6141A2
SLOS634A –MARCH 2009–REVISED AUGUST 2009.................................................................................................................................................... www.ti.com
TYPICAL CHARACTERISTICS
TA = 25°C, AVDD (VDD) = 3.6 V, GAIN = 0 dB, CHPVDD = CHPVSS = 2.2 μF, CINPUT = CFLYING = 1 μF, Outputs out of phase
QUIESCENT SUPPLY CURRENT
TOTAL HARMONIC DISTORTION + NOISE
vs
vs
SUPPLY VOLTAGE
OUTPUT POWER
10
9
8
7
6
5
4
3
2
1
0
100
f = 1 kHz
R
L
= 16 Ω
V
DD
= 3.6 V
10
1
In Phase
Out of Phase
0.1
0.01
2.5
3.0
3.5
4.0
4.5
5.0
5.5
0.0001
0.001
0.01
0.1
V
DD
− Supply Voltage − V
P
O
− Output Power − W
G001
G002
Figure 1.
Figure 2.
TOTAL HARMONIC DISTORTION + NOISE
TOTAL HARMONIC DISTORTION + NOISE
vs
vs
OUTPUT POWER
OUTPUT POWER
100
100
f = 1 kHz
= 16 Ω
f = 1 kHz
R = 32 Ω
L
R
L
V
= 2.5 V
= 3.6 V
DD
V
= 2.5 V
DD
10
1
10
1
V
DD
V
= 3.6 V
DD
V
DD
= 5 V
V
DD
= 5 V
0.1
0.01
0.1
0.01
0.0001
0.001
0.01
0.1
0.0001
0.001
0.01
0.1
P
O
− Output Power − W
P
O
− Output Power − W
G003
G004
Figure 3.
Figure 4.
TOTAL HARMONIC DISTORTION + NOISE
TOTAL HARMONIC DISTORTION + NOISE
vs
vs
FREQUENCY
FREQUENCY
1
1
R
L
= 16 Ω
R
L
= 32 Ω
V
DD
= 2.5 V
V
DD
= 2.5 V
P
O
= 1 mW
P
= 1 mW
O
per Channel
per Channel
0.1
0.1
P
O
= 10 mW
per Channel
0.01
0.01
P
O
= 10 mW
per Channel
P
O
= 4 mW
per Channel
P
O
= 4 mW
per Channel
0.001
0.001
20
100
1k
10k 20k
20
100
1k
10k 20k
f − Frequency − Hz
f − Frequency − Hz
G005
G006
Figure 5.
Figure 6.
6
Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s): TPA6141A2
TPA6141A2
www.ti.com.................................................................................................................................................... SLOS634A –MARCH 2009–REVISED AUGUST 2009
TYPICAL CHARACTERISTICS (continued)
TA = 25°C, AVDD (VDD) = 3.6 V, GAIN = 0 dB, CHPVDD = CHPVSS = 2.2 μF, CINPUT = CFLYING = 1 μF, Outputs out of phase
TOTAL HARMONIC DISTORTION + NOISE
TOTAL HARMONIC DISTORTION + NOISE
vs
vs
FREQUENCY
FREQUENCY
1
1
R
= 16 Ω
= 3.6 V
R
= 32 Ω
= 3.6 V
L
L
P
= 1 mW
O
V
DD
V
DD
P
O
= 1 mW
per Channel
per Channel
P
= 10 mW
O
0.1
0.1
P
O
= 10 mW
per Channel
per Channel
0.01
0.01
P
= 15 mW
O
P
= 20 mW
O
per Channel
per Channel
0.001
0.001
20
100
1k
10k 20k
20
100
1k
10k 20k
f − Frequency − Hz
f − Frequency − Hz
G007
G008
Figure 7.
Figure 8.
TOTAL HARMONIC DISTORTION + NOISE
TOTAL HARMONIC DISTORTION + NOISE
vs
vs
FREQUENCY
FREQUENCY
1
1
R
= 16 Ω
= 5 V
R
= 32 Ω
= 5 V
L
L
P
= 1 mW
O
V
DD
V
DD
P
O
= 1 mW
per Channel
per Channel
P
= 10 mW
0.1
0.1
O
P
= 10 mW
O
per Channel
per Channel
0.01
0.01
P
O
= 15 mW
per Channel
P
O
= 20 mW
per Channel
0.001
0.001
20
100
1k
10k 20k
20
100
1k
10k 20k
f − Frequency − Hz
f − Frequency − Hz
G009
G010
Figure 9.
Figure 10.
OUTPUT POWER PER CHANNEL
OUTPUT POWER PER CHANNEL
vs
vs
SUPPLY VOLTAGE
SUPPLY VOLTAGE
60
50
40
30
20
10
0
60
50
40
30
20
10
0
R
= 16 Ω
R = 32 Ω
L
In Phase
L
In Phase
THD+N = 10%
THD+N = 1%
THD+N = 10%
THD+N = 1%
2.5
3.0
3.5
4.0
4.5
5.0
5.5
2.5
3.0
3.5
4.0
4.5
5.0
5.5
V
DD
− Supply Voltage − V
V
DD
− Supply Voltage − V
G011
G012
Figure 11.
Figure 12.
Copyright © 2009, Texas Instruments Incorporated
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SLOS634A –MARCH 2009–REVISED AUGUST 2009.................................................................................................................................................... www.ti.com
TYPICAL CHARACTERISTICS (continued)
TA = 25°C, AVDD (VDD) = 3.6 V, GAIN = 0 dB, CHPVDD = CHPVSS = 2.2 μF, CINPUT = CFLYING = 1 μF, Outputs out of phase
OUTPUT POWER
vs
OUTPUT POWER
vs
LOAD RESISTANCE
LOAD RESISTANCE
50
45
40
35
30
25
20
15
10
5
50
45
40
35
30
25
20
15
10
5
THD+N = 1%
Out of Phase
THD+N = 1%
In Phase
V
= 5 V
DD
V
= 5 V
DD
V
DD
= 3.6 V
V
DD
= 2.5 V
V
DD
= 3.6 V
V
DD
= 2.5 V
0
0
10
100
− Load Resistance − Ω
1k
10
100
R − Load Resistance − Ω
L
1k
R
L
G013
G014
Figure 13.
Figure 14.
SUPPLY RIPPLE REJECTION RATIO
SUPPLY RIPPLE REJECTION RATIO
vs
vs
FREQUENCY
FREQUENCY
0
−20
0
−20
R
= 32 Ω
R
= 16 Ω
L
L
Supply Ripple = 0.2 V Sine Wave
Supply Ripple = 0.2 V Sine Wave
pp
pp
−40
−40
−60
−60
V
DD
= 2.5 V
V
DD
= 3.6 V
V
DD
= 2.5 V
V
DD
= 5 V
V
DD
= 3.6 V
V
DD
= 5 V
−80
−80
−100
−120
−100
−120
20
100
1k
10k 20k
20
100
1k
10k 20k
f − Frequency − Hz
f − Frequency − Hz
G016
G015
Figure 15.
Figure 16.
SUPPLY CURRENT
vs
SUPPLY CURRENT
vs
TOTAL OUTPUT POWER
TOTAL OUTPUT POWER
100
10
1
100
10
1
f = 1 kHz
= 16 Ω
f = 1 kHz
R
L
R
L
= 32 Ω
V
DD
= 3.6 V
V
DD
= 3.6 V
V
= 2.5 V
DD
V
= 2.5 V
DD
V
DD
= 5 V
10
V
DD
= 5 V
10
0.001
0.01
0.1
1
100
0.001
0.01
0.1
1
100
P
O
− Total Output Power − mW
P
O
− Total Output Power − mW
G017
G018
Figure 17.
Figure 18.
8
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Product Folder Link(s): TPA6141A2
TPA6141A2
www.ti.com.................................................................................................................................................... SLOS634A –MARCH 2009–REVISED AUGUST 2009
TYPICAL CHARACTERISTICS (continued)
TA = 25°C, AVDD (VDD) = 3.6 V, GAIN = 0 dB, CHPVDD = CHPVSS = 2.2 μF, CINPUT = CFLYING = 1 μF, Outputs out of phase
TOTAL POWER DISSIPATION
vs
OUTPUT VOLTAGE
vs
TOTAL OUTPUT POWER
SUPPLY VOLTAGE
1k
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
f = 1 kHz
THD+N = 1%
R
L
= 1 kΩ
R
L
= 600 Ω
100
R
= 16Ω
L
10
R
= 32Ω
R
L
= 32 Ω
L
R
L
= 16 Ω
1
0.01
2.5
3.0
3.5
4.0
4.5
5.0
5.5
0.1
1
10
100
P
− Total Output Power − mW
V
DD
− Supply Voltage − V
O
G019
G020
Figure 19.
Figure 20.
CROSSTALK
vs
OUTPUT AMPLITUDE
vs
FREQUENCY
FREQUENCY
0
−20
0
−30
R
P
= 16 Ω
= 15 mW
Single Channel
= 16 Ω
L
R
O
L
−40
−60
−60
−90
−80
−120
−150
−100
20
100
1k
10k 20k
0
5000
10000
15000
20000
f − Frequency − Hz
f − Frequency − Hz
G021
G022
Figure 21.
Figure 22.
STARTUP WAVEFORM
SHUTDOWN WAVEFORM
vs
vs
TIME
TIME
5
4
3
2
5
4
RL = 16 Ω
RL = 16 Ω
VIN = 0.5 Vrms @ 20 kHz
VIN = 0.5 Vrms @ 1 kHz
EN pin
Enable
3
2
1
0
1
V
OUT
V
OUT
0
-1
-1
0
1
2
3
4
5
6
7
8
9
10
0
50
100
150
200
t - Time - ms
t - Time - ms
Figure 23.
Figure 24.
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APPLICATION INFORMATION
APPLICATION CIRCUIT
1 mF
OUTR+
OUTR-
OUTL+
OUTL-
INR+
INR-
INL+
INL-
OUTR
OUTL
CODEC
TPA6141A2
SGND
AGND
EN
EN
GAIN
GAIN
AVDD
Vbat
SW
HPVSS
CPN
2.2 mH
HPVDD
2.2 mF
CPP
2.2 mF
1 mF
Figure 25. Typical Application Configuration with Differential Input Signals
1 mF
INR+
OUTR
OUTL
INR-
INL+
INL-
OUTR
OUTL
CODEC
TPA6141A2
SGND
AGND
EN
EN
GAIN
GAIN
AVDD
Vbat
SW
HPVSS
CPN
2.2 mH
HPVDD
2.2 mF
CPP
2.2 mF
1 mF
Figure 26. Typical Application Configuration with Single-Ended Input Signals
10
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CLASS-G HEADPHONE AMPLIFIER
Class-G amplifiers use adaptive supply rails. The TPA6141A2 includes a built-in step-down converter to create
the headphone amplifier positive supply voltage, HPVDD. A charge pump inverts HPVDD and creates the
amplifier negative supply voltage, HPVSS. This allows the headphone amplifier output to be centered at 0 V.
When audio signal amplitude is low, the step-down converter generates a low HPVDD voltage. This minimizes
TPA6141A2 power consumption while playing low noise, high fidelity audio. If audio amplitude increases, either
due to louder music or a transient peak, then the step-down converter generates a higher HPVDD voltage. The
HPVDD rise rate is faster than the audio peak rise time. This prevents audio distortion or clipping. Audio quality
and noise floor are not affected by HPVDD.
This adaptive HPVDD minimizes TPA6141A2 supply current while avoiding clipping and distortion. Because
normal listening levels are below 200 mVRMS, HPVDD is most often at its lowest voltage. Thus, the TPA6141A2
has higher efficiency than traditional Class-AB headphone amplifiers.
The following equations compare a Class-AB amplifier to a Class-G amplifier. Both operate with identical battery
voltage, load impedance, and output voltage swing. For this study case, we assume a normal listening level of
200 mVRMS with no DirectPath™ in order to simplify the calculations.
•
•
•
•
•
•
•
•
•
PSUP: Supplied power
VSUP: Supply voltage
ISUP: Supply current
VREG: DC/DC converter output voltage
PREG: DC/DC converter output power
VLOAD: Voltage across the load
RLOAD: Load impedance
PLOAD: Power dissipated at the load
ILOAD: Current supplied to the load
Given an amplifier driving 200 mVRMS into a 32 Ω load, the output current to the load is:
VLOAD 200 mVRMS
ILOAD
=
=
= 6.25 mA
RLOAD
32 W
(1)
(2)
(3)
Assuming a quiescent current of 1 mA (IDDQ) the total current supplied to the amplifier is:
ISUP = ILOAD + IDDQ = 7.25 mA
The total power supplied to a Class-AB amplifier is then calculated as:
PSUP = VSUP ´ISUP = 4.2 V ´ 7.25 mA = 30.45 mW
For a Class-G amplifier where the voltage rails are generated by a switching DC/DC converter, the supplied
power will depend on the DC/DC converter output voltage and efficiency. Assuming the DC/DC converter output
voltage is 1.3 V:
PREG = VREG ´ISUP = 1.3 V ´ 7.25 mA = 9.425 mW
(4)
The total supplied power will be the DC/DC converter output power divided by the efficiency of the DC/DC
converter. Assuming 90% step-down efficiency, total power supplied to the Class-G amplifier is:
PREG
PSUP
=
= 11.09 mW
90%
(5)
Class-G headphone amplifiers achieve much higher efficiency than equivalent Class-AB amplifiers.
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SLOS634A –MARCH 2009–REVISED AUGUST 2009.................................................................................................................................................... www.ti.com
INDUCTOR SELECTION
The TPA6141A2 requires one inductor for its DC/DC converter. The following table lists recommended inductors.
Inductors not shown on this table can be used if they have similar performance characteristics.
When selecting an inductor observe the following rules:
•
•
•
Lower DCR increases DC/DC converter efficiency.
The minimum working inductance should never be below 1 μH.
Include temperature and aging derating factors into the inductor value calculations.
MANUFACTURER
PART NUMBER
MDT2012-CH2R2A
TOKO
LQM21PN2R2MC0D
LQH2MCN2R2M02L
BRL2012T2R2M
Murata
Taiyo Yuden
BRC1608T2R2M
GAIN CONTROL
The TPA6141A2 has two gain settings which are controlled with the GAIN pin. The following table gives an
overview of the gain function.
GAIN VOLTAGE
≤0.6 V
AMPLIFIER GAIN
0 dB
6 dB
≥1.3 V
GROUND SENSE FUNCTION
The ground sense pin, SGND, reduces ground-loop noise when the audio output jack is connected to a different
ground reference than codec and amplifier ground. Always connect the SGND pin to the headphone jack. This
reduces output offset voltage and eliminates turn-on pop. Figure 27 shows how to connect SGND when an FM
radio antenna function is implemented on the headphone wire. The nH coil and capacitor separate the RF signal
from the audio GND signal. In this case, SGND is used to eliminate the offset voltage that is generated from the
audio signal current and the RF coil low-frequency impedance.
The voltage difference between SGND and AGND cannot be greater than ±300 mV. The amplifier performance
degrades if the voltage difference between SGND and AGND is greater than ±300 mV.
CODEC
TPA6141A2
OUTR+
OUTR-
OUTL+
OUTL-
INR+
INR-
OUTR
OUTL
INL+
INL-
SGND
AGND
EN
EN
GAIN
Vbat
GAIN
AVDD
SW
HPVSS
CPN
2.2 mH
2.2 mF
HPVDD
CPP
FM Tuner
2.2 mF
nH coil
1mF
Figure 27. Sense Ground
12
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TPA6141A2
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HEADPHONE AMPLIFIERS
Single-supply headphone amplifiers typically require dc-blocking capacitors to remove dc bias from their output
voltage. The top drawing in Figure 28 illustrates this connection. If dc bias is not removed, large dc current will
flow through the headphones which wastes power, clips the output signal, and potentially damages the
headphones.
These dc-blocking capacitors are often large in value and size. Headphone speakers have a typical resistance
between 16 Ω and 32 Ω. This combination creates a high-pass filter with a cutoff frequency as shown in
Equation 6, where RL is the load impedance, CO is the dc-block capacitor, and fC is the cutoff frequency.
1
fC =
2pRLCO
(6)
For a given high-pass cutoff frequency and load impedance, the required dc-blocking capacitor is found as:
1
CO
=
2pfCRL
(7)
Reducing fC improves low frequency fidelity and requires a larger dc-blocking capacitor. To achieve a 20 Hz
cutoff with 16 Ω headphones, CO must be at least 500 μF. Large capacitor values require large packages,
consuming PCB area, increasing height, and increasing cost of assembly. During start-up or shutdown the
dc-blocking capacitor has to be charged or discharged. This causes an audible pop on start-up and power-down.
Large dc-blocking capacitors also reduce audio output signal fidelity.
Two different headphone amplifier architectures are available to eliminate the need for dc-blocking capacitors.
The capless amplifier architecture provides a reference voltage to the headphone connector shield pin as shown
in the middle drawing of Figure 28. The audio output signals are centered around this reference voltage, which is
typically half of the supply voltage to allow symmetrical output voltage swing.
When using a capless amplifier do not connect the headphone jack shield to any ground reference or large
currents will result. This makes capless amplifiers ineffective for plugging non-headphone accessories into the
headphone connector. capless amplifiers are useful only with floating GND headphones.
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Conventional
C
O
V
V
OUT
OUT
C
O
GND
Capless
V
V
OUT
OUT
GND
V
BIAS
DirectPath™
V
DD
V
GND
OUT
V
SS
Figure 28. Amplifier Applications
The DirectPath™ amplifier architecture operates from a single supply voltage and uses an internal charge pump
to generate a negative supply rail for the headphone amplifier. The output voltages are centered around 0 V and
are capable of positive and negative voltage swings as shown in the bottom drawing of Figure 28. DirectPath
amplifiers require no output dc-blocking capacitors. The headphone connector shield pin connects to ground and
will interface with headphones and non-headphone accessories. The TPA6141A2 is a DirectPath amplifier.
ELIMINATING TURN-ON POP AND POWER SUPPLY SEQUENCING
The TPA6141A2 has excellent noise and turn-on / turn-off pop performance. It uses an integrated click-and-pop
suppression circuit to allow fast start-up and shutdown without generating any voltage transients at the output
pins. Typical start-up time from shutdown is 5 ms.
DirectPath technology keeps the output dc voltage at 0 V even when the amplifier is powered up. The DirectPath
technology together with the active pop-and-click suppression circuit eliminates audible transients during start up
and shutdown.
Use input coupling capacitors to ensure inaudible turn-on pop. Activate the TPA6141A2 after all audio sources
have been activated and their output voltages have settled. On power-down, deactivate the TPA6141A2 before
deactivating the audio input source. The EN pin controls device shutdown: Set to EN to VIL or lower to deactivate
the TPA6141A2; set to VIH or higher to activate. Refer to the Recommended Operating Conditions table for the
VIL and VIH values.
14
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RF AND POWER SUPPLY NOISE IMMUNITY
The TPA6141A2 employs a new differential amplifier architecture to achieve high power supply noise rejection
and RF noise rejection. RF and power supply noise are common in modern electronics. Although RF frequencies
are much higher than the 20 kHz audio band, signal modulation often falls in-band. This, in turn, modulates the
supply voltage, allowing a coupling path into the audio amplifier. A common example is the 217 Hz GSM
frame-rate buzz often heard from an active speaker when a cell phone is placed nearby during a phone call.
The TPA6141A2 has excellent rejection of power supply and RF noise, preventing audio signal degradation.
INPUT COUPLING CAPACITORS
Input coupling capacitors block any dc bias from the audio source and ensure maximum dynamic range. Input
coupling capacitors also minimize TPA6141A2 turn-on pop to an inaudible level.
The input capacitors are in series with TPA6141A2 internal input resistors, creating a high-pass filter. Equation 8
calculates the high-pass filter corner frequency. The input impedance, RIN, is dependent on device gain. Larger
input capacitors decrease the corner frequency. See the Operating Characteristics table for input impedance
values.
1
fC =
2pRINCIN
(8)
For a given high-pass cutoff frequency, the minimum input coupling capacitor is found as:
1
CIN
=
2pfCRIN
(9)
Example: Design for a 20 Hz corner frequency with a TPA6141A2 gain of +6 dB. The Operating Characteristics
table gives RIN as 13.2 kΩ. Equation 9 shows the input coupling capacitors must be at least 0.6 μF to achieve a
20 Hz high-pass corner frequency. Choose a 0.68 μF standard value capacitor for each TPA6141A2 input (X5R
material or better is required for best performance).
Input capacitors can be removed provided the TPA6141A2 inputs are driven differentially with less than ±1 VRMS
and the common-mode voltage is within the input common-mode range of the amplifier. Without input capacitors
turn-on pop performance may be degraded and should be evaluated in the system.
CHARGE PUMP FLYING CAPACITOR AND HPVSS CAPACITOR
The TPA6141A2 uses a built-in charge pump to generate a negative voltage supply for the headphone
amplifiers. The charge pump flying capacitor connects between CPP and CPN. It transfers charge to generate
the negative supply voltage. The HPVSS capacitor must be at least equal in value to the flying capacitor to allow
maximum charge transfer. Use low equivalent-series-resistance (ESR) ceramic capacitors (X5R material or
better is required for best performance) to maximize charge pump efficiency. Typical values are 1 μF to 2.2 μF
for the HPVSS and flying capacitors. Although values down to 0.47 μF can be used, total harmonic distortion
(THD) will increase.
OPERATION WITH DACs AND CODECs AND INPUT RF NOISE REJECTION
When using amplifiers with CODECs and DACs, sometimes there is an increase in the output noise floor from
the audio amplifier. This occurs when the output out–of–band noise of the CODEC/DAC folds back into the audio
frequency due to the limited gain bandwidth product of the audio amplifier. Single–ended RF noise can also fold
back into the audio band thus degrading the audio signal even further
The TPA6141A2 has a built-in low-pass filter to reduce CODEC/DAC out–of–band noise and RF noise, that
could fold back into the audio frequency.
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SLOS634A –MARCH 2009–REVISED AUGUST 2009.................................................................................................................................................... www.ti.com
POWER SUPPLY AND HPVDD DECOUPLING CAPACITORS AND CONNECTIONS
The TPA6141A2 DirectPath headphone amplifier requires adequate power supply decoupling to ensure that
output noise and total harmonic distortion (THD) remain low. Use good low equivalent-series-resistance (ESR)
ceramic capacitors (X5R material or better is required for best performance). Place a 2.2 μF capacitor within
5 mm of the AVDD pin. Reducing the distance between the decoupling capacitor and AVDD minimizes parasitic
inductance and resistance, improving TPA6141A2 supply rejection performance. Use 0402 or smaller size
capacitors if possible. Ensure that the ground connection of each of the capacitors has a minimum length return
path to the device. Failure to properly decouple the TPA6141A2 may degrade audio or EMC performance.
For additional supply rejection, connect an additional 10 μF or higher value capacitor between AVDD and
ground. This will help filter lower frequency power supply noise. The high power supply rejection ratio (PSRR) of
the TPA6141A2 makes the 10 μF capacitor unnecessary in most applications.
Connect a 2.2 μF capacitor between HPVDD and ground. This ensures the amplifier internal bias supply remains
stable and maximizes headphone amplifier performance.
DO NOT connect HPVDD directly to AVDD or an external supply voltage. The
voltage at HPVDD is generated internally. Connecting HPVDD to an external
voltage can damage the device.
LAYOUT RECOMMENDATIONS
GND CONNECTIONS
The SGND pin is an input reference and must be connected to the headphone ground connector pin. This
ensures no turn-on pop and minimizes output offset voltage. Do not connect more than ±0.3 V to SGND.
AGND is a power ground. Connect supply decoupling capacitors for AVDD, HPVDD, and HPVSS to AGND.
BOARD LAYOUT
In making the pad size for the WCSP balls, it is recommended that the layout use non-solder-mask defined
(NSMD) land. With this method, the solder mask opening is made larger than the desired land area, and the
opening size is defined by the copper pad width. Figure 29 and Table 1 shows the appropriate diameters for a
WCSP layout.
16
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TPA6141A2
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Copper
Trace Width
Solder
Pad Width
Solder Mask
Opening
Solder Mask
Thickness
Copper Trace
Thickness
Figure 29. Land Pattern Dimensions
Table 1. Land Pattern Dimensions(1) (2) (3) (4)
(5)
(6) (7)
SOLDER PAD
DEFINITIONS
SOLDER MASK
OPENING
COPPER
THICKNESS
STENCIL
OPENING
STENCIL
THICKNESS
COPPER PAD
Non-solder-mask
defined (NSMD)
275 μm × 275 μm Sq.
(rounded corners)
230 μm (+0.0, –25 μm) 310 μm (+0.0, –25 μm)
1 oz max (32 μm)
100 μm thick
(1) Circuit traces from NSMD defined PWB lands should be 75 μm to 100 μm wide in the exposed area inside the solder mask opening.
Wider trace widths reduce device stand off and impact reliability.
(2) Best reliability results are achieved when the PWB laminate glass transition temperature is above the operating the range of the
intended application
(3) Recommend solder paste is Type 3 or Type 4.
(4) For a PWB using a Ni/Au surface finish, the gold thickness should be less 0,5 mm to avoid a reduction in thermal fatigue performance.
(5) Solder mask thickness should be less than 20 μm on top of the copper circuit pattern
(6) Best solder stencil performance is achieved using laser cut stencils with electro polishing. Use of chemically etched stencils results in
inferior solder paste volume control.
(7) Trace routing away from WCSP device should be balanced in X and Y directions to avoid unintentional component movement due to
solder wetting forces.
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TRACE WIDTH
Recommended trace width at the solder balls is 75 μm to 100 μm to prevent solder wicking onto wider PCB
traces. For high current pins (VDD, HPVDD, HPVSS, CPP, CPN, OUTL, and OUTR) of the TPA6141A2, use 100
μm trace widths at the solder balls and at least 500 μm PCB traces to ensure proper performance and output
power for the device. For the remaining signals of the TPA6141A2, use 75 μm to 100 μm trace widths at the
solder balls. The audio input pins (INL–, INL+, INR– and INR+) must run side-by-side to maximize
common-mode noise cancellation.
Package Dimensions
D
E
Max = 1590µm
Min = 1530µm
Max = 1590µm
Min = 1530µm
18
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Product Folder Link(s): TPA6141A2
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
PACKAGING INFORMATION
Orderable Device
TPA6141A2YFFR
TPA6141A2YFFT
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
-40 to 85
Top-Side Markings
Samples
Drawing
Qty
(1)
(2)
(3)
(4)
ACTIVE
DSBGA
DSBGA
YFF
16
16
3000
Green (RoHS
& no Sb/Br)
SNAGCU
SNAGCU
Level-1-260C-UNLIM
ASBI
ASBI
ACTIVE
YFF
250
Green (RoHS
& no Sb/Br)
Level-1-260C-UNLIM
-40 to 85
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
28-Sep-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPA6141A2YFFR
TPA6141A2YFFR
TPA6141A2YFFT
TPA6141A2YFFT
DSBGA
DSBGA
DSBGA
DSBGA
YFF
YFF
YFF
YFF
16
16
16
16
3000
3000
250
180.0
180.0
180.0
180.0
8.4
8.4
8.4
8.4
1.71
1.71
1.71
1.71
1.71
1.71
1.71
1.71
0.81
0.81
0.81
0.81
4.0
4.0
4.0
4.0
8.0
8.0
8.0
8.0
Q1
Q1
Q1
Q1
250
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
28-Sep-2013
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPA6141A2YFFR
TPA6141A2YFFR
TPA6141A2YFFT
TPA6141A2YFFT
DSBGA
DSBGA
DSBGA
DSBGA
YFF
YFF
YFF
YFF
16
16
16
16
3000
3000
250
182.0
220.0
220.0
182.0
182.0
220.0
220.0
182.0
17.0
34.0
34.0
17.0
250
Pack Materials-Page 2
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