TPA6203A1NMBR [TI]
1.25-W MONO FULLY DIFFERENTIAL AUDIO POWER AMPLIFIER;
| 型号： | TPA6203A1NMBR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 1.25-W MONO FULLY DIFFERENTIAL AUDIO POWER AMPLIFIER 放大器 功率放大器 |
| 文件： | 总36页 (文件大小：2292K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPA6203A1
GQV, ZQV
DRB
DGN
www.ti.com .......................................................................................................................................................... SLOS364F–MARCH 2002–REVISED JUNE 2008
1.25-W MONO FULLY DIFFERENTIAL AUDIO POWER AMPLIFIER
1
FEATURES
APPLICATIONS
•
Designed for Wireless or Cellular Handsets
and PDAs
2
•
1.25 W Into 8 Ω From a 5-V Supply at
THD = 1% (Typical)
•
•
•
Low Supply Current: 1.7 mA Typical
Shutdown Control < 10 µA
DESCRIPTION
The TPA6203A1 is a 1.25-W mono fully differential
amplifier designed to drive a speaker with at least
8-Ω impedance while consuming less than 37 mm2
(ZQV package option) total printed-circuit board
(PCB) area in most applications. This device operates
from 2.5 V to 5.5 V, drawing only 1.7 mA of quiescent
supply current. The TPA6203A1 is available in the
space-saving 2 mm x 2 mm MicroStar Junior™ BGA
package, and the space saving 3 mm x 3 mm QFN
(DRB) package.
Only Five External Components
–
Improved PSRR (90 dB) and Wide Supply
Voltage (2.5 V to 5.5 V) for Direct Battery
Operation
–
–
–
Fully Differential Design Reduces RF
Rectification
Improved CMRR Eliminates Two Input
Coupling Capacitors
C(BYPASS) Is Optional Due to Fully
Differential Design and High PSRR
Features like 85-dB PSRR from 90 Hz to 5 kHz,
improved RF-rectification immunity, and small PCB
area makes the TPA6203A1 ideal for wireless
handsets. A fast start-up time of 4 µs with minimal
pop makes the TPA6203A1 ideal for PDA
applications.
•
Avaliable in a 2 mm x 2 mm MicroStar
Junior ™ BGA Package (GQV, ZQV)
•
•
Available in 3 mm x 3 mm QFN Package (DRB)
Available in an 8-Pin PowerPAD™ MSOP
(DGN)
APPLICATION CIRCUIT
Actual Solution Size
V
DD
R
F
To Battery
R
F
C
s
R
I
-
IN-
C
V
_
+
O+
S
(1)
C
B
In From
DAC
5,25 mm
R
I
V
O-
+
IN+
R
I
R
I
R
F
GND
SHUTDOWN
Bias
Circuitry
R
F
6,9 mm
C BYPASS
(
)
(Optional)
Applies to the GQV/ZQV Packages Only
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
Junior, PowerPAD, MicroStar Junior are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2002–2008, Texas Instruments Incorporated
TPA6203A1
SLOS364F–MARCH 2002–REVISED JUNE 2008.......................................................................................................................................................... www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION
PACKAGED DEVICES(1)(2)(3)
MicroStar Junior™
(GQV)
MicroStar Junior™
(ZQV)
QFN
(DRB)
MSOP
(DGN)
Device
TPA6203A1GQVR
AADI
TPA6203A1ZQVR
AAEI
TPA6203A1DRB
AAJI
TPA6203A1DGN
AAII
Symbolization
(1) The GQV is the standard MicroStar Junior package. The ZQV is a lead-free option and is qualified for 260° lead-free assembly.
(2) The GQV and ZQV packages are only available taped and reeled. The suffix R designates taped and reeled parts.
(3) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted(1)
UNIT
Supply voltage, VDD
-0.3 V to 6 V
-0.3 V to VDD + 0.3 V
See Dissipation Rating Table
-40°C to 85°C
Input voltage, VI
INx and SHUTDOWN pins
Continuous total power dissipation
Operating free-air temperature, TA
Junction temperature, TJ
Storage temperature, Tstg
-40°C to 125°C
-65°C to 150°C
260°C
ZQV, DRB, DGN
GQV
Lead temperature 1,6 mm (1/16 Inch) from case for 10 seconds
235°C
(1) Stresses beyond those listed under "absolute maximum ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
MIN
2.5
2
TYP
MAX UNIT
Supply voltage, VDD
5.5
V
V
High-level input voltage, VIH
Low-level input voltage, VIL
Common-mode input voltage, VIC
Operating free-air temperature, TA
Load impedance, ZL
SHUTDOWN
SHUTDOWN
0.8
VDD-0.8
85
V
VDD = 2.5 V, 5.5 V, CMRR ≤ -60 dB
0.5
-40
6.4
V
°C
Ω
8
DISSIPATION RATINGS
T
A ≤ 25°C
TA = 70°C
POWER RATING
TA = 85°C
POWER RATING
PACKAGE
DERATING FACTOR
POWER RATING
GQV, ZQV
DRB
885 mW
8.8 mW/°C
486 mW
354 mW
2.7 W
21.8 mW/°C
1.7 W
1.4 W
2
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Product Folder Link(s): TPA6203A1
TPA6203A1
www.ti.com .......................................................................................................................................................... SLOS364F–MARCH 2002–REVISED JUNE 2008
ELECTRICAL CHARACTERISTICS
TA = 25°C, Gain = 1 V/V
PARAMETER
TEST CONDITIONS
VI = 0 V, VDD = 2.5 V to 5.5 V
MIN
TYP MAX
UNIT
mV
Output offset voltage (measured
differentially)
|VOO
|
9
PSRR
Power supply rejection ratio
VDD = 2.5 V to 5.5 V
-90
-70
-62
-70
-65
-55
dB
VDD = 3.6 V to 5.5 V, VIC = 0.5 V to VDD-0.8
VDD = 2.5 V, VIC = 0.5 V to 1.7 V
CMRR Common-mode rejection ratio
dB
VDD = 5.5 V
VDD = 3.6 V
VDD = 2.5 V
VDD = 5.5 V
VDD = 3.6 V
VDD = 2.5 V
0.30 0.46
0.22
RL = 8 Ω, VIN+ = VDD
VIN- = 0 V or VIN+ = 0 V, VIN- = VDD
,
VOL
Low-level output voltage
High-level output voltage
V
0.19 0.26
5.12
4.8
2.1
RL = 8 Ω, VIN+ = VDD
,
VOH
3.28
V
VIN- = 0 V or VIN+ = 0 V, VIN- = VDD
2.24
|IIH
|
High-level input current
Low-level input current
Supply current
VDD = 5.5 V, VI = 5.8 V
VDD = 5.5 V, VI = -0.3 V
1.2
µA
µA
mA
µA
|IIL|
1.2
IDD
VDD = 2.5 V to 5.5 V, No load, SHUTDOWN = 2 V
1.7
2
IDD(SD)
Supply current in shutdown mode SHUTDOWN = 0.8 V, VDD = 2.5 V to 5.5 V, No load
0.01
0.9
OPERATING CHARACTERISTICS
TA = 25°C, Gain = 1 V/V, RL = 8 Ω
PARAMETER
TEST CONDITIONS
VDD = 5 V
MIN
TYP
1.25
MAX UNIT
PO
Output power
THD + N = 1%, f = 1 kHz
VDD = 3.6 V
VDD = 2.5 V
0.63
W
0.3
VDD = 5 V, PO = 1 W, f = 1 kHz
0.06%
0.07%
0.08%
Total harmonic distortion
plus noise
THD+N
VDD = 3.6 V, PO = 0.5 W, f = 1 kHz
VDD = 2.5 V, PO = 200 mW, f = 1 kHz
C(BYPASS) = 0.47 °F,
VDD = 3.6 V to 5.5 V,
Inputs ac-grounded with CI = 2 µF
f = 217 Hz to 2 kHz,
VRIPPLE = 200 mVPP
-87
-82
C(BYPASS) = 0.47 µF,
Supply ripple rejection ratio VDD = 2.5 V to 3.6 V,
Inputs ac-grounded with CI = 2 µF
f = 217 Hz to 2 kHz,
VRIPPLE = 200 mVPP
kSVR
dB
C(BYPASS) = 0.47 µF,
VDD = 2.5 V to 5.5 V,
Inputs ac-grounded with CI = 2 µF
f = 40 Hz to 20 kHz,
VRIPPLE = 200 mVPP
≤-74
SNR
Vn
Signal-to-noise ratio
Output voltage noise
VDD = 5 V, PO= 1 W
104
17
dB
No weighting
A weighting
f = 20 Hz to 20 kHz
µVRMS
13
VDD = 2.5 V to 5.5 V,
resistor tolerance = 0.1%,
gain = 4V/V, VICM = 200 mVPP
f = 20 Hz to 1 kHz
≤-85
Common-mode rejection
ratio
CMRR
dB
f = 20 Hz to 20 kHz
≤-74
ZI
Input impedance
2
MΩ
ZO
Output impedance
Shutdown attenuation
Shutdown mode
>10k
f = 20 Hz to 20 kHz, RF = RI = 20 kΩ
-80
dB
Copyright © 2002–2008, Texas Instruments Incorporated
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SLOS364F–MARCH 2002–REVISED JUNE 2008.......................................................................................................................................................... www.ti.com
MicroStar Junior™ (GQV or ZQV) PACKAGE
(TOP VIEW)
GND
1 2
3
A
B
C
V
V
V
DD
O+
O-
SHUTDOWN
BYPASS
IN-
IN+
(SIDE VIEW)
8-PIN QFN (DRB) PACKAGE
(TOP VIEW)
1
2
3
4
8
7
6
5
SHUTDOWN
BYPASS
IN+
V
O-
GND
V
DD
IN-
V
O+
8-PIN MSOP (DGN) PACKAGE
(TOP VIEW)
V
8
SHUTDOWN
BYPASS
IN+
1
O-
GND
7
6
5
2
3
4
V
DD
IN-
V
O+
Terminal Functions
TERMINAL
GQV
I/O
DESCRIPTION
DRB,
DGN
NAME
BYPASS
GND
IN-
C1
B2
C3
C2
2
7
4
3
1
6
5
8
I
I
Mid-supply voltage. Adding a bypass capacitor improves PSRR.
High-current ground
I
Negative differential input
IN+
I
Positive differential input
SHUTDOWN
B1
A3
B3
A1
I
Shutdown terminal (active low logic)
Supply voltage terminal
VDD
VO+
VO-
I
O
O
Positive BTL output
Negative BTL output
Connect to ground. Thermal pad must be soldered down in all applications to properly secure device
on the PCB.
Thermal Pad
4
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Product Folder Link(s): TPA6203A1
TPA6203A1
www.ti.com .......................................................................................................................................................... SLOS364F–MARCH 2002–REVISED JUNE 2008
TYPICAL CHARACTERISTICS
Table of Graphs
FIGURE
vs Supply voltage
vs Load resistance
vs Output power
1
PO
PD
Output power
2, 3
Power dissipation
4, 5
Maximum ambient temperature
vs Power dissipation
vs Output power
6
7, 8
Total harmonic distortion + noise
vs Frequency
9, 10, 11, 12
vs Common-mode input voltage
vs Frequency
13
Supply voltage rejection ratio
Supply voltage rejection ratio
GSM Power supply rejection
GSM Power supply rejection
14, 15, 16, 17
vs Common-mode input voltage
vs Time
18
19
20
21
22
23
24
25
26
27
vs Frequency
vs Frequency
CMRR Common-mode rejection ratio
vs Common-mode input voltage
vs Frequency
Closed loop gain/phase
Open loop gain/phase
vs Frequency
vs Supply voltage
vs Shutdown voltage
vs Bypass capacitor
IDD
Supply current
Start-up time
Copyright © 2002–2008, Texas Instruments Incorporated
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Product Folder Link(s): TPA6203A1
TPA6203A1
SLOS364F–MARCH 2002–REVISED JUNE 2008.......................................................................................................................................................... www.ti.com
TYPICAL CHARACTERISTICS
OUTPUT POWER
vs
SUPPLY VOLTAGE
OUTPUT POWER
vs
LOAD RESISTANCE
OUTPUT POWER
vs
LOAD RESISTANCE
1.8
1.6
1.4
1.2
1
1.8
1.6
1.4
1.2
1.4
1.2
1
f = 1 kHz
THD+N = 10%
Gain = 1 V/V
R
= 8 Ω
f = 1 kHz
THD+N = 1%
Gain = 1 V/V
L
f = 1 kHz
Gain = 1 V/V
V
= 5 V
DD
V
= 5 V
DD
THD+N = 10%
V
= 3.6 V
V
DD
V
= 3.6 V
DD
0.8
0.6
0.4
1
0.8
V
= 2.5 V
DD
0.8
0.6
0.4
= 2.5 V
DD
0.6
0.4
0.2
THD+N = 1%
0.2
0
0.2
0
0
2.5
3
3.5
4
4.5
5
8
13
18
23
28
32
8
13
18
23
28
32
V
- Supply Voltage - V
R
L
- Load Resistance - Ω
DD
R
L
- Load Resistance - Ω
Figure 1.
Figure 2.
Figure 3.
MAXIMUM AMBIENT
TEMPERATURE
vs
POWER DISSIPATION
vs
POWER DISSIPATION
vs
OUTPUT POWER
OUTPUT POWER
POWER DISSIPATION
0.4
0.35
0.3
90
80
70
60
50
40
30
20
10
0
0.7
V
= 5 V
V
= 3.6 V
DD
DD
0.6
0.5
0.4
0.3
0.2
0.1
0
8 Ω
8 Ω
0.25
0.2
0.15
0.1
16 Ω
16 Ω
ZQV Package Only
0.05
0
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8
0
0.2
0.4
0.6
0.8
0
0.2 0.4
0.6
0.8
1
1.2 1.4
P - Power Dissipation - W
D
P
- Output Power - W
P
- Output Power - W
O
O
Figure 4.
Figure 5.
Figure 6.
TOTAL HARMONIC DISTORTION +
TOTAL HARMONIC DISTORTION +
TOTAL HARMONIC DISTORTION +
NOISE
vs
NOISE
vs
NOISE
vs
OUTPUT POWER
OUTPUT POWER
FREQUENCY
10
10
5
10
R
= 16 Ω
V
= 5 V
L
DD
5
5
2
50 mW
f = 1 kHz
C = 2 µF
I
2
1
C
= 0 to 1 µF
R = 8 Ω
L
(Bypass)
2.5 V
2
1
Gain = 1 V/V
C
= 0 to 1 µF
(Bypass)
3.6 V
0.5
Gain = 1 V/V
1
0.2
0.1
250 mW
0.5
5 V
0.5
2.5 V
3.6 V
5 V
0.05
0.2
0.1
0.2
0.1
0.02
0.01
1 W
0.05
0.05
R
C
= 8 Ω, f = 1 kHz
0.005
L
= 0 to 1 µF
(Bypass)
0.02
0.01
0.02
0.01
0.002
0.001
Gain = 1 V/V
10 m
100 m
1
2
3
10 m
100 m
1
2
20
100 200
1 k 2 k
10 k 20 k
f - Frequency - Hz
P
- Output Power - W
P
- Output Power - W
O
O
Figure 7.
Figure 8.
Figure 9.
6
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Product Folder Link(s): TPA6203A1
TPA6203A1
www.ti.com .......................................................................................................................................................... SLOS364F–MARCH 2002–REVISED JUNE 2008
TYPICAL CHARACTERISTICS (continued)
TOTAL HARMONIC DISTORTION +
TOTAL HARMONIC DISTORTION +
TOTAL HARMONIC DISTORTION +
NOISE
vs
NOISE
vs
NOISE
vs
FREQUENCY
FREQUENCY
FREQUENCY
10
5
10
5
10
5
V
= 3.6 V
DD
V
= 2.5 V
V
= 3.6 V
DD
25 mW
DD
C = 2 µF
R
C
I
15 mW
C = 2 µF
R
C
C = 2 µF
I
R
C
I
2
1
2
1
2
1
= 8 Ω
L
25 mW
= 8 Ω
= 16 Ω
L
= 0 to 1 µF
(Bypass)
L
= 0 to 1 µF
(Bypass)
= 0 to 1 µF
(Bypass)
Gain = 1 V/V
0.5
0.5
0.5
Gain = 1 V/V
Gain = 1 V/V
0.2
0.1
0.2
0.1
0.2
0.1
125 mW
125 mW
75 mW
0.05
0.05
0.05
0.02
0.01
0.02
0.01
0.02
0.01
500 mW
200 mW
250 mW
0.005
0.005
0.005
0.002
0.001
0.002
0.001
0.002
0.001
20
50 100 200 500 1 k 2 k 5 k 10 k 20 k
20
50 100 200 500 1 k 2 k 5 k 10 k 20 k
20
50 100 200 500 1 k 2 k 5 k 10 k 20 k
f - Frequency - Hz
f - Frequency - Hz
f - Frequency - Hz
Figure 10.
Figure 11.
Figure 12.
TOTAL HARMONIC DISTORTION +
SUPPLY VOLTAGE REJECTION
SUPPLY VOLTAGE REJECTION
NOISE
RATIO
vs
RATIO
vs
vs
COMMON MODE INPUT VOLTAGE
FREQUENCY
FREQUENCY
0
-10
-20
0
-10
-20
10
Gain = 5 V/V
f = 1 kHz
C = 2 µF
I
C = 2 µF
I
P
= 200 mW
R = 8 Ω
L
O
R
C
V
= 8 Ω
L
C
= 0.47 µF
(Bypass)
= 200 mV
= 0.47 µF
(Bypass)
= 200 mV
V
p-p
-30
-40
-50
-60
-70
-80
-30
-40
-50
-60
-70
-80
p-p
Inputs ac-Grounded
Inputs ac-Grounded
Gain = 1 V/V
1
V
=2. 5 V
DD
V
= 2.5 V
DD
V
V
= 5 V
DD
V
=2. 5 V
DD
0.10
0.01
V
= 5 V
DD
= 3.6 V
DD
V
= 3.6 V
DD
-90
-90
V
= 3.6 V
DD
-100
-100
20 50 100 200 500 1 k 2 k 5 k 10 k 20 k
20 50 100 200 500 1 k 2 k 5 k 10 k 20 k
0
0.5
1
1.5
2
2.5
3
3.5
f - Frequency - Hz
f - Frequency - Hz
V
- Common Mode Input Voltage - V
IC
Figure 13.
Figure 14.
Figure 15.
SUPPLY VOLTAGE REJECTION
SUPPLY VOLTAGE REJECTION
SUPPLY VOLTAGE REJECTION
RATIO
vs
RATIO
vs
RATIO
vs
FREQUENCY
FREQUENCY
COMMON MODE INPUT VOLTAGE
0
-10
-20
0
-10
-20
-10
-20
-30
-40
-50
-60
-70
f = 217 Hz
V
= 3.6 V
C = 2 µF
DD
C = 2 µF
I
C
R
= 0.47 µF
(Bypass)
R
L
= 8 Ω
I
= 8 Ω
R
= 8 Ω
L
Inputs Floating
Gain = 1 V/V
L
Gain = 1 V/V
Inputs ac-Grounded
Gain = 1 V/V
-30
-40
-50
-60
-70
-80
-30
-40
-50
-60
-70
-80
V
= 2.5 V
V
= 3.6 V
DD
DD
C
= 0
(Bypass)
C
= 0.47 µF
(Bypass)
V
=2. 5 V
DD
C
= 1 µF
(Bypass)
V
= 5 V
DD
V
= 3.6 V
DD
C
= 0.1 µF
(Bypass)
-80
-90
V
= 5 V
-90
-90
DD
-100
-100
20 50 100 200 500 1 k 2 k 5 k 10 k 20 k
20 50 100 200 500 1 k 2 k 5 k 10 k 20 k
0
1
2
3
4
5
V
- Common Mode Input Voltage - V
IC
f - Frequency - Hz
f - Frequency - Hz
Figure 16.
Figure 17.
Figure 18.
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TYPICAL CHARACTERISTICS (continued)
GSM POWER SUPPLY
GSM POWER SUPPLY
REJECTION
vs
REJECTION
vs
COMMON MODE REJECTION RATIO
vs
TIME
FREQUENCY
FREQUENCY
0
0
V
DD
V
V
R
= 2.5 V to 5 V
DD
C1
Frequency
217.41 Hz
-10
-20
-30
-40
-50
-60
-70
-80
= 200 mV
IC
p-p
-50
= 8 Ω
L
Gain = 1 V/V
C1 - Duty
20 %
-100
-150
C1 High
3.598 V
0
V
Shown in Figure 19
DD
C = 2 µF,
I
-50
C1 Pk-Pk
504 mV
C
= 0.47 µF,
(Bypass)
Inputs ac-Grounded
Gain = 1V/V
V
O
-100
-150
-90
Ch1 100 mV/div
Ch4 10 mV/div
2 ms/div
-100
0
200 400 600 800 1k 1.2k 1.4k1.6k1.8k 2k
20 50 100 200 500 1 k 2 k 5 k 10 k 20 k
f - Frequency - Hz
t - Time - ms
f - Frequency - Hz
Figure 19.
Figure 20.
Figure 21.
COMMON MODE REJECTION RATIO
CLOSED LOOP GAIN/PHASE
OPEN LOOP GAIN/PHASE
vs
vs
vs
FREQUENCY
200
COMMON MODE INPUT VOLTAGE
0
FREQUENCY
40
30
20
10
220
200
Phase
V
R
= 3.6 V
DD
= 8 Ω
R
= 8 Ω
180
140
100
60
-10
-20
-30
-40
L
150
100
50
150
100
50
L
Gain = 1 V/V
Gain
Gain
0
-10
-20
-30
-40
-50
V
= 2.5 V
DD
20
0
-50
-60
-70
-80
0
V
= 5 V
-20
DD
-50
-60
-50
-100
Phase
-100
-140
-180
-220
-100
V
R
= 3.6 V
DD
= 8 Ω
L
-150
-200
-150
-200
-60
-70
-90
Gain = 1 V/V
V
= 3.6 V
DD
-100
10 100
1 k
10 k 100 k 1 M
10 M
100
1 k
10 k
100 k
1 M
10 M
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
f - Frequency - Hz
f - Frequency - Hz
V
- Common Mode Input Voltage - V
IC
Figure 22.
Figure 23.
Figure 24.
SUPPLY CURRENT
vs
SUPPLY VOLTAGE
SUPPLY CURRENT
vs
SHUTDOWN VOLTAGE
START-UP TIME(1)
vs
BYPASS CAPACITOR
1.8
1.6
1.4
1.2
6
5
1.8
1.6
1.4
V
= 2.5 V
DD
4
3
2
1
0
1.2
1.0
0.8
V
= 3.6 V
DD
1
V
= 5 V
DD
0.8
0.6
0.4
0.2
0
0.6
0.4
0.2
0
0
0.5
(Bypass)
1
1.5
2
C
- Bypass Capacitor - µF
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9
1
2
V
- Supply Voltage - V
Voltage on SHUTDOWN Terminal - V
DD
(1)
Start-Up time is the time it takes (from a
low-to-high transition on SHUTDOWN) for the
gain of the amplifier to reach -3 dB of the final
gain.
Figure 25.
Figure 26.
Figure 27.
8
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APPLICATION INFORMATION
negative channels equally and cancels at the
differential output. However, removing the bypass
capacitor slightly worsens power supply rejection
ratio (kSVR), but a slight decrease of kSVR may be
acceptable when an additional component can be
eliminated (see Figure 17).
Better RF-immunity: GSM handsets save power
by turning on and shutting off the RF transmitter at
a rate of 217 Hz. The transmitted signal is
picked-up on input and output traces. The fully
differential amplifier cancels the signal much
better than the typical audio amplifier.
FULLY DIFFERENTIAL AMPLIFIER
The TPA6203A1 is a fully differential amplifier with
differential inputs and outputs. The fully differential
amplifier consists of a differential amplifier and a
common- mode amplifier. The differential amplifier
ensures that the amplifier outputs a differential
voltage that is equal to the differential input times the
gain. The common-mode feedback ensures that the
common-mode voltage at the output is biased around
VDD/2 regardless of the common- mode voltage at the
input.
•
APPLICATION SCHEMATICS
Advantages of Fully Differential Amplifiers
•
Input coupling capacitors not required: A fully
differential amplifier with good CMRR, like the
TPA6203A1, allows the inputs to be biased at
voltage other than mid-supply. For example, if a
DAC has mid-supply lower than the mid-supply of
the TPA6203A1, the common-mode feedback
circuit adjusts for that, and the TPA6203A1
outputs are still biased at mid-supply of the
TPA6203A1. The inputs of the TPA6203A1 can
be biased from 0.5 V to VDD - 0.8 V. If the inputs
are biased outside of that range, input coupling
capacitors are required.
Figure 28 through Figure 30 show application
schematics for differential and single-ended inputs.
Typical values are shown in Table 1.
Table 1. Typical Component Values
COMPONENT
VALUE
10 kΩ
10 kΩ
0.22 µF
1 µF
RI
RF
(1)
C(BYPASS)
CS
CI
0.22 µF
•
Mid-supply bypass capacitor, C(BYPASS)
,
not
(1) C(BYPASS) is optional
required: The fully differential amplifier does not
require a bypass capacitor. This is because any
shift in the mid-supply affects both positive and
V
DD
R
F
To Battery
C
s
R
I
-
IN-
_
+
V
O+
In From
DAC
V
R
I
O-
+
IN+
R
F
GND
SHUTDOWN
Bias
Circuitry
C BYPASS
(
)
(Optional)
Figure 28. Typical Differential Input Application Schematic
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V
DD
R
F
To Battery
C
C
C
s
I
R
I
IN-
-
_
+
V
O+
IN
R
I
V
O-
IN+
+
I
R
F
GND
SHUTDOWN
Bias
Circuitry
C BYPASS
(
)
(Optional)
Figure 29. Differential Input Application Schematic Optimized With Input Capacitors
V
DD
R
F
To Battery
C
I
C
s
R
I
IN-
_
+
V
O+
IN
R
V
I
O-
IN+
C
I
R
F
GND
SHUTDOWN
C BYPASS
Bias
Circuitry
(
)
(Optional)
Figure 30. Single-Ended Input Application Schematic
Bypass Capacitor (CBYPASS) and Start-Up Time
The internal voltage divider at the BYPASS pin of this
Selecting Components
Resistors (RF and RI)
device sets mid-supply voltage for internal
a
references and sets the output common mode
voltage to VDD/2. Adding a capacitor to this pin filters
The input (RI) and feedback resistors (RF) set the
gain of the amplifier according to Equation 1.
any noise into this pin and increases the kSVR
.
Gain = RF/RI
(1)
C(BYPASS)also determines the rise time of VO+ and VO-
when the device is taken out of shutdown. The larger
the capacitor, the slower the rise time. Although the
output rise time depends on the bypass capacitor
value, the device passes audio 4 µs after taken out of
shutdown and the gain is slowly ramped up based on
RF and RI should range from 1 kΩ to 100 kΩ. Most
graphs were taken with RF = RI = 20 kΩ.
Resistor matching is very important in fully differential
amplifiers. The balance of the output on the reference
voltage depends on matched ratios of the resistors.
CMRR, PSRR, and the cancellation of the second
harmonic distortion diminishes if resistor mismatch
occurs. Therefore, it is recommended to use 1%
tolerance resistors or better to keep the performance
optimized.
C(BYPASS)
.
To minimize pops and clicks, design the circuit so the
impedance (resistance and capacitance) detected by
both inputs, IN+ and IN-, is equal.
10
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Input Capacitor (CI)
Decoupling Capacitor (CS)
The TPA6203A1 does not require input coupling
capacitors if using a differential input source that is
biased from 0.5 V to VDD - 0.8 V. Use 1% tolerance
or better gain-setting resistors if not using input
coupling capacitors.
The TPA6203A1 is a high-performance CMOS audio
amplifier that requires adequate power supply
decoupling to ensure the output total harmonic
distortion (THD) is as low as possible. Power supply
decoupling also prevents oscillations for long lead
lengths between the amplifier and the speaker. For
higher frequency transients, spikes, or digital hash on
the line, a good low equivalent-series- resistance
(ESR) ceramic capacitor, typically 0.1 µF to 1 µF,
placed as close as possible to the device VDD lead
works best. For filtering lower frequency noise
signals, a 10-µF or greater capacitor placed near the
audio power amplifier also helps, but is not required
in most applications because of the high PSRR of this
device.
In the single-ended input application an input
capacitor, CI, is required to allow the amplifier to bias
the input signal to the proper dc level. In this case, CI
and RI form a high-pass filter with the corner
frequency determined in Equation 2.
1
f
+
c
2pR C
I
I
(2)
–3 dB
USING LOW-ESR CAPACITORS
Low-ESR capacitors are recommended throughout
this applications section. A real (as opposed to ideal)
capacitor can be modeled simply as a resistor in
series with an ideal capacitor. The voltage drop
across this resistor minimizes the beneficial effects of
the capacitor in the circuit. The lower the equivalent
value of this resistance the more the real capacitor
behaves like an ideal capacitor.
f
c
The value of CI is important to consider as it directly
affects the bass (low frequency) performance of the
circuit. Consider the example where RI is 10 kΩ and
the specification calls for a flat bass response down
to 100 Hz. Equation 2 is reconfigured as Equation 3.
DIFFERENTIAL OUTPUT VERSUS
SINGLE-ENDED OUTPUT
Figure 31 shows a Class-AB audio power amplifier
(APA) in
a fully differential configuration. The
TPA6203A1 amplifier has differential outputs driving
both ends of the load. There are several potential
benefits to this differential drive configuration, but
initially consider power to the load. The differential
drive to the speaker means that as one side is
slewing up, the other side is slewing down, and vice
versa. This in effect doubles the voltage swing on the
load as compared to a ground referenced load.
Plugging 2 × VO(PP) into the power equation, where
voltage is squared, yields 4× the output power from
the same supply rail and load impedance (see
Equation 4).
1
C
+
I
2pR f
c
I
(3)
In this example, CI is 0.16 µF, so one would likely
choose a value in the range of 0.22 µF to 0.47 µF. A
further consideration for this capacitor is the leakage
path from the input source through the input network
(RI, CI) and the feedback resistor (RF) to the load.
This leakage current creates a dc offset voltage at the
input to the amplifier that reduces useful headroom,
especially in high gain applications. For this reason, a
ceramic capacitor is the best choice. When polarized
capacitors are used, the positive side of the capacitor
should face the amplifier input in most applications,
as the dc level there is held at VDD/2, which is likely
higher than the source dc level. It is important to
confirm the capacitor polarity in the application.
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V
V
low-frequency performance of the system. This
frequency-limiting effect is due to the high pass filter
network created with the speaker impedance and the
coupling capacitance and is calculated with
Equation 5.
O(PP)
V(rms)
+
Ǹ
2 2
2
(rms)
1
Power +
f
+
c
R
2pR C
L
(4)
L C
(5)
V
DD
For example, a 68-µF capacitor with an 8-Ω speaker
would attenuate low frequencies below 293 Hz. The
BTL configuration cancels the dc offsets, which
eliminates the need for the blocking capacitors.
Low-frequency performance is then limited only by
the input network and speaker response. Cost and
PCB space are also minimized by eliminating the
bulky coupling capacitor.
V
O(PP)
V
DD
2x V
O(PP)
R
L
V
DD
V
O(PP)
C
C
V
O(PP)
–V
O(PP)
R
L
–3 dB
Figure 31. Differential Output Configuration
In a typical wireless handset operating at 3.6 V,
bridging raises the power into an 8-Ω speaker from a
singled-ended (SE, ground reference) limit of 200
mW to 800 mW. In sound power that is a 6-dB
improvement—which is loudness that can be heard.
In addition to increased power there are frequency
response concerns. Consider the single-supply SE
f
c
configuration shown in Figure 32.
A
coupling
capacitor is required to block the dc offset voltage
from reaching the load. This capacitor can be quite
large (approximately 33 µF to 1000 µF) so it tends to
be expensive, heavy, occupy valuable PCB area, and
Figure 32. Single-Ended Output and Frequency
Response
Increasing power to the load does carry a penalty of
increased internal power dissipation. The increased
dissipation is understandable considering that the
BTL configuration produces 4× the output power of
the SE configuration.
have
the
additional
drawback
of
limiting
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FULLY DIFFERENTIAL AMPLIFIER
EFFICIENCY AND THERMAL INFORMATION
V
O
Class-AB amplifiers are inefficient. The primary cause
of these inefficiencies is voltage drop across the
output stage transistors. There are two components
of the internal voltage drop. One is the headroom or
dc voltage drop that varies inversely to output power.
The second component is due to the sinewave nature
of the output. The total voltage drop can be
calculated by subtracting the RMS value of the output
voltage from VDD. The internal voltage drop multiplied
by the average value of the supply current, IDD(avg),
determines the internal power dissipation of the
amplifier.
V
(LRMS)
I
DD
I
DD(avg)
Figure 33. Voltage and Current Waveforms for
BTL Amplifiers
An easy-to-use equation to calculate efficiency starts
out as being equal to the ratio of power from the
power supply to the power delivered to the load. To
accurately calculate the RMS and average values of
power in the load and in the amplifier, the current and
voltage waveform shapes must first be understood
(see Figure 33).
Although the voltages and currents for SE and BTL
are sinusoidal in the load, currents from the supply
are very different between SE and BTL
configurations. In an SE application the current
waveform is a half-wave rectified shape, whereas in
BTL it is a full-wave rectified waveform. This means
RMS conversion factors are different. Keep in mind
that for most of the waveform both the push and pull
transistors are not on at the same time, which
supports the fact that each amplifier in the BTL
device only draws current from the supply for half the
waveform. The following equations are the basis for
calculating amplifier efficiency.
P
L
Efficiency of a BTL amplifier +
P
SUP
where:
2
2
V rms
L
V
V
P
2R
P
P
+
, andV
+
, therefore, P
+
L
LRMS
L
Ǹ
R
2
L
L
p
2V
V
R
p
V
P
1
p
P
L
1
p
P
+
+
sin(t) dt
[cos(t)]
0
ŕ
P
+ V
I
avg
and
I
avg +
and
p R
SUP
DD DD
DD
R
L
0
L
Therefore,
2 V
V
DD
P
P
+
SUP
p R
L
PL = Power delivered to load
substituting PL and PSUP into equation 6,
2
PSUP = Power drawn from power supply
VLRMS = RMS voltage on BTL load
RL = Load resistance
VP = Peak voltage on BTL load
IDDavg = Average current drawn from the
power supply
V
P
2 R
p V
L
P
Efficiency of a BTL amplifier +
+
4 V
2 V
V
DD
DD
p R
P
L
where:
V
VDD = Power supply voltage
ηBTL = Efficiency of a BTL amplifier
+ Ǹ2 P R
L
P
L
(6)
13
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Therefore,
1
1
Θ
+
+
+ 113°CńW
JA
0.0088
Derating Factor
(9)
p Ǹ2 P R
L
L
Given θJA, the maximum allowable junction
temperature, and the maximum internal dissipation,
the maximum ambient temperature can be calculated
with the following equation. The maximum
recommended
TPA6203A1 is 125°C.
Max + T Max * Θ
h
+
BTL
4 V
DD
(7)
Table 2. Efficiency and Maximum Ambient
Temperature vs Output Power in 5-V 8-Ω BTL
Systems
junction
temperature
for
the
T
P
Power
From
Max
Ambient
A
J
JA Dmax
Output
Power
(W)
Internal
Dissipation
(W)
Efficiency
(%)
(
)
+ 125 * 113 0.634 + 53.3°C
Supply Temperature
(10)
(W)
0.75
1.12
1.59
1.78
(°C)
Equation 10 shows that the maximum ambient
temperature is 53.3°C at maximum power dissipation
with a 5-V supply.
0.25
0.50
1.00
1.25
31.4
44.4
62.8
70.2
0.55
0.62
0.59
0.53
62
54
58
Table 2 shows that for most applications no airflow is
required to keep junction temperatures in the
specified range. The TPA6203A1 is designed with
thermal protection that turns the device off when the
junction temperature surpasses 150°C to prevent
damage to the IC. Also, using more resistive than 8-Ω
speakers dramatically increases the thermal
performance by reducing the output current.
65
Table 2 employs Equation 7 to calculate efficiencies
for four different output power levels. Note that the
efficiency of the amplifier is quite low for lower power
levels and rises sharply as power to the load is
increased resulting in a nearly flat internal power
dissipation over the normal operating range. Note that
the internal dissipation at full output power is less
than in the half power range. Calculating the
efficiency for a specific system is the key to proper
power supply design. For a 1.25-W audio system with
8-Ω loads and a 5-V supply, the maximum draw on
the power supply is almost 1.8 W.
PCB LAYOUT
In making the pad size for the BGA balls, it is
recommended that the layout use solder-
mask-defined (SMD) land. With this method, the
copper pad is made larger than the desired land area,
and the opening size is defined by the opening in the
solder mask material. The advantages normally
associated with this technique include more closely
controlled size and better copper adhesion to the
laminate. Increased copper also increases the
thermal performance of the IC. Better size control is
the result of photo imaging the stencils for masks.
Small plated vias should be placed near the center
ball connecting ball B2 to the ground plane. Added
plated vias and ground plane act as a heatsink and
increase the thermal performance of the device.
Figure 34 shows the appropriate diameters for a 2
mm X 2 mm MicroStar Junior™ BGA layout.
A final point to remember about Class-AB amplifiers
is how to manipulate the terms in the efficiency
equation to the utmost advantage when possible.
Note that in Equation 7, VDD is in the denominator.
This indicates that as VDD goes down, efficiency goes
up.
A simple formula for calculating the maximum power
dissipated, PDmax, may be used for a differential
output application:
2 V2
DD
+
P
p2 R
D max
L
(8)
It is very important to keep the TPA6203A1 external
components very close to the TPA6203A1 to limit
noise pickup. The TPA6203A1 evaluation module
(EVM) layout is shown in the next section as a layout
example.
PDmax for a 5-V, 8-Ω system is 634 mW.
The maximum ambient temperature depends on the
heat sinking ability of the PCB system. The derating
factor for the 2 mm x 2 mm Microstar Junior™
package is shown in the dissipation rating table.
Converting this to θJA:
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0.38 mm
0.25 mm
0.28 mm
C1
B1
A1
VIAS to Ground Plane
C2
C3
B2
B3
Solder Mask
A3
Paste Mask (Stencil)
Copper Trace
Figure 34. MicroStar Junior™ BGA Recommended Layout
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8-Pin QFN (DRB) Layout
Use the following land pattern for board layout with the 8-pin QFN (DRB) package. Note that the solder paste
should use a hatch pattern to fill solder paste at 50% to ensure that there is not too much solder paste under the
package.
0.7 mm
0.33 mm plugged vias (5 places)
1.4 mm
0.38 mm
0.65 mm
1.95 mm
Solder Mask: 1.4 mm x 1.85 mm centered in package
Make solder paste a hatch pattern to fill 50%
3.3 mm
Figure 35. TPA6203A1 8-Pin QFN (DRB) Board Layout (Top View)
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PACKAGE OPTION ADDENDUM
www.ti.com
31-Mar-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
HPA00194DGNR
TPA6203A1DGN
TPA6203A1DGNR
TPA6203A1DRB
TPA6203A1DRBR
TPA6203A1NMBR
TPA6203A1ZQVR
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
LIFEBUY
HVSSOP
HVSSOP
HVSSOP
SON
DGN
DGN
DGN
DRB
DRB
NMB
ZQV
8
8
8
8
8
8
8
2500 RoHS & Green
80
2500 RoHS & Green NIPDAU | NIPDAUAG Level-1-260C-UNLIM
NIPDAU
Level-1-260C-UNLIM
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
AAII
AAII
AAII
AAJI
AAJI
AAEI
AAEI
RoHS & Green NIPDAU | NIPDAUAG Level-1-260C-UNLIM
121
RoHS & Green
NIPDAU
NIPDAU
SNAGCU
SNAGCU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
SON
3000 RoHS & Green
2500 RoHS & Green
2500 RoHS & Green
NFBGA
BGA
MICROSTAR
JUNIOR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
31-Mar-2021
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
1-Apr-2021
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPA6203A1DGNR
TPA6203A1DGNR
TPA6203A1DRBR
TPA6203A1NMBR
TPA6203A1ZQVR
HVSSOP DGN
HVSSOP DGN
8
8
8
8
8
2500
2500
3000
2500
2500
330.0
330.0
330.0
330.0
330.0
12.4
12.4
12.4
8.4
5.3
5.3
3.3
2.3
2.3
3.4
3.4
3.3
2.3
2.3
1.4
1.4
1.1
1.4
1.4
8.0
8.0
8.0
4.0
4.0
12.0
12.0
12.0
8.0
Q1
Q1
Q2
Q1
Q1
SON
DRB
NMB
ZQV
NFBGA
BGA MI
CROSTA
R JUNI
OR
8.4
8.0
TPA6203A1ZQVR
BGA MI
CROSTA
R JUNI
OR
ZQV
8
2500
330.0
8.4
2.3
2.3
1.4
4.0
8.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
1-Apr-2021
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPA6203A1DGNR
TPA6203A1DGNR
TPA6203A1DRBR
TPA6203A1NMBR
TPA6203A1ZQVR
HVSSOP
HVSSOP
SON
DGN
DGN
DRB
NMB
ZQV
8
8
8
8
8
2500
2500
3000
2500
2500
364.0
358.0
367.0
338.1
350.0
364.0
335.0
367.0
338.1
350.0
27.0
35.0
35.0
20.6
43.0
NFBGA
BGA MICROSTAR
JUNIOR
TPA6203A1ZQVR
BGA MICROSTAR
JUNIOR
ZQV
8
2500
338.1
338.1
20.6
Pack Materials-Page 2
PACKAGE OUTLINE
DRB0008A
VSON - 1 mm max height
SCALE 4.000
PLASTIC SMALL OUTLINE - NO LEAD
3.1
2.9
B
A
PIN 1 INDEX AREA
3.1
2.9
C
1 MAX
SEATING PLANE
0.08 C
0.05
0.00
DIM A
OPT 1
(0.1)
OPT 2
(0.2)
1.5 0.1
4X (0.23)
EXPOSED
THERMAL PAD
(DIM A) TYP
4
5
2X
1.95
1.75 0.1
8
1
6X 0.65
0.37
0.25
8X
PIN 1 ID
0.1
C A B
C
(OPTIONAL)
(0.65)
0.05
0.5
0.3
8X
4218875/A 01/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
DRB0008A
VSON - 1 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(1.5)
(0.65)
SYMM
8X (0.6)
(0.825)
8
8X (0.31)
1
SYMM
(1.75)
(0.625)
6X (0.65)
4
5
(R0.05) TYP
(
0.2) VIA
(0.23)
TYP
(0.5)
(2.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:20X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
EXPOSED
METAL
EXPOSED
METAL
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4218875/A 01/2018
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
DRB0008A
VSON - 1 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(0.65)
4X (0.23)
SYMM
METAL
TYP
8X (0.6)
4X
(0.725)
8
1
8X (0.31)
(2.674)
(1.55)
SYMM
6X (0.65)
4
5
(R0.05) TYP
(1.34)
(2.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD
84% PRINTED SOLDER COVERAGE BY AREA
SCALE:25X
4218875/A 01/2018
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
PACKAGE OUTLINE
NFBGA - 1 mm max height
PLASTIC BALL GRID ARRAY
NMB0008A
A
2.1
1.9
B
BALL A1 CORNER
2.1
1.9
1 MAX
C
SEATING PLANE
0.12 C
BALL TYP
0.25
0.15
1
TYP
0.5 TYP
C
0.5 TYP
0.5 TYP
0.5 TYP
SYMM
1
B
A
TYP
0.35
0.25
8X Ø
1
2
3
0.15
0.05
C A B
C
SYMM
4224891/A 04/2019
NanoFree is a trademark of Texas Instruments.
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
EXAMPLE BOARD LAYOUT
NFBGA - 1 mm max height
PLASTIC BALL GRID ARRAY
NMB0008A
(0.5) TYP
1
2
3
(0.5) TYP
A
B
SYMM
8X (Ø0.25)
C
SYMM
LAND PATTERN EXAMPLE
SCALE: 25X
0.05 MIN
ALL AROUND
0.05 MAX
ALL AROUND
METAL UNDER
SOLDER MASK
EXPOSED
METAL
(Ø 0.25)
SOLDER MASK
OPENING
EXPOSED
METAL
(Ø 0.25)
METAL
SOLDER MASK
OPENING
NON- SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
NOT TO SCALE
4224891/A 04/2019
NOTES: (continued)
3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints. Refer to Texas Instruments
Literature number SNVA009 (www.ti.com/lit/snva009).
www.ti.com
EXAMPLE STENCIL DESIGN
NFBGA - 1 mm max height
PLASTIC BALL GRID ARRAY
NMB0008A
(0.5) TYP
1
2
3
(0.5) TYP
A
B
SYMM
(R0.05)
C
8X ( 0.25)
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.100 mm THICK STENCIL
SCALE: 25X
4224891/A 04/2019
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
www.ti.com
GENERIC PACKAGE VIEW
DGN 8
3 x 3, 0.65 mm pitch
PowerPAD VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4225482/A
www.ti.com
PACKAGE OUTLINE
DGN0008D
PowerPADTM VSSOP - 1.1 mm max height
S
C
A
L
E
4
.
0
0
0
SMALL OUTLINE PACKAGE
C
5.05
4.75
TYP
A
0.1 C
SEATING
PLANE
PIN 1 INDEX AREA
6X 0.65
8
1
2X
3.1
2.9
1.95
NOTE 3
4
5
0.38
8X
0.25
3.1
2.9
0.13
C A B
B
NOTE 4
0.23
0.13
SEE DETAIL A
EXPOSED THERMAL PAD
4
5
0.25
GAGE PLANE
1.89
1.63
9
1.1 MAX
8
0.15
0.05
1
0.7
0.4
0 -8
A
20
DETAIL A
TYPICAL
1.57
1.28
4225481/A 11/2019
PowerPAD is a trademark of Texas Instruments.
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-187.
www.ti.com
EXAMPLE BOARD LAYOUT
DGN0008D
PowerPADTM VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE
(2)
NOTE 9
METAL COVERED
BY SOLDER MASK
(1.57)
SOLDER MASK
DEFINED PAD
SYMM
8X (1.4)
(R0.05) TYP
8
8X (0.45)
1
(3)
NOTE 9
SYMM
(1.89)
9
(1.22)
6X (0.65)
5
4
(
0.2) TYP
VIA
SEE DETAILS
(0.55)
(4.4)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 15X
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
METAL
EXPOSED METAL
EXPOSED METAL
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
NON-SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
15.000
(PREFERRED)
SOLDER MASK DETAILS
4225481/A 11/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
8. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
9. Size of metal pad may vary due to creepage requirement.
www.ti.com
EXAMPLE STENCIL DESIGN
DGN0008D
PowerPADTM VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE
(1.57)
BASED ON
0.125 THICK
STENCIL
SYMM
(R0.05) TYP
8X (1.4)
8
1
8X (0.45)
(1.89)
SYMM
BASED ON
0.125 THICK
STENCIL
6X (0.65)
5
4
METAL COVERED
BY SOLDER MASK
SEE TABLE FOR
DIFFERENT OPENINGS
FOR OTHER STENCIL
THICKNESSES
(4.4)
SOLDER PASTE EXAMPLE
EXPOSED PAD 9:
100% PRINTED SOLDER COVERAGE BY AREA
SCALE: 15X
STENCIL
THICKNESS
SOLDER STENCIL
OPENING
0.1
1.76 X 2.11
1.57 X 1.89 (SHOWN)
1.43 X 1.73
0.125
0.15
0.175
1.33 X 1.60
4225481/A 11/2019
NOTES: (continued)
10. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
11. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
DGN0008G
PowerPADTM VSSOP - 1.1 mm max height
S
C
A
L
E
4
.
0
0
0
SMALL OUTLINE PACKAGE
C
5.05
4.75
TYP
A
0.1 C
SEATING
PLANE
PIN 1 INDEX AREA
6X 0.65
8
1
2X
3.1
2.9
1.95
NOTE 3
4
5
0.38
8X
0.25
3.1
2.9
0.13
C A B
B
NOTE 4
0.23
0.13
SEE DETAIL A
EXPOSED THERMAL PAD
4
5
0.25
GAGE PLANE
2.15
1.95
9
1.1 MAX
8
0.15
0.05
1
0.7
0.4
0 -8
A
20
DETAIL A
TYPICAL
1.846
1.646
4225480/A 11/2019
PowerPAD is a trademark of Texas Instruments.
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-187.
www.ti.com
EXAMPLE BOARD LAYOUT
DGN0008G
PowerPADTM VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE
(2)
NOTE 9
(1.846)
SYMM
METAL COVERED
BY SOLDER MASK
SOLDER MASK
DEFINED PAD
8X (1.4)
(R0.05) TYP
8
8X (0.45)
1
(3)
NOTE 9
SYMM
9
(2.15)
(1.22)
6X (0.65)
5
4
(
0.2) TYP
VIA
SEE DETAILS
(0.55)
(4.4)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 15X
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
METAL
EXPOSED METAL
EXPOSED METAL
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
NON-SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
15.000
(PREFERRED)
SOLDER MASK DETAILS
4225480/A 11/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
8. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
9. Size of metal pad may vary due to creepage requirement.
www.ti.com
EXAMPLE STENCIL DESIGN
DGN0008G
PowerPADTM VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE
(1.846)
BASED ON
0.125 THICK
STENCIL
SYMM
(R0.05) TYP
8X (1.4)
8
1
8X (0.45)
(2.15)
SYMM
BASED ON
0.125 THICK
STENCIL
6X (0.65)
5
4
METAL COVERED
BY SOLDER MASK
SEE TABLE FOR
DIFFERENT OPENINGS
FOR OTHER STENCIL
THICKNESSES
(4.4)
SOLDER PASTE EXAMPLE
EXPOSED PAD 9:
100% PRINTED SOLDER COVERAGE BY AREA
SCALE: 15X
STENCIL
THICKNESS
SOLDER STENCIL
OPENING
0.1
2.06 X 2.40
1.846 X 2.15 (SHOWN)
1.69 X 1.96
0.125
0.15
0.175
1.56 X 1.82
4225480/A 11/2019
NOTES: (continued)
10. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
11. Board assembly site may have different recommendations for stencil design.
www.ti.com
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