TPA6205A1NMBR [TI]
TPA6205A1 1.25-W Mono Fully Differential Audio Power Amplifier With 1.8-V Input logic Thresholds;
| 型号： | TPA6205A1NMBR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | TPA6205A1 1.25-W Mono Fully Differential Audio Power Amplifier With 1.8-V Input logic Thresholds |
| 文件： | 总46页 (文件大小：2572K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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SLOS490TPA6205A1
SLOS490C –JULY 2006–REVISED NOVEMBER 2015
TPA6205A1 1.25-W Mono Fully Differential Audio Power Amplifier
With 1.8-V Input logic Thresholds
1 Features
3 Description
The TPA6205A1 device is a 1.25-W mono fully
1
•
1.25 W Into 8-Ω From a 5-V Supply at THD = 1%
differential amplifier designed to drive a speaker with
at least 8-Ω impedance while consuming less than 37
mm2 (ZQV package option) total printed-circuit-board
(PCB) area in most applications. This device operates
from 2.5 V to 5.5 V, drawing only 1.7 mA of quiescent
supply current. The TPA6205A1 is available in the
space-saving 2-mm × 2-mm MicroStar Junior BGA
package, and the space saving 3-mm × 3-mm QFN
(DRB) package.
(Typical)
•
•
•
•
Shutdown Pin has 1.8-V Compatible Thresholds
Low Supply Current: 1.7 mA Typical
Shutdown Current < 10 µA
Only Five External Components
–
Improved PSRR (90 dB) and Wide Supply
Voltage (2.5 V to 5.5 V) for Direct Battery
Operation
Features like 85-dB PSRR from 90 Hz to 5 kHz,
improved RF-rectification immunity, and small PCB
area makes the TPA6205A1 ideal for wireless
handsets. A fast start-up time of 4s with minimal pop
makes the TPA6205A1 ideal for PDA applications.
–
–
–
Fully Differential Design Reduces RF
Rectification
Improved CMRR Eliminates Two Input
Coupling Capacitors
C(BYPASS) Is Optional Due to Fully Differential
Design and High PSRR
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
•
•
•
Available in 3-mm × 3-mm QFN Package (DRB)
Available in an 8-Pin PowerPAD™ MSOP (DGN)
MSOP-PowerPAD (8) 3.00 mm × 3.00 mm
SON (8)
3.00 mm × 3.00 mm
2.00 mm × 2.00 mm
TPA6205A1
Available in a 2-mm × 2-mm MicroStar Junior™
BGA Package (ZQV)
BGA MICROSTAR
JUNIOR (8)
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
2 Applications
•
Designed for Wireless Handsets, PDAs, and
Other Mobile Devices
•
Compatible With Low Power (1.8-V Logic) I/O
Threshold Control Signals
Application Circuit
Example Solution Size
Actual Solution Size
V
DD
R
F
R
F
To Battery
C
s
R
I
-
C
IN-
S
V
_
+
(1)
C
O+
B
In From
DAC
5,25 mm
R
I
V
O-
+
IN+
R
I
R
F
GND
R
I
SHUTDOWN
C BYPASS
Bias
Circuitry
R
F
(
)
(Optional)
6,9 mm
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SLOS490TPA6205A1
SLOS490C –JULY 2006–REVISED NOVEMBER 2015
www.ti.com
Table of Contents
9.2 Functional Block Diagram ....................................... 11
9.3 Feature Description................................................. 11
9.4 Device Functional Modes........................................ 15
10 Application and Implementation........................ 18
10.1 Application Information.......................................... 18
10.2 Typical Applications .............................................. 18
11 Power Supply Recommendations ..................... 22
11.1 Power Supply Decoupling Capacitors.................. 22
12 Layout................................................................... 23
12.1 Layout Guidelines ................................................. 23
12.2 Layout Example .................................................... 24
13 Device and Documentation Support ................. 26
13.1 Community Resources.......................................... 26
13.2 Trademarks........................................................... 26
13.3 Electrostatic Discharge Caution............................ 26
13.4 Glossary................................................................ 26
1
2
3
4
5
6
7
Features.................................................................. 1
Applications ........................................................... 1
Description ............................................................. 1
Revision History..................................................... 2
Device Comparison Table..................................... 3
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
7.1 Absolute Maximum Ratings ...................................... 4
7.2 ESD Ratings.............................................................. 4
7.3 Recommended Operating Conditions....................... 4
7.4 Thermal Information.................................................. 4
7.5 Electrical Characteristics........................................... 5
7.6 Operating Characteristics.......................................... 5
7.7 Dissipation Ratings ................................................... 6
7.8 Typical Characteristics.............................................. 6
Parameter Measurement Information ................ 11
Detailed Description ............................................ 11
9.1 Overview ................................................................. 11
8
9
14 Mechanical, Packaging, and Orderable
Information ........................................................... 26
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (June 2008) to Revision C
Page
•
Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional
Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device
and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1
•
Removed Ordering Information table .................................................................................................................................... 1
2
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SLOS490C –JULY 2006–REVISED NOVEMBER 2015
5 Device Comparison Table
DEVICE NUMBER
SPEAKER
CHANNELS
SPEAKER AMP
TYPE
OUTPUT POWER (W)
PSRR (dB)
TPA6203A1
TPA6204A1
Mono
Class AB
Class AB
Class AB
Class AB
1.25
1.7
90
85
90
85
Mono
TPA6205A1 (1.8-V comp SD)
TPA6211A1
Mono
1.25
3.1
Mono
6 Pin Configuration and Functions
ZQV Package
8-Pin BGA MICROSTAR JUNIOR
Top View
DRB Package
8-Pin SON
Top View
GND
1 2
3
A
B
C
1
2
3
4
8
SHUTDOWN
BYPASS
IN+
V
V
V
O-
V
DD
O+
O-
SHUTDOWN
BYPASS
7
GND
IN-
6
5
V
DD
V
O+
IN+
(SIDE VIEW)
IN-
DGN Package
8-Pin MSOP-PowerPAD
Top View
V
8
SHUTDOWN
BYPASS
IN+
1
O-
GND
7
6
5
2
3
4
V
DD
IN-
V
O+
Pin Functions
PIN
I/O
DESCRIPTION
BGA MICROSTAR
JUNIOR
SON,
MSOP-PowerPAD
NAME
BYPASS
GND
C1
B2
C3
C2
B1
A3
B3
A1
2
7
4
3
1
6
5
8
I
I
Mid-supply voltage. Adding a bypass capacitor improves PSRR.
High-current ground
IN–
I
Negative differential input
IN+
I
Positive differential input
SHUTDOWN
VDD
I
Shutdown terminal (active low logic)
Supply voltage terminal
I
VO+
O
O
Positive BTL output
VO–
Negative BTL output
Connect to ground. Thermal pad must be soldered down in all
applications to properly secure device on the PCB.
Thermal Pad
N/A
—
—
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–0.3
–0.3
MAX
6
UNIT
V
VDD
VI
Supply voltage
Input voltage
INx and SHUTDOWN pins
0.3
V
See Dissipation
Continuous total power dissipation
Ratings
TA
TJ
Operating free-air temperature
Junction temperature
–40
–40
85
ºC
ºC
125
Lead temperature 1.6 mm (1/16 inch) from
case for 10 seconds
ZQV, DRB, DGN
260
150
ºC
°C
Tstg
Storage temperature
–65
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
7.2 ESD Ratings
VALUE
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
±4000
V(ESD)
Electrostatic discharge
V
Charged-device model (CDM), per JEDEC specification JESD22-
C101(2)
±1500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
2.5
NOM
MAX
UNIT
V
VDD
VIH
VIL
VIC
TA
Supply voltage
5.5
High-level input voltage
Low-level input voltage
Common-mode input voltage
Operating free-air temperature
Load impedance
SHUTDOWN
1.15
V
SHUTDOWN
0.5
VDD–0.8
85
V
VDD = 2.5 V, 5.5 V, CMRR ≤ –60 dB
0.5
–40
6.4
V
°C
Ω
ZL
8
7.4 Thermal Information
TPA6205A1
BGA MICROSTAR
JUNIOR
MSOP
THERMAL METRIC(1)
SON
UNIT
PowerPAD
8 PINS
109.5
67.8
8 PINS
8 PINS
57.3
84.0
32.2
3.7
RθJA
Junction-to-ambient thermal resistance
134.4
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
79.8
71.1
5.3
47.6
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
4.7
ψJB
71.0
—
32.2
11.8
47.2
RθJC(bot)
15.9
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
4
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SLOS490C –JULY 2006–REVISED NOVEMBER 2015
7.5 Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
mV
Output offset voltage
(measured differentially)
[VOO
]
VI = 0 V, VDD = 2.5 V to 5.5 V
9
PSRR
CMRR
Power supply rejection ratio
VDD = 2.5 V to 5.5 V
–90
–70
–62
0.3
–70
–65
–55
0.46
dB
VDD = 3.6 V to 5.5 V, VIC = 0.5 V to VDD – 0.8
VDD = 2.5 V, VIC = 0.5 V to 1.7 V
VDD = 5.5 V
Common-mode rejection ratio
dB
RL = 8 Ω, VIN+ = VDD, VIN–
0 V or VIN+ = 0 V, VIN– = VDD
=
VOL
Low-level output voltage
High-level output voltage
VDD = 3.6 V
VDD = 2.5 V
VDD = 5.5 V
VDD = 3.6 V
VDD = 2.5 V
0.22
0.19
5.12
3.28
2.24
V
0.26
4.8
2.1
RL = 8 Ω, VIN+ = VDD, VIN–
0 V or VIN+ = 0 V, VIN– = VDD
=
VOH
V
[IIH
]
High-level input current
Low-level input current
Supply current
VDD = 5.5 V, VI = 5.8 V
VDD = 5.5 V, VI = –0.3 V
1.2
1.2
2
µA
µA
[IIL]
IDD
VDD = 2.5 V to 5.5 V, No load, SHUTDOWN = VIH
1.7
mA
Supply current in shutdown
mode
IDD(SD)
SHUTDOWN = VIL , VDD = 2.5 V to 5.5 V, No load
0.01
0.9
µA
7.6 Operating Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
1.25
MAX
UNIT
VDD = 5 V
THD + N = 1%, f = 1
kHz
PO
Output power
VDD = 3.6 V
VDD = 2.5 V
0.63
W
0.3
VDD = 5 V, PO = 1 W, f = 1 kHz
VDD = 3.6 V, PO = 0.5 W, f = 1 kHz
VDD = 2.5 V, PO = 200 mW, f = 1 kHz
C(BYPASS) = 0.47°F,
0.06%
0.07%
0.08%
Total harmonic distortion plus
noise
THD+N
VDD = 3.6 V to 5.5 V,
Inputs AC-grounded
with CI = 2 F
f = 217 Hz to 2 kHz, VRIPPLE
= 200 mVPP
–87
–82
C(BYPASS) = 0.47 F,
VDD = 2.5 V to 3.6 V,
Inputs AC-grounded
with CI = 2 F
f = 217 Hz to 2 kHz, VRIPPLE
= 200 mVPP
kSVR
Supply ripple rejection ratio
dB
C(BYPASS) = 0.47 F,
VDD = 2.5 V to 5.5 V,
Inputs AC-grounded
with CI = 2 F
f = 40 Hz to 20 kHz, VRIPPLE
= 200 mVPP
≤ –74
SNR
Vn
Signal-to-noise ratio
Output voltage noise
VDD = 5 V, PO= 1 W
f = 20 Hz to 20 kHz
104
17
dB
No weighting
A weighting
VRMS
13
VDD= 2.5 V to 5.5 V,
Resistor tolerance =
0.1%, Gain = 4V/V,
VICM = 200 mVPP
f = 20 Hz to 1 kHz
≤ –85
dB
CMRR
Common-mode rejection ratio
f = 20 Hz to 20 kHz
≤ –74
ZI
Input impedance
2
MΩ
kΩ
dB
ZO
Output impedance
Shutdown attenuation
Shutdown mode
>10
f = 20 Hz to 20 kHz, RF = RI = 20 kΩ
–80
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7.7 Dissipation Ratings
PACKAGE
TA ≤ 25°C POWER
DERATING
FACTOR
TA ≤ 70°C POWER RATING TA ≤ 85°C POWER RATING
RATING
885 mW
2.13 W
2.7 W
ZQV
DGN
DRB
8.8 mW/°C
17.1 mW/°C
21.8 mW/°C
486 mW
1.36 W
1.7 W
354 mW
1.11 W
1.4 W
7.8 Typical Characteristics
Table 1. Table of Graphs
FIGURE
vs Supply voltage
Figure 1
PO
PD
Output power
vs Load resistance
vs Output power
vs Power dissipation
vs Output power
Figure 2, Figure 3
Figure 4, Figure 5
Figure 6
Power dissipation
Maximum ambient temperature
Figure 7, Figure 8
Total harmonic distortion + noise vs Frequency
vs Common-mode input voltage
vs Frequency
Figure 9, Figure 10, Figure 11, Figure 12
Figure 13
Supply voltage rejection ratio
Supply voltage rejection ratio
GSM Power supply rejection
GSM Power supply rejection
Figure 14, Figure 15, Figure 16, Figure 17
vs Common-mode input voltage
vs Time
Figure 18
Figure 19
Figure 20
Figure 21
Figure 22
Figure 23
Figure 24
Figure 25
Figure 26
vs Frequency
vs Frequency
CMRR
Common-mode rejection ratio
vs Common-mode input voltage
vs Frequency
Closed loop gain/phase
Open loop gain/phase
Supply current
vs Frequency
IDD
vs Supply voltage
vs Bypass capacitor
Start-up time
1.4
1.2
1
1.8
1.6
1.4
f = 1 kHz
THD+N = 1%
Gain = 1 V/V
V
= 5 V
DD
1.2
THD+N = 10%
V
= 3.6 V
DD
0.8
0.6
0.4
1
V
= 2.5 V
0.8
DD
0.6
THD+N = 1%
0.4
0.2
0.2
0
0
2.5
3
3.5
4
4.5
5
8
13
18
23
28
32
V
- Supply V oltage - V
R
L
- Load Resistance -
W
DD
Figure 1. Output Power vs Supply Voltage
Figure 2. Output Power vs Load Resistance
6
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1.8
1.6
1.4
1.2
1
0.4
0.35
0.3
f = 1 kHz
V
= 3.6 V
DD
THD+N = 10%
Gain = 1 V/V
8 W
V
= 5 V
DD
0.25
0.2
V
= 3.6 V
DD
0.8
0.6
0.4
V
= 2.5 V
DD
0.15
0.1
16 W
0.05
0
0.2
0
8
13
18
23
28
32
0
0.2
0.4
0.6
0.8
R
L
- Load Resistance - W
P
- Output Power - W
O
Figure 3. Output Power vs Load Resistance
Figure 4. Power Dissipation vs Output Power
90
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
V
= 5 V
DD
80
70
60
50
40
30
8 W
16 W
ZQV Package Only
20
10
0
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8
- Power Dissipation - W
0
0.2 0.4
0.6
0.8
1
1.2 1.4
P
P
- Output Power - W
D
O
Figure 6. Maximum Ambient Temperature vs Power
Dissipation
Figure 5. Power Dissipation vs Output Power
10
10
5
R
L
= 16 W
5
2
f = 1 kHz
C
= 0 to 1 mF
(Bypass)
2.5 V
2
1
0.5
Gain = 1 V/V
3.6 V
1
0.5
5 V
2.5 V
5 V
0.2
0.1
0.2
0.1
3.6 V
0.05
0.05
R
C
= 8 W, f = 1 kHz
L
= 0 to 1 mF
(Bypass)
0.02
0.01
0.02
0.01
Gain = 1 V/V
10 m
100 m
1
2 3
10 m
100 m
- Output Power - W
1
2
P
- Output Power - W
P
O
O
Figure 7. Total Harmonic Distortion + Noise vs Output
Power
Figure 8. Total Harmonic Distortion + Noise vs Output
Power
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10
10
5
V
= 3.6 V
DD
V
= 5 V
DD
5
25 mW
C = 2 mF
I
50 mW
C = 2 mF
I
2
1
2
1
R
C
= 8 W
L
R
C
= 8 W
L
= 0 to 1 mF
(Bypass)
= 0 to 1 mF
(Bypass)
Gain = 1 V/V
0.5
0.5
Gain = 1 V/V
0.2
0.1
0.2
0.1
250 mW
125 mW
0.05
0.05
0.02
0.01
0.02
0.01
1 W
500 mW
0.005
0.005
0.002
0.001
0.002
0.001
20
100 200
1 k 2 k
10 k 20 k
20
50 100 200 500 1 k 2 k 5 k 10 k 20 k
f - Frequency - Hz
f - Frequency - Hz
Figure 9. Total Harmonic Distortion + Noise vs Frequency
Figure 10. Total Harmonic Distortion + Noise vs Frequency
10
10
V
= 2.5 V
5
V
= 3.6 V
DD
5
DD
15 mW
C = 2 mF
I
C = 2 mF
I
2
1
2
1
25 mW
R
C
= 8 W
R
C
= 16 W
L
L
= 0 to 1 mF
= 0 to 1 mF
(Bypass)
(Bypass)
0.5
0.5
Gain = 1 V/V
Gain = 1 V/V
0.2
0.1
0.2
0.1
125 mW
75 mW
0.05
0.05
0.02
0.01
0.02
0.01
200 mW
250 mW
0.005
0.005
0.002
0.001
0.002
0.001
20
50 100 200 500 1 k 2 k 5 k 10 k 20 k
f - Frequency - Hz
20
50 100 200 500 1 k 2 k 5 k 10 k 20 k
f - Frequency - Hz
Figure 11. Total Harmonic Distortion + Noise vs Frequency
Figure 12. Total Harmonic Distortion + Noise vs Frequency
0
10
f = 1 kHz
C = 2 mF
I
-10
-20
-30
-40
-50
-60
-70
-80
P
= 200 mW
R
C
= 8 W
O
L
= 0.47 mF
(Bypass)
V
= 200 mV
p-p
1
Inputs ac-Grounded
Gain = 1 V/V
V
= 2.5 V
DD
V
V
=2. 5 V
DD
0.10
0.01
V
= 5 V
DD
= 3.6 V
DD
-90
V
= 3.6 V
DD
-100
20 50 100 200 500 1 k 2 k 5 k 10 k 20 k
f - Frequency - Hz
0
0.5
1
1.5
2
2.5
3
3.5
V
- Common Mode Input V oltage - V
IC
Figure 13. Total Harmonic Distortion + Noise vs Common-
Mode Input Voltage
Figure 14. Supply Voltage Rejection Ratio vs Frequency
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0
0
Gain = 5 V/V
C = 2 mF
C = 2 mF
I
-10
-10
I
R
L
= 8 W
R
C
= 8 W
-20
-30
-40
-50
-60
-70
-80
L
-20
-30
-40
-50
-60
-70
-80
Inputs Floating
Gain = 1 V/V
= 0.47 mF
(Bypass)
V
= 200 mV
p-p
Inputs ac-Grounded
V
=2. 5 V
DD
V
=2. 5 V
DD
V
= 5 V
DD
V
= 5 V
DD
V
= 3.6 V
DD
V
= 3.6 V
DD
-90
-90
-100
-100
20 50 100 200 500 1 k 2 k 5 k 10 k 20 k
f - Frequency - Hz
20 50 100 200 500 1 k 2 k 5 k 10 k 20 k
f - Frequency - Hz
Figure 15. Supply Voltage Rejection Ratio vs Frequency
Figure 16. Supply Voltage Rejection Ratio vs Frequency
0
-10
V
= 3.6 V
f = 217 Hz
DD
-10
-20
-30
-40
-50
-60
-70
-80
C = 2 mF
I
C = 0.47 mF
(Bypass)
-20
-30
-40
-50
-60
-70
R
= 8 W
R = 8 W
L
L
Inputs ac-Grounded
Gain = 1 V/V
Gain = 1 V/V
V
= 2.5 V
V
= 3.6 V
DD
DD
C
= 0
(Bypass)
C
= 0.47 mF
(Bypass)
C
= 1 mF
(Bypass)
C
= 0.1 mF
(Bypass)
-80
-90
V
= 5 V
-90
DD
-100
20 50 100 200 500 1 k 2 k 5 k 10 k 20 k
f - Frequency - Hz
0
1
2
3
4
5
V
- Common Mode Input V oltage - V
IC
Figure 18. Supply Voltage Rejection Ratio vs Common-
Mode Input Voltage
Figure 17. Supply Voltage Rejection Ratio vs Frequency
0
V
DD
C1
-50
-100
Frequency
217.41 Hz
C1 - Duty
20 %
C1 High
3.598 V
0
-150
V
Shown in Figure 19
DD
C = 2 mF,
I
-50
C1 Pk-Pk
504 mV
C
= 0.47 mF,
(Bypass)
Inputs ac-Grounded
Gain = 1V/V
V
O
-100
-150
Ch1 100 mV/div
Ch4 10 mV/div
2 ms/div
0
200 400 600 800 1k 1.2k 1.4k1.6k1.8k 2k
f - Frequency - Hz
t - Time - ms
Figure 20. GSM Power Supply Rejection vs Frequency
Figure 19. GSM Power Supply Rejection vs Time
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0
0
V
V
= 2.5 V to 5 V
DD
R
= 8 W
-10
-10
-20
-30
-40
-50
-60
-70
-80
L
= 200 mV
IC
p-p
Gain = 1 V/V
-20
-30
-40
R
= 8 W
L
Gain = 1 V/V
V
= 2.5 V
DD
-50
-60
-70
-80
V
= 5 V
DD
-90
-90
V
= 3.6 V
DD
-100
-100
20 50 100 200 500 1 k 2 k 5 k 10 k 20 k
f - Frequency - Hz
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
V
- Common Mode Input Voltage - V
IC
Figure 21. Common-Mode Rejection Ratio vs Frequency
Figure 22. Common-Mode Rejection Ratio vs Common-
Mode Input Voltage
40
30
20
10
220
180
140
100
60
200
150
100
50
200
150
100
50
Phase
V
= 3.6 V
DD
R
= 8 W
L
Gain
Gain
0
-10
-20
-30
-40
-50
20
0
0
-20
-50
-60
-50
-100
Phase
-100
-140
-180
-220
-100
V
= 3.6 V
DD
R
= 8 W
L
-150
-200
-150
-200
-60
-70
Gain = 1 V/V
10 100 1 k
10 k 100 k 1 M
10 M
100
1 k
10 k
100 k
1 M
10 M
f - Frequency - Hz
f - Frequency - Hz
Figure 23. Closed-Loop Gain / Phase vs Frequency
Figure 24. Open-Loop Gain / Phase vs Frequency
6
1.8
1.6
1.4
1.2
5
4
3
2
1
0
1
0.8
0.6
0.4
0.2
0
0
0.5
(Bypass)
1
1.5
- Bypass Capacitor - mF
2
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
C
V
- Supply V oltage - V
DD
Start-Up time is the time it takes (from a low-to-high transition on
SHUTDOWN) for the gain of the amplifier to reach –3 dB of the
final gain
Figure 26. Start-Up Time vs Bypass Capacitor
Figure 25. Supply Current vs Supply Voltage
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8 Parameter Measurement Information
All parameters are measured according to the conditions described in the Specifications section.
9 Detailed Description
9.1 Overview
The TPA6205A1 is a 1.25-W mono fully differential amplifier. The devices operates in the range of 2.5 V to 5.5 V
and with at least 8-Ω impedance load. It's fully differential input allows it to avoid using input coupling capacitors
and improves its RF-immunity.
9.2 Functional Block Diagram
V
DD
R
F
To Battery
C
s
R
I
-
IN-
V
_
+
O+
In From
DAC
R
I
V
O-
+
IN+
R
F
GND
SHUTDOWN
Bias
Circuitry
C BYPASS
(
)
(Optional)
9.3 Feature Description
9.3.1 Fully Differential Amplifiers
The TPA6205A1 is a fully differential amplifier with differential inputs and outputs. The fully differential amplifier
consists of a differential amplifier and a common-mode amplifier. The differential amplifier ensures that the
amplifier outputs a differential voltage that is equal to the differential input times the gain. The common-mode
feedback ensures that the common-mode voltage at the output is biased around VDD/2 regardless of the
common-mode voltage at the input.
9.3.1.1 Advantages of Fully Differential Amplifiers
•
Input coupling capacitors not required: A fully differential amplifier with good CMRR, like the TPA6205A1,
allows the inputs to be biased at voltage other than mid-supply. For example, if a DAC has mid-supply lower
than the mid-supply of the TPA6205A1, the common-mode feedback circuit adjusts for that, and the
TPA6205A1 outputs are still biased at mid-supply of the TPA6205A1. The inputs of the TPA6205A1 can be
biased from 0.5 V to VDD – 0.8 V. If the inputs are biased outside of that range, input coupling capacitors are
required.
•
•
Mid-supply bypass capacitor, C(BYPASS), not required: The fully differential amplifier does not require a bypass
capacitor. This is because any shift in the mid-supply affects both positive and negative channels equally and
cancels at the differential output. However, removing the bypass capacitor slightly worsens power supply
rejection ratio (kSVR), but a slight decrease of kSVR may be acceptable when an additional component can be
eliminated (see Figure 17).
Better RF-immunity: GSM handsets save power by turning on and shutting off the RF transmitter at a rate of
217 Hz. The transmitted signal is picked-up on input and output traces. The fully differential amplifier cancels
the signal much better than the typical audio amplifier.
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Feature Description (continued)
9.3.2 Fully Differential Amplifier Efficiency and Thermal Information
Class-AB amplifiers are inefficient. The primary cause of these inefficiencies is voltage drop across the output
stage transistors. There are two components of the internal voltage drop. One is the headroom or DC voltage
drop that varies inversely to output power. The second component is due to the sinewave nature of the output.
The total voltage drop can be calculated by subtracting the RMS value of the output voltage from VDD. The
internal voltage drop multiplied by the average value of the supply current, IDD(avg), determines the internal power
dissipation of the amplifier.
An easy-to-use equation to calculate efficiency starts Although the voltages and currents for SE and BTL out as
being equal to the ratio of power from the are sinusoidal in the load, currents from the supply power supply to the
power delivered to the load. To are very different between SE and BTL accurately calculate the RMS and
average values of configurations. In an SE application the current power in the load and in the amplifier, the
current and waveform is a half-wave rectified shape, whereas in voltage waveform shapes must first be
understood BTL it is a full-wave rectified waveform. This means (see Figure 27). RMS conversion factors are
different. Keep in mind that for most of the waveform both the push and pull transistors are not on at the same
time, which supports the fact that each amplifier in the BTL device only draws current from the supply for half the
waveform. Equation 1 through Equation 7 are the basis for calculating amplifier efficiency.
V
O
V
(LRMS)
I
DD
I
DD(avg)
Figure 27. Voltage and Current Waveforms for BTL Amplifiers
P
L
Efficiencya BTL amplifier =
PSUP
where
•
VLrms2
RL
P =
L
VP
=
VLRMS
2
•
•
•
•
•
•
PL = Power delivered to load
PSUP = Power drawn from power supply
VLRMS = RMS voltage on BTL load
RL = Load resistance
VP = Peak voltage on BTL load
(1)
(2)
Therefore, PL is calculated by Equation 2:
2
VL
P =
L
2RL
And PSUP is calculated by Equation 3:
PSUP = VDDIDDavg
where
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Feature Description (continued)
•
•
•
PSUP = Power drawn from power supply
IDDavg = Average current drawn from the power supply
VDD = Power supply voltage
(3)
(4)
(5)
IDDavg can be found in Equation 4:
p VP
VP
RL
2VP
1
1 ò0
p
IDDavg =
sin(t) dt = -
´
cos(t)
[
=
0
]
p
RL
p
pRL
Therefore PSUP is calculated by Equation 5:
2VDDVP
PSUP =
pRL
substituting PL and PSUP into Equation 6,
2
VP
2RL
Efficiency of a BTL amplifier =
2VDDVP
pVP
=
4VDD
pRL
where
VP = 2P RL
L
•
(6)
(7)
Therefore:
p 2P RL
L
hBTL
=
4VDD
where
•
ηBTL = Efficiency of a BTL amplifier
Table 2. Efficiency and Maximum Ambient Temperature vs Output Power in 5-V 8- Ω BTL Systems
OUTPUT POWER
(W)
INTERNAL
DISSIPATION (W)
MAX AMBIENT
TEMPERATURE (°C)
EFFICIENCY (%)
POWER FROM SUPPLY (W)
0.25
0.5
1
31.4
44.4
62.8
70.2
0.55
0.62
0.59
0.53
0.75
1.12
1.59
1.78
62
54
58
65
1.25
Table 2 employs Equation 7 to calculate efficiencies for four different output power levels. Note that the efficiency
of the amplifier is quite low for lower power levels and rises sharply as power to the load is increased resulting in
a nearly flat internal power dissipation over the normal operating range. Note that the internal dissipation at full
output power is less than in the half power range. Calculating the efficiency for a specific system is the key to
proper power supply design. For a 1.25-W audio system with 8-Ω loads and a 5-V supply, the maximum draw on
the power supply is almost 1.8 W.
A final point to remember about Class-AB amplifiers is how to manipulate the terms in the efficiency equation to
the utmost advantage when possible. Note that in Equation 7, VDD is in the denominator. This indicates that as
VDD goes down, efficiency goes up.
Equation 8 is a simple formula for calculating the maximum power dissipated, PDmax, may be used for a
differential output application:
2 V2
DD
PDmax
=
2
p RL
(8)
13
PDmax for a 5-V, 8-Ω system is 634 mW.
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The maximum ambient temperature depends on the heat sinking ability of the PCB system. The derating factor
for the 2 mm × 2 mm Microstar Junior package is shown in the dissipation rating table. Converting this to θJA is
shown in Equation 9:
1
1
QJA
=
=
Derating Factor 0.0088
= 113°C / W
(9)
Given θJA, the maximum allowable junction temperature, and the maximum internal dissipation, the maximum
ambient temperature can be calculated with Equation 10. The maximum recommended junction temperature for
the TPA6205A1 is 125°C.
TAMax = TJMax - QJAPDmax
= 125 -113(0.634) = 53.3°C
(10)
Equation 10 shows that the maximum ambient temperature is 53.3°C at maximum power dissipation with a 5-V
supply. Table 2 shows that for most applications no airflow is required to keep junction temperatures in the
specified range. The TPA6205A1 is designed with thermal protection that turns the device off when the junction
temperature surpasses 150°C to prevent damage to the IC. Also, using more resistive than 8-Ω packages, it is
good practice minimize the speakers dramatically increases the thermal performance by reducing the output
current.
9.3.3 Differential Output Versus Single-Ended Output
Figure 28 shows a Class-AB audio power amplifier (APA) in a fully differential configuration. The TPA6205A1
amplifier has differential outputs driving both ends of the load. There are several potential benefits to this
differential drive configuration, but initially consider power to the load. The differential drive to the speaker means
that as one side is slewing up, the other side is slewing down, and vice versa. This in effect doubles the voltage
swing on the load as compared to a ground referenced load. Plugging 2 × VO(PP) into the power equation, where
voltage is squared, yields 4× the output power from the same supply rail and load impedance (see Equation 11).
VO PP
(
)
V rms
=
(
)
2 2
2
V
(rms)
Power =
RL
(11)
V
DD
V
O(PP)
2x V
O(PP)
R
L
V
DD
–V
O(PP)
Figure 28. Differential Output Configuration
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In a typical wireless handset operating at 3.6 V, bridging raises the power into an 8-Ω speaker from a singled-
ended (SE, ground reference) limit of 200 mW to 800 mW. In sound power that is a 6-dB improvement—which is
loudness that can be heard. In addition to increased power there are frequency response concerns. Consider the
single-supply SE configuration shown in Figure 29. A coupling capacitor is required to block the DC offset voltage
from reaching the load. This capacitor can be quite large (approximately 33 μF to 1000 μF) so it tends to be
expensive, heavy, occupy valuable PCB area, and have the additional drawback of limiting low-frequency
performance of the system. This frequency-limiting effect is due to the high pass filter network created with the
speaker impedance and the coupling capacitance and is calculated with Equation 12.
1
fc =
2pRLCC
(12)
For example, a 68-μF capacitor with an 8-Ω speaker would attenuate low frequencies below 293 Hz. The BTL
configuration cancels the DC offsets, which eliminates the need for the blocking capacitors. Low-frequency
performance is then limited only by the input network and speaker response. Cost and PCB space are also
minimized by eliminating the bulky coupling capacitor.
V
DD
V
O(PP)
C
C
V
O(PP)
R
L
–3 dB
f
c
Figure 29. Single-Ended Output and Frequency Response
Increasing power to the load does carry a penalty of increased internal power dissipation. The increased
dissipation is understandable considering that the BTL configuration produces 4× the output power of the SE
configuration.
9.4 Device Functional Modes
9.4.1 Summing Input Signals With The TPA6205A1
Most wireless phones or PDAs need to sum signals at the audio power amplifier or just have two signal sources
that need separate gain. The TPA6205A1 makes it easy to sum signals or use separate signal sources with
different gains. Many phones now use the same speaker for the earpiece and ringer, where the wireless phone
would require a much lower gain for the phone earpiece than for the ringer. PDAs and phones that have stereo
headphones require summing of the right and left channels to output the stereo signal to the mono speaker.
9.4.1.1 Summing Two Differential Input Signals
Two extra resistors are needed for summing differential signals (a total of 10 components). The gain for each
input source can be set independently (see Equation 13 and Equation 14, and Figure 30).
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Device Functional Modes (continued)
VO
RF
R
V
V
æ
ö
Gain 1=
Gain 2 =
= -
ç
÷
V
I1 è
ø
I1
(13)
(14)
VO
RF
R
V
V
æ
ç
ö
= -
÷
V
I2 è
ø
I2
C
C
R
R
I2
I2
-
Differential
Input 2
I2
V
V
I2
DD
+
R
F
To Battery
C
S
C
R
R
I1
I1
-
IN-
O+
_
+
Differential
Input 1
V
C
O-
I1
+
I1
IN+
R
F
GND
SHUTDOWN
Bias
Circuitry
C BYPASS
(
)
(Optional)
Figure 30. Application Schematic With TPA6205A1 Summing Two Differential Inputs
9.4.1.2 Summing a Differential Input Signal and a Single-Ended Input Signal
Figure 31 shows how to sum a differential input signal and a single-ended input signal. Ground noise can couple
in through IN+ with this method. It is better to use differential inputs. To assure that each input is balanced, the
single-ended input must be driven by a low-impedance source even if the input is not in use. Both input nodes
must see the same impedance for optimum performance, thus the use of RP and CP.
VO
RF
R
V
V
æ
ö
Gain 1=
= -
ç
÷
V
I1 è
ø
I1
(15)
(16)
VO
RF
R
V
V
æ
ö
Gain 2 =
= -
ç
÷
V
I2 è
ø
I2
9.4.1.3 Summing Two Single-Ended Input Signals
Four resistors and three capacitors are needed for summing single-ended input signals. The gain and corner
frequencies (fc1 and fc2) for each input source can be set independently. Resistor, RP, and capacitor, CP, are
needed on the IN+ terminal to match the impedance on the IN- terminal. The single-ended inputs must be driven
by low impedance sources even if one of the inputs is not outputting an AC signal.
Vo
2´150 kW
Gain 1 =
=
V
RI2
I1
(17)
(18)
(19)
Vo
2´150 kW
Gain 2 =
=
V
RI2
I2
1
CI1
=
2pRI1FC1
1
CI2
=
2pRI2FC2
(20)
(21)
CP = CI1 + CI2
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Device Functional Modes (continued)
RI1 ´ RI2
RP
=
RI1 + RI2
(22)
C
I2
R
R
I2
V
DD
Single Ended
Input 2
R
F
To Battery
C
I1
C
s
I1
Single Ended
Input 1
IN-
_
+
V
O+
R
V
P
O-
IN+
C
P
R
F
GND
SHUTDOWN
C BYPASS
Bias
Circuitry
(
)
(Optional)
Figure 31. Application Schematic With TPA6205A1 Summing Two Single-Ended Inputs
9.4.2 Shutdown Mode
The TPA6205A1 can be put in shutdown mode when asserting SHUTDOWN pin to a logic LOW. While in
shutdown mode, the device output stage is turned off, making the current consumption very low. The device exits
shutdown mode when a HIGH logic level is applied to SHUTDOWN pin. SHUTDOWN pin is 1.8-V compatible.
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10 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information
These typical connection diagrams highlight the required external components and system level connections for
proper operation of the device in several popular cases. Each of these configurations can be realized using the
Evaluation Modules (EVMs) for the device. These flexible modules allow full evaluation of the device in the most
common modes of operation. Any design variation can be supported by TI through schematic and layout reviews.
Visit http://e2e.ti.com for design assistance and join the audio amplifier discussion forum for additional
information.
10.2 Typical Applications
Figure 32 through Figure 31 show application schematics for differential and single-ended inputs.
10.2.1 TPA6205A1 With Differential Input
The TPA6205A1 can be used with differential input without input capacitors. This section describes the design
considerations for this application.
V
DD
R
F
To Battery
C
s
R
I
-
IN-
_
+
V
O+
In From
DAC
V
R
I
O-
+
IN+
R
F
GND
SHUTDOWN
Bias
Circuitry
C BYPASS
(
)
(Optional)
Figure 32. Typical Differential Input Application Schematic
10.2.1.1 Design Requirements
Table 3 lists the design parameters of the device.
Table 3. Design Parameters
PARAMETER
EXAMPLE VALUE
5 V
Power Supply
High > 2 V
Low < 0.8 V
8 Ω
Shutdown Input
Speaker
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10.2.1.2 Detailed Design Procedure
10.2.1.2.1 Selecting Components
Typical values are shown in Table 4.
Table 4. Typical Component Values
COMPONENT
VALUE
10 kΩ
RI
RF
10 kΩ
(1)
C(BYPASS)
0.22 µF
1 µF
CS
CI
0.22 µF
(1) C(BYPASS) is optional
10.2.1.2.1.1 Resistors (RF and RI)
The input (RI) and feedback resistors (RF) set the gain of the amplifier according to Equation 23.
Gain - RF / RI
(23)
RF and RI should range from 1 kΩ to 100 kΩ. Most graphs were taken with RF = RI = 20 kΩ.
Resistor matching is very important in fully differential amplifiers. The balance of the output on the reference
voltage depends on matched ratios of the resistors. CMRR, PSRR, and the cancellation of the second harmonic
distortion diminishes if resistor mismatch occurs. Therefore, it is recommended to use 1% tolerance resistors or
better to keep the performance optimized.
10.2.1.2.1.2 Bypass Capacitor (CBYPASS) and Start-Up Time
The internal voltage divider at the BYPASS pin of this device sets a mid-supply voltage for internal references
and sets the output common mode voltage to VDD/2. Adding a capacitor to this pin filters any noise into this pin
and increases the kSVR. C(BYPASS)also determines the rise time of VO+ and VO– when the device is taken out of
shutdown. The larger the capacitor, the slower the rise time. Although the output rise time depends on the
bypass capacitor value, the device passes audio 4 μs after taken out of shutdown and the gain is slowly ramped
up based on C(BYPASS)
.
To minimize pops and clicks, design the circuit so the impedance (resistance and capacitance) detected by both
inputs, IN+ and IN–, is equal.
10.2.1.2.1.3 Input Capacitor (CI)
The TPA6205A1 does not require input coupling capacitors if using a differential input source that is biased from
0.5 V to VDD – 0.8 V. Use 1% tolerance or better gain-setting resistors if not using input coupling capacitors.
In the single-ended input application an input capacitor, CI, is required to allow the amplifier to bias the input
signal to the proper DC level. In this case, CI and RI form a high-pass filter with the corner frequency determined
in Equation 24.
1
fc =
2pRICI
(24)
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–3 dB
f
c
Figure 33. CI and RI High-Pass Filter Cutoff Frequency
The value of CI is important to consider as it directly affects the bass (low frequency) performance of the circuit.
Consider the example where RI is 10 kΩ and the specification calls for a flat bass response down to 100 Hz.
Equation 24 is reconfigured as Equation 25.
1
CI =
2pRIfc
(25)
In this example, CI is 0.16 μF, so one would likely choose a value in the range of 0.22 μF to 0.47 μF. A further
consideration for this capacitor is the leakage path from the input source through the input network
(RI , CI) and the feedback resistor (RF ) to the load. This leakage current creates a DC offset voltage at the input
to the amplifier that reduces useful headroom, especially in high gain applications. For this reason, a ceramic
capacitor is the best choice. When polarized capacitors are used, the positive side of the capacitor should face
the amplifier input in most applications, as the dc level there is held at VDD/2, which is likely higher than the
source dc level. It is important to confirm the capacitor polarity in the application.
10.2.1.2.1.4 Decoupling Capacitor (CS)
The TPA6205A1 is a high-performance CMOS audio amplifier that requires adequate power supply decoupling to
ensure the output total harmonic distortion (THD) is as low as possible. Power supply decoupling also prevents
oscillations for long lead lengths between the amplifier and the speaker. For higher frequency transients, spikes,
or digital hash on the line, a good low equivalent-series-resistance (ESR) ceramic capacitor, typically 0.1 μF to 1
μF, placed as close as possible to the device VDD lead works best. For filtering lower frequency noise signals, a
10-μF or greater capacitor placed near the audio power amplifier also helps, but is not required in most
applications because of the high PSRR of this device.
10.2.1.2.2 Using Low-ESR Capacitors
Low-ESR capacitors are recommended throughout this applications section. A real (as opposed to ideal)
capacitor can be modeled simply as a resistor in series with an ideal capacitor. The voltage drop across this
resistor minimizes the beneficial effects of the capacitor in the circuit. The lower the equivalent value of this
resistance the more the real capacitor behaves like an ideal capacitor.
20
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SLOS490C –JULY 2006–REVISED NOVEMBER 2015
10.2.1.3 Application Curves
1.8
1.6
1.4
1.2
1.8
1.6
1.4
1.2
THD+N = 10%
1
1
0.8
0.8
0.6
0.4
0.2
THD+N = 1%
0.6
0.4
0.2
0
0
2.5
3
3.5
4
4.5
5
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
V
- Supply V oltage - V
V
DD
- Supply V oltage - V
DD
Figure 34. Output Power vs Supply Voltage
Figure 35. Supply Current vs Supply Voltage
10.2.2 TPA6205A1 With Differential Input and Input Capacitors
The TPA6205A1 supports differential input operation with input capacitors. This section describes the design
considerations for this application.
V
DD
R
F
To Battery
C
C
s
I
I
R
I
IN-
-
_
+
V
O+
IN
R
I
V
O-
IN+
+
C
R
F
GND
SHUTDOWN
Bias
Circuitry
C BYPASS
(
)
(Optional)
Figure 36. Differential Input Application Schematic Optimized With Input Capacitors
10.2.2.1 Design Requirements
Refer to the Design Requirements.
10.2.2.2 Detailed Design Procedure
Refer to the Detailed Design Procedure.
10.2.2.3 Application Curves
Refer to the Application Curves.
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10.2.3 TPA6205A1 With Single-Ended Input
The TPA6205A1 can be used with single-ended inputs, using Input capacitors. This section describes the design
considerations for this application.
V
DD
R
F
To Battery
C
I
C
s
R
I
IN-
_
+
V
O+
IN
R
V
I
O-
IN+
C
I
R
F
GND
SHUTDOWN
C BYPASS
Bias
Circuitry
(
)
(Optional)
Figure 37. Single-Ended Input Application Schematic
10.2.3.1 Design Requirements
Refer to the Design Requirements.
10.2.3.2 Detailed Design Procedure
Refer to the Detailed Design Procedure.
10.2.3.3 Application Curves
Refer to the Application Curves.
11 Power Supply Recommendations
The TPA6205A1 is designed to operate from an input voltage supply range between 2.5-V and 5.5-V. Therefore,
the output voltage range of power supply should be within this range and well regulated. The current capability of
upper power should not exceed the maximum current limit of the power switch.
11.1 Power Supply Decoupling Capacitors
The TPA6205A1 requires adequate power supply decoupling to ensure a high efficiency operation with low total
harmonic distortion (THD). Place a low equivalent-series-resistance (ESR) ceramic capacitor, typically 0.1 μF,
within 2 mm of the VDD pin. This choice of capacitor and placement helps with higher frequency transients,
spikes, or digital hash on the line. In addition to the 0.1 μF ceramic capacitor, is recommended to place a 2.2 μF
to 10 μF capacitor on the VDD supply trace. This larger capacitor acts as a charge reservoir, providing energy
faster than the board supply, thus helping to prevent any drop in the supply voltage.
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SLOS490C –JULY 2006–REVISED NOVEMBER 2015
12 Layout
12.1 Layout Guidelines
Placing the decoupling capacitors as close as possible to the device is important for the efficiency of the class-D
amplifier. Any resistance or inductance in the trace between the device and the capacitor can cause a loss in
efficiency.
For the DRB (QFN/SON) and DGN (MSOP) to presence of voids within the exposed thermal pad
interconnection. Total elimination is difficult, but the design of the exposed pad stencil is key. The stencil design
proposed in the Texas Instruments application note QFN/SON PCB Attachment (SLUA271) enables out-gassing
of the solder paste during reflow as well as regulating the finished solder thickness. Typically the solder paste
coverage is approximately 50% of the pad area.
In making the pad size for the BGA balls, it is recommended that the layout use soldermask-defined (SMD) land.
With this method, the copper pad is made larger than the desired land area, and the opening size is defined by
the opening in the solder mask material. The advantages normally associated with this technique include more
closely controlled size and better copper adhesion to the laminate. Increased copper also increases the thermal
performance of the IC. Better size control is the result of photo imaging the stencils for masks. Small plated vias
should be placed near the center ball connecting ball B2 to the ground plane. Added plated vias and ground
plane act as a heatsink and increase the thermal performance of the device. Figure 38 shows the appropriate
diameters for a 2 mm × 2 mm MicroStar Junior™ BGA layout.
It is very important to keep the TPA6205A1 external components very close to the TPA6205A1 to limit noise
pickup. The TPA6205A1 layout is shown in the next section as a layout example.
0.38 mm
0.25 mm
0.28 mm
C1
B1
A1
VIAS to Ground Plane
C2
B2
Solder Mask
C3
B3
A3
Paste Mask (Stencil)
Copper Trace
Figure 38. MicroStar Junior™ BGA Recommended Layout
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www.ti.com
12.2 Layout Example
SHUTDOWN
OUT -
C1
C2
C3
B1
B2
B3
A1
A3
Decoupling capacitor
placed as close as
possible to the device
+
IN
IN
TPA6205A1
OUT +
-
Top Layer Ground Plane
Top Layer Traces
Via to Power Supply
Pad to Top Layer Ground Plane
Via to Bottom Layer Ground Plane
Figure 39. TPA6205A1 BGA Layout
OUT -
SHUTDOWN
1
2
8
7
Decoupling capacitor
placed as close as
possible to the device
3
4
6
5
+
IN
IN
OUT +
-
TPA6205A1
Top Layer Ground Plane
Pad to Top Layer Ground Plane
Via to Bottom Layer Ground Plane
Top Layer Traces
Thermal Pad
Via to Power Supply
Figure 40. TPA6205A1 HVSSOP Layout
24
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SLOS490C –JULY 2006–REVISED NOVEMBER 2015
Layout Example (continued)
SHUTDOWN
8
1
2
3
4
OUT -
Decoupling capacitor
placed as close as
possible to the device
7
6
IN
IN
+
-
5
OUT +
TPA6205A1
Top Layer Ground Plane
Top Layer Traces
Thermal Pad
Pad to Top Layer Ground Plane
Via to Bottom Ground Plane
Via to Power Supply
Figure 41. TPA6205A1 VSON Layout
Copyright © 2006–2015, Texas Instruments Incorporated
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www.ti.com
13 Device and Documentation Support
13.1 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
13.2 Trademarks
MicroStar Junior, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
13.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
13.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
31-Mar-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
HPA00801DRBR
TPA6205A1DGN
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
LIFEBUY
SON
HVSSOP
HVSSOP
HVSSOP
HVSSOP
SON
DRB
DGN
DGN
DGN
DGN
DRB
DRB
NMB
ZQV
8
8
8
8
8
8
8
8
8
3000 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
AAOI
AAPI
AAPI
AAPI
AAPI
AAOI
AAOI
AANI
AANI
80
80
RoHS & Green NIPDAU | NIPDAUAG Level-1-260C-UNLIM
RoHS & Green NIPDAU Level-1-260C-UNLIM
TPA6205A1DGNG4
TPA6205A1DGNR
TPA6205A1DGNRG4
TPA6205A1DRBR
TPA6205A1DRBT
TPA6205A1NMBR
TPA6205A1ZQVR
2500 RoHS & Green NIPDAU | NIPDAUAG Level-1-260C-UNLIM
2500 RoHS & Green
3000 RoHS & Green
NIPDAU
NIPDAU
NIPDAU
SNAGCU
SNAGCU
Level-1-260C-UNLIM
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
SON
250
RoHS & Green
NFBGA
2500 RoHS & Green
2500 RoHS & Green
BGA
MICROSTAR
JUNIOR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
31-Mar-2021
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
1-Apr-2021
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPA6205A1DGNR
TPA6205A1DGNR
TPA6205A1DGNR
TPA6205A1DRBR
TPA6205A1DRBT
TPA6205A1DRBT
TPA6205A1NMBR
TPA6205A1ZQVR
HVSSOP DGN
HVSSOP DGN
HVSSOP DGN
8
8
8
8
8
8
8
8
2500
2500
2500
3000
250
330.0
330.0
330.0
330.0
180.0
180.0
330.0
330.0
12.4
12.4
12.4
12.4
12.4
12.4
8.4
5.3
5.3
5.3
3.3
3.3
3.3
2.3
2.3
3.4
3.4
3.4
3.3
3.3
3.3
2.3
2.3
1.4
1.4
1.4
1.1
1.1
1.1
1.4
1.4
8.0
8.0
8.0
8.0
8.0
8.0
4.0
4.0
12.0
12.0
12.0
12.0
12.0
12.0
8.0
Q1
Q1
Q1
Q2
Q2
Q2
Q1
Q1
SON
SON
DRB
DRB
DRB
NMB
ZQV
SON
250
NFBGA
2500
2500
BGA MI
CROSTA
R JUNI
OR
8.4
8.0
TPA6205A1ZQVR
BGA MI
CROSTA
R JUNI
OR
ZQV
8
2500
330.0
8.4
2.3
2.3
1.4
4.0
8.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
1-Apr-2021
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPA6205A1DGNR
TPA6205A1DGNR
TPA6205A1DGNR
TPA6205A1DRBR
TPA6205A1DRBT
TPA6205A1DRBT
TPA6205A1NMBR
TPA6205A1ZQVR
HVSSOP
HVSSOP
HVSSOP
SON
DGN
DGN
DGN
DRB
DRB
DRB
NMB
ZQV
8
8
8
8
8
8
8
8
2500
2500
2500
3000
250
358.0
364.0
853.0
367.0
210.0
210.0
338.1
338.1
335.0
364.0
449.0
367.0
185.0
185.0
338.1
338.1
35.0
27.0
35.0
35.0
35.0
35.0
20.6
20.6
SON
SON
250
NFBGA
2500
2500
BGA MICROSTAR
JUNIOR
TPA6205A1ZQVR
BGA MICROSTAR
JUNIOR
ZQV
8
2500
350.0
350.0
43.0
Pack Materials-Page 2
PACKAGE OUTLINE
NFBGA - 1 mm max height
PLASTIC BALL GRID ARRAY
NMB0008A
A
2.1
1.9
B
BALL A1 CORNER
2.1
1.9
1 MAX
C
SEATING PLANE
0.12 C
BALL TYP
0.25
0.15
1
TYP
0.5 TYP
C
0.5 TYP
0.5 TYP
0.5 TYP
SYMM
1
B
A
TYP
0.35
0.25
8X Ø
1
2
3
0.15
0.05
C A B
C
SYMM
4224891/A 04/2019
NanoFree is a trademark of Texas Instruments.
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
EXAMPLE BOARD LAYOUT
NFBGA - 1 mm max height
PLASTIC BALL GRID ARRAY
NMB0008A
(0.5) TYP
1
2
3
(0.5) TYP
A
B
SYMM
8X (Ø0.25)
C
SYMM
LAND PATTERN EXAMPLE
SCALE: 25X
0.05 MIN
ALL AROUND
0.05 MAX
ALL AROUND
METAL UNDER
SOLDER MASK
EXPOSED
METAL
(Ø 0.25)
SOLDER MASK
OPENING
EXPOSED
METAL
(Ø 0.25)
METAL
SOLDER MASK
OPENING
NON- SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
NOT TO SCALE
4224891/A 04/2019
NOTES: (continued)
3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints. Refer to Texas Instruments
Literature number SNVA009 (www.ti.com/lit/snva009).
www.ti.com
EXAMPLE STENCIL DESIGN
NFBGA - 1 mm max height
PLASTIC BALL GRID ARRAY
NMB0008A
(0.5) TYP
1
2
3
(0.5) TYP
A
B
SYMM
(R0.05)
C
8X ( 0.25)
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.100 mm THICK STENCIL
SCALE: 25X
4224891/A 04/2019
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
www.ti.com
PACKAGE OUTLINE
DRB0008A
VSON - 1 mm max height
SCALE 4.000
PLASTIC SMALL OUTLINE - NO LEAD
3.1
2.9
B
A
PIN 1 INDEX AREA
3.1
2.9
C
1 MAX
SEATING PLANE
0.08 C
0.05
0.00
DIM A
OPT 1
(0.1)
OPT 2
(0.2)
1.5 0.1
4X (0.23)
EXPOSED
THERMAL PAD
(DIM A) TYP
4
5
2X
1.95
1.75 0.1
8
1
6X 0.65
0.37
0.25
8X
PIN 1 ID
0.1
C A B
C
(OPTIONAL)
(0.65)
0.05
0.5
0.3
8X
4218875/A 01/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
DRB0008A
VSON - 1 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(1.5)
(0.65)
SYMM
8X (0.6)
(0.825)
8
8X (0.31)
1
SYMM
(1.75)
(0.625)
6X (0.65)
4
5
(R0.05) TYP
(
0.2) VIA
(0.23)
TYP
(0.5)
(2.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:20X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
EXPOSED
METAL
EXPOSED
METAL
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4218875/A 01/2018
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
DRB0008A
VSON - 1 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(0.65)
4X (0.23)
SYMM
METAL
TYP
8X (0.6)
4X
(0.725)
8
1
8X (0.31)
(2.674)
(1.55)
SYMM
6X (0.65)
4
5
(R0.05) TYP
(1.34)
(2.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD
84% PRINTED SOLDER COVERAGE BY AREA
SCALE:25X
4218875/A 01/2018
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
GENERIC PACKAGE VIEW
DGN 8
3 x 3, 0.65 mm pitch
PowerPAD VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4225482/A
www.ti.com
PACKAGE OUTLINE
DGN0008D
PowerPADTM VSSOP - 1.1 mm max height
S
C
A
L
E
4
.
0
0
0
SMALL OUTLINE PACKAGE
C
5.05
4.75
TYP
A
0.1 C
SEATING
PLANE
PIN 1 INDEX AREA
6X 0.65
8
1
2X
3.1
2.9
1.95
NOTE 3
4
5
0.38
8X
0.25
3.1
2.9
0.13
C A B
B
NOTE 4
0.23
0.13
SEE DETAIL A
EXPOSED THERMAL PAD
4
5
0.25
GAGE PLANE
1.89
1.63
9
1.1 MAX
8
0.15
0.05
1
0.7
0.4
0 -8
A
20
DETAIL A
TYPICAL
1.57
1.28
4225481/A 11/2019
PowerPAD is a trademark of Texas Instruments.
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-187.
www.ti.com
EXAMPLE BOARD LAYOUT
DGN0008D
PowerPADTM VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE
(2)
NOTE 9
METAL COVERED
BY SOLDER MASK
(1.57)
SOLDER MASK
DEFINED PAD
SYMM
8X (1.4)
(R0.05) TYP
8
8X (0.45)
1
(3)
NOTE 9
SYMM
(1.89)
9
(1.22)
6X (0.65)
5
4
(
0.2) TYP
VIA
SEE DETAILS
(0.55)
(4.4)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 15X
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
METAL
EXPOSED METAL
EXPOSED METAL
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
NON-SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
15.000
(PREFERRED)
SOLDER MASK DETAILS
4225481/A 11/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
8. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
9. Size of metal pad may vary due to creepage requirement.
www.ti.com
EXAMPLE STENCIL DESIGN
DGN0008D
PowerPADTM VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE
(1.57)
BASED ON
0.125 THICK
STENCIL
SYMM
(R0.05) TYP
8X (1.4)
8
1
8X (0.45)
(1.89)
SYMM
BASED ON
0.125 THICK
STENCIL
6X (0.65)
5
4
METAL COVERED
BY SOLDER MASK
SEE TABLE FOR
DIFFERENT OPENINGS
FOR OTHER STENCIL
THICKNESSES
(4.4)
SOLDER PASTE EXAMPLE
EXPOSED PAD 9:
100% PRINTED SOLDER COVERAGE BY AREA
SCALE: 15X
STENCIL
THICKNESS
SOLDER STENCIL
OPENING
0.1
1.76 X 2.11
1.57 X 1.89 (SHOWN)
1.43 X 1.73
0.125
0.15
0.175
1.33 X 1.60
4225481/A 11/2019
NOTES: (continued)
10. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
11. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
DGN0008G
PowerPADTM VSSOP - 1.1 mm max height
S
C
A
L
E
4
.
0
0
0
SMALL OUTLINE PACKAGE
C
5.05
4.75
TYP
A
0.1 C
SEATING
PLANE
PIN 1 INDEX AREA
6X 0.65
8
1
2X
3.1
2.9
1.95
NOTE 3
4
5
0.38
8X
0.25
3.1
2.9
0.13
C A B
B
NOTE 4
0.23
0.13
SEE DETAIL A
EXPOSED THERMAL PAD
4
5
0.25
GAGE PLANE
2.15
1.95
9
1.1 MAX
8
0.15
0.05
1
0.7
0.4
0 -8
A
20
DETAIL A
TYPICAL
1.846
1.646
4225480/A 11/2019
PowerPAD is a trademark of Texas Instruments.
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-187.
www.ti.com
EXAMPLE BOARD LAYOUT
DGN0008G
PowerPADTM VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE
(2)
NOTE 9
(1.846)
SYMM
METAL COVERED
BY SOLDER MASK
SOLDER MASK
DEFINED PAD
8X (1.4)
(R0.05) TYP
8
8X (0.45)
1
(3)
NOTE 9
SYMM
9
(2.15)
(1.22)
6X (0.65)
5
4
(
0.2) TYP
VIA
SEE DETAILS
(0.55)
(4.4)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 15X
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
METAL
EXPOSED METAL
EXPOSED METAL
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
NON-SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
15.000
(PREFERRED)
SOLDER MASK DETAILS
4225480/A 11/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
8. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
9. Size of metal pad may vary due to creepage requirement.
www.ti.com
EXAMPLE STENCIL DESIGN
DGN0008G
PowerPADTM VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE
(1.846)
BASED ON
0.125 THICK
STENCIL
SYMM
(R0.05) TYP
8X (1.4)
8
1
8X (0.45)
(2.15)
SYMM
BASED ON
0.125 THICK
STENCIL
6X (0.65)
5
4
METAL COVERED
BY SOLDER MASK
SEE TABLE FOR
DIFFERENT OPENINGS
FOR OTHER STENCIL
THICKNESSES
(4.4)
SOLDER PASTE EXAMPLE
EXPOSED PAD 9:
100% PRINTED SOLDER COVERAGE BY AREA
SCALE: 15X
STENCIL
THICKNESS
SOLDER STENCIL
OPENING
0.1
2.06 X 2.40
1.846 X 2.15 (SHOWN)
1.69 X 1.96
0.125
0.15
0.175
1.56 X 1.82
4225480/A 11/2019
NOTES: (continued)
10. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
11. Board assembly site may have different recommendations for stencil design.
www.ti.com
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
permission to use these resources only for development of an application that uses the TI products described in the resource. Other
reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party
intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages,
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TI’s products are provided subject to TI’s Terms of Sale (https:www.ti.com/legal/termsofsale.html) or other applicable terms available either
on ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s
applicable warranties or warranty disclaimers for TI products.IMPORTANT NOTICE
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2021, Texas Instruments Incorporated
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