TPD1E05U06_V01 [TI]
TPDxE05U06 1, 4, 6 Channel ESD Protection Device for Super-Speed (Up to 6 Gbps) Interface;
| 型号： | TPD1E05U06_V01 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | TPDxE05U06 1, 4, 6 Channel ESD Protection Device for Super-Speed (Up to 6 Gbps) Interface 光电二极管 |
| 文件： | 总36页 (文件大小：3073K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPD1E05U06, TPD4E05U06, TPD6E05U06
SLVSBO7M – DECEMBER 2012 – REVISED DECEMBER 2021
TPDxE05U06 1, 4, 6 Channel ESD Protection Device
for Super-Speed (Up to 6 Gbps) Interface
1 Features
3 Description
•
IEC 61000-4-2 level 4 ESD protection
– ±12-kV contact discharge
The TPDxE05U06 is a family of unidirectional
Transient Voltage Suppressor (TVS) based
Electrostatic Discharge (ESD) protection diodes with
ultra-low capacitance. Each device can dissipate ESD
strikes above the maximum level specified by the IEC
61000-4-2 international standard. The TPDxE05U06s
ultra-low loading capacitance makes it ideal for
protecting any high-speed signal pins.
– ±15-kV air gap discharge
IEC 61000-4-4 EFT protection
– 80 A (5/50 ns)
IEC 61000-4-5 surge protection
– 2.5 A (8/20 µs)
IO capacitance 0.42 pF to 0.5 pF (typical)
DC breakdown voltage 6.5 V (minimum)
Ultra low leakage current 10 nA (maximum)
Low ESD clamping voltage
Industrial temperature range: –40°C to +125°C
Easy straight-through routing packages
Industry standard SOD-523 package
(0.8 mm × 1.2 mm)
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Typical applications for TPDxE05U06 includes high
speed signal lines in HDMI 1.4b, HDMI 2.0, USB 3.0,
MHL, LVDS, DisplayPort, PCI-Express®, eSata, and
V-by-One® HS.
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
0.60 mm × 1.00 mm
0.80 mm × 1.20 mm
2.50 mm × 1.00 mm
3.50 mm × 1.35 mm
X1SON (2)
TPD1E05U06
2 Applications
SOD-523 (2)
USON (10)
USON (14)
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HDMI 1.4b
HDMI 2.0
USB 3.0
TPD4E05U06
TPD6E05U06
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
MHL
LVDS interfaces
DisplayPort
PCI-express®
eSata interfaces
V-by-One® HS
1
2
TPD4E05U06
4
5
3
8
D0+
D0-
D1+
D1-
D2+
D1+
D1-
D2+
D2-
D2-
GND
CLK+
TPD4E05U06 Functional Block Diagram
CLK-
1
2
TPD4E05U06
4
5
3
8
Simplified Schematic
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPD1E05U06, TPD4E05U06, TPD6E05U06
SLVSBO7M – DECEMBER 2012 – REVISED DECEMBER 2021
www.ti.com
Table of Contents
1 Features............................................................................1
2 Applications.....................................................................1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................4
6 Specifications.................................................................. 6
Absolute Maximum Ratings.............................................. 6
6.1 ESD Ratings—JEDEC Specification...........................6
6.2 ESD Ratings—IEC Specification................................ 6
Recommended Operating Conditions...............................6
6.3 Thermal Information....................................................7
6.4 Electrical Characteristics.............................................7
6.5 Typical Characteristics................................................9
7 Detailed Description......................................................11
7.1 Overview................................................................... 11
7.2 Functional Block Diagram......................................... 11
7.3 Feature Description...................................................12
7.4 Device Functional Modes..........................................12
8 Application and Implementation..................................13
8.1 Application Information............................................. 13
8.2 Typical Applications.................................................. 13
9 Power Supply Recommendations................................16
10 Layout...........................................................................17
10.1 Layout Guidelines................................................... 17
10.2 Layout Example...................................................... 17
11 Device and Documentation Support..........................19
11.1 Documentation Support.......................................... 19
11.2 Receiving Notification of Documentation Updates..19
11.3 Support Resources................................................. 19
11.4 Trademarks............................................................. 19
11.5 Electrostatic Discharge Caution..............................19
11.6 Glossary..................................................................19
12 Mechanical, Packaging, and Orderable
Information.................................................................... 19
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision L (January 2017) to Revision M (December 2021)
Page
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•
•
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•
Updated the numbering format for tables, figures, and cross-references throughout the document..................1
Updated the Features section to include SOD-523 package information...........................................................1
Added the DYA package to the Device Information table...................................................................................1
Added the DYA package to the Pin Configuration and Functions section..........................................................4
Changed the DC breakdown voltage from 6 V minimum to 6.5 V minimum.....................................................12
Changed the reverse standoff voltage from 5 V minimum to 5.5 V minimum...................................................12
Updated the Related Documentation section................................................................................................... 19
Changes from Revision K (November 2016) to Revision L (January 2017)
Page
Updated DPY pinout image................................................................................................................................ 4
Updated title from TPD4E05U06 to TPD6E05U06 in Figure 7-3 ..................................................................... 11
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Changes from Revision J (March 2016) to Revision K (November 2016)
Page
•
Changed min value of VBR from 6 V to 6.5 V in the Electrical Characteristics table...........................................6
Changes from Revision I (June 2015) to Revision J (March 2016)
Page
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Replaced all instances of X2SON with X1SON .................................................................................................1
Update the Pin Functions table ..........................................................................................................................4
Added the Power Supply Recommendations section.......................................................................................16
Changes from Revision H (May 2015) to Revision I (June 2015)
Page
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Added trademarks ............................................................................................................................................. 1
Corrected TPD6E05U06 Pin 13 name................................................................................................................4
Corrected TLP definition.....................................................................................................................................6
Changes from Revision G (July 2014) to Revision H (May 2015)
Page
Added additional application...............................................................................................................................1
Updated with HDMI 2.0 Eye Diagrams.............................................................................................................14
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•
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Changes from Revision F (November 2013) to Revision G (July 2014)
Page
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Added 61000-4-4 EFT compliance.....................................................................................................................1
Added Thermal Information table....................................................................................................................... 6
Added Handling Ratings table............................................................................................................................ 6
Added the Detailed Description section............................................................................................................11
Added the Application and Implementation section..........................................................................................13
Added Layout section. ..................................................................................................................................... 17
Changes from Revision * (December 2012) to Revision A (December 2012)
Page
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Added TPS2EUSB30A part to document........................................................................................................... 1
Changes from Revision A (December 2012) to Revision B (January 2013)
Page
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Added Insertion Loss Graphic............................................................................................................................ 9
Added Eye Diagrams........................................................................................................................................14
Changes from Revision B (January 2013) to Revision C (March 2013)
Page
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Changed IO Capacitance range......................................................................................................................... 1
Changed test conditions and typ values for Vclamp ............................................................................................ 6
Added typ RDYN values for DQA and RVZ packages......................................................................................... 6
Added CL values for DQA and RVZ packages................................................................................................... 6
Changed CURRENT vs VOLTAGE graphic........................................................................................................9
Changed Insertion Loss graphic.........................................................................................................................9
Changed HDMI Eye Diagrams......................................................................................................................... 14
Changes from Revision C (March 2013) to Revision D ()
Page
Updated Title.......................................................................................................................................................1
Removed Ordering Information table..................................................................................................................4
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Changes from Revision D (August 2013) to Revision E (November 2013)
Page
Updated document formatting............................................................................................................................ 1
Added additional application...............................................................................................................................1
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•
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5 Pin Configuration and Functions
ID Area
I/O
1
1
2
2
GND
Figure 5-2. DYA Package 2-Pin SOD-523 Top View
Figure 5-1. DPY Package 2-Pin X1SON Top View
Table 5-1. Pin Functions TPD1E05U06 DPY and DYA
PIN
TYPE
DESCRIPTION
NAME
GND
I/O
NO.
2
Ground
I/O
Ground; Connect to ground
ESD protected channel(1)
1
(1) Place as close to the connector as possible.
D1+
D1–
1
2
10
9
NC
NC
GND
3
8
GND
D2+
D2–
4
5
7
6
NC
NC
Figure 5-3. DQA Package 10-Pin USON Top View
Table 5-2. Pin Functions TPD4E05U06 DQA
PIN
TYPE
DESCRIPTION
NAME
D1+
NO.
1
I/O
I/O
I/O
I/O
ESD protected channel(1)
ESD protected channel(1)
ESD protected channel(1)
ESD protected channel(1)
D1–
D2+
D2–
GND
GND
NC
2
4
5
3
Ground
Ground; Connect to ground
8
6
NC
7
—
Not connected; Used for optional straight-through routing. Can be left floating or grounded
NC
9
NC
10
(1) Place as close to the connector as possible.
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NC
NC
NC
1
2
3
14
13
12
D1+
D1–
D2+
NC
GND
NC
4
5
6
7
11
10
9
D2–
GND
D3+
D3–
NC
8
Figure 5-4. RVZ Package 14-Pin USON Top View
Table 5-3. Pin Functions TPD6E05U06 RVZ
PIN
TYPE
DESCRIPTION
NAME
D1+
D1–
D2+
D2–
D3+
D3–
GND
GND
NC
NO.
14
13
12
11
9
I/O
I/O
I/O
I/O
I/O
I/O
ESD protected channel(1)
ESD protected channel(1)
ESD protected channel(1)
ESD protected channel(1)
ESD protected channel(1)
ESD protected channel(1)
8
5
Ground
Ground; Connect to ground
10
1
NC
2
NC
3
—
Not connected; Used for optional straight-through routing. Can be left floating or grounded
NC
4
NC
6
NC
7
(1) Place as close to the connector as possible.
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6 Specifications
Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
UNIT
Electrical Fast Transient
IEC 61000-4-4 (5/50ns)
80
A
(2) (3)
IEC 61000-4-5 Current
(8/20us)
2.5
40
A
Peak Pulse (2) (3)
IEC 61000-4-5 Power
(8/20us)
W
Ambient Operating
Temperature
TA
-40
-65
125
155
°C
°C
Tstg
Storage Temperature
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2) Voltages are with respect to GND unless otherwise noted.
(3) Measured at 25℃
6.1 ESD Ratings—JEDEC Specification
VALUE
UNIT
Human body model (HBM), per ANSI/ESDA/
JEDEC JS-001 (1)
±4000
V
V
V
V
V(ESD)
Electrostatic discharge – DPY, DQA, and RVZ
Electrostatic discharge – DYA
Charged device model (CDM), per JEDEC
specification JESD22-C101 (2)
±1500
±2500
±1000
Human body model (HBM), per ANSI/ESDA/
JEDEC JS-001
V(ESD)
Charged device model (CDM), per JEDEC
specification JS-002
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 500-V HBM is possible with the necessary precautions. Pins listed as ±4000 V may actually have higher performance.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 250-V CDM is possible with the necessary precautions. Pins listed as ±1500 V may actually have higher performance.
6.2 ESD Ratings—IEC Specification
VALUE
±12000
±15000
UNIT
IEC 61000-4-2 contact discharge
IEC 61000-4-2 air-gap discharge
V(ESD)
Electrostatic discharge
V
Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
VIO
TA
Input pin voltage
0
5.5
V
Operating free-air
temperature
-40
125
°C
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6.3 Thermal Information
TPD1E05U06
TPD4E05U06
DQA (USON)
10 PINS
TPD6E05U06
RVZ (USON)
14 PINS
THERMAL METRIC (1)
DPY (X1SON)
DYA (SOD523)
2 PINS
UNIT
2 PINS
RθJA
Junction-to-ambient thermal resistance
697.3
772.1
327
197.9
°C/W
°C/W
°C/W
°C/W
Junction-to-case (top) thermal
resistance
RθJC(top)
RθJB
471
444.6
540.4
159.9
189.5
257.7
60.9
119.1
92.6
22
Junction-to-board thermal resistance
575.9
175.7
Junction-to-top characterization
parameter
ΨJT
Junction-to-board characterization
parameter
ΨJB
575.1
533.9
257
91.6
°C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.4 Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
INPUT - OUTPUT RESISTANCE
VRWM Reverse stand-off voltage
TEST CONDITION
MIN
TYP MAX UNIT
IIO < 10µA
IIO = 1 mA
5.5
8.5
V
V
VBR
Break-down voltage
6.5
IPP = 1 A, TLP, from I/O to GND (1)
IPP = 5 A, TLP, from I/O to GND (1)
IPP = 1 A, TLP, from GND to I/O (1)
IPP = 5 A, TLP, from GND to I/O (1)
VIO = 2.5V
10
14
VClamp Clamp voltage
ILEAK Leakage current
V
3
7
0.01
0.8
0.8
0.8
0.7
0.8
0.8
0.8
0.8
10 nA
I/O to GND (2)
DPY package
DYA package
DQA package
RVZ package
GND to I/O (2)
I/O to GND (2)
GND to I/O (2)
Dynamic
RDYN
Ω
I/O to GND (2)
resistance
GND to I/O (2)
I/O to GND (2)
GND to I/O (2)
CAPACITANCE
TPD1E05U06
DPY
package
0.42
0.42
0.5
TPD1E05U06
DYA
package
VIO = 2.5 V; ƒ = 1 MHz , I/O to
GND
CL
Line capacitance (3)
pF
TPD4E05U06
DQA
package
TPD6E05U06
RVZ
package
0.47
0.05
Δ CIO-
GND Pin = 0 V, f = 1 MHz, VBIAS = 2.5 V,
Channel x pin to GND – channel y pin to GND
Variation of input capacitance
0.07
pF
TO-GND
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6.4 Electrical Characteristics (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITION
MIN
TYP MAX UNIT
CCROS
GND Pin = 0 V, f = 1 MHz, VBIAS = 2.5 V,
between channel pins
Channel to channel input capacitance
0.01
0.06
pF
S
(1) Transition line pulse with 100 ns width, 200 ps rise time.
(2) Extraction of RDYN using least squares fit of TLP characteristics between I = 10 A and I = 20 A.
(3) Capacitance data is taken at 25°C.
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6.5 Typical Characteristics
1.0
0.8
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
50
Current
45
Power
0.6
40
35
30
25
20
15
10
5
0.4
0.2
0.0
œ0.2
œ0.4
œ0.6
œ0.8
œ1.0
0
œ2 œ1
0
1
2
3
4
5
6
7
8
9
10
0
5
10 15 20 25 30 35 40 45 50
œ5
C001
C002
Voltage (V)
Time (ꢀs)
.
.
Figure 6-1. DC Voltage Sweep I-V Curve
Figure 6-2. Surge Curve (tp = 8/20 μs), Pin IO to GND
35
30
25
20
15
10
5
25
20
15
10
5
0
œ5
0
0
5
10
15
20
25
30
35
40
0
5
10
15
20
25
C003
C008
Voltage (V)
Voltage (V)
.
.
Figure 6-3. Positive TLP Plot IO to GND
Figure 6-4. Negative TLP Plot IO to GND
300
250
200
150
100
50
80
70
60
50
40
30
20
10
0
0
œ10
œ40
œ20
0
20
40
60
80
100
120
0
25
50
75
100
125
150
175
200
C004
C005
Temperature (°C)
Time (ns)
.
.
Figure 6-5. Leakage vs Temperature
Figure 6-6. 8-kV IEC Waveform
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6.5 Typical Characteristics (continued)
10
0
0
œ1
œ2
œ10
œ20
œ30
œ40
œ50
œ60
œ70
œ80
œ90
œ3
œ4
œ5
œ6
œ7
œ8
œ9
œ10
œ11
œ12
100k
1M
10M
100M
1G
10G
0
25
50
75
100
125
150
175
200
C007
Frequency (Hz)
C006
Time (ns)
.
.
Figure 6-8. TPD1E05U06 Insertion Loss
Figure 6-7. –8-kV IEC Waveform
0
œ1
œ2
œ3
œ4
œ5
œ6
0
œ1
œ2
œ3
œ4
œ5
œ6
100k
1M
10M
100M
1G
10G
100k
1M
10M
100M
1G
10G
C009
C010
Frequency (Hz)
Frequency (Hz)
.
.
Figure 6-9. TPD4E05U06 Insertion Loss
Figure 6-10. TPD6E05U06 Insertion Loss
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7 Detailed Description
7.1 Overview
The TPDxE05U06 is a family of unidirectional Transient Voltage Suppressor (TVS) based Electrostatic
Discharge (ESD) protection diodes with ultra-low capacitance. Each device can dissipate ESD strikes above
the maximum level specified by the IEC 61000-4-2 international standard. The TPDxE05U06s ultra-low loading
capacitance makes it ideal for protecting any high-speed signal pins.
7.2 Functional Block Diagram
I/O
GND
Figure 7-1. TPD1E05U06 Block Diagram
D1+
D1-
D2+
D2-
GND
Figure 7-2. TPD4E05U06 Block Diagram
D1+
D1-
D2+
D2-
D3+
D3-
GND
Figure 7-3. TPD6E05U06 Block Diagram
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7.3 Feature Description
The TPDxE05U06 is a family of unidirectional Transient Voltage Suppressor (TVS) Electrostatic Discharge
(ESD) protection diodes with ultra-low capacitance. Each device can dissipate ESD strikes above the maximum
level specified by the IEC 61000-4-2 international standard. The TPDxE05U06s ultra-low loading capacitance
makes it ideal for protecting any high-speed signal pins.
7.3.1 ±15-kV IEC61000-4-2 Level 4 ESD Protection
The I/O pins can withstand ESD events up to ±12-kV contact and ±15-kV air. An ESD-surge clamp diverts the
current to ground.
7.3.2 IEC61000-4-4 EFT Protection
The I/O pins can withstand an electrical fast transient burst of up to 80 A (5/50 ns waveform, 4 kV with 50-Ω
impedance). An ESD-surge clamp diverts the current to ground. This has been validated on the TPD4E05U06
only.
7.3.3 IEC61000-4-5 Surge Protection
The I/O pins can withstand surge events up to 2.5 A and 40 W (8/20 µs waveform). An ESD-surge clamp diverts
this current to ground.
7.3.4 I/O Capacitance
The capacitance between each I/O pin to ground is 0.42 pF (TPD1E05U06), 0.5 pF (TPD4E05U06) or 0.47 pF
(TPD6E05U06). These devices support data rates up to 6 Gbps.
7.3.5 DC Breakdown Voltage
The DC breakdown voltage of each I/O pin is a minimum of 6.5 V. This ensures that sensitive equipment is
protected from surges above the reverse standoff voltage of 5.5 V.
7.3.6 Ultra-Low Leakage Current
The I/O pins feature an ultra-low leakage current of 10 nA (maximum) with a bias of 2.5 V.
7.3.7 Low ESD Clamping Voltage
The I/O pins feature an ESD clamp that is capable of clamping the voltage to 10 V (IPP = 1 A).
7.3.8 Industrial Temperature Range
This device features an industrial operating range of –40°C to +125°C.
7.3.9 Easy Flow-Through Routing
The layout of this device makes it simple and easy to add protection to an existing layout. The packages offers
flow-through routing, requiring minimal modification to an existing layout.
7.4 Device Functional Modes
The TPDxE05U06 is a passive integrated circuit that triggers when voltages are above VBR or below the lower
diodes Vf (–0.6 V). During ESD events, voltages as high as ±15 kV (air) can be directed to ground via the
internal diode network. When the voltages on the protected line fall below the trigger levels of TPDxE05U06
(usually within 10s of nano-seconds) the device reverts to passive.
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8 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
8.1 Application Information
The TPDxE05U06 is a diode type TVS which is typically used to provide a path to ground for dissipating ESD
events on hi-speed signal lines between a human interface connector and a system. As the current from ESD
passes through the TVS, only a small voltage drop is present across the diode. This is the voltage presented to
the protected IC. The low RDYN of the triggered TVS holds this voltage, VCLAMP, to a safe level for the protected
IC.
8.2 Typical Applications
8.2.1 HDMI 2.0 Application
TPD4E05U06DQA
D2+
D2-
D2+
D2-
1
2
10
9
HOT PLUG 1
UTILITY 2
UTI_CON
3
4
8
7
TMDS D2+ 3
D1+
D1-
5V Source
D1+
D1-
TMDS_GND 4
TMDS D2- 5
5
6
TMDS D1+ 6
TPD4E05U06DQA
TMDS_GND 7
D0+
D0-
D0+
D0-
1
10
TMDS D1- 8
2
9
TMDS D0+ 9
8
7
3
4
TMDS_GND 10
CLK+
CLK-
CLK+
CLK-
TMDS D0- 11
TMDS CLK+ 12
TMDS_GND 13
TMDS CLK- 14
5
6
TPD5S116YFF
HDMI Controller
CEC_SYS
CEC_CON
CEC 15
SCL_SYS
SDA_SYS
VCCA
DDC/CEC GND 16
SCL 17
SCL_CON
SDA_CON
SDA 18
EN
5V_SYS
HPD_SYS
5V_CON
P 5V0 19
GND 20
HPD_CON
UTI_CON
GND
0.1 µF
0.1 µF
Figure 8-1. HDMI 2.0 Schematic
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8.2.1.1 Design Requirements
For this design example, the two TPD4E05U06 devices, and a TPD5S116 are being used in an HDMI 2.0
application. This provides a complete port protection scheme.
Given the HDMI 2.0 application, the parameters listed in Table 8-1 are known.
Table 8-1. Design Parameters
DESIGN PARAMETER
Signal range on pins 1, 2, 4, or 5
Operating frequency
VALUE
0 V to 5 V
3 GHz
8.2.1.2 Detailed Design Procedure
8.2.1.2.1 Signal Range on Pin 1, 2, 4, or 5
The TPD4E05U06 has 4 identical protection channels for signal lines. The symmetry of the device provides
flexibility when selecting which of the 4 I/O channels is going to protect which signal lines. Any I/O supports a
signal range of 0 to 5.5 V.
8.2.1.3 Application Curves
Figure 8-2. 3.4-Gbps HDMI 1.4 TP1 Eye Diagram
Unpopulated EVM
Figure 8-3. 3.4-Gbps HDMI 1.4 TP1 Eye Diagram
TPD1E05U06
Figure 8-4. 3.4-Gbps HDMI 1.4 TP1 Eye Diagram
TPD4E05U06
Figure 8-5. 3.4-Gbps HDMI 1.4 TP1 Eye Diagram
TPD6E05U06
Figure 8-6. 6-Gbps HDMI 2.0 (TP1) Eye Diagram
Unpopulated EVM
Figure 8-7. 6-Gbps HDMI 2.0 (TP1) Eye Diagram
TPD1E05U06
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Figure 8-8. 6-Gbps HDMI 2.0 (TP1) Eye Diagram
TPD4E05U06
Figure 8-9. 6-Gbps HDMI 2.0 (TP1) Eye Diagram
TPD6E05U06
8.2.2 HDMI 2.0 Application
1
TPD1E05U06
1
TPD1E05U06
1
TPD1E05U06
1
TPD1E05U06
2
2
2
2
D0+
D0-
D1+
D1-
D2+
D2-
CLK+
CLK-
1
TPD1E05U06
1
TPD1E05U06
1
TPD1E05U06
1
TPD1E05U06
2
2
2
2
Figure 8-10. HDMI 2.0 Schematic
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SLVSBO7M – DECEMBER 2012 – REVISED DECEMBER 2021
www.ti.com
8.2.2.1 Design Requirements
For this design example, the TPD1E05U06 and the TPD5S116 are used to protect the data pairs and control
lines of the HDMI 2.0 connection. This provides full HDMI 2.0 port protection.
Given the HDMI 2.0 application, the following parameters in Table 8-2 are known.
Table 8-2. Design Parameters
DESIGN PARAMETER
Signal range on data lines
Operating frequency
VALUE
0 V to 5 V
3 GHz
8.2.2.2 Detailed Design Procedure
8.2.2.2.1 Signal Range
The TPD1E05U06 has 1 protection channel for signal lines, supporting a signal range of 0 V to 5.5 V.
8.2.2.2.2 Operating Frequency
The TPD1E05U06 has 0.42 pF of capacitance, which supports HDMI 2.0 data rates.
8.2.2.3 Application Curves
Refer to the Section 8.2.1.3 section.
9 Power Supply Recommendations
This device is a passive ESD protection device and there is no need to power it. Care must be taken to make
sure that the maximum voltage specifications for each line are not violated.
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10 Layout
10.1 Layout Guidelines
•
The optimum placement is as close to the connector as possible.
– EMI during an ESD event can couple from the trace being struck to other nearby unprotected traces,
resulting in early system failures.
– The PCB designer needs to minimize the possibility of EMI coupling by keeping any unprotected traces
away from the protected traces which are between the TVS and the connector.
Route the protected traces as straight as possible.
Eliminate any sharp corners on the protected traces between the TVS and the connector by using rounded
corners with the largest radii possible.
•
•
– Electric fields tend to build up on corners, increasing EMI coupling.
10.2 Layout Example
10.2.1 TPD4E05U06 Layout Example
This application is typical of an HDMI 1.4 layout.
VIA to GND Plane
Figure 10-1. TPD4E05U06 Layout
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10.2.2 TPD1E05U06 Layout Example
This application is typical of an HDMI 2.0 layout.
VIA to GND Plane
Figure 10-2. TPD1E05U06 Layout
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11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
For related documentation, see the following:
•
•
•
•
•
•
•
•
Texas Instruments, Reading and Understanding an ESD Protection data sheet
Texas Instruments, ESD Layout Guide application reports
Texas Instruments, TPD6E05U06RVZ EVM user's guide
Texas Instruments, Picking ESD Diodes for Ultra High-Speed Data Lines application reports
Texas Instruments, ESD PROTECTION DIODES EVM user's guide
Texas Instruments, TPD1E05U06DPY EVM user's guide
Texas Instruments, TPD4E05U06DQA EVM user's guide
Texas Instruments, Generic ESD Evaluation Module user's guide
11.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
11.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
PCI-express® and PCI-Express® are registered trademarks of PCI-SIG .
V-by-One® are registered trademarks of Thine Electronics, Inc.
All trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
11.6 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
5-Jan-2022
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
PTPD1E05U06DYAR
TPD1E05U06DPYR
ACTIVE
ACTIVE
SOT-5X3
X1SON
DYA
DPY
2
2
3000
TBD
Call TI
Call TI
-40 to 125
-40 to 125
10000 RoHS & Green
250 RoHS & Green
NIPDAU
NIPDAU
NIPDAU
NIPDAU
Level-1-260C-UNLIM
(BK, C1, C6)
C2
TPD1E05U06DPYT
TPD4E05U06DQAR
TPD6E05U06RVZR
ACTIVE
ACTIVE
ACTIVE
X1SON
USON
USON
DPY
DQA
RVZ
2
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
-40 to 125
(BK, C1, C6)
C2
10
14
3000 RoHS & Green
3000 RoHS & Green
(BLG, BRG)
BRY
(BV, BVY)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
5-Jan-2022
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TPD1E05U06, TPD4E05U06 :
Automotive : TPD1E05U06-Q1, TPD4E05U06-Q1
•
NOTE: Qualified Version Definitions:
Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
•
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
12-Jan-2022
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPD1E05U06DPYR
TPD1E05U06DPYR
TPD1E05U06DPYR
TPD1E05U06DPYT
TPD1E05U06DPYT
TPD4E05U06DQAR
TPD4E05U06DQAR
TPD4E05U06DQAR
TPD6E05U06RVZR
TPD6E05U06RVZR
X1SON
X1SON
X1SON
X1SON
X1SON
USON
USON
USON
USON
USON
DPY
DPY
DPY
DPY
DPY
DQA
DQA
DQA
RVZ
RVZ
2
2
10000
10000
10000
250
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
178.0
180.0
8.4
9.5
9.5
9.5
8.4
8.4
9.5
9.5
13.5
13.2
0.07
0.66
0.73
0.66
0.07
1.23
1.23
1.18
1.6
1.1
1.15
1.13
1.15
1.1
0.47
0.66
0.5
2.0
2.0
2.0
2.0
2.0
4.0
4.0
4.0
4.0
4.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
12.0
12.0
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
2
2
0.66
0.47
0.6
2
250
10
10
10
14
14
3000
3000
3000
3000
3000
2.7
2.7
0.7
2.68
3.75
3.8
0.72
0.7
1.65
0.7
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
12-Jan-2022
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPD1E05U06DPYR
TPD1E05U06DPYR
TPD1E05U06DPYR
TPD1E05U06DPYT
TPD1E05U06DPYT
TPD4E05U06DQAR
TPD4E05U06DQAR
TPD4E05U06DQAR
TPD6E05U06RVZR
TPD6E05U06RVZR
X1SON
X1SON
X1SON
X1SON
X1SON
USON
USON
USON
USON
USON
DPY
DPY
DPY
DPY
DPY
DQA
DQA
DQA
RVZ
RVZ
2
2
10000
10000
10000
250
203.2
184.0
189.0
184.0
203.2
203.2
184.0
189.0
189.0
184.0
196.8
184.0
185.0
184.0
196.8
196.8
184.0
185.0
185.0
184.0
33.3
19.0
36.0
19.0
33.3
33.3
19.0
36.0
36.0
19.0
2
2
2
250
10
10
10
14
14
3000
3000
3000
3000
3000
Pack Materials-Page 2
PACKAGE OUTLINE
DYA0002A
SOT (SOD-523) - 0.77 mm max height
PLASTIC SMALL OUTLINE
1.7
1.5
PIN 1
ID AREA
A
0.85
0.75
NOTE 3
2
1
1.3
1.1
0.3
0.1
0.7
0.5
B
2X
TYP
0.77 MAX
C
SEATING PLANE
0.05 C
0.15
2X
0.08
SYMM
SYMM
0.35
0.25
2X
0.1
0.05
C A B
0.4
0.2
2X
4224978/B 09/2021
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. Reference JEITA SC-79 registration except for package height
www.ti.com
EXAMPLE BOARD LAYOUT
DYA0002A
SOT (SOD-523) - 0.77 mm max height
PLASTIC SMALL OUTLINE
SYMM
2X (0.67)
(R0.05) TYP
SYMM
2
1
2X (0.4)
(1.48)
LAND PATTERN EXAMPLE
SCALE:40X
0.05 MIN
AROUND
0.05 MAX
AROUND
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDERMASK DETAILS
4224978/B 09/2021
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DYA0002A
SOT (SOD-523) - 0.77 mm max height
PLASTIC SMALL OUTLINE
SYMM
2X (0.67)
(R0.05) TYP
SYMM
2
1
2X (0.4)
(1.48)
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
SCALE:40X
4224978/B 09/2021
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
DQA0010A
USON - 0.55 mm max height
SCALE 6.000
PLASTIC SMALL OUTLINE - NO LEAD
1.1
0.9
A
B
PIN 1 INDEX AREA
2.6
2.4
C
0.55 MAX
SEATING PLANE
(0.13) TYP
0.08 C
0.05
0.00
5
6
4X 0.5
(R0.125)
2X
2
0.45
0.35
2X
0.1
C A
B
0.05
1
10
0.25
0.15
8X
PIN 1 ID
(OPTIONAL)
0.1
0.05
C A
B
0.43
0.30
10X
C
4220328/A 12/2015
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
EXAMPLE BOARD LAYOUT
DQA0010A
USON - 0.55 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
10X (0.565)
8X (0.2)
1
10
SYMM
2X (0.4)
4X (0.5)
6
5
(R0.05) TYP
SYMM
(0.835)
LAND PATTERN EXAMPLE
SCALE:30X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4220328/A 12/2015
NOTES: (continued)
3. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271).
www.ti.com
EXAMPLE STENCIL DESIGN
DQA0010A
USON - 0.55 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
10X (0.565)
8X (0.2)
1
10
METAL
TYP
SYMM
2X (0.36)
8
3
4X (0.5)
6
5
(R0.05) TYP
SYMM
(0.835)
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
EXPOSED PADS 3 & 8:
90% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:40X
4220328/A 12/2015
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
PACKAGE OUTLINE
DPY0002A
X1SON - 0.45 mm max height
S
C
A
L
E
1
1
.
0
0
0
PLASTIC SMALL OUTLINE - NO LEAD
1.1
0.9
B
A
PIN 1 INDEX AREA
0.7
0.5
0.45
0.30
C
SEATING PLANE
0.08 C
0.05
0.00
0.65
1
2
SYMM
0.55
0.45
2X
0.1
C A B
SYMM
0.3
0.2
2X
0.05
C A B
4224561/B 03/2021
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M
2. This drawing is subject to change without notice.
www.ti.com
EXAMPLE BOARD LAYOUT
DPY0002A
X1SON - 0.45 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
2X (0.3)
SYMM
1
2
SYMM
2X (0.5)
(R0.05) TYP
(0.7)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:60X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
METAL EDGE
METAL UNDER
SOLDER MASK
EXPOSED
METAL
EXPOSED
METAL
SOLDER MASK
OPENING
SOLDER MASK
OPENING
SOLDER MASK
DEFINED
(PREFERRED)
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4224561/B 03/2021
NOTES: (continued)
3. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271).
4. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view.
It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
DPY0002A
X1SON - 0.45 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(0)
2X (0.3)
2X (0.5)
SYMM
PCB PAD METAL
UNDER SOLDER PASTE
SYMM
2
1
(R0.05) TYP
(0.7)
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
SCALE:60X
4224561/B 03/2021
NOTES: (continued)
5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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