TPD1E10B06_V02 [TI]

TPD1E10B06 Single-Channel ESD Protection Diode;
TPD1E10B06_V02
型号: TPD1E10B06_V02
厂家: TEXAS INSTRUMENTS    TEXAS INSTRUMENTS
描述:

TPD1E10B06 Single-Channel ESD Protection Diode

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TPD1E10B06  
SLLSEB1F – FEBRUARY 2012 – REVISED OCTOBER 2021  
TPD1E10B06 Single-Channel ESD Protection Diode  
1 Features  
3 Description  
Provides system-level ESD protection for low-  
voltage I/O interface  
IEC 61000-4-2 level 4 ESD protection  
– ±30 kV contact discharge  
– ±30 kV air-gap discharge  
IEC 61000-4-5 surge: 6 A (8/20 µs)  
I/O capacitance 12 pF (typical)  
RDYN 0.4 Ω (typical)  
DC breakdown voltage ±6 V (minimum)  
Ultralow leakage current 100 nA (maximum)  
10-V clamping voltage (maximum at IPP = 1 A)  
Industrial temperature range: –40°C to 125°C  
Small 0402 footprint  
The TPD1E10B06 is a single-channel ESD TVS  
diode in a small 0402 package convenient for space  
contrained applications and an industry standard  
SOD-523 package. This TVS protection product offers  
±30 kV contact ESD, ±30 kV IEC air-gap protection,  
and has an ESD clamp circuit with a back-to-back  
TVS diode for bipolar or bidirectional signal support.  
The 12 pF line capacitance of this ESD protection  
diode is suitable for a wide range of applications  
supporting data rates up to 400 Mbps.  
Typical applications of this ESD protection product  
are circuit protection for audio lines (microphone,  
earphone, and speakerphone), SD interfacing, keypad  
or other buttons, VBUS pin and ID pin of USB ports,  
and general-purpose I/O ports.This ESD clamp is  
good for the protection of end equipment like portable  
devices, wearables, set-top boxes, electronic point-of-  
sale equipment, appliances, and products for building  
automation.  
(1 mm × 0.6 mm × 0.5 mm)  
Industry standard SOD-523 package  
(0.8 mm × 1.2 mm)  
2 Applications  
End equipment:  
Portable devices  
Wearables  
– Set-top boxes  
– Electronic point of sale (EPOS)  
Appliances  
Device Information(1)  
PART NUMBER  
PACKAGE  
X1SON (2)  
SOD-523 (2)  
BODY SIZE (NOM)  
0.60 mm × 1.00 mm  
0.80 mm × 1.20 mm  
TPD1E10B06  
Building automation  
Interfaces:  
– Audio lines  
(1) For all available packages, see the orderable addendum at  
the end of the data sheet.  
– Push-buttons  
IO Line 1  
– General-purpose input or output (GPIO)  
IO Line 2  
Connector  
(source of ESD)  
ESD sensitive  
device  
1
2
1
2
GND Line  
Application Schematic  
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,  
intellectual property matters and other important disclaimers. PRODUCTION DATA.  
 
 
 
TPD1E10B06  
SLLSEB1F – FEBRUARY 2012 – REVISED OCTOBER 2021  
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Table of Contents  
1 Features............................................................................1  
2 Applications.....................................................................1  
3 Description.......................................................................1  
4 Revision History.............................................................. 2  
5 Pin Configuration and Functions...................................4  
6 Specifications.................................................................. 5  
6.1 Absolute Maximum Ratings ....................................... 5  
6.2 ESD Ratings—JEDEC Specification ..........................5  
6.3 ESD Ratings—IEC Specification ............................... 5  
6.4 Recommended Operating Conditions ........................5  
6.5 Thermal Information ...................................................5  
6.6 Electrical Characteristics ............................................6  
6.7 Typical Characteristics................................................7  
7 Detailed Description........................................................9  
7.1 Overview.....................................................................9  
7.2 Functional Block Diagram...........................................9  
7.3 Feature Description.....................................................9  
7.4 Device Functional Modes............................................9  
8 Application and Implementation..................................10  
8.1 Application Information............................................. 10  
8.2 Typical Application.................................................... 10  
9 Power Supply Recommendations................................12  
10 Layout...........................................................................12  
10.1 Layout Guidelines................................................... 12  
10.2 Layout Example...................................................... 12  
11 Device and Documentation Support..........................13  
11.1 Receiving Notification of Documentation Updates..13  
11.2 Support Resources................................................. 13  
11.3 Trademarks............................................................. 13  
11.4 Electrostatic Discharge Caution..............................13  
11.5 Glossary..................................................................13  
12 Mechanical, Packaging, and Orderable  
Information.................................................................... 13  
4 Revision History  
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.  
Changes from Revision E (June 2021) to Revision F (October 2021)  
Page  
Updated the Application Schematic figure..........................................................................................................1  
Updated the Description of Pin 1 and pin 2 in the Pin Configuration and Functions section..............................4  
Changed HBM spec to per JS-001....................................................................................................................5  
Changed CDM spec to per JESD22-C101 ........................................................................................................ 5  
Changed HBM spec to Q101-001.......................................................................................................................5  
Changed CDM spec to Q101-005 ..................................................................................................................... 5  
Updated the Typical Application Schematic figure............................................................................................10  
Changed the system-level ESD protection from: ±20 kV Contact/± 25 kV Air-Gap to: ±8 kV Contact/± 15 kV  
Air-Gap .............................................................................................................................................................11  
Changes from Revision D (Novemeber 2015) to Revision E (June 2021)  
Page  
Updated the numbering format for tables, figures, and cross-references throughout the document..................1  
Added the DYA package.....................................................................................................................................1  
Updated the Features section.............................................................................................................................1  
Updated the Applications section....................................................................................................................... 1  
Updated the Description section.........................................................................................................................1  
Added Thermal information for DYA package.....................................................................................................5  
Updated the Overview section............................................................................................................................9  
Updated the Functional Block Diagram section..................................................................................................9  
Updated the Feature Description section........................................................................................................... 9  
Changes from Revision C (April 2015) to Revision D (November 2015)  
Page  
Added frequency test condition to capacitance specification............................................................................ 6  
Changes from Revision B (October 2012) to Revision C (April 2015)  
Page  
Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device  
Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout  
section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information  
section ............................................................................................................................................................... 1  
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Changes from Revision A (March 2012) to Revision B (October 2012)  
Page  
Added THERMAL INFORMATION table.............................................................................................................5  
Changes from Revision * (February 2011) to Revision A (March 2012)  
Page  
Updated FEATURES.......................................................................................................................................... 1  
Added graphs to TYPICAL CHARACTERISTICS section..................................................................................7  
Added APPLICATION INFORMATION section.................................................................................................10  
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5 Pin Configuration and Functions  
1
2
Figure 5-1. DPY Package  
2-Pin X1SON  
Top View  
ID Area  
1
2
Figure 5-2. DYA Package  
2-Pin SOD-523  
Top View  
Table 5-1. Pin Functions  
PIN  
1
I/O  
DESCRIPTION  
I/O  
ESD Protected I/O. Connect other pin ground.  
2
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6 Specifications  
6.1 Absolute Maximum Ratings  
over operating free-air temperature range (unless otherwise noted)(1)  
MIN  
MAX  
90  
UNIT  
W
IEC 61000-4-5 power (tp - 8/20 µs) at 25°C  
Peak pulse  
IEC 61000-4-5 current (tp - 8/20 µs) at 25°C  
6
A
TA  
Operating free-air temperature  
Storage temperature  
-40  
125  
155  
°C  
Tstg  
–65  
°C  
(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress  
ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated  
under Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device  
reliability.  
6.2 ESD Ratings—JEDEC Specification  
VALUE  
UNIT  
Human body model (HBM), per ANSI/ESDA/  
JEDEC JS-001  
±2500  
V
V(ESD)  
Electrostatic discharge - DPY  
Electrostatic discharge - DYA  
Charged device model (CDM), per JEDEC  
specification JESD22-C101  
±1000  
±2500  
±1000  
V
V
V
Human body model (HBM), per ANSI/ESDA/  
JEDEC JS-001  
V(ESD)  
Charged device model (CDM), per JEDEC  
specification JS-002  
6.3 ESD Ratings—IEC Specification  
VALUE  
±30000  
±30000  
UNIT  
IEC 61000-4-2 Contact Discharge, all pins  
IEC 61000-4-2 Air-gap Discharge, all pins  
V(ESD)  
Electrostatic discharge  
V
6.4 Recommended Operating Conditions  
over operating free-air temperature range (unless otherwise noted)  
MIN  
–5.5  
-40  
NOM  
MAX  
UNIT  
V
Operating  
Pin 1 to 2 or Pin 2 to 1  
voltage  
5.5  
TA  
Operating free-air temperature  
125  
°C  
6.5 Thermal Information  
TPD1E10B06  
THERMAL METRIC(1)  
DPY (X1SON)  
2 PINS  
615.5  
DYA (SOD523)  
2 PINS  
730.8  
UNIT  
RθJA  
RθJC(top)  
RθJB  
ΨJT  
Junction-to-ambient thermal resistance  
Junction-to-case (top) thermal resistance  
Junction-to-board thermal resistance  
°C/W  
°C/W  
°C/W  
°C/W  
°C/W  
404.8  
413.4  
493.3  
497.7  
Junction-to-top characterization parameter  
Junction-to-board characterization parameter  
127.7  
129.7  
ΨJB  
493.3  
491.8  
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6.5 Thermal Information (continued)  
TPD1E10B06  
THERMAL METRIC(1)  
DPY (X1SON)  
2 PINS  
DYA (SOD523)  
UNIT  
2 PINS  
RθJC(bot)  
Junction-to-case (bottom) thermal resistance  
162  
-
°C/W  
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application  
report.  
6.6 Electrical Characteristics  
over operating free-air temperature range (unless otherwise noted)  
PARAMETER  
Reverse stand-off voltage  
Leakage current  
TEST CONDITION  
MIN  
TYP  
MAX  
5.5  
UNIT  
V
VRWM  
ILEAK  
Pin 1 to 2 or Pin 2 to 1  
Pin 1 = 5 V, Pin 2 = 0 V  
IPP = 1 A, tp = 8/20 µs(2)  
100  
nA  
Clamp voltage with surge strike on pin 1,  
pin 2 grounded.  
VClamp1,2  
10  
14  
V
V
Clamp voltage with surge strike on pin 1,  
pin 2 grounded.  
VClamp1,2  
IPP =5 A, tp = 8/20 µs(2)  
IPP = 1 A, tp = 8/20 µs(2)  
IPP = 5 A, tp = 8/20 µs(2)  
Pin 1 to Pin 2(1)  
8.5  
14  
Clamp voltage with surge strike on pin 2,  
pin 1 grounded.  
VClamp2,1  
V
0.32  
0.38  
12  
RDYN  
Dynamic resistance  
Ω
Pin 2 to Pin 1(1)  
CIO  
I/O capacitance  
VIO = 2.5 V; ƒ = 1 MHz  
IIO = 1 mA  
pF  
V
VBR1,2  
VBR2,1  
Break-down voltage, pin 1 to pin 2  
Break-down voltage, pin 2 to pin 1  
6
6
IIO = 1 mA  
V
(1) Extraction of RDYN using least squares fit of TLP characteristics between IPP = 10 A and IPP = 20 A.  
(2) Nonrepetitive current pulse 8 to 20 µs exponentially decaying waveform according to IEC 61000-4-5  
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6.7 Typical Characteristics  
Figure 6-1. IEC 61000-4-2 Clamp Voltage +8 kV Contact ESD  
Figure 6-2. IEC 61000-4-2 Clamp Voltage –8-kV Contact ESD  
Figure 6-3. Transmission Line Pulse (TLP) Waveform Pin 1 to  
Pin 2  
Figure 6-4. Transmission Line Pulse (TLP) Waveform Pin 2 to  
Pin 1  
Figure 6-5. IV Curve  
Figure 6-6. Positive Surge Waveform 8 to 20 µs  
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6.7 Typical Characteristics (continued)  
Figure 6-7. Negative Surge Waveform 8 to 20 µs  
Figure 6-8. Pin Capacitance Across VBIAS  
Figure 6-9. Insertion Loss  
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7 Detailed Description  
7.1 Overview  
The TPD1E108B06 is a single-channel ESD TVS diode in a small 0402 package convenient for space  
constrained applications and an industry standard SOD-523 package. This TVS protection product offers ±30 kV  
IEC air-gap, ±30 kV contact ESD protection, and has an ESD clamp circuit with a back-to-back TVS diode for  
bipolar or bidirectional signal support. The 12 pF line capacitance of this ESD protection diode is suitable for a  
wide range of applications supporting data rates up to 400 Mbps.  
Typical application of this ESD protection product is the circuit protection for audio lines (microphone, earphone,  
and speakerphone), SD interfacing, keypad or other buttons, VBUS pin and ID pin of USB ports, and general-  
purpose I/O ports. This ESD clamp is a good fit for the protection of the end equipment like ebooks, tablets,  
remote controllers, wearables, set-top boxes, and electronic point of sale equipment.  
7.2 Functional Block Diagram  
1
2
7.3 Feature Description  
TPD1E10B06 is a bidirectional TVS with high ESD protection level. This device protects circuit from ESD strikes  
up to ±30 kV contact and ±30 kV air-gap specified in the IEC 61000-4-2 international standard. The device can  
also handle up to 6-A surge current (IEC61000-4-5 8/20 µs). The I/O capacitance of 12 pF supports a data  
rate up to 400 Mbps. This clamping device has a small dynamic resistance of 0.4 Ω typically, which makes the  
clamping voltage low when the device is actively protecting other circuits. For example, the clamping voltage is  
only 10 V when the device is taking 1-A transient current. The breakdown is bidirectional so that this protection  
device is a good fit for GPIO and especially audio lines which carry bidirectional signals. Low leakage allows  
the diode to conserve power when working below the VRWM. The industrial temperature range of –40°C to  
125°C makes this ESD device work at extensive temperatures in most environments. The 0402 package can fit  
into small electronic devices like mobile equipment and wearables whereas the SOD-523 package is good for  
industrial applications.  
7.4 Device Functional Modes  
TPD1E10B06 is a passive clamp that has low leakage during normal operation when the voltage between pin 1  
and pin 2 is below VRWM and activates when the voltage between pin 1 and pin 2 goes above VBR. During IEC  
ESD events, transient voltages as high as ±30 kV can be clamped between the two pins. When the voltages on  
the protected lines fall below the trigger voltage, the device reverts back to the low leakage passive state.  
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8 Application and Implementation  
Note  
Information in the following applications sections is not part of the TI component specification,  
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for  
determining suitability of components for their purposes, as well as validating and testing their design  
implementation to confirm system functionality.  
8.1 Application Information  
When a system contains a human interface connector, the system becomes vulnerable to large system-level  
ESD strikes that standard ICs cannot survive. TVS ESD protection diodes are typically used to suppress ESD at  
these connectors. TPD1E10B06 is a single-channel ESD protection device containing back-to-back TVS diodes,  
which is typically used to provide a path to ground for dissipating ESD events on bidirectional signal lines  
between a human interface connector and a system. As the current from ESD passes through the device, only a  
small voltage drop is present across the diode structure. This is the voltage presented to the protected IC. The  
low RDYN of the triggered TVS holds this voltage, VCLAMP, to a tolerable level to the protected IC.  
8.2 Typical Application  
L Audio  
Audio amplifier  
L Audio IN  
class AB  
L
(ESD sensitive)  
GND  
Speaker  
connector  
(source of ESD)  
R Audio  
GND  
Audio amplifier  
class AB  
(ESD sensitive)  
R Audio IN  
R
1
2
1
2
GND  
Figure 8-1. Typical Application Schematic  
8.2.1 Design Requirements  
For this design example, two TPD1E10B06s will be used to protect left and right audio channels. For this audio  
application, the following system parameters are known.  
Table 8-1. Design Parameters  
DESIGN PARAMETER  
VALUE  
AB  
Audio Amplifier Class  
Audio signal voltage range  
Audio frequency content  
–3 V to 3 V  
20 Hz to 20 kHz  
±20 kV Contact/ ±25 kV Air-Gap  
Required IEC 61000-4-2 ESD Protection  
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8.2.2 Detailed Design Procedure  
To begin the design process, some parameters must be decided upon; the designer should make sure:  
Voltage range on the protected line must not exceed the reverse standoff voltage of one or more TVS diodes  
(VRWM  
)
Operating frequency is supported by the I/O capacitance CIO of the TVS diode  
IEC 61000-4-2 protection requirement is covered by the IEC performance of the TVS diode  
For this application, the audio signal voltage range is –3 V to 3 V. The VRWM for the TVS is –5.5 V to 5.5 V;  
therefore, the bidirectional TVS will not break down during normal operation, and therefore normal operation of  
the audio signal will not be effected due to the signal voltage range. In this application, a bidirectional TVS like  
TPD1E10B06 is required.  
Next, consider the frequency content of this audio signal. In this application with the class AB amplifier, the  
frequency content is from 20 Hz to 20 kHz; ensure that the TVS I/O capacitance will not distort this signal by  
filtering it. With TPD1E10B06 typical capacitance of 12 pF, which leads to a typical 3-dB bandwidth of 400 MHz,  
this diode has sufficient bandwidth to pass the audio signal without distorting it.  
Finally, the human interface in this application requires above standard Level 4 IEC 61000-4-2 system-level  
ESD protection (±8 kV Contact/ ±15 kV Air-Gap). A standard TVS cannot survive this level of IEC ESD stress.  
However, TPD1E10B06 can survive at least ±30 kV Contact/ ±30 kV Air-Gap. Therefore, the device can provide  
sufficient ESD protection for the interface, even though the requirements are stringent. For any TVS diode to  
provide the full range of ESD protection capabilities, as well as to minimize the noise and EMI disturbances the  
board will see during ESD events, a system designer must use proper board layout of their TVS ESD protection  
diodes. See Section 10 for instructions on properly laying out TPD1E10B06.  
8.2.3 Application Curves  
Figure 8-2. IEC 61000-4-2 Clamp Voltage +8 kV  
Contact ESD  
Figure 8-3. IEC 61000-4-2 Clamp Voltage –8 kV  
Contact ESD  
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9 Power Supply Recommendations  
This device is a passive TVS diode-based ESD protection device, therefore there is no requirement to power it.  
Take care to make sure that the maximum voltage specifications for each pin are not violated.  
10 Layout  
10.1 Layout Guidelines  
The optimum placement is as close to the connector as possible.  
– EMI during an ESD event can couple from the trace being struck to other nearby unprotected traces,  
resulting in early system failures.  
– The PCB designer must minimize the possibility of EMI coupling by keeping any unprotected traces away  
from the protected traces which are between the TVS and the connector.  
Route the protected traces as straight as possible.  
Eliminate any sharp corners on the protected traces between the TVS and the connector by using rounded  
corners with the largest radii possible.  
– Electric fields tend to build up on corners, increasing EMI coupling.  
If pin 1 or pin 2 is connected to ground, use a thick and short trace for this return path  
10.2 Layout Example  
To connector  
To protected IC  
Place pin 1 on the signal line  
Minimum  
distance  
from  
connector  
(source of  
ESD)  
Thick and short return path to GND  
Figure 10-1. Layout Recommendation  
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11 Device and Documentation Support  
11.1 Receiving Notification of Documentation Updates  
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on  
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For  
change details, review the revision history included in any revised document.  
11.2 Support Resources  
TI E2Esupport forums are an engineer's go-to source for fast, verified answers and design help — straight  
from the experts. Search existing answers or ask your own question to get the quick design help you need.  
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do  
not necessarily reflect TI's views; see TI's Terms of Use.  
11.3 Trademarks  
TI E2Eis a trademark of Texas Instruments.  
All trademarks are the property of their respective owners.  
11.4 Electrostatic Discharge Caution  
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled  
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.  
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may  
be more susceptible to damage because very small parametric changes could cause the device not to meet its published  
specifications.  
11.5 Glossary  
TI Glossary  
This glossary lists and explains terms, acronyms, and definitions.  
12 Mechanical, Packaging, and Orderable Information  
The following pages include mechanical, packaging, and orderable information. This information is the most  
current data available for the designated devices. This data is subject to change without notice and revision of  
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.  
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PACKAGE OPTION ADDENDUM  
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8-Dec-2021  
PACKAGING INFORMATION  
Orderable Device  
Status Package Type Package Pins Package  
Eco Plan  
Lead finish/  
Ball material  
MSL Peak Temp  
Op Temp (°C)  
Device Marking  
Samples  
Drawing  
Qty  
(1)  
(2)  
(3)  
(4/5)  
(6)  
TPD1E10B06DPYR  
TPD1E10B06DPYT  
TPD1E10B06DYAR  
ACTIVE  
ACTIVE  
ACTIVE  
X1SON  
X1SON  
DPY  
DPY  
DYA  
2
2
2
10000 RoHS & Green  
250 RoHS & Green  
3000 RoHS & Green  
NIPDAU  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
Level-3-260C-168 HR  
-40 to 125  
-40 to 125  
-40 to 125  
(B1, B2, B6, BI)  
NIPDAU  
SN  
(B1, B2, B6, BI)  
1KF  
SOT-5X3  
(1) The marketing status values are defined as follows:  
ACTIVE: Product device recommended for new designs.  
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.  
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.  
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.  
OBSOLETE: TI has discontinued the production of the device.  
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance  
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may  
reference these types of products as "Pb-Free".  
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.  
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based  
flame retardants must also meet the <=1000ppm threshold requirement.  
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.  
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.  
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation  
of the previous line and the two combined represent the entire Device Marking for that device.  
(6)  
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two  
lines if the finish value exceeds the maximum column width.  
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information  
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and  
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.  
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.  
Addendum-Page 1  
PACKAGE OPTION ADDENDUM  
www.ti.com  
8-Dec-2021  
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.  
OTHER QUALIFIED VERSIONS OF TPD1E10B06 :  
Automotive : TPD1E10B06-Q1  
NOTE: Qualified Version Definitions:  
Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects  
Addendum-Page 2  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
5-Dec-2021  
TAPE AND REEL INFORMATION  
*All dimensions are nominal  
Device  
Package Package Pins  
Type Drawing  
SPQ  
Reel  
Reel  
A0  
B0  
K0  
P1  
W
Pin1  
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant  
(mm) W1 (mm)  
TPD1E10B06DPYR  
TPD1E10B06DPYR  
TPD1E10B06DPYR  
TPD1E10B06DPYT  
TPD1E10B06DPYT  
TPD1E10B06DPYT  
TPD1E10B06DPYT  
TPD1E10B06DYAR  
X1SON  
X1SON  
X1SON  
X1SON  
X1SON  
X1SON  
X1SON  
DPY  
DPY  
DPY  
DPY  
DPY  
DPY  
DPY  
2
2
2
2
2
2
2
2
10000  
10000  
10000  
250  
180.0  
178.0  
180.0  
180.0  
178.0  
180.0  
180.0  
178.0  
8.4  
8.4  
9.5  
9.5  
8.4  
8.4  
9.5  
9.5  
0.07  
0.7  
1.1  
0.47  
0.47  
0.66  
0.66  
0.47  
0.47  
0.5  
2.0  
2.0  
2.0  
2.0  
2.0  
2.0  
2.0  
4.0  
8.0  
8.0  
8.0  
8.0  
8.0  
8.0  
8.0  
8.0  
Q1  
Q1  
Q1  
Q1  
Q1  
Q1  
Q1  
Q1  
1.15  
1.15  
1.15  
1.15  
1.1  
0.66  
0.66  
0.7  
250  
250  
0.07  
0.73  
0.5  
250  
1.13  
1.94  
SOT-5X3 DYA  
3000  
0.73  
Pack Materials-Page 1  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
5-Dec-2021  
*All dimensions are nominal  
Device  
Package Type Package Drawing Pins  
SPQ  
Length (mm) Width (mm) Height (mm)  
TPD1E10B06DPYR  
TPD1E10B06DPYR  
TPD1E10B06DPYR  
TPD1E10B06DPYT  
TPD1E10B06DPYT  
TPD1E10B06DPYT  
TPD1E10B06DPYT  
TPD1E10B06DYAR  
X1SON  
X1SON  
X1SON  
X1SON  
X1SON  
X1SON  
X1SON  
SOT-5X3  
DPY  
DPY  
DPY  
DPY  
DPY  
DPY  
DPY  
DYA  
2
2
2
2
2
2
2
2
10000  
10000  
10000  
250  
203.2  
205.0  
184.0  
184.0  
205.0  
203.2  
189.0  
210.0  
196.8  
200.0  
184.0  
184.0  
200.0  
196.8  
185.0  
200.0  
33.3  
33.0  
19.0  
19.0  
33.0  
33.3  
36.0  
42.0  
250  
250  
250  
3000  
Pack Materials-Page 2  
PACKAGE OUTLINE  
DPY0002A  
X1SON - 0.45 mm max height  
S
C
A
L
E
1
1
.
0
0
0
PLASTIC SMALL OUTLINE - NO LEAD  
1.1  
0.9  
B
A
PIN 1 INDEX AREA  
0.7  
0.5  
0.45  
0.30  
C
SEATING PLANE  
0.08 C  
0.05  
0.00  
0.65  
1
2
SYMM  
0.55  
0.45  
2X  
0.1  
C A B  
SYMM  
0.3  
0.2  
2X  
0.05  
C A B  
4224561/B 03/2021  
NOTES:  
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing  
per ASME Y14.5M  
2. This drawing is subject to change without notice.  
www.ti.com  
EXAMPLE BOARD LAYOUT  
DPY0002A  
X1SON - 0.45 mm max height  
PLASTIC SMALL OUTLINE - NO LEAD  
2X (0.3)  
SYMM  
1
2
SYMM  
2X (0.5)  
(R0.05) TYP  
(0.7)  
LAND PATTERN EXAMPLE  
EXPOSED METAL SHOWN  
SCALE:60X  
0.07 MIN  
ALL AROUND  
0.07 MAX  
ALL AROUND  
METAL EDGE  
METAL UNDER  
SOLDER MASK  
EXPOSED  
METAL  
EXPOSED  
METAL  
SOLDER MASK  
OPENING  
SOLDER MASK  
OPENING  
SOLDER MASK  
DEFINED  
(PREFERRED)  
NON SOLDER MASK  
DEFINED  
SOLDER MASK DETAILS  
4224561/B 03/2021  
NOTES: (continued)  
3. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271).  
4. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view.  
It is recommended that vias under paste be filled, plugged or tented.  
www.ti.com  
EXAMPLE STENCIL DESIGN  
DPY0002A  
X1SON - 0.45 mm max height  
PLASTIC SMALL OUTLINE - NO LEAD  
(0)  
2X (0.3)  
2X (0.5)  
SYMM  
PCB PAD METAL  
UNDER SOLDER PASTE  
SYMM  
2
1
(R0.05) TYP  
(0.7)  
SOLDER PASTE EXAMPLE  
BASED ON 0.1 mm THICK STENCIL  
SCALE:60X  
4224561/B 03/2021  
NOTES: (continued)  
5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate  
design recommendations.  
www.ti.com  
PACKAGE OUTLINE  
DYA0002A  
SOT (SOD-523) - 0.77 mm max height  
PLASTIC SMALL OUTLINE  
1.7  
1.5  
PIN 1  
ID AREA  
A
0.85  
0.75  
NOTE 3  
2
1
1.3  
1.1  
0.3  
0.1  
0.7  
0.5  
B
2X  
TYP  
0.77 MAX  
C
SEATING PLANE  
0.05 C  
0.15  
2X  
0.08  
SYMM  
SYMM  
0.35  
0.25  
2X  
0.1  
0.05  
C A B  
0.4  
0.2  
2X  
4224978/B 09/2021  
NOTES:  
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing  
per ASME Y14.5M.  
2. This drawing is subject to change without notice.  
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not  
exceed 0.15 mm per side.  
4. Reference JEITA SC-79 registration except for package height  
www.ti.com  
EXAMPLE BOARD LAYOUT  
DYA0002A  
SOT (SOD-523) - 0.77 mm max height  
PLASTIC SMALL OUTLINE  
SYMM  
2X (0.67)  
(R0.05) TYP  
SYMM  
2
1
2X (0.4)  
(1.48)  
LAND PATTERN EXAMPLE  
SCALE:40X  
0.05 MIN  
AROUND  
0.05 MAX  
AROUND  
SOLDER MASK  
OPENING  
METAL UNDER  
SOLDER MASK  
METAL  
SOLDER MASK  
OPENING  
NON SOLDER MASK  
DEFINED  
SOLDER MASK  
DEFINED  
(PREFERRED)  
SOLDERMASK DETAILS  
4224978/B 09/2021  
NOTES: (continued)  
5. Publication IPC-7351 may have alternate designs.  
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.  
www.ti.com  
EXAMPLE STENCIL DESIGN  
DYA0002A  
SOT (SOD-523) - 0.77 mm max height  
PLASTIC SMALL OUTLINE  
SYMM  
2X (0.67)  
(R0.05) TYP  
SYMM  
2
1
2X (0.4)  
(1.48)  
SOLDER PASTE EXAMPLE  
BASED ON 0.1 mm THICK STENCIL  
SCALE:40X  
4224978/B 09/2021  
NOTES: (continued)  
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate  
design recommendations.  
8. Board assembly site may have different recommendations for stencil design.  
www.ti.com  
IMPORTANT NOTICE AND DISCLAIMER  
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE  
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”  
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY  
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD  
PARTY INTELLECTUAL PROPERTY RIGHTS.  
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate  
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable  
standards, and any other safety, security, regulatory or other requirements.  
These resources are subject to change without notice. TI grants you permission to use these resources only for development of an  
application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license  
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will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these  
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TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with  
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