TPD1S414 [TI]
具有 ESD 功能的 USB 充电器过压保护开关;
| 型号： | TPD1S414 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有 ESD 功能的 USB 充电器过压保护开关 开关 |
| 文件： | 总15页 (文件大小：1368K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPD1S414
www.ti.com.cn
ZHCSBQ5A –OCTOBER 2013–REVISED OCTOBER 2013
支持静电放电 (ESD) ，用于 VBUS_CON 引脚的 USB 充电器过压保护 (OVP)
开关
查询样品: TPD1S414
1
特性
应用范围
•
•
•
VBUS_CON 上的输入直流电压保护高达 30V
低 RON nFET 开关支持主机和充电模式
•
•
•
手机
电子书
耐受高达 100V 开路浪涌电压（按照 IEC61000-4-5
标准）
便携式媒体播放器
说明
•
•
内部 15ms 启动延迟
TPD1S414 是一款用于 USB 连接器的 VBUS 线路保护
的单芯片解决方案。 此双向 nFET 开关在保护内部系
统电路不受任何 VBUS_CON 引脚上过压情况影响的同
时，可确保充电和主机模式下的安全电流流量。 在
内部 30ms 软启动延迟以最大限度地减小 USB 涌
入电流
•
ESD 性能 VBUS_CON
–
–
±15kV 接触放电 (IEC 61000-4-2)
±15kV 空气间隙放电 (IEC 61000-4-2)
VBUS_CON 引脚上，这个器件能够处理高达 30V 超压保
•
•
•
集成输入启用和状态输出信号
热关断特性
护。在 EN 引脚切换为低电平时，TPD1S414 在接通
nFET 之前通过一个软启动延迟来等待 20ms。 ACK
引脚表示 FET 完全接通。
节省空间的晶圆芯片级 (WCSP) 封装
(1.4mm x 1.89mm)
YZ PACKAGE
(TOP VIEW - SEE THROUGH)
GND
GND
VBUS_SYS
VBUS_SYS
VBUS_CON
VBUS_SYS
VBUS_CON
VBUS_CON
GND
GND
ACK
EN
12-YZ Pin Mapping
1
2
3
4
A
B
C
GND
ACK
EN
VBUS_SYS
VBUS_SYS
VBUS_CON
VBUS_SYS
VBUS_CON
VBUS_CON
GND
GND
GND
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2013, Texas Instruments Incorporated
English Data Sheet: SLLSEH9
TPD1S414
ZHCSBQ5A –OCTOBER 2013–REVISED OCTOBER 2013
www.ti.com.cn
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
FUNCTIONAL BLOCK DIAGRAM
VBUS
_
VBUS_SYS
CON
Precision
Surge
Clamping
Circuit
Control Logic
and Charge
Pump
/ACK
Internal Bandgap
Reference
/EN
GND
Table 1. DEVICE OPERATION
Voltage Condition
VBUS_SYS
Current Condition
VBUS_CON
EN
Current Flow
No Flow
Comment
Switch off
ACK Pin
High-Z
X
X
<VBUS_CON
High
High
>VBUS_CON
VBUS_SYS to VBUS_CON
Switch off, current flows through the body diode
High-Z
Current flows through the switch, normal device
charging mode
<OVP
<OVP
<VBUS_CON
>VBUS_CON
Low
Low
VBUS_CON to VBUS_SYS
VBUS_SYS to VBUS_CON
Low
Low
Current flows through the switch, normal host
mode
>OVP
>OVP
<VBUS_CON
>VBUS_CON
Low
Low
No Flow
Switch off due to OVP
High-Z
High-Z
VBUS_SYS to VBUS_CON
Switch off, current flows through the body diode
No Flow/ Current thru
Body Diode
X
X
X
THERMAL SHUTDOWN CONDITION
Low Voltage is cut-off from the system
High-Z
High-Z
<VUVLO
<VBUS_CON
Low
No Flow
2
Copyright © 2013, Texas Instruments Incorporated
TPD1S414
www.ti.com.cn
ZHCSBQ5A –OCTOBER 2013–REVISED OCTOBER 2013
PIN DESCRIPTIONS
PIN NAME
PIN NUMBER
B1
PIN TYPE
DESCRIPTION
ACK
O
Open-Drain Acknowledge pin. See the Device Operation section.
Enable Active-Low Input. Drive EN low to enable the switch. Drive EN high to
disable the switch.
EN
C1
I
Connect to USB connector VBUS_CON
IEC61000-4-2 ESD protection
IEC61000-4-5 Surge protection
;
VBUS_CON
C3, C2, B3
I/O
VBUS_SYS
GND
A3, A2, B2
I/O
Connect to internal VBUS plane
Connect to PCB ground plane
A1, A4, B4, C4
Ground
For the most current package and ordering information, see the Package Option Addendum at the end of this
document, or see the TI Web site at www.ti.com.
(1)(2)
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
MIN
–0.3
–0.5
–0.5
–0.5
–40
MAX
30
UNIT
V
Supply voltage from USB connector, VBUS_CON
Internal Supply DC voltage Rail on the PCB, VBUS_SYS
Voltage on Input pin (EN). VEN
7
V
7
V
Voltage on ACK pin
7
V
Storage temperature range, TSTG
Operating Free Air Temperature, TA
IEC 61000-4-2 Contact Discharge
IEC 61000-4-2 Air-gap Discharge
Human-Body Model
150
85
°C
°C
kV
kV
kV
A
–40
VBUS_CON pin
VBUS_CON pin
ALL Pins
±15
±15
±2
IEC 61000-4-5 Peak Pulse Current (tp = 8/20 μs)
IEC 61000-4-5 Peak Pulse Power (tp = 8/20 μs)
IEC 61000-4-5 Open circuit voltage (tp = 1.2/50 µs)
Output load capacitance, CLOAD
VBUS_CON pin
VBUS_CON pin
VBUS_CON pin
VBUS_SYS pin
VBUS_CON pin
21
700
100
50
W
V
0.1
0.1
µF
µF
Input capacitance, CON
50
(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not implied.
(2) The algebraic convention, whereby the most negative value is a minimum and the most positive value is a maximum.
THERMAL INFORMATION
YZ
THERMAL METRIC(1)
UNITS
12 PINS
89
θJA
Junction-to-ambient thermal resistance
θJC(top)
θJB
Junction-to-case(top) thermal resistance
Junction-to-board thermal resistance
0.6
16.3
2.7
°C/W
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case(bottom) thermal resistance
ψJB
16.2
n/A
θJC(bottom)
(1) 有关传统和全新热度量的更多信息，请参阅 IC 封装热度量 应用报告 （文献号：ZHCA543）。
Copyright © 2013, Texas Instruments Incorporated
3
TPD1S414
ZHCSBQ5A –OCTOBER 2013–REVISED OCTOBER 2013
www.ti.com.cn
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
PARAMETER
MIN
NOM
MAX
UNIT
V
VBUS_CON
VBUS_SYS
CLOAD
Supply voltage from USB connector
Internal Supply DC voltage Rail on the PCB
Output load capacitance
5.9
5.9
V
VBUS_SYS pin
VBUS_CON pin
ACK pin
2.2
1
µF
µF
kΩ
CIN
Input capacitance
RPULLUP
Pull up resistor
4.3
100
3.5
1
VBUS_CON
VBUS_SYS
IVBUS
Continuous current on VBUS_CON and VBUS_SYS pins
Continuous current through the FET body diode
A
A
IDIODE
SUPPLY CURRENT CONSUMPTION
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Measured at VBUS_CON pin,
VBUS_CON = 5 V, EN =5V
IVBUS_SLEEP
IVBUS
30
70
µA
VBUS_CON Operating Current
Consumption
Measured at VBUS_CON pin,
VBUS_CON = 5 V, EN 0 V and no load
175
373
373
µA
µA
Measured at VBUS_SYS pin,
VBUS_SYS = 5 V, EN = 0 V and
VBUS_CON = Hi Z
VBUS_CON Operating Current
Consumption
IVBUS_SYS
175
Measured at VBUS_SYS
.
IHOST_LEAK
Host Mode Leakage current
VBUS_CON = Hi Z, EN = 5 V,
VBUS_SYS = 5V
90
200
µA
ELECTRICAL CHARACTERISTICS (EN, ACK PINS)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
V
VIH
VIL
IIL
High-level input voltage, EN
Low-level input voltage, EN
Input Leakage Current EN
Low-level output voltage, ACK
1.2
6
0.8
1
V
VI = 3.3 V
IOL = 3 mA
µA
V
VOL
0.4
ELECTRICAL CHARACTERISTICS (OVP CIRCUIT)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Input overvoltage protection
threshold, VBUS_CON
VOVP_RISING
VHYS_OVP
VOVP_FALLING
VUVLO
VBUS_CON increasing from 5 V
6
6.2
6.4
V
VBUS_CON decreasing from 7 V to
5 V
Hysteresis on OVP, VBUS_CON
50
mV
V
Input overvoltage protection
threshold, VBUS_CON
VBUS_CON decreasing from 7 V to
5 V
5.93
3.1
6.37
3.5
Input under voltage lockout,
VBUS_CON
VBUS_CON voltage rising from 0 V
to 5 V
3.3
100
3.2
3.6
V
Difference between rising and
falling UVLO thresholds
VHYS_UVLO
VUVLO_FALLING
VUVLO_SYS
Hysteresis on UVLO, VBUS_CON
mV
V
Input under voltage lockout,
VBUS_CON
VBUS_CON voltage rising from 5 V
to 0 V
3
3.4
4.3
VBUS_SYS under voltage lockout,
VBUS_SYS
VBUS_SYS voltage rising from 0 V
to 5 V
3.1
V
4
Copyright © 2013, Texas Instruments Incorporated
TPD1S414
www.ti.com.cn
ZHCSBQ5A –OCTOBER 2013–REVISED OCTOBER 2013
ELECTRICAL CHARACTERISTICS (OVP CIRCUIT) (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Difference between rising and
falling UVLO thresholds on
VBUS_SYS
VBUS_SYS UVLO Hysteresis,
VBUS_SYS
VHYS_UVLO_SYS
480
mV
VBUS_SYS undervoltage lockout,
VBUS_SYS
VBUS_SYS voltage falling from 7 V
to 5 V
VUVLO_SYS_FALL
3
3.2
3.4
V
THERMAL SHUTDOWN FEATURE
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
145
35
MAX
UNIT
°C
Thermal Shutdown
Junction temperature
Junction temperature
TSHDN
Thermal-Shutdown Hysteresis
°C
SWITCHING CHARACTERISTICS (nFET)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VBUS_CON = 5 V, IOUT = 1 A,
TA = 25˚C
RDS(on)
Switch ON Resistance
39
50
mΩ
TIMING REQUIREMENTS
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Measured from EN asserted LOW to
nFET beginning to Turn ON(1)
excluding soft-start time
tDELAY
USB Charging Turn-ON Delay
20
25
4
ms
Measure from VBUS_SYS rises above
25% (with 1 MΩ load/ NO CLOAD) until
ACK goes Low (10%)
USB Charging rise time (Soft
Start Delay)
tSS
ms
µs
Measured from EN asserted High to
VBUS_SYS falling to 10% with RLOAD =
tOFF_DELAY
USB Charging Turn-OFF time
10 Ω and No CLOAD on VBUS_SYS
Over Voltage Protection
tOVP_response OVP Response time
Measured from OVP Condition to FET
Turn OFF(1)(2). VBUS_CON rises at 1V /
100ns
100
ns
Measured from OVP Clear to FET Turn
ON(1)(3)
tOVP_Recov
Recovery Time
20
ms
(1) Shown in TIMING DIAGRAM Plots
(2) Parameters provided for reference only, and do not constitute part of TI's published device specifications for purposes of TI's product
warranty.
(3) Excludes soft start time
Copyright © 2013, Texas Instruments Incorporated
5
TPD1S414
ZHCSBQ5A –OCTOBER 2013–REVISED OCTOBER 2013
www.ti.com.cn
TYPICAL CHARACTERISTICS
800
700
600
500
400
300
200
100
0
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
TA = t30C
TA = 25C
T = 85C
A
0
5
10
15
20
25
30
35
0
20
40
60
80
100
±40
±20
Input Voltage (V)
Temperature (C)
C001
C002
Figure 1. Input Supply Current vs. Supply Voltage
Figure 2. Normalized RDS(ON) vs. Temperature
3.0
1.10
1.05
1.00
0.95
0.90
2.5
2.0
1.5
1.0
0.5
0.0
0.1
0.6
1.1
1.6
2.1
2.6
0
20
40
60
80
100
±40
±20
Output Current (A)
Temperature (C)
C003
C004
Figure 3. Normalized RDS(ON) vs. Output Current
Figure 4. Normalized VOVP
2.00
1.80
1.60
1.40
1.20
1.00
0.80
0.60
0.40
0.20
0.00
14
12
10
8
6
4
VBUS_SYS
VBUS_CON
200 400
2
0
0
20
40
60
80
100
0
600
800
1000
1200
1400
±40
±20
Temperature (C)
Time (ns)
C005
C006
Figure 5. Normalized TDELAY
Figure 6. VOVP Response Time
6
Copyright © 2013, Texas Instruments Incorporated
TPD1S414
www.ti.com.cn
ZHCSBQ5A –OCTOBER 2013–REVISED OCTOBER 2013
TYPICAL CHARACTERISTICS (continued)
6
5
50
45
40
35
30
25
20
15
10
5
Vsys (V)
Vcon (V)
Icon (A)
TPD1S414YZ
8/20 Surge Waveforms
80 V (into an open), Powered Down
4
3
2
VBUS_SYS
VBUS_CON
I_VBUS_CON
1
0
0
±1
±5
0
5
10
15
20
25
30
35
0
10
20
30
40
50
60
70
80
90
±15 ±10 ±5
±10
Time (ms)
Time (µs)
C007
C008
Figure 7. Power Up With 2.2 µF on VBUS_SYS
Figure 8. Response to a 100-V Surge
Copyright © 2013, Texas Instruments Incorporated
7
TPD1S414
ZHCSBQ5A –OCTOBER 2013–REVISED OCTOBER 2013
www.ti.com.cn
DEVICE INFORMATION
DEVICE OPERATION
The TPD1S414 provides a single-chip ESD protection, surge protection and over voltage protection solution for
portable USB charging and Host interfaces. It offers over voltage protection at the VBUS_CON pin up to 30 V. The
TPD1S414 also provides a ACK pin that indicates to the system if a fault condition has occurred. The TPD1S414
offers an ESD clamp and a Surge Clamp for VBUS_CON pin, thus eliminating the need for external TVS clamp
circuits in the application.
The TPD1S414 has an internal oscillator and charge pump that controls the turn-on of the internal nFET switch.
The internal oscillator controls the timers that enable the charge pump and resets the open-drain ACK output. If
VBUS_CON is less than VOVP, the internal charge pump is enabled. After a 15 ms internal delay, the charge-pump
starts-up, turns on the internal nFET switch through a soft start. Once the nFET is completely turned ON,
TPD1S414 asserts ACK pin LOW. At any time, if VBUS_CON rises above VOVP, the ACK pin is in High-Z and is
pulled HIGH through external resistors. The nFET switch is turned OFF.
OVP OPERATION
When the VBUS_CON voltage rises above VOVP, the internal nFET switch is turned OFF, removing power from the
system. The response is rapid, with the FET switch turning off in less than 100 ns. The ACK pin is set to High-Z
when an overvoltage condition is detected and the nFET is turned OFF. This pin can be pulled up through
external resistors to indicate a OVP condition. When the VBUS_CON voltage returns below VOVP – VHYS-OVP, the
nFET switch is turned on again after the internal delay of tOVP_Recov. This delay time ensures that the VBUS_CON
supply has stabilized before turning the switch back on. After tOVP_Recov, the TPD1S414 turns ON the nFET
through a soft start to ensure that the USB Inrush current compliance is met. When the OVP condition is cleared
and the nFET is completely turned ON, the ACK is reset LOW.
TIMING DIAGRAMS
Overtemperature
Condition
VOVP
VBUS_CON
VUVLO
tDELAY
EN
tOFF_DELAY
tSS
VBUS_SYS
Figure 9. Thermal Shutdown Operation
8
Copyright © 2013, Texas Instruments Incorporated
TPD1S414
www.ti.com.cn
ZHCSBQ5A –OCTOBER 2013–REVISED OCTOBER 2013
APPLICATION INFORMATION
VBUS
DP
VBUS_CON VBUS_SYS
CIN
CLOAD
TPD1S414
to VCC
RPULLUP
DM
ID
ACK
to µP
PMIC
EN
GND
to µP
GND
ESD
TPD3E105
GND
Figure 10. Typical Application Configuration for TPD1S414
The IEC 61000-4-5 standard specifies the lightning and industrial surge model. Power lines like the VBUS line on
the USB port is subject to switching and lightning transients. Power supply switching transients can enter the
system due to capacitor bank switching on the rail, minor load switching on the system and various system faults
like arcing to the grounding system of the installation. Direct lightning to the outer installations cause an over
voltage condition on the VBUS line. In the event of an over voltage condition, the OVP block of the Processor or
the protection circuitry turns off isolating the system from these transients. Abruptly turning off the Load, causes a
further ripple due to the inductive nature of the charging cable. End systems require protection against these
transients. These transients have greater energy than the ESD events. Systems cannot be protected from these
transients using simple ESD diodes. The TPD1S414 has a precision trigger and precision clamping circuit that
ensures a DC tolerance of 30 V while suppressing surge voltage up to 100V under 35 V.
Copyright © 2013, Texas Instruments Incorporated
9
TPD1S414
ZHCSBQ5A –OCTOBER 2013–REVISED OCTOBER 2013
www.ti.com.cn
BOARD LAYOUT
TPD1S414 can be routed in a single layer PCB. PCB traces to VBUS_SYS, VBUS_CON, and GND can be routed in
the fashion shown in Figure 11.
Figure 11. VBUS_SYS, VBUS_CON, and GND pins tied together
Tying VBUS_SYS, VBUS_CON, and GND pins respectively together provides lower resistance connectivity between
the USB connector and the PMIC. For this example, the trace widths to VBUS_SYS, VBUS_CON are 25 mils (0.635
mm) under TPD1S414. There are no VIAs required within the SMD pads in this design. Stitching VIAs for GND
can be placed near the component instead.
The decoupling capacitors per the recommended operating settings should be placed as close as possible to the
TPD1S414. There should be a short path from the device ground pins to the system ground plane. This ensures
best protection under ESD and surge transients.
10
Copyright © 2013, Texas Instruments Incorporated
TPD1S414
www.ti.com.cn
ZHCSBQ5A –OCTOBER 2013–REVISED OCTOBER 2013
REVISION HISTORY
Changes from Original (October 2013) to Revision A
Page
•
•
•
将说明中的文本从：TPD1S414 在接通 nFET 前等待 15ms 更改为：TPD1S414 在接通 nFET 前等待 20ms .................... 1
Deleted Peak input current on VBUS_CON pin, IBUS from the ABSOLUTE MAXIMUM RATINGS table .................................. 3
Deleted Continuous forward current through the FET body diode, IDIODE from the ABSOLUTE MAXIMUM RATINGS
table ...................................................................................................................................................................................... 3
•
•
•
Added Voltage on ACK pin to the ABSOLUTE MAXIMUM RATINGS table ........................................................................ 3
Added values to the THERMAL INFORMATION table ......................................................................................................... 3
Added Continuous current on VBUS_CON and VBUS_SYS pins to the RECOMMENDED OPERATING CONDITIONS
table ...................................................................................................................................................................................... 4
•
Added Continuous forward current through the FET body diode, IDIODE to the RECOMMENDED OPERATING
CONDITIONS table ............................................................................................................................................................... 4
•
•
•
Changed the IHOST_LEAK MAX value From: 160 To: 200 µA in the SUPPLY CURRENT CONSUMPTION table ................. 4
Changed horizontal axis labeling on Figure 6 ...................................................................................................................... 6
Deleted graphs: Enabling the Load Switch, Connecting VBUS_CON, and OVP Operation from the TIMING DIAGRAMS
section ................................................................................................................................................................................... 8
•
•
Changed Figure 10 ............................................................................................................................................................... 9
Added text to the APPLICATION INFORMATION section ................................................................................................... 9
Copyright © 2013, Texas Instruments Incorporated
11
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPD1S414YZR
ACTIVE
DSBGA
YZ
12
3000 RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 85
RH414
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
18-Jan-2020
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPD1S414YZR
TPD1S414YZR
DSBGA
DSBGA
YZ
YZ
12
12
3000
3000
180.0
178.0
8.4
9.2
1.5
1.99
1.99
0.75
0.75
4.0
4.0
8.0
8.0
Q2
Q2
1.49
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
18-Jan-2020
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPD1S414YZR
TPD1S414YZR
DSBGA
DSBGA
YZ
YZ
12
12
3000
3000
182.0
220.0
182.0
220.0
20.0
35.0
Pack Materials-Page 2
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