TPD2E009 [TI]
2-CHANNEL ESD SOLUTION FOR HIGH-SPEED (6 GBPS) DIFFERENTIAL INTERFACE; 2通道ESD解决方案适用于高速（ 6 Gbps）的差分接口
| 型号： | TPD2E009 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 2-CHANNEL ESD SOLUTION FOR HIGH-SPEED (6 GBPS) DIFFERENTIAL INTERFACE |
| 文件： | 总13页 (文件大小：920K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPD2E009
www.ti.com.............................................................................................................................................................. SLVS953A–JUNE 2009–REVISED JUNE 2009
2-CHANNEL ESD SOLUTION FOR HIGH-SPEED (6 GBPS) DIFFERENTIAL INTERFACE
1
FEATURES
DBZ/DRT PACKAGE
•
0.05-pF Matching Capacitance Between the
Differential Signal Pair
(TOP VIEW)
1
D+
D–
•
Single-Pair Differential Lines to Protect the
Differential Data and Clock Lines of the LVDS,
SATA, Ethernet, or USB High-Speed (HS)
Interface
3
GND
2
•
Flow-Through Pin Mapping for the High-Speed
Lines Ensures Zero Additional Skew Due to
Board Layout While Placing ESD-Protection
Chip Near the Connector
DRY PACKAGE
(TOP VIEW)
6
5
4
N.C.
1
2
3
D+
V
•
•
Supports Data Rates in Excess of 6 Gbps
GND
N.C
CC
ESD Protection Meets or Exceeds
IEC61000-4-2 (Level 4)
D–
•
5-A Peak Pulse Current (8/20 µs Pulse) for
VBUS and D+, D–, and ID Lines
N.C. – No internal connection
•
•
Industrial Temperature Range: –40°C to 85°C
Multiple Space-Saving Package Options
APPLICATIONS
•
•
•
•
•
Notebooks
Set-Top Boxes
DVD Players
Media Players
Portable Computers
DESCRIPTION/ORDERING INFORMATION
The TPD2E009 provides 2 ESD clamp circuits with flow-through pin mapping for ease of board layout. This
device has been designed to protect sensitive components which are connected to ultra high-speed data and
transmission lines. The TPD2E009 offers protection from stress caused by ESD (electrostatic discharge). This
device also offers 5 A (8/20 µs) peak pulse current ratings per IEC 61000-4-5 (lightning) specification.
The monolithic silicon technology allows matching between the differential signal pairs. The less than differential
0.05-pF capacitance ensures that the differential signal distortion due to added ESD clamp remains minimal. The
0.7-pF line capacitance is suitable for high-speed data rate (in excess of 6 Gbps).
The TPD2E009 conforms to IEC61000-4-2 (Level 4) ESD protection. The DRT (1 mm × 1 mm) package is
offered for space-saving portable applications. The industry standard DBZ (2.4 mm × 2.9 mm) package offers
additional flexibility in the board layout for the system designer.
The TPD2E009 is characterized for operation over ambient air temperature range of –40°C to 85°C.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2009, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
TPD2E009
SLVS953A–JUNE 2009–REVISED JUNE 2009.............................................................................................................................................................. www.ti.com
ORDERING INFORMATION
TA
PACKAGE(1)(2)
ORDERABLE PART NUMBER
TPD2E009DRYR
TOP-SIDE MARKING
SON – DRY
SOP – DBZ
SOT– DRT
Tape and reel
PREVIEW
NFLR
4T
–40°C to 85°C
Tape and reel
Tape and reel
TPD2E009DBZR
TPD2E009DRTR
(1) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
(2) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
CIRCUIT DIAGRAMS
DRY Circuit
VCC
D–
D+
GND
DBZ/DRT Circuit
D–
D+
GND
TERMINAL FUNCTIONS
TERMINAL
TYPE
DESCRIPTION
DBZ/DRT
PIN NO.
DRY(1)
PIN NO.
NAME
High-speed ESD clamp, provides ESD protection to the high-speed differential
data lines
D+, D-
1, 2
4, 6
ESD port
VCC
–
3
5
3
Supply
GND
Power supply
Ground
GND
(1) Product Preview
2
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Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s): TPD2E009
TPD2E009
www.ti.com.............................................................................................................................................................. SLVS953A–JUNE 2009–REVISED JUNE 2009
ABSOLUTE MAXIMUM RATINGS(1)
over operating free-air temperature range (unless otherwise noted)
MIN
0
MAX UNIT
IO voltage tolerance
D+, D– pins
6
TA
Operating free-air temperature range
Storage temperature range
–40
–65
85
125
±8
±8
5
°C
°C
kV
kV
A
Tstg
IEC 61000-4-2 Contact Discharge
IEC 61000-4-2 Air-Gap Discharge
D+, D– pins
D+, D– pins
D+, D– pins
D+, D– pins
ESD protection
Peak pulse current (tp = 8/20 µs)
Peak pulse power (tp = 8/20 µs)
45
W
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the
specifications is not implied. Exposure to absolute maximum-rated conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
D+,D– pins to ground
MIN
TYP
MAX UNIT
VRWM
Vclamp
IIO
Reverse stand-off voltage
Clamp voltage
5.5
8
V
V
D+,D– pins to ground,
VIO = 2.5 V, ID = 8 mA
IIO = 1 A
Current from IO port to supply pins
0.01
0.8
0.1
µA
D+,D– pins,
lower clamp diode,
VIO = 2.5 V, ID = 8 mA
VCC = 0 V, ID = –8 mA
0.6
0.6
0.95
VD
Diode forward voltage
V
D+,D– pins,
upper clamp diode,
DRY package
0.8
0.95
Rdyn
Dynamic resistance
IO capacitance
D+,D– pins,
I = 1 A
1
Ω
D+,D– pins, DBZ
Package
VIO = 2.5 V
0.9
pF
CIO
D+,D– pins, DRT
Package
VIO = 2.5 V
0.7
pF
V
VBR
Break-down voltage
IIO = 1 mA
7
Copyright © 2009, Texas Instruments Incorporated
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3
Product Folder Link(s): TPD2E009
TPD2E009
SLVS953A–JUNE 2009–REVISED JUNE 2009.............................................................................................................................................................. www.ti.com
TYPICAL OPERATING CHARACTERISTICS
10
1.20E-12
1.10E-12
1.00E-12
9.00E-13
8.00E-13
7.00E-13
6.00E-13
5.00E-13
T
= 25°C
A
5
0
–5
–10
–15
–20
–25
–30
–35
–40
DBZ Package
DRT Package
D–
D+
V
= 2.5 V
IO
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
–40
25
55
85
Voltage (V)
Temperature (°C)
Figure 1. IO Capacitance vs IO Voltage
Figure 2. Leakage Current vs Temperature
11
10
9
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
60
55
50
45
40
35
30
25
20
15
10
5
Measured at one IO,
the other IO open
8
7
6
5
Current (A)
4
3
Power (W)
2
1
0
0
5
10
15
20
25
30
35
40
45
50
0
Time (ms)
0
5
10
15
20
25
30
35
40
Voltage (V)
Figure 3. Peak Pulse Waveforms
Figure 4. D+,D– Transmission Line Pulser Plot (100 ns
Pulse, 10 ns Rise Time)
100
90
80
70
60
50
40
30
20
10
0
20
10
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-10
-20
0
25
50
75
100
125
150
175
200
0
25
50
75
100
125
150
175
200
Time (ns)
Time (ns)
Figure 5. IEC Clamping Waveforms (8 kV Contact)
Figure 6. IEC Clamping Waveforms (–8 kV Contact)
4
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Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s): TPD2E009
TPD2E009
www.ti.com.............................................................................................................................................................. SLVS953A–JUNE 2009–REVISED JUNE 2009
TYPICAL OPERATING CHARACTERISTICS (continued)
Eye Diagrams
Figure 7. Eye Diagram With TPD2E009
(3.3 Gbps Data Rate)
Figure 8. Eye Diagram Without TPD2E009
(3.3 Gbps Data Rate)
(3-Pin DBZ Package)
(3-Pin DBZ Package)
Figure 9. Eye Diagram With TPD2E009
(5.0 Gbps Data Rate)
Figure 10. Eye Diagram Without TPD2E009
(5.0 Gbps Data Rate)
(3-Pin DBZ Package)
(3-Pin DBZ Package)
Copyright © 2009, Texas Instruments Incorporated
Submit Documentation Feedback
5
Product Folder Link(s): TPD2E009
TPD2E009
SLVS953A–JUNE 2009–REVISED JUNE 2009.............................................................................................................................................................. www.ti.com
TYPICAL OPERATING CHARACTERISTICS (continued)
Figure 11. Eye Diagram With TPD2E009
(6.0 Gbps Data Rate)
Figure 12. Eye Diagram Without TPD2E009
(6.0 Gbps Data Rate)
(3-Pin DBZ Package)
(3-Pin DBZ Package)
6
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Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s): TPD2E009
TPD2E009
www.ti.com.............................................................................................................................................................. SLVS953A–JUNE 2009–REVISED JUNE 2009
APPLICATION INFORMATION
Typical Application
Figure 13. TPD2E009 in Differential eSATA Interface
Figure 13 shows the board layout scheme for the D+/D– lines of a single differential pair. It allows the differential
signal pairs couple together right after they touch the ESD ports (pin 1 and pin 2) of the TPD2E009.
Designing with High-Speed Differential Signals
Layout considerations, such as package selection, trace routing, etc. must be taken into account while designing
the ESD clamp circuit for high-speed interface. Difficult routing can lead the designer to use vias or stubs in the
board traces, creating significant disruption in the line impedance in the high-speed signal path. Poor package
choice can force designer to route differential traces with unequal lengths and add the skew in the signals. It is
recommended to closely couple the differential traces to reduce the EMI interference.
The TPD2E009 can provide system level ESD protection to the high-speed differential ports (>6 Gbps data rate).
The flow-through package offers flexibility for board routing with traces up to 15 mills wide. Figure 14 and
Figure 15 show the board layout scheme for the D+/D– lines of a single differential pair. It allows the differential
signal pairs couple together right after they touch the ESD ports (pin 1 and pin 2) of the TPD2E009.
Copyright © 2009, Texas Instruments Incorporated
Submit Documentation Feedback
7
Product Folder Link(s): TPD2E009
TPD2E009
SLVS953A–JUNE 2009–REVISED JUNE 2009.............................................................................................................................................................. www.ti.com
1.27 mm
1.27 mm
BOARD LAYOUT
FOR DRT PACKAGE
TPD2E009DRTR AT
eSATA PORT
GND
D+
D–
GND VIA
Figure 14. TPD2E009DRTR at eSATA Connector Interface
1.27 mm
1.27 mm
BOARD LAYOUT
FOR DBZ PACKAGE
TPD2E009DBZR AT
eSATA PORT
GND
GND VIA
D+
D–
Figure 15. TPD2E009DBZR at eSATA Connector Interface
8
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Product Folder Link(s): TPD2E009
PACKAGE MATERIALS INFORMATION
www.ti.com
7-Aug-2009
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPD2E009DBZR
TPD2E009DRTR
SOT-23
SOT
DBZ
DRT
3
3
3000
3000
180.0
180.0
9.2
8.4
3.18
1.16
3.28
1.16
1.32
0.63
4.0
4.0
8.0
8.0
Q3
Q3
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
7-Aug-2009
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPD2E009DBZR
TPD2E009DRTR
SOT-23
SOT
DBZ
DRT
3
3
3000
3000
202.0
180.0
201.0
180.0
28.0
85.0
Pack Materials-Page 2
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