TPD2E2U06_14 [TI]
Dual-Channel High-Speed ESD Protection Device;
| 型号： | TPD2E2U06_14 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | Dual-Channel High-Speed ESD Protection Device |
| 文件： | 总8页 (文件大小：252K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPD2E2U06
www.ti.com
SLLSEG9A –JUNE 2013–REVISED JUNE 2013
Dual-Channel High-Speed ESD Protection Device
Check for Samples: TPD2E2U06
1
FEATURES
DESCRIPTION
The TPD2E2U06 is
a
dual-channel ultra-low
2
•
Provides System-Level ESD Protection for
Low-Voltage IO Interface
capacitance ESD-protection device. The device offers
±25-KV IEC contact and ±30-KV IEC air-gap ESD
protection. The 1.5-pF line capacitance of the
TPD2E2U06 makes the device suitable for a wide
range of applications. Typical application interfaces
are USB 2.0, LVDS, and I2C™.
•
IEC 61000-4-2 Level 4
–
–
±25 kV (contact discharge)
±30 kV (air-gap discharge)
•
•
•
•
•
IO Capacitance 1.5 pF (Typ)
DC Breakdown Voltage 6.5 V (Min)
Ultra-Low Leakage Current 10 nA (Max)
Low ESD Clamping Voltage
DRL
1.65 mm × 1.2 mm × 0.6 mm
(0.5-mm PITCH)
Industrial Temperature Range: –40°C to
+125°C
5
1
IO2
NC
NC
•
Small Easy-to-Route DRL Package
2
3
APPLICATIONS
•
•
•
•
Gaming Machines
eBook
IO1
4
GND
Portable Media Players
Digital Camera
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
I2C is a trademark of NXP Semiconductors.
PRODUCT PREVIEW information concerns products in the
formative or design phase of development. Characteristic data and
other specifications are design goals. Texas Instruments reserves
the right to change or discontinue these products without notice.
Copyright © 2013, Texas Instruments Incorporated
TPD2E2U06
SLLSEG9A –JUNE 2013–REVISED JUNE 2013
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
5.5(1)
85(1)
±30(1)
±25(1)
125
UNIT
A
IPP
Peak pulse current (tp = 8/20 μs)
Peak pulse power (tp = 8/20 μs)
IEC 61000-4-2 air-gap ESD
IEC 61000-4-2 contact ESD
Operating temperature
PPP
W
kV
kV
°C
°C
–40
–65
Storage temperature
155
(1) Measured at 25°C.
ELECTRICAL CHARACTERISTICS
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VRWM
Reverse stand-off voltage
IO to GND
IIO < 10 µA
5.5
V
VCLAMP
IPP = 1 A, TLP(1)
IPP = 5 A, TLP(1)
IPP = 1 A, TLP(1)
IPP = 5 A, TLP(1)
IO to GND(2)
9.7
12.4
1.9
V
VCLAMP
GND to IO
V
4
RDYN
RDYN
CL
Dynamic resistance
Dynamic resistance
Line capacitance
0.5
Ω
Ω
GND to IO(2)
f = 1 MHz, VBIAS = 2.5 V(3)
0.25
1.5
1.9
pF
pF
CCROSS
Channel-to-channel input
capacitance
Pin 4 = 0 V, f = 1 MHz, VBIAS = 2.5 V, between
channel pins(3)
0.02
0.03
∆
Variation of channel input
capacitance
Pin 4 = 0 V, f = 1 MHz, VBIAS = 2.5 V,
channel_x pin to GND – channel_y pin to GND
0.03
1
0.1
pF
CIO-TO-GND
(3)
VBR
Break-down voltage
Leakage current
IIO = 1 mA
VIO = 2.5 V
6.5
8.5
10
V
ILEAK
nA
(1) Transmission Line Pulse with 10-ns rise time, 100-ns width.
(2) Extraction of RDYN Using least squares fit of TLP characteristics between I = 20 A and I = 30 A.
(3) Measured at 25°C.
2
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Copyright © 2013, Texas Instruments Incorporated
Product Folder Links: TPD2E2U06
TPD2E2U06
www.ti.com
SLLSEG9A –JUNE 2013–REVISED JUNE 2013
DEVICE INFORMATION
FUNCTIONAL BLOCK DIAGRAM
IO1
IO2
GND
Figure 1. CIRCUIT SCHEMATIC DIAGRAM
PIN FUNCTIONS
PIN
I/O
DESCRIPTION
NAME
IO1
NO.
3
I/O
I/O
-
The IO1 and IO2 pins are an ESD protected channel. Connect these pins to the data line as
close to the connector as possible.
IO2
5
NC
1, 2
4
This pin is not connected and is left floating, grounded, or connected to VCC.
The GND (ground) pin is connected to ground.
GND
-
Copyright © 2013, Texas Instruments Incorporated
Submit Documentation Feedback
3
Product Folder Links: TPD2E2U06
TPD2E2U06
SLLSEG9A –JUNE 2013–REVISED JUNE 2013
www.ti.com
TYPICAL CHARACTERISTICS
TLP, DATA TO GND
TLP, GND TO DATA
30
25
20
15
10
5
30
25
20
15
10
5
0
0
0
5
10
15
20
25
30
35
40
45
50
0
5
10
15
20
25
30
35
40
45
50
C002
C003
Voltage (V)
Voltage (V)
Figure 2.
Figure 3.
IEC 61000-4-2 CLAMPING VOLTAGE,
+8 kV CONTACT
IEC 61000-4-2 CLAMPING VOLTAGE,
–8 kV CONTACT
120
105
90
15
0
œ15
œ30
œ45
œ60
œ75
œ90
œ105
œ120
œ135
œ150
75
60
45
30
15
0
œ15
0
25
50
75
100
125
150
175
200
15
40
65
90
115
140
165
190
œ10
C004
C005
Time (ns)
Time (ns)
Figure 4.
Figure 5.
ILEAK
vs
TEMPERATURE,
VIN 2.5 V
IV CURVE,
TA = 25°C
0.001
0.0005
0
500
400
300
200
100
-0.0005
-0.001
0
0
1
2
3
4
5
6
7
8
9
10
œ2
œ1
0
20
40
60
80
100
120
C006
Voltage (V)
C007
Temperature (ƒC)
Figure 7.
Figure 6.
4
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Copyright © 2013, Texas Instruments Incorporated
Product Folder Links: TPD2E2U06
TPD2E2U06
www.ti.com
SLLSEG9A –JUNE 2013–REVISED JUNE 2013
TYPICAL CHARACTERISTICS (continued)
CAPACITANCE ACROSS VBIAS
f = 1 mHZ
SURGE CURVE (tp = 8/20 μs)
IO TO GND
6.5
5.2
3.9
2.6
1.3
0.0
100
90
80
70
60
50
40
30
20
10
0
2.2
2
Current
Power
1.8
1.6
1.4
1.2
0
5
10
15
20
25
30
35
40
45
50
œ5
F = 1 MHz
C009
Time (ꢀS)
1
0
1
2
3
4
5
C008
IO Voltage (V)
Figure 8.
Figure 9.
INSERTION LOSS
1
0
œ1
œ2
œ3
œ4
œ5
œ6
œ7
œ8
œ9
œ10
œ11
œ12
100k
1M
10M
Frequency (Hz)
Figure 10.
100M
1000M
10000M
C010
Copyright © 2013, Texas Instruments Incorporated
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5
Product Folder Links: TPD2E2U06
PACKAGE OPTION ADDENDUM
www.ti.com
28-Jun-2013
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
TPD2E2U06DRLR-P
ACTIVE
SOT
DRL
5
4000
TBD
Call TI
Call TI
DT6
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
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provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
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