TPD3S716-Q1_技术文档

TPD3S716-Q1

ZHCSAL0D –MARCH 2016 –REVISED AUGUST 2020

TPD3S716-Q1 可提供可调电流限制、电池短路保护和其他短路保护的汽车类

USB 2.0 接口保护器件

1 特性

3 说明

• 符合AEC-Q100 标准（1 级）

– 工作温度范围：–40°C 至+125°C

• 提供功能安全

TPD3S716-Q1 是一套具有可调节电流限制功能的单芯

片解决方案，可为汽车应用中 USB 连接器的 V_BUS

和

数据线路提供电池短路保护、短路保护以及 ESD 保

护。集成的数据开关提供了出色的带宽，能够在提供

18V 电池短路保护的同时最大限度地减少信号衰减。

该器件具有 1GHz 的高带宽，适用于一些采用 USB2.0

高速数据速率的应用，如 Car Play。此外，该器件还

具有 720MHz 以上的附加带宽裕量，有助于保持一个

干净的 USB 2.0 眼图，并且支持使用较长的不可分离

电缆（常见于汽车 USB 环境中）。电池短路保护可将

内部系统电路隔离，防止其受到 V_{BUS_CON}、VD+ 和

VD– 引脚上的任何过压情况的影响。在这些引脚上，

TPD3S716-Q1 能够处理高达 18V 的过压情况（热插

拔和直流事件）。过压保护电路可提供业内一流的电池

短路保护，能够极为可靠地关断数据开关以保护上游电

路免遭有害电压和电流尖峰的影响。

– 可帮助进行功能安全系统设计的文档

• V_{BUS_CON}引脚上具有电池短路保护（高达18V）

和接地短路保护

• VD+ 和VD–引脚上具有电池短路保护（高达

18V）和V_BUS短路保护

• 在V_{BUS_CON}

、

VD+、VD–上提供IEC 61000-4-2 ESD 保护

– ±8kV 接触放电

– ±15kV 气隙放电

• V_{BUS_CON}、VD+ 和VD–引脚上具有ISO 10605

330pF、330ΩESD 保护

– ±8kV 接触放电

– ±15kV 气隙放电

• 低R_ONnFET V_BUS开关（典型值为63mΩ）

• 高速数据开关（3dB 带宽为1GHz）

• 可调节断续电流限制高达2.4A

• 短暂过压响应时间

V_{BUS_CON}引脚还提供可调节的电流限制负载开关以及

接地短路保护功能。该器件支持高达 2.4A 的 V_BUS

电

流，支持 USB BC1.2、USB Type-C 5V/1.5A 以及最

高达2.4A 的专用充电方案。独立的数据和 VBUS 使能

引脚可用于配置主机和客户端-OTG 模式。此外，

TPD3S716-Q1 还在 V_{BUS_CON}、VD+ 和 VD– 引脚上

集成了系统级 IEC 61000-4-2 和 ISO 10605 ESD 保

护，无需使用高电压、低容值的外部二极管。

– V_BUS开关的典型值为2µs

– 数据开关的典型值为200ns

• 独立的V_BUS和数据使能引脚（用于配置主机和客

户端/OTG 模式）

• 故障输出信号

• 热关断特性

• 16 引脚SSOP 封装

器件信息⁽¹⁾

封装尺寸（标称值）

器件型号

封装

SSOP (16)

TPD3S716-Q1

4.90mm × 3.90mm

(4.9mm x 3.9mm)，直通布线

(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附

录。

2 应用

• 终端设备

– 音响主机

– 后座娱乐系统

– 远程信息处理

– USB 集线器

– 导航模块

– 媒体接口

• 接口

5

V

TPD3S716-Q1

V_{BUS_SYS}

V_{BUS_CON}

V_BUS

100 µF

V

1

µF

100

X7R

10 kΩ

7

V

FLT

USB

Transceiver

Dœ

VDt

VD+

GND

Dt

10 nH

D+

USB2.0

CMC

VEN

From Processor

GND

DEN

V_IN

I_ADJ

3.3

V

R_ADJ

1

7

µF

V

Copyright

典型应用原理图

– USB 2.0

本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问

www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SLVSDH9

TPD3S716-Q1

ZHCSAL0D –MARCH 2016 –REVISED AUGUST 2020

www.ti.com.cn

Table of Contents

8.3 Feature Description...................................................13

8.4 Device Functional Modes..........................................16

9 Application and Implementation..................................18

9.1 Application Information............................................. 18

9.2 Typical Application.................................................... 18

10 Power Supply Recommendations..............................23

10.1 V_BUSPath................................................................23

10.2 V_INPin.....................................................................23

11 Layout...........................................................................23

11.1 Layout Guidelines................................................... 23

11.2 Layout Example...................................................... 23

11.3 Layout Optimized for Thermal Performance........... 24

12 Device and Documentation Support..........................26

12.1 Documentation Support.......................................... 26

12.2 支持资源..................................................................26

12.3 Trademarks.............................................................26

12.4 静电放电警告.......................................................... 26

12.5 术语表..................................................................... 26

13 Mechanical, Packaging, and Orderable

1 特性................................................................................... 1

2 应用................................................................................... 1

3 说明................................................................................... 1

4 Revision History.............................................................. 2

5 Pin Configuration and Functions...................................3

Pin Functions.................................................................... 3

6 Specifications.................................................................. 4

6.1 Absolute Maximum Ratings........................................ 4

6.2 ESD Ratings—AEC Specification...............................4

6.3 ESD Ratings—IEC Specification................................ 4

6.4 ESD Ratings—ISO Specification................................ 4

6.5 Recommended Operating Conditions.........................4

6.6 Thermal Information....................................................5

6.7 Electrical Characteristics.............................................5

6.8 Timing Characteristics.................................................8

6.9 Typical Characteristics................................................9

7 Parameter Measurement Information..........................12

8 Detailed Description......................................................13

8.1 Overview...................................................................13

8.2 Functional Block Diagram.........................................13

Information.................................................................... 26

4 Revision History

Changes from Revision C (June 2016) to Revision D (August 2020)

Page

• 向特性部分添加了功能安全链接........................................................................................................................ 1

• 更新了整个文档中的表格、图和交叉参考的编号格式.........................................................................................1

Changes from Revision B (April 2016) to Revision C (June 2016)

Page

• 将特性部分中的可调节断续电流限制从1.7A 更改为2.4A................................................................................1

• 更新了说明部分..................................................................................................................................................1

• Changed Current through V_BUSswitch from 1.7 A to 2.4 A................................................................................4

• Updated the R_ADJminimum resistance to 57 kΩin Recommended Operating Conditions table...................... 4

• aDDED new current limit values to Electrical Characteristics table ...................................................................5

• Updated 图8-1 ................................................................................................................................................ 14

• Updated I_VBUSOperating Maximum in 图9-7 to go up to 2.4 A....................................................................... 21

Changes from Revision A (April 2016) to Revision B (April 2016)

Page

• 更改了电气特性表..............................................................................................................................................1

Changes from Revision * (March 2016) to Revision A (April 2016)

Page

• 将器件状态从产品预发布更改为量产数据.........................................................................................................1

2

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5 Pin Configuration and Functions

I_ADJ

NC

V_{BUS_CON}

GND

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

V_{BUS_SYS}

GND

Dœ

VDœ

D+

VD+

VEN

FLT

V_IN

DEN

图5-1. DBQ Package 16-Pin SSOP Top View

Pin Functions

TYPE

DESCRIPTION

NO.

NAME

NC

1

2

3

4

5

6

NC

O

No connect, leave floating or connect to ground. Do not connect to V_{BUS_CON}

Connect to USB connector V_BUS; provides IEC 61000-4-2 ESD protection

V_{BUS_CON}

GND

O

Ground Connect to PCB ground plane

I/O

VD–

Connect to USB connector D–; provides IEC 61000-4-2 ESD protection

VD+

Connect to USB connector D+; provides IEC 61000-4-2 ESD protection

Enable Active-Low Input. Drive VEN low to enable the V_BUSpath of the device. Drive VEN high to

disable the V_BUSpath of the device

7

8

VEN

DEN

I

Enable Active-Low Input. Drive DEN low to enable the data path of the device. Drive DEN high to

disable the data path of the device

9

V_IN

FLT

I

Connect to 3.3-V I/O. Controls the OVP threshold for VD+/VD–

Open-Drain fault pin. See the Detailed Description section for operation

Connect to the internal transceiver D+ pin

10

11

12

13

14

15

16

O

D+

I/O

D–

Connect to the internal transceiver D–pin

GND

Ground Connect to PCB ground plane

V_{BUS_SYS}

I_ADJ

I

Connect to internal V_BUSplane

I

Connect to a resistor to GND to adjust the current limit threshold

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6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted) ^{(1) (2)}

MIN

MAX

18

UNIT

V_{BUS_CON}

V_{BUS_SYS}

Supply voltage from USB connector

V

–0.3

Internal Supply DC voltage Rail on the PCB

Voltage range from connector-side USB data lines

Voltage range for internal USB data lines

Voltage range for V_INsupply input

6

18

VD+, VD–

D+, D–

V_IN

V_IN+ 0.3

V

A

4

7

DEN

Voltage on enable pins

VEN

7

I_BUS

Maximum DC output current on V_{BUS_CON}pin⁽³⁾

Voltage range for I_ADJpin

2.4

V_{VBUS_SYS}

0.3

+

V_IADJ

V

–0.3

V_FLT

T_A

Voltage range for the FLT pin

Operating free air temperature⁽³⁾

Storage temperature

7

V

–0.3

–40

–65

125

150

°C

T_STG

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under

Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device

reliability.

(2) The algebraic convention, whereby the most negative value is a minimum and the most positive value is a maximum.

(3) Thermal limits and power dissipation limits must be observed.

6.2 ESD Ratings—AEC Specification

VALUE

±4000

±1500

UNIT

Human-body model (HBM), per AEC Q100-002⁽¹⁾

Charged-device model (CDM), per AEC Q100-011

V_(ESD)

Electrostatic discharge

V

(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

6.3 ESD Ratings—IEC Specification

VALUE

UNIT

Contact discharge⁽¹⁾

Air-gap discharge⁽¹⁾

±8000

IEC 61000-4-2, V_{BUS_CON}

VD+, VD–pins

,

V_(ESD)

Electrostatic discharge

V

±15000

(1) See 图7-2 for details on system level ESD testing setup.

6.4 ESD Ratings—ISO Specification

VALUE

±8000

UNIT

Contact discharge⁽¹⁾

Air-gap discharge⁽¹⁾

ISO 10605 (330 pF, 330 Ω),

V_{BUS_CON}, VD+, VD–pins

V_(ESD)

Electrostatic discharge

V

±15000

(1) See 图7-2 for details on system level ESD testing setup.

6.5 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

NOM

MAX

UNIT

V

V_{BUS_CON}

V_{BUS_SYS}

Supply voltage from USB connector

5.9

Internal supply DC voltage Rail on the PCB

4.75

V

4

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6.5 Recommended Operating Conditions (continued)

over operating free-air temperature range (unless otherwise noted)

MIN

0

NOM

MAX

V_IN+ 0.3

3.6

UNIT

V

Voltage range from connector-side USB data lines

Voltage range for internal USB data lines

Voltage range for V_INsupply

VD+, VD–

D+, D–

V_IN

0

V

3

V

I_BUS

Current through V_BUSswitch⁽¹⁾

2.4

A

VEN, DEN

C_SYS

Voltage range for enable

0

5.9

V

Input capacitance⁽²⁾

V_{BUS_SYS}pin

100

µF

kΩ

C_LOAD

C_VIN

Output load capacitance⁽²⁾

V_INcapacitance⁽²⁾

V_{BUS_CON}pin

V_INpin

1

R_ADJ

Resistance of R_ADJresistor⁽²⁾

I_ADJpin

57

(1) Depending on your I_BUScurrent level, maximum operating junction temperature derating may be required. For I_BUS> 1.5A, care should

be taken in the PCB design to improve the board's thermal coefficient. Please see both the Power Dissipation and Junction

Temperature and Layout Optimized for Thermal Performance sections for more details.

(2) See the 图9-1 for configuration details.

6.6 Thermal Information

TPD3S716-Q1

THERMAL METRIC⁽¹⁾

DBQ (SSOP)

16 PINS

98.8

UNIT

Junction-to-ambient thermal resistance

°C/W

θ_JA

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

48.0

θ_JCtop

θ_JB

41.6

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

See the Layout Optimized for Thermal Performance section

8.5

ψ_JT

41.2

ψ_JB

N/A

θ_JCbot

θ_JA(Custom)

57.0

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report, SPRA953.

6.7 Electrical Characteristics

over operating free-air temperature range, VEN = 0 V, DEN = 0 V, V_{BUS_SYS}= 5 V, V_IN= 3.3 V, VD+/VD–/D+/D–/V_{BUS_CON}

= float (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

SUPPLY CURRENT CONSUMPTION

I_{VBUS_SLEEP}

I_VBUS

V_BUSSleep current consumption

Measured at V_{BUS_SYS}pin, VEN = 5 V, DEN = 5 V

Measured at V_{BUS_SYS}pin

45

285

12

150

380

20

µA

V_BUSOperating current consumption

Leakage current for V_IN

I_VIN

Measured at V_INpin, V_IN= 3.6 V

Leakage into V_{BUS_SYS}while shorted to Measured flowing into V_{BUS_SYS}pin, V_{BUS_SYS}= 5

I_ON(LEAK)

225

300

50

1

µA

battery and powered on

V, V_{BUS_CON}= 18 V

Leakage through V_BUSpath while

shorted to battery and unpowered

Measured flowing out of V_{BUS_SYS}pin, V_{BUS_SYS}= 0

V, V_{BUS_CON}= 18 V

I_OFF(LEAK)

Leakage out of data path while shorted Measured flowing out of D+ or D–pins, V_{BUS_SYS}

to battery and unpowered

=

I_{D(OFF_LEAK)}

–1

0 V, VD+ or VD–= 18 V, V_IN= 0 V, D+/D–= 0 V

Leakage out of data path while shorted Measured flowing out of D+ or D–pins, V_{BUS_SYS}

to battery and powered on

=

I_{D(ON_LEAK)}

1

µA

5 V, VD+ or VD–= 18 V, V_IN= 3.3 V, D+/D–= 0 V

Leakage into data path while shorted to Measured flowing in to VD+ or VD–pins, V_{BUS_SYS}

battery and unpowered

I_{VD(OFF_LEAK)}

85

= 0 V, VD+ or VD–= 18 V, V_IN= 0 V, D+/D–= 0 V

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6.7 Electrical Characteristics (continued)

over operating free-air temperature range, VEN = 0 V, DEN = 0 V, V_{BUS_SYS}= 5 V, V_IN= 3.3 V, VD+/VD–/D+/D–/V_{BUS_CON}

= float (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

Measured flowing in to VD+ or VD–pins, V_{BUS_SYS}

= 5 V, VD+ or VD–= 18 V, V_IN= 3.3 V D+/D–= 0

V

Leakage into data path while shorted to

battery and powered on

I_{VD(ON_LEAK)}

85

µA

V

V_INPIN

Undervoltage lockout

rising for V_IN

Ramp V_INup until V_BUSand Data FETs turn on,

VEN =0 V, DEN = 0 V

V_UVLO(RISING)

2.6

2.5

2.7

2.6

2.9

2.8

V_IN

Undervoltage lockout

falling for V_IN

Ramp V_INdown until V_BUSand Data FETs turn off,

VEN =0 V, DEN = 0 V

V_{UVLO(FALLING)}

VEN, DEN, FLT PINS

V_IH

Set VEN ( DEN)= 0 V; Sweep VEN ( DEN) to 1.4 V;

Measure when V_BUS(Data) FET turns off

High-level input voltage VEN, DEN

1.2

V

Set VEN ( DEN) = 3.3 V; Sweep VEN ( DEN) from

3.3 V to 0.5 V; Measure when V_BUS(Data) FET

turns on

V_IL

Low-level input voltage

Input Leakage Current

VEN, DEN

0.8

V_{( VEN)}(V_{( DEN)})= 3.3 V ; Measure Current into VEN

( DEN) pin

I_IL

1

µA

V

V_OL

Low-level output voltage FLT

I_OL= 3 mA

0.4

OCP CIRCUIT—V_BUS

Overcurrent limit, R_ADJ

280 kΩ± 1%

=

Progressively load V_{BUS_CON}until device asserts

FLT

I_LIM

V_BUS

505

0.905

1.005

1.505

1.8

620

1.1

mA

A

Overcurrent limit, R_ADJ

158 kΩ± 1%

Progressively load V_{BUS_CON}until device asserts

FLT

Overcurrent limit, R_ADJ

143 kΩ± 1%

Progressively load V_{BUS_CON}until device asserts

FLT

1.2

A

Overcurrent limit, R_ADJ

93.1 kΩ± 1%

Progressively load V_{BUS_CON}until device asserts

FLT

1.8

A

Overcurrent limit, R_ADJ

76.8 kΩ± 1%

Progressively load V_{BUS_CON}until device asserts

FLT

2.16

2.57

2.93

850

1.7

A

Overcurrent limit, R_ADJ

66.5 kΩ± 1%

Progressively load V_{BUS_CON}until device asserts

FLT

2.105

2.405

550

A

Overcurrent limit, R_ADJ

57.6 kΩ± 1%

Progressively load V_{BUS_CON}until device asserts

FLT

A

Overcurrent limit, I_ADJ

GND

=

Progressively load V_{BUS_CON}until device asserts

FLT

700

1.4

mA

A

Overcurrent limit, I_ADJ

V_{BUS_SYS}

=

Progressively load V_{BUS_CON}until device asserts

FLT

1.1

OVER TEMPERATURE PROTECTION

The rising over-temperature protection

shutdown threshold

V_{BUS_SYS}= 5 V, VEN = 0 V, DEN = 0 V, No Load on

V_{BUS_CON}, T_Astepped up until FLT is asserted

T_SD(RISING)

150

125

10

165

130

35

180

142

55

℃

V_{BUS_SYS}= 5 V, VEN = 0 V, DEN = 0 V, No Load on

V_{BUS_CON}, T_Astepped down from T_SD(RISING)until

FLT is deasserted

The falling over-temperature protection

shutdown threshold

T_SD(FALLING)

The over-temperature protection

shutdown threshold hysteresis

T_SD(HYST)

T_SD(RISING)–T_SD(FALLING)

OVP CIRCUIT—V_BUS

V_OVP(RISING)

Input overvoltage

V_{BUS_CON}

Increase V_{BUS_CON}from 5 V to 7 V. Measure when

FLT is asserted

5.6

5.8

50

6

V

mV

V

protection threshold

Difference between rising and falling OVP

thresholds on V_{BUS_CON}

V_HYS(OVP)

Hysteresis on OVP

V_{BUS_CON}

Input overvoltage

protection threshold

Decrease V_{BUS_CON}from 7 V to 5 V. Measure when

FLT is deasserted

V_OVP(FALLING)

5.52

140

5.75

5.98

260

Set V_{BUS_SYS}to 5 V. Increase V_{BUS_CON}from

V_{BUS_SYS}to V_{BUS_SYS}+ 300 mV. Measure the value

of V_{BUS_CON}–V_{BUS_SYS}when FLT asserts.

25°C ≤T_A≤125°C

Reverse supply

detection threshold

V_{BUS_CON}

V_{BUS_SYS}

–

V_{REV_SUPPLY(RISING)}

200

mV

6

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6.7 Electrical Characteristics (continued)

over operating free-air temperature range, VEN = 0 V, DEN = 0 V, V_{BUS_SYS}= 5 V, V_IN= 3.3 V, VD+/VD–/D+/D–/V_{BUS_CON}

= float (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

Set V_{BUS_SYS}to 5 V. Decrease V_{BUS_CON}from

V_{BUS_SYS}+ 300 mV to V_{BUS_SYS}. Measure the value

of V_{BUS_CON}–V_{BUS_SYS}when FLT deasserts.

25°C ≤T_A≤125°C

Reverse supply

detection threshold

V_{BUS_CON}

V_{BUS_SYS}

–

V_{REV_SUPPLY(FALLING)}

70

120

165

mV

Hysteresis on reverse

supply detection

Difference between rising and falling reverse supply

detection thresholds

V_{BUS_CON}

V_{BUS_SYS}

V_{REV_SUPPLY(HYST)}

V_{UVLO(SYS_RISING)}

V_{HYS(UVLO_SYS)}

80

3.3

75

mV

V

Undervoltage lockout

rising for V_{BUS_SYS}

V_{BUS_SYS}

V_{BUS_SYS}voltage rising from 0 V to 5 V

3.1

50

3

3.6

100

3.5

V_{BUS_SYS}UVLO

Hysteresis

Difference between rising and falling UVLO

thresholds on V_{BUS_SYS}

mV

V

Undervoltage lockout

falling for V_{BUS_SYS}

V_{UVLO(SYS_FALLING)}

V_{BUS_SYS}voltage falling from 5 V to 2.9 V

3.2

Short-to-ground

comparator rising

threshold

Increase V_{BUS_CON}voltage from 0 V until the device

transitions from the short-circuit to over-current

mode of operation

V_SHRT(RISING)

V_{BUS_CON}

2.5

2.4

2.6

2.7

2.6

V

Set V_{BUS_SYS}= 5 V; V_IN= 3.3 V; VEN = 0 V, DEN =

0 V; Decrease V_{BUS_CON}voltage from 5 V until the

device transitions from the over-current to short-

circuit mode of operation

Short-to-ground

comparator falling

threshold

V_{SHRT(FALLING)}

V_{BUS_CON}

2.5

Short-to-ground

comparator hysteresis

Difference between V_SHRT(RISING)and

V_{SHRT(FALLING)}

V_SHRT(HYST)

I_SHRT

OVP CIRCUIT—VD+/VD–

Input overvoltage

V_{BUS_CON}

125

mV

mA

Short-to-ground current

source

Current sourced from V_{BUS_SYS}when device is in

short-circuit mode

150

350

Increase VD+ or VD–(with D+ and D–) from 3.3

V to 4.5 V. Measure the value at which FLT is

asserted

V_OVP(RISING)

V_IN+ 0.6 V_IN+ 0.8 V_IN+ 1

V

VD+/VD–

protection threshold

Difference between rising and falling OVP

thresholds on VD+/VD–

V_HYS(OVP)

Hysteresis on OVP

50

V_IN

mV

V

VD+/VD–

Input overvoltage

protection threshold

V_IN

0.525

+

V_IN+

Decrease VD+ or VD–(with D+ or D–) from 4.5 V

to 2 V. Measure the value at FLT is deasserted

V_OVP(FALLING)

0.75 0.975

SHORT TO BATTERY

V_{(VBUS_STB)}

V_BUShotplug short-to-

battery tolerance

V_{BUS_CON}

18

V

Charge battery-equivalent capacitor to test voltage

then discharge to pin under test through a 1 meter,

18 gauge wire. (See 图7-1 for more details)

Data line hotplug short-

to-battery tolerance

V_{(DATA_STB)}

VD+/VD–

DATA LINE SWITCHES—VD+ to D+ or VD–to D–

Capacitance of D+/D–switches when enabled –

measure on connector side at VDx = 0.4 V

C_ON

Equivalent On Capacitance

On Resistance

6.9

pF

Measure resistance between D+ and VD+ or D–

and VD–, voltage between 0 V and 0.4 V

R_ON

4

0.2

6.5

1

Ω

Measure resistance between D+ and VD+ or D–

and VD–, sweep voltage between 0 V and 0.4 V

R_ON(Flat)

On Resistance flatness

On Bandwidth (–3dB)

Measure S₂₁bandwidth from D+ to VD+ or D–to

VD–with voltage swing = 400 mVpp, V_CM= 0.2 V

BW_ON

910

MHz

Measure S_DD21bandwidth from D+ to VD+ and D–

to VD–with voltage swing = 800 mVpp differential,

V_CM= 0.2 V

BW_{ON_DIFF}

1050

MHz

dB

On Bandwidth (–3dB)

Measure S₂₁bandwidth from D+ to VD–or D–to

VD+ with voltage swing = 400 mVpp. Make sure to

terminate open sides to 50 ohms. f = 480 MHz

X_talk

Crosstalk

–28

nFET SWITCH—V_BUS

VEN = 5 V, DEN = 5 V, Set V_{BUS_CON}= 5 V and

measure current flow to ground

R_(DISCHARGE)

Output discharge resistance

18

30

kΩ

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6.7 Electrical Characteristics (continued)

over operating free-air temperature range, VEN = 0 V, DEN = 0 V, V_{BUS_SYS}= 5 V, V_IN= 3.3 V, VD+/VD–/D+/D–/V_{BUS_CON}

= float (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

135

V_{BUS_CON}= 5 V, I_OUT= 1.5 A. See 图9-8 for a plot

of the maximum V_BUSR_ONpossible at a given

junction temperature

R_ON

V_BUSpath ON resistance

63

mΩ

6.8 Timing Characteristics

over operating free-air temperature range, VEN = 0 V, DEN = 0 V, V_{BUS_SYS}= 5 V, V_IN= 3.3 V, D+/D–= 45 Ωto GND,

VD+/VD–/V_{BUS_CON}= float (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN TYP MAX

UNIT

ENABLE PIN

Time between VEN and DEN asserted low and V_BUSand

Data FETs turn on, C_{VBUS_CON}= 0 µF

t_{ON_HOST}

Host mode enable on time

Client mode enable on time

Host mode disable time

Client mode disable time

5.7

2.4

30

5

ms

µs

Time between DEN asserted low and Data FETs turn on.

VEN remains high

t_{ON_CLIENT}

t_{OFF_HOST}

t_{OFF_CLIENT}

Time between VEN and DEN deasserted high and V_BUS

and Data FETs turn off, C_{VBUS_CON}= 0 µF

Time between DEN deasserted high and Data FETs turn

off. VEN remains high

µs

t_{HOST_TO_CLIE}Host to Client mode transition Time between VEN deasserted high and V_BUSFET turns

time off. DEN remains low, C_{VBUS_CON}= 0 µF

70

3.4

µs

NT

t_{CLIENT_TO_HO}Client to Host mode transition Time between VEN asserted low and V_BUSFET turns on.

ms

time

DEN remains low, C_{VBUS_CON}= 0 µF

ST

OVER CURRENT PROTECTION

Time from overcurrent condition until FLT assertion and

V_BUSFET turn off

t_BLANK

t_RETRY

t_RECV

Overcurrent blanking time

2

ms

Time from overcurrent FET shut off until FET turns back

on

Overcurrent retry time

100

8

Time from end of t_RETRYuntil FLT deassertion if

overcurrent condition is removed

Overcurrent recovery time

OVER VOLTAGE PROTECTION

t_{OVP_response}

Measured from OVP Condition to FET turnoff

2

4

µs

ns

OVP Response time –V_BUS

OVP Response time –data

switches

200

t_{OVP_}

OVP FLT assertion time

Measured from an OVP Condition to FLT assertion

14

µs

FLT_ASSERT

SHORT TO GROUND PROTECTION

Time from short condition until current falls below 120%

of I_SHRT, C_{VBUS_CON}= 0 µF

t_SHRT

Short to ground response time

2

4

2

µs

Short to ground FLT assertion Time from short condition until FLT is asserted,

time C_{VBUS_CON}= 0 µF

t_{SHRT_FLTZ}

20

REVERSE SUPPLY DETECTION

t_{REV_SUPPLY_}

Reverse supply blanking time Time from reverse current condition until FLT assertion

ms

BLANK

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6.9 Typical Characteristics

140

120

100

80

60

40

20

60

0

40

20

-20

-40

-60

-80

-100

0

-20

-40

-60

-80

VD-

D-

VD-

D-

-10

0

10 20 30 40 50 60 70 80 90 100 110

Time (ns)

-10

0

10 20 30 40 50 60 70 80 90 100 110

Time (ns)

D002

D001

图6-2. –8-kV IEC Contact Waveform

图6-1. 8-kV IEC Contact Waveform

1

0.75

0.5

8

7

6

5

4

3

2

1

V_{BUS_CON}

/VEN

/FLT

0.25

0

-0.25

-0.5

-0.75

-1

VD+

VD-

0

-15

-5

0

5

10

Voltage (V)

15

20

25

-10

-5

Time (ms)

0

5

D003

D0034

图6-3. Data Line I-V Curve

图6-4. V_BUSt_ONTime

100

80

60

40

20

0

6

5

4

3

2

1

-40 C

25 C

85 C

130 C

Unpowered

Powered, Enabled

0

-40

-20

0

20

40

60

80

100 120 140

0.1

0.2

Bias Voltage (V)

0.3

0.4

Temperature (èC)

D007

D008

图6-5. VD± Leakage Current at 18-V across

图6-6. Data Switch R_ONvs Bias Voltage

Temperature

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8

7

6

5

4

3

2

1

0

1600

1400

1200

1000

800

600

400

200

0

6

5

4

3

2

1

0

1500

V_{BUS_CON}

I_{VBUS_CON}

/FLT

V_{BUS_CON}

I_{VBUS_CON}

/FLT

1250

1000

750

500

250

0

-4.8 -4.4 -4 -3.6 -3.2 -2.8 -2.4 -2 -1.6 -1.2 -0.8

Time (ms)

-40 -20

0

20

40

60

Time (ms)

80 100 120 140 160

D009

D010

图6-7. Overcurrent t_BLANKResponse Waveform

图6-8. Overcurrent t_{BLANK_RETRY}Response

Waveform

50

40

30

20

10

0

12.5

10

7.5

5

9.5

V_{BUS_CON}

I_{VBUS_CON}

V_{BUS_SYS}

/FLT

V_{BUS_CON}

I_{VBUS_CON}

V_{BUS_SYS}

/FLT

8.5

7.5

6.5

5.5

4.5

3.5

2.5

1.5

0.5

-0.5

-1.5

-2.5

2.5

0

-10

-20

-2.5

-5

-10

0

10

20

30

40

Time (ms)

D012

-8

-3

2

7

12

Time (ms)

17

22

27 30

D011

图6-10. V_BUSShort-to-18 V Response Waveform

图6-9. V_BUSShort-to-Ground Response Waveform

12.5

25

VD-

I_VD-

D-

/FLT

VD-

I_VD-

D-

/FLT

10.5

20

8.5

15

6.5

4.5

2.5

0.5

-1.5

10

5

0

-5

-0.5

-0.75

-0.25

0.25

0.75

0

0.5

1

Time (ms)

D014

Time (ms)

D005

图6-11. Data Switch Short-to-5 V Response

图6-12. Data Switch Short-to-18 V Response

Waveform

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29

12.5

10

0

-10

-20

-30

-40

-50

-60

-70

-80

VD-

I_VD-

D-

24

19

14

9

/FLT

7.5

5

2.5

0

4

D- to VD+

D+ to VD-

-1

-2.5

4

9

14

19

Time (ms)

D013

0

1E+9

2E+9

3E+9

Frequency (Hz)

D017

图6-13. Data Switch Short-to-18 V Response

图6-14. Data Switch Crosstalk

Waveform (Long)

图6-15. USB2.0 Eye Diagram (no TPD3S716-Q1)

图6-16. USB2.0 Eye Diagram (with TPD3S716-Q1)

0

-1

-2

-3

-4

-5

-6

-3

-6

-9

-12

1E+7

1E+8

Frequency (Hz)

1E+9

3E+9

1E+7

1E+8

Frequency (Hz)

1E+9

3E+9

D016

D015

图6-18. Data Switch Single-Ended Bandwidth

图6-17. Data Switch Differential Bandwidth

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7 Parameter Measurement Information

5 V

V_{BUS_SYS}

V_{BUS_CON}

100 µF

7 V

1 µF

100 V

X7R

10 kΩ

FLT

VDœ

VD+

GND

Dœ

10 nH

45 Ω

D+

USB2.0

CMC

45 Ω

VEN

1-m Cable

STB

Strike

From GPIO

DEN

V_IN

From GPIO

I_ADJ

DC Power

Output

3.3 V

Supply

22 mF

35 V

R_ADJ

TPD3S716-Q1

1 µF

7 V

STB Test Aparatus

图7-1. Short-to-Battery System Test Setup

5 V

V_{BUS_SYS}

V_{BUS_CON}

100 µF

7 V

1 µF

100 V

X7R

10 kΩ

FLT

VDœ

VD+

GND

Dœ

10 nH

45 Ω

D+

USB2.0

CMC

45 Ω

VEN

From GPIO

DEN

V_IN

From GPIO

I_ADJ

3.3 V

R_ADJ

TPD3S716-Q1

1 µF

7 V

图7-2. ESD System Test Setup

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8 Detailed Description

8.1 Overview

The TPD3S716-Q1 provides a single-chip ESD protection and over voltage protection solution for automotive

USB interfaces. It offers short to battery protection up to 18 V and short to ground protection on V_{BUS_CON}. The

TPD3S716-Q1 also provides a FLT pin that indicates to the system if a fault condition has occurred. The

TPD3S716-Q1 offers ESD clamps on the V_{BUS_CON}, VD+, and VD– pins, therefore eliminating the need for

external TVS clamp circuits in the application.

The TPD3S716-Q1 has internal circuitry that controls the turnon of the internal nFET switches. An internal

oscillator controls the timers that enable the switches and resets the open-drain FLT output. If V_{BUS_CON}and

VD+/VD– are less than V_OVP, the switches are enabled. After an internal delay the charge-pump starts-up and

turns on the internal nFET switches through a soft start. At any time, if any of the external USB pins rise above

their respective V_OVPthresholds, the nFET switches are turned OFF and the FLT pin is pulled LOW.

8.2 Functional Block Diagram

V_{BUS_CON}

V_{BUS_SYS}

Short to

Ground

Detection

Undervoltage

Lockout

-

ESD

Clamp

+

R_ADJ

I_ADJ

Overcurrent

Detection

Over-

voltage

Protection

Control Logic

VEN

FLT

DEN

V_IN

VD+

D+

ESD

Clamps

VDœ

Dœ

8.3 Feature Description

8.3.1 AEC-Q100 Qualified

The TPD3S716-Q1 is an automotive qualified device according to the AEC-Q100 standards. The TPD3S716-Q1

is qualified to operate from –40 to +125°C ambient temperature.

8.3.2 Short-to-Battery and Short-to-Ground Protection on V_{BUS_CON}

The V_{BUS_CON}pin is protected against shorts to battery and shorts to ground.

If a voltage on V_{BUS_CON}is detected as too low (below the V_SHRTthreshold) after the device is enabled, the

device enters short-circuit protection mode and asserts FLT. It sources the I_SHRTcurrent until it detects the

voltage rising above the V_SHRTthreshold, where it resumes standard operating mode and deasserts FLT.

If a voltage above the V_OVPthreshold is detected by the device, it shuts off all FETs and assert a fault on the FLT

pin. When the excessive voltage is removed, the device automatically re-enables and FLT deasserts.

8.3.3 Short-to-Battery and Short-to-V_BUSProtection on VD+, VD–

The VD+ and VD– pins are protected against shorts to battery and shorts to bus. The OVP threshold on the

VD+ and VD–pins is low enough that it protects against shorts to V_BUS

.

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When a voltage above the V_OVPthreshold is detected by the device, it shuts off all FETs and asserts a fault on

the FLT pin. When the excessive voltage is removed, the device automatically re-enables and FLT deasserts.

8.3.4 ESD Protection on V_{BUS_CON}, VD+, VD–

The protected pins (V_{BUS_CON}, VD+, VD–) are tested to pass the IEC 61000-4-2 ESD standard up to Level 4

ESD protection. Additionally, these pins are tested against ISO 10605 with the 330-pF, 330- Ω equivalent

network. This guarantees passing of at least ±8-kV contact discharge and ±15-kV air gap discharge according to

both standards. See 图7-2 for the test set-up used for testing IEC 61000-4-2 and ISO 10605.

8.3.5 Low R_ONnFET V_BUSSwitch

The V_BUSswitch has a low R_ONthat provides minimal voltage droop from system to connector. Typical

resistance is 63 mΩand is specified for 135 mΩat 150°C junction temperature.

8.3.6 High Speed Data Switches

The D+ and D– switches have a very low capacitance and a high bandwidth (1-GHz typical), allowing for a

clean USB 2.0 eye diagram.

8.3.7 Adjustable Hiccup Current Limit up to 2.4-A

The V_BUSpath of this device has an integrated overcurrent protection circuit. The current limit threshold for the

overcurrent protection is adjustable via an external resistor R_ADJto GND on the I_ADJpin. 方程式 1 to 方程式 3

approximate the minimum, nominal, and maximum current limit values for TPD3S716-Q1 assuming a 1%

tolerant resistor:

(–0.983)

I_LIM(TYP)= 143 × R_ADJ

(1)

(2)

(3)

I_LIM(MIN)= 129 × R_ADJ^(–0.981)–0.02

I_LIM(MAX)= 141.5 × R_ADJ^(–0.962)+ 0.015

where

• I_LIM(TYP)is the nominal current limit value in (A)

• I_LIM(MIN)is the minimum current limit value in (A)

• I_LIM(MAX)is the maximum current limit value in (A)

• R_ADJis the nominal resistor to GND on the I_ADJpin in (Ω)

3

2.8

2.6

2.4

2.2

2

I_LIM(MIN)

I_LIM(TYP)

I_LIM(MAX)

1.8

1.6

1.4

1.2

1

0.8

0.6

0.4

50 70 90 110 130 150 170 190 210 230 250 270

R_ADJ(kW)

D009

图8-1. TPD3S716-Q1 Current Limit Thresholds vs. R_ADJ

方程式 1, 方程式 2 and 方程式 3 are useful for approximating the current limit threshold of TPD3S716-Q1;

however, they do not constitute as part of TI's published device specifications for purposes of TI's product

warranty. For the officially tested current limit threshold values, see the Electrical Characteristics table.

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When the V_BUScurrent exceeds the overcurrent threshold, the device goes into a fault state where it limits the

current to the overcurrent threshold value and asserts the FLT pin. After a short blanking time, the device cycles

on and off to try to check if the connected device is still in overcurrent.

8.3.8 Fast Over-Voltage Response Time

The over-voltage FETs are designed to have a fast turnoff time to protect the upstream SoC as quickly as

possible. Typical response time for complete turnoff is 2 µs for the V_BUSpath and 200 ns for the data path.

8.3.9 Independent V_BUSand Data Enable Pins for Configuring both Host and Client/OTG Mode

The TPD3S716-Q1 has two enable inputs to turn on and off the device's internal FETs. The VEN pin disables

and enables the V_BUSpath. The DEN pin disables and enables the data path. Independent control of the V_BUS

and data paths enables the TPD3S716-Q1 to be configured for both USB Host and Client/OTG mode. See 表

8-1.

8.3.10 Fault Output Signal

The TPD3S716-Q1 has a fault pin , FLT that indicates when there is any sort of fault condition because of an

OVP, OCP, short-circuit, reverse-current, or thermal shutdown event occurring.

8.3.11 Thermal Shutdown Feature

In the event that the device exceeds the maximum allowable junction temperature, the thermal shutdown circuit

disables the V_BUSand data switches and assert the fault pin low.

8.3.12 16-Pin SSOP Package

The TPD3S716-Q1 is packaged in a standard 16-pin SSOP leaded package.

8.3.13 Reverse Current Detection

If V_{BUS_CON}exceeds V_{BUS_SYS}by a voltage greater than V_{REV_SUPPLY(RISING)}for t_{REV_SUPPLY_BLANK}, then

TPD3S716-Q1 detects this reverse current condition and asserts the fault pin. When V_{BUS_CON}– V_{BUS_SYS}falls

below V_{REV_SUPPLY(FALLING)}, the fault pin is be deasserted and TPD3S716-Q1 enters back into its normal

operating mode.

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8.4 Device Functional Modes

8.4.1 Normal Operation

The TPD3S716-Q1 operates in normal operation modes when enabled, both V_{BUS_SYS}and V_INare above their

UVLO thresholds, and the device is not in any fault conditions. 表 8-1 shows the normal operating modes of the

TPD3S716-Q1.

表8-1. Device Normal Operating Mode Table

MODE

USB Host

VEN

DEN

V_BUSPATH

DATA PATH

ON

0

1

0

1

0

1

ON

Power Only

USB Client/OTG

Disabled

ON

OFF

ON

OFF

8.4.2 Overvoltage Condition

When the VD+, VD–, or V_{BUS_CON}pins exceed their OVP threshold, the device enters the overvoltage state. All

FETs are disabled and the FLT pin is asserted. When the protected pins drop below their OVP threshold, the

device automatically turns back on and deasserts the FLT pin. An overvoltage condition is only detected on an

enabled path. For example, if the data path is enabled and the V_BUSpath is disabled (USB Client/OTG mode), if

an overvoltage condition occurs on V_{BUS_CON}, the fault pin is not be asserted. However, because the FETs of

disabled paths are already turned off, proper protection from overvoltage conditions are still guaranteed by the

device on disabled paths.

8.4.3 Overcurrent Condition

When the current through the V_BUSpath exceeds the I_LIMcurrent threshold, the device enters into the

overcurrent state. The TPD3S716-Q1 limits current to the I_LIMthreshold by dropping voltage across the V_BUS

FET to maintain constant current. When it continues to sense an overcurrent condition for the blanking time

(t_BLANK), the device disables itself for the retry time (t_RETRY) and then retry automatically for the retry time

(t_{BLANK_RETRY}). In the event that the current is below the overcurrent threshold, the device deasserts fault and

resumes normal operation.

8.4.4 Short-Circuit Condition

If the voltage on the V_{BUS_CON}side is pulled below the V_SHRTthreshold while the device is enabled, the

TPD3S716-Q1 enters the short-circuit mode. It sources a constant current of I_SHRTuntil it rises above the V_SHRT

threshold. When that occurs, the device automatically re-enters normal operation and deasserts the fault pin.

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8.4.5 Device Logic Table

表8-2 shows the TPD3S716-Q1 logic table.

表8-2. TPD3S716-Q1 Logic Table

V_{BUS_SYS}

V_IN

,

Mode

VEN DEN

V_{BUS_CON}

VDx

I_VBUS

T_J

FLT

V_BUSPATH

DATA PATH

Unpowered

Disabled

X

H

X

H

X

None

< UVLO

> UVLO

X

H

OFF

< TSD

< OVP & <

V_{BUS_SYS}

200 mV(typical) & >

V_SHRT

+

Host

L

H

L

< OVP < OCP > UVLO

< TSD

H

ON

OFF

ON

Client/OTG

Power Only

X

< OVP None

> UVLO

< OVP & <

V_{BUS_SYS}

200 mV(typical) & >

V_SHRT

+

H

X

< OCP > UVLO

OFF

Thermal

Shutdown

X

L

X

L

X

None

> UVLO

> TSD

< TSD

L

OFF

Host: V_BUS

OVP Fault

> OVP

Host: Data

OVP Fault

X

> OVP None

< OVP & <

Host: OCP

Fault

V_{BUS_SYS}

200 mV(typical) & >

V_SHRT

+

CURRENT LIMITED,

AUTO-RETRY

L

X

> OCP > UVLO

< TSD

L

AUTO-RETRY

Host: Short-

Circuit Fault

CURRENT LIMITED

250 mA (typical)

L

H

L

< V_SHRT

X

> UVLO

< TSD

L

OFF

ON

< OVP & >

V_{BUS_SYS}

200 mV (typical)

Host: RCP

Fault

+

ON

OFF

OTG: Data

OVP Fault

L

X

> OVP None

OFF

Power Only:

V_BUSOVP

Fault

H

> OVP

X

None

Power Only:

OCP Fault

CURRENT LIMITED,

AUTO-RETRY

> OCP > UVLO

Power Only:

Short-Circuit

Fault

CURRENT LIMITED

250 mA (typical)

< V_SHRT

X

> UVLO

< OVP & >

V_{BUS_SYS}

200 mV (typical)

Power Only:

RCP Fault

L

H

+

X

< TSD

L

ON

OFF

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9 Application and Implementation

Note

以下应用部分的信息不属于TI 组件规范，TI 不担保其准确性和完整性。客户应负责确定 TI 组件是否适

用于其应用。客户应验证并测试其设计，以确保系统功能。

9.1 Application Information

The TPD3S716-Q1 offers fully featured automotive USB2.0 protection including short-to-battery, overcurrent,

and ESD protection. Care must be taken during the implementation to make sure the device provides adequate

protection to the system.

9.2 Typical Application

图 9-1 shows a fully featured USB2.0 high speed port, with an 18-V short-to-battery requirement on the

connector side.

5 V

TPD3S716-Q1

V_{BUS_SYS}

V_{BUS_CON}

V_BUS

100 µF

7 V

1 µF

100 V

X7R

10 kΩ

FLT

USB

Transceiver

Dœ

VDt

VD+

GND

Dt

10 nH

D+

USB2.0

CMC

VEN

From Processor

GND

DEN

V_IN

From Processor

3.3 V

I_ADJ

R_ADJ

1 µF

7 V

图9-1. Typical Application Configuration for TPD3S716-Q1

9.2.1 Design Requirements

表9-1 shows the TPD3S716-Q1 input parameters for this application example.

表9-1. Design Parameters

DESIGN PARAMETER

Short-to-battery tolerance on VD+, VD–, V_{BUS_CON}

Max current in normal operation on V_BUS

Current Limit Setting on V_BUS

EXAMPLE VALUE

18 V

1.5 A

1.505 A (minimum)

105°C

Maximum Ambient Temperature Requirement

USB Data Rate

480 Mbps

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9.2.2 Detailed Design Procedure

The following parameters must be known to the designer to begin the design process:

• Short-to-battery tolerance on connector pins

• Maximum current in normal operation on V_BUS

• Maximum operating ambient temperature

• USB Data Rate

9.2.2.1 Short-to-Battery Tolerance

The TPD3S716-Q1 is capable of handling up to 18 V DC on the VD+, VD–, and V_{BUS_CON}pins. In the event of

a short-to-battery on V_{BUS_CON}, significant ringing would be expected because of the hot plug-like nature of the

short-to-battery event. In typical ceramic capacitor configurations, a standard RLC response is expected which

results in a ringing of nearly two times the applied DC voltage. The TPD3S716-Q1 is capable of withstanding the

transient ringing from hot plug-like events, assuming some precautions are taken.

Careful capacitor selection on the V_{BUS_CON}pin must be observed. A capacitor with a low derating percentage

under the applied voltages must be used to prevent excess ringing. In the example, a 1-µF, 100-V tolerant

ceramic X7R capacitor is used. It is best practice to carefully select the capacitors used in this circuit to prevent

derating-based voltage spikes under hot plug events. See 图 9-4 and 图 9-5 to compare ringing of a 50-V

capacitor to a 100-V capacitor. 图9-6 shows the 100-V capacitor with the TPD3S716-Q1 installed.

Another alternative to a high rated ceramic capacitor is to implement either a standard R-C snubber circuit, or a

small external TVS diode. Depending on the short-to-battery tolerance needed, no special precautions may be

needed.

9.2.2.2 Maximum Current on V_BUS

The TPD3S716-Q1 is capable of operating up to 2.4 A maximum DC current. In this example, the maximum

current for USB2.0 BC1.2 of 1.5 A has been chosen.

9.2.2.3 Power Dissipation and Junction Temperature

This section demonstrates how to analyze the power dissipation and junction temperature of the TPD3S716-Q1

to validate that the application requirements of an I_VBUSoperating current level of 1.5 A and a maximum

operating ambient temperature of 105 °C can be met.

It is good design practice to estimate power dissipation and maximum expected junction temperature of

TPD3S716-Q1. This is important to insure the device does not go into thermal shutdown in normal operation and

that the long term reliability of the device is maintained. Using 方程式 4 to 方程式 6, the system designer can

control choices of the device's proximity to other power dissipating devices and the design of the printed circuit

board (PCB). These have a direct influence on maximum junction temperature. Other factors, such as airflow

and maximum ambient temperature, are often determined by system considerations. It is important to remember

that these calculations do not include the effects of adjacent heat sources, and enhanced or restricted air flow.

Addition of extra PCB copper area around these devices is recommended to reduce the thermal impedance and

maintain the junction temperature as low as practical.

For TPD3S716-Q1, the operating junction temperature must be kept below 150°C in order to prevent the device

from going into thermal shutdown. 方程式4 is used to calculate the junction temperature of the device:

T_J= T_A+ [(I_OUT²× R_ON) × R_θJA

]

(4)

where

• I_OUT= Rated OUT pin current (A)

• R_ON= Power path on-resistance at an assumed T_J(Ω)

• T_A= Maximum ambient temperature (°C)

• T_J= Maximum junction temperature (°C)

• R_θJA= Thermal resistance (°C/W)

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This application example requires an I_VBUSoperating current level of 1.5 A. TPD3S716-Q1 has maximum

junction temperature derating requirements depending on the maximum operating current of the device

according to 方程式5:

T_J(MAX)= –15.6 × (I_{VBUS(MAX OPERATING)}) + 161.5 (°C)

(5)

where

• T_J(MAX)= Maximum allowed junction temperature (°C)

• I_{VBUS(MAX OPERATING)}= Maximum I_VBUSoperating current (A)

See 图 9-7 for a plot of the reliability curve equation. Using this equation, 138.1°C is the maximum allowed

junction temperature in this application.

This example requires a maximum operating ambient temperature of 105°C. To determine if this can be

supported using 方程式 4, the maximum V_BUSpath R_ONmust be determined. 方程式 6 calculates the maximum

V_BUSpath R_ONpossible for TPD3S716-Q1 for a given junction temperature:

R_ON(MAX)= (T_J+ 183.15) / 2726.7 (Ω)

(6)

where

• R_ON(MAX)= Maximum V_BUSR_ONat a given junction temperature (Ω)

• T_J= Device junction temperature (°C)

See 图 9-8 for a plot of the maximum V_BUSpath R_ONvs. Junction Temperature curve. Using the above equation,

the maximum V_BUSR_ONpossible for TPD3S716-Q1 at 138.1°C is R_ON(MAX)= 0.118 Ω.

Using the calculated parameters for this example and the standard datasheet R_θJAfor TPD3S716-Q1, the

maximum operating ambient temperature possible in this example is T_A= 111°C. Because this is greater than

the application requirement of 105°C, TPD3S716-Q1 can safely be operated at 1.5 A with R_θJA= 98.8 (°C/W). If

the resulting ambient temperature in the above calculations resulted in a T_A< 105 °C, methods for improving

R_θJAwould need to be taken. See the Layout Optimized for Thermal Performance section for guidelines on

improving R_θJAfor TPD3S716-Q1. The example given in the Layout Optimized for Thermal Performance yields

an R_θJA= 57 (°C/W). Excellent thermal performance of TPD3S716-Q1 can be achieved with the proper PCB

layout.

9.2.2.4 USB Data Rate

The TPD3S716-Q1 is capable of operating at the maximum USB2.0 High Speed data rate of 480-Mbps because

of the high data switch bandwidth of 1-GHz (typical). In this design example the maximum data rate of 480-Mbps

has been chosen.

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9.2.3 Application Curves

图9-3. USB2.0 Eye Diagram (System from Typical

图9-2. USB2.0 Eye Diagram (Board only, Through

Application Schematic)

Path)

60

40

Voltage

Current

Voltage

Current

50

40

30

20

10

0

30

20

10

0

-10

-20

-10

0

10

20

30

Time (ms)

40

50

60

70

-10

0

10

20

30

Time (ms)

40

50

60

70

D018

图9-4. 50-V, 1-µF X7R Ceramic Shorted to 18-V

图9-5. 100-V, 1-µF X7R Ceramic Shorted to 18 V

(Not Recommended)

35

165

160

155

150

145

140

135

130

125

120

Voltage

Current

30

25

20

15

10

5

0

-5

-10

-15

0

0.4

0.8

1.2

1.6

I_VBUSOperating Maximum (A)

2

2.4

-20 -10

0

10

20

30

Time (ms)

40

50

60

70

80

D006

D018

图9-7. TPD3S716-Q1 I_VBUSTemperature Derating

图9-6. TPD3S716-Q1 and 100-V, 1-µF X7R Shorted

Curve

to 18 V (Powered Off)

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130

120

110

100

90

80

70

60

50

40

-40 -20

0

20

40

60

80 100 120 140

Temperature (èC)

D006

图9-8. TPD3S716-Q1 Maximum V_BUSR_ONvs. Junction Temperature

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10 Power Supply Recommendations

10.1 V_BUSPath

The V_{BUS_SYS}pins provide power to the chip and supply current through the load switch to V_{BUS_CON}. A 100-µF

bulk capacitor is recommended on V_{BUS_SYS}to supply the USB port and maintain compliance. A 1-µF capacitor

is recommended on the V_{BUS_CON}pin with adequate voltage rating to tolerate short-to-battery conditions. A

supply voltage above the UVLO threshold for V_{BUS_SYS}must be supplied for the device to power on.

10.2 V_INPin

The V_INpin provides a voltage reference for the data switch OVP level as well as a bypass for ESD clamping. A

1-µF capacitor must be placed as close to the pin as possible and the supply must be set to be above the UVLO

threshold for V_IN.

11 Layout

11.1 Layout Guidelines

Proper routing and placement maintains signal integrity for high-speed signals. The following guidelines apply to

the TPD3S716-Q1:

• Place the bypass capacitors as close as possible to the V_IN, V_{BUS_SYS}, and V_{BUS_CON}pins. Capacitors must

be attached to a solid ground. This minimizes voltage disturbances during transient events such as short-to-

battery, ESD, or overcurrent conditions.

• High speed traces (data switch path) must be routed as straight as possible and any sharp bends must be

minimized.

Standard ESD recommendations apply to the VD+, VD–, and V_{BUS_CON}pins as well:

• The optimum placement is as close to the connector as possible.

– EMI during an ESD event can couple from the trace being struck to other nearby unprotected traces,

resulting in early system failures.

– The PCB designer must minimize the possibility of EMI coupling by keeping any unprotected traces away

from the protected traces which are between the TVS and the connector.

• Route the protected traces as straight as possible.

• Eliminate any sharp corners on the protected traces between the TVS and the connector by using rounded

corners with the largest radii possible.

– Electric fields tend to build up on corners, increasing EMI coupling.

11.2 Layout Example

图 11-1 shows a full layout for a standard USB2.0 port. A common mode choke and inductors are used on the

high speed data lines, and the requisite bypassing caps are placed on V_{BUS_CON}, V_{BUS_SYS}, and V_IN.

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V_BUS

I_ADJ

V_{BUS_SYS}

N.C.

V_{BUS_CON}

GND

D-

GND

D-

TPD3S716-Q1

VD-

VD+

VEN

DEN

To Transceiver

D+

FLT

V_IN

To Processor

D+

Legend

Pin to GND

GND

VIA to 3.3V Plane

VIA to 5V Plane

VIA to GND Plane

USB2.0 Connector

图11-1. Typical Layout Example for TPD3S716-Q1

11.3 Layout Optimized for Thermal Performance

图 11-2 and 图 11-3 show images from a real PCB design optimized for the best thermal performance for

TPD3S716-Q1. This PCB layout has 6 layers (2 signal and 4 plane layers). The 2 signal layers are the outer

layers of the PCB and constructed with 2-oz copper, and the 4 internal plane layers are constructed with 1-oz

copper. Using this PCB layout yielded an R_θJA(CUSTOM)= 57 (°C/W). The images contain rough dimensions of

the copper traces and pours used around the device. One key strategy to optimize thermal performance of the

device is to maximize the area of the copper pours and traces used to route the device power, GND, and signal

pins when possible. Another key strategy is to maximize the copper weight of the PCB metal layers. This

example demonstrates that excellent thermal performance can be achieved with TPD3S716-Q1 with the proper

PCB layout.

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图11-2. Thermally Optimized PCB Layout Top Layer

图11-3. Thermally Optimized PCB Layout Bottom Layer

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12 Device and Documentation Support

12.1 Documentation Support

12.1.1 Related Documentation

For related documentation see the following:

TPD3S716-Q1 Evaluation Module, SLVUAL9

12.2 支持资源

TI E2E^™中文支持论坛是工程师的重要参考资料，可直接从专家处获得快速、经过验证的解答和设计帮助。搜索

现有解答或提出自己的问题，获得所需的快速设计帮助。

链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅

TI 的使用条款。

12.3 Trademarks

TI E2E^™is a trademark of Texas Instruments.

所有商标均为其各自所有者的财产。

12.4 静电放电警告

静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理

和安装程序，可能会损坏集成电路。

ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参

数更改都可能会导致器件与其发布的规格不相符。

12.5 术语表

TI 术语表

本术语表列出并解释了术语、首字母缩略词和定义。

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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PACKAGE MATERIALS INFORMATION

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TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

A0

B0

K0

P1

W

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

TPD3S716QDBQRQ1

SSOP

DBQ

16

2500

330.0

12.4

6.4

5.2

2.1

8.0

12.0

Q1

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

31-Jul-2020

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SSOP DBQ 16

SPQ

Length (mm) Width (mm) Height (mm)

367.0 367.0 35.0

TPD3S716QDBQRQ1

2500

Pack Materials-Page 2

PACKAGE OUTLINE

DBQ0016A

SSOP - 1.75 mm max height

SCALE 2.800

SHRINK SMALL-OUTLINE PACKAGE

C

SEATING PLANE

.228-.244 TYP

[5.80-6.19]

.004 [0.1] C

A

PIN 1 ID AREA

14X .0250

[0.635]

16

1

2X

.189-.197

[4.81-5.00]

NOTE 3

.175

[4.45]

8

9

16X .008-.012

[0.21-0.30]

B

.150-.157

[3.81-3.98]

NOTE 4

.069 MAX

[1.75]

.007 [0.17]

C A

B

.005-.010 TYP

[0.13-0.25]

SEE DETAIL A

.010

[0.25]

GAGE PLANE

.004-.010

[0.11-0.25]

0 - 8

.016-.035

[0.41-0.88]

DETAIL A

TYPICAL

(.041 )

[1.04]

4214846/A 03/2014

NOTES:

1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.

Dimensioning and tolerancing per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed .006 inch, per side.

4. This dimension does not include interlead flash.

5. Reference JEDEC registration MO-137, variation AB.

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EXAMPLE BOARD LAYOUT

DBQ0016A

SSOP - 1.75 mm max height

SHRINK SMALL-OUTLINE PACKAGE

16X (.063)

[1.6]

SEE

DETAILS

SYMM

1

16

16X (.016 )

[0.41]

14X (.0250 )

[0.635]

8

9

(.213)

[5.4]

LAND PATTERN EXAMPLE

SCALE:8X

SOLDER MASK

OPENING

SOLDER MASK

OPENING

METAL

.002 MAX

[0.05]

ALL AROUND

.002 MIN

[0.05]

ALL AROUND

SOLDER MASK

DEFINED

NON SOLDER MASK

DEFINED

SOLDER MASK DETAILS

4214846/A 03/2014

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

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EXAMPLE STENCIL DESIGN

DBQ0016A

SSOP - 1.75 mm max height

SHRINK SMALL-OUTLINE PACKAGE

16X (.063)

[1.6]

SYMM

1

16

16X (.016 )

[0.41]

SYMM

14X (.0250 )

[0.635]

9

8

(.213)

[5.4]

SOLDER PASTE EXAMPLE

BASED ON .005 INCH [0.127 MM] THICK STENCIL

SCALE:8X

4214846/A 03/2014

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

9. Board assembly site may have different recommendations for stencil design.

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TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE

邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	TPD3S716-Q1
厂家：	TEXAS INSTRUMENTS
描述：	汽车类 USB 0.5A 至 2.4A 可调节电流限制和 VBUS/D+/D- VBATT 短路保护
文件：	总33页 (文件大小：3133K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TPD3S716-Q1 [TI]

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