TPD4S311_V01 [TI]
TPD4S311, TPD4S311A USB Type-C⢠Port Protector: Short-to-VBUS Overvoltage and IEC ESD Protection;
| 型号： | TPD4S311_V01 |
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| 描述： | TPD4S311, TPD4S311A USB Type-C⢠Port Protector: Short-to-VBUS Overvoltage and IEC ESD Protection 光电二极管 |
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TPD4S311, TPD4S311A
SLVSF72C – DECEMBER 2019 – REVISED FEBRUARY 2021
TPD4S311, TPD4S311A USB Type-C™ Port Protector: Short-to-VBUS Overvoltage
and IEC ESD Protection
These non-ideal equipments and mechanical events
1 Features
make it necessary for the CC and SBU pins to be
20-V tolerant, even though the pins only operate at 5
V or lower. The TPD4S311 enables the CC and SBU
pins to be 20-V tolerant without interfering with normal
operation by providing over-voltage protection on the
CC and SBU pins. The device places high voltage
FETs in series on the SBU and CC lines. When
a voltage above the OVP threshold is detected on
these lines, the high voltage switches are opened up,
isolating the rest of the system from the high voltage
condition present on the connector.
•
4-Channels of Short-to-VBUS overvoltage
protection (CC1, CC2, SBU1, SBU2 ): 24-VDC
tolerant
•
•
4-Channels of IEC 61000-4-2 ESD protection
(CC1, CC2, SBU1, SBU2)
CC1 and CC2 overvoltage protection FETs for
passing VCONN power
– 400-mA VCONN power (TPD4S311)
– 600-mA VCONN power (TPD4S311A)
±35-V surge protection on CC pins (TPD4S311A)
±30-V surge protection on SBU pins (TPD4S311A)
CC dead battery resistors integrated for handling
dead battery use case in mobile devices
1.69-mm × 1.69-mm DSBGA package
•
•
•
Finally, most systems require IEC 61000-4-2 system
level ESD protection for external pins. The TPD4S311
integrates IEC 61000-4-2 ESD protection for the CC1,
CC2, SBU1, and SBU2 pins, eliminating the need
to place high voltage TVS diodes externally on the
connector.
•
2 Applications
•
•
•
•
•
•
Desktop PC/motherboard
Standard notebook PC
Chromebook and WOA
Docking station
Port/cable adapters and dongles
Smartphones
Device Information(1)
PART NUMBER
TPD4S311
PACKAGE
DSBGA (16)
DSBGA (16)
BODY SIZE (NOM)
1.69 mm × 1.69 mm
1.69 mm × 1.69 mm
TPD4S311A
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
3 Description
The TPD4S311 is a single-chip USB Type-C port
protection device that provides 20-V Short-to-VBUS
overvoltage and IEC ESD protection.
Battery
DC/DC
FET
OVP
Since the release of the USB Type-C connector,
many products and accessories for USB Type-C have
been released that do not meet the USB Type-C
specification. One example of this is USB Type-C
Power Delivery adaptors that only place 20 V on the
VBUS line. Another concern for USB Type-C is that
mechanical twisting and sliding of the connector could
short pins due to the close proximity they have in
this small connector. This can cause 20-V VBUS to
be shorted to the CC and SBU pins. Also due to the
proximity of the pins in the Type-C connector, there
is a heightened concern that debris and moisture will
cause the 20-V VBUS pin to be shorted to the CC and
SBU pins.
FET
OVP, OCP
CC Analog
USB PD Phy &
Controller
Power Switch Control
TPD4S311
SBU Mux
CC and SBU Overvoltage Protection
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPD4S311, TPD4S311A
SLVSF72C – DECEMBER 2019 – REVISED FEBRUARY 2021
www.ti.com
Table of Contents
1 Features............................................................................1
2 Applications.....................................................................1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Device Comparison Table...............................................3
6 Pin Configuration and Functions...................................4
7 Specifications.................................................................. 5
7.1 Absolute Maximum Ratings........................................ 5
7.2 ESD Ratings—JEDEC Specification...........................5
7.3 ESD Ratings—IEC Specification................................ 5
7.4 Recommended Operating Conditions.........................5
7.5 Thermal Information....................................................6
7.6 Electrical Characteristics.............................................6
7.7 Timing Requirements..................................................8
7.8 Typical Characteristics................................................9
8 Detailed Description......................................................14
8.1 Overview...................................................................14
8.2 Functional Block Diagram.........................................14
8.3 Feature Description...................................................15
8.4 Device Functional Modes..........................................17
9 Application and Implementation..................................18
9.1 Application Information............................................. 18
9.2 Typical Application.................................................... 18
10 Power Supply Recommendations..............................23
11 Layout...........................................................................24
11.1 Layout Guidelines................................................... 24
11.2 Layout Example...................................................... 24
12 Device and Documentation Support..........................25
12.1 Documentation Support.......................................... 25
12.2 Receiving Notification of Documentation Updates..25
12.3 Support Resources................................................. 25
12.4 Trademarks.............................................................25
12.5 Electrostatic Discharge Caution..............................25
12.6 Glossary..................................................................25
13 Mechanical, Packaging, and Orderable
Information.................................................................... 25
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (August 2020) to Revision C (February 2021)
Page
•
•
•
•
•
•
•
Added A version of the device............................................................................................................................1
Added A version of the device............................................................................................................................3
Added A version of the device to Absolute Maximum Ratings table.................................................................. 5
Added A version to ESD Ratings—IEC Specification table................................................................................5
Added A version to Recommended Operating Conditions table........................................................................ 5
Added A version to Electrical Characteristics table............................................................................................ 6
Added A version of the device to Detailed Description section........................................................................ 16
Changes from Revision A (April 2020) to Revision B (August 2020)
Page
•
•
•
•
•
•
•
•
•
•
•
Updated the numbering format for tables, figures and cross-references throughout the document...................1
Added IO row in Absolute Maximum Ratings table............................................................................................. 5
Deleted 1.2 A spec from Recommended Operating Conditions table................................................................ 5
Updated IVCONN max current to 400 mA in Recommended Operating Conditions table.................................... 5
Added table note to Recommended Operating Conditions table........................................................................5
Updated Figure 7-3 caption to 24 V....................................................................................................................9
Updated Figure 7-4 caption to 24 V....................................................................................................................9
Updated Figure 7-17 caption to 24 V..................................................................................................................9
Updated Figure 7-18 caption to 24 V..................................................................................................................9
Updated Figure 7-17 ..........................................................................................................................................9
Updated Figure 7-18 ..........................................................................................................................................9
Changes from Revision * (December 2019) to Revision A (September 2020)
Page
Updated Applications section with links..............................................................................................................1
Changed package-type name from WCSP to DSBGA; global change...............................................................1
•
•
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5 Device Comparison Table
Vconn
Current
CC On
Resistance
Part Number
Channels and Protection
4-Ch (CC1, CC2, SBU1, SBU2 ) overvoltage protection.
4-Ch (CC1, CC2, SBU1, SBU2) IEC 61000-4-2 ESD protection.
TPD4S311
400 mA
600 mA
378 mΩ
232 mΩ
4-Ch (CC1, CC2, SBU1, SBU2 ) overvoltage protection.
4-Ch (CC1, CC2, SBU1, SBU2) IEC 61000-4-2 ESD protection.
4-Ch (CC1, CC2, SBU1, SBU2) IEC 61000-4-5 Surge Protection.
TPD4S311A
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6 Pin Configuration and Functions
Top View
Bottom View
A1
A2
A3
A4
D2
D3
D4
D1
C_SBU2
C_CC1
C_CC2
VBIAS
CC1
SBU2
CC2
SBU1
B1
B2
B3
B4
C1
C2
C3
C4
C_SBU1
RPD_G1
RPD_G2
GND
GND
GND
VPWR
FLT
C1
C2
C3
C4
B1
B2
B3
B4
C_SBU1
RPD_G1
RPD_G2
GND
GND
GND
VPWR
FLT
D1
D2
D3
D4
A1
A2
A3
A4
C_SBU2
SBU1
SBU2
CC1
CC2
C_CC1
C_CC2
VBIAS
Figure 6-1. YBF Package 16-Pin DSBGA
Table 6-1. Pin Functions
PIN
TYPE(1)
DESCRIPTION
NO.
NAME
Connector side of the SBU2 OVP FET. Connect to either SBU pin of the USB Type-C
connector.
A1
A2
C_SBU2
C_CC1
I/O
I/O
Connector side of the CC1 OVP FET. Connect to either CC pin of the USB Type-C
connector.
Connector side of the CC2 OVP FET. Connect to either CC pin of the USB Type-C
connector.
A3
A4
B1
C_CC2
VBIAS
I/O
P
Pin for ESD support capacitor. Place a 0.1-µF capacitor on this pin to ground.
Connector side of the SBU1 OVP FET. Connect to either SBU pin of the USB Type-C
connector.
C_SBU1
I/O
Short to C_CC1 if dead battery resistors are needed. If dead battery resistors are not
needed, short pin to GND.
B2
RPD_G1
RPD_G2
I/O
I/O
Short to C_CC2 if dead battery resistors are needed. If dead battery resistors are not
needed, short pin to GND.
B3
B4
FLT
GND
VPWR
SBU1
SBU2
CC1
O
GND
P
Open drain for fault reporting.
C1, C2, C3
Ground
C4
D1
D2
D3
D4
2.7-V to 4.5-V power supply.
I/O
I/O
I/O
I/O
System side of the SBU1 OVP FET. Connect to either SBU pin of the SBU MUX.
System side of the SBU2 OVP FET. Connect to either SBU pin of the SBU MUX.
System side of the CC1 OVP FET. Connect to either CC pin of the CC/PD controller.
System side of the CC2 OVP FET. Connect to either CC pin of the CC/PD controller.
CC2
(1) I = input, O = output, I/O = input and output, GND = ground, P = power
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
MAX
5
UNIT
V
VPWR
VI
Input voltage
Output voltage
I/O voltage
RPD_G1, RPD_G2
24
6
V
FLT
V
VO
VIO
IO
VBIAS
24
6
V
CC1, CC2, SBU1, SBU2
C_CC1, C_CC2, C_SBU1, C_SBU2
C_CC1, C_CC2 (TPD4S311)
C_CC1, C_CC2 (TPD4S311A)
V
24
950
1.2
85
150
V
mA
A
Output Current
TA
Operating free air temperature
Storage temperature
–40
–65
°C
°C
Tstg
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
7.2 ESD Ratings—JEDEC Specification
VALUE
±2000
±500
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
V(ESD)
Electrostatic discharge
V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as
±2000 V may actually have higher performance.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as ±500
V may actually have higher performance.
7.3 ESD Ratings—IEC Specification
VALUE
±8000
±15000
±6000
±15000
±35
UNIT
V
V(ESD)
V(ESD)
V(ESD)
V(ESD)
Electrostatic discharge(1)
Electrostatic discharge(1)
Electrostatic discharge(1)
Electrostatic discharge(1)
IEC 61000-4-2, C_CC1, C_CC2
Contact discharge
Air-gap discharge
Contact discharge
Air-gap discharge
IEC 61000-4-2, C_CC1, C_CC2
V
IEC 61000-4-2, C_SBU1, C_SBU2
IEC 61000-4-2, C_SBU1, C_SBU2
IEC 61000-4-5, C_CC1, C_CC2 (TPD4S311A)
IEC 61000-4-5, C_SBU1, C_SBU2 (TPD4S311A)
V
V
V
V(Surge)
Lightning and Surge
±30
V
(1) Tested with connection to the TPS65982 EVM.
7.4 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
2.7
0
NOM
3.3
MAX
4.5
5.5
5.5
5.5
4.3
UNIT
VPWR
V
V
V
V
V
VI
Input voltage
Output voltage
I/O voltage
RPD_G1, RPD_G2
VO
VIO
FLT Pull-up resistor power rail
CC1, CC2, C_CC1, C_CC2
SBU1, SBU2, C_SBU1, C_SBU2
2.7
0
0
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7.4 Recommended Operating Conditions (continued)
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
Current flowing into CC1/2 and flowing out of
C_CC1/2,
4.5 ≤ CCx ≤ 5.5, TJ ≤ 85 ℃ (TPD4S311)
400(1)
600
mA
Current flowing into CC1/2 and flowing out of
C_CC1/2,
IVCONN
VCONN Current
mA
A
4.5 ≤ CCx ≤ 5.5, TJ ≤ 105 ℃ (TPD4S311A)
Current flowing into CC1/2 and flowing out of
C_CC1/2,
1.2
4.5 ≤ CCx ≤ 5.5, TJ ≤ 70 ℃ (TPD4S311A)
FLT Pull-up resistance
VBIAS capacitance(3)
VPWR Capacitance
1.7
0.3
300
kΩ
µF
µF
External Components(2)
0.1
1
(1) Vconn current loading beyond the values listed in Recommended Operating Conditions may degrade the operating lifetime of the
device.
(2) For recommended values for capacitors and resistors, the typical values assume a component placed on the board near the pin.
Minimum and maximum values listed are inclusive of manufacturing tolerances, voltage derating, board capacitance, and temperature
variation. The effective value presented should be within the minimum and maximums listed in the table.
(3) The VBIAS pin requires a minimum 35-VDC rated capacitor. A 50-VDC rated capacitor is recommended to reduce capacitance
derating.
See the VBIAS Capacitor Selection section for more information on selecting the VBIAS capacitor.
7.5 Thermal Information
TPD4S311
THERMAL METRIC(1)
YBF DSBGA
16 PINS
84.0
UNIT
RθJA
RθJC(top)
RθJB
ψJT
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
0.5
21.2
Junction-to-top characterization parameter
Junction-to-board characterization parameter
0.3
ψJB
21.1
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
7.6 Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
CC OVP Switches
CCx = 5.5 V, TJ ≤ 85 ℃ (TPD4S311)
CCx = 5.5 V, TJ ≤ 85 ℃ (TPD4S311A)
378
232
550
405
mΩ
mΩ
RON
On Resistance of CC OVP FETs
Equivalent on Capacitance
Capacitance from CCx or C_CCx to
GND when device is powered. Measure
atVC_CCx/VCCx = 0 V to 1.2 V, f = 400
kHz.
CON_CC
45
74
120
pF
Dead Battery Pull-Down Resistors (only
present when device is unpowered)
RD_DB
VC_CCx = 2.6 V
IC_CCx = 80 μA
4.1
0.5
5.1
0.9
6.1
1.2
kΩ
V
Threshold voltage of the pull-down FET
in series with RD during dead battery
VTH_DB
Place 5.5 V on C_CCx. Step up C_CCx
until FLT pin is asserted. Put 100-mA
load through the CC FET and see the
FET shuts off.
VOVPCC
OVP Threshold on CC Pins
5.75
6.0
6.2
V
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7.6 Electrical Characteristics (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Place 6.5 V on C_CCx. Step down the
voltage on C_CCx until the FLT pin is
deasserted. Measure difference
between rising and falling OVP
threshold for C_CCx.
VOVPCC_HYS
Hysteresis on CC OVP
50
mV
Measure the -3 dB bandwidth from
C_CCx to CCx. Single ended
measurement, 50-Ω system. Vcm = 0.1
V to 1.2 V.
BWON
On Bandwidth Single Ended (-3dB)
100
MHz
V
Hot-Plug C_CCx with a 1 meter USB
Short-to-VBUS tolerance on the CC pins Type C Cable, place a 30-Ω load on
CCx
VSTBUS_CC
24
Hot-Plug C_CCx with a 1 meter USB
Short-to-VBUS System-Side Clamping
Voltage on the CC pins (CCx)
Type C Cable. Hot-Plug voltage
C_CCx = 24 V. VPWR = 3.3 V. Place
a 30-Ω load on CCx.
VSTBUS_CC_CLAMP
8
V
SBU OVP Switches
RON
On Resistance of SBU OVP FETs
Equivalent on Capacitance
SBUx = 3.6 V. –40°C ≤ TJ ≤ +85°C
4
6
6.5
4.7
Ω
Capacitance from SBUx or C_SBUx to
GND when device is powered. Measure
at VC_SBUx/VSBUx = 0.3 V to 4.2 V.
CON_SBU
pF
Place 3.6 V on C_SBUx. Step up
C_SBUx until FLT pin is asserted.
VOVPSBU
OVP Threshold on SBU Pins
Hysteresis on SBU OVP
4.35
4.5
50
V
Place 5 V on C_CCx. Step down the
voltage on C_CCx until the FLT pin is
deasserted. Measure difference
between rising and falling OVP
threshold for C_SBUx.
VOVPSBU_HYS
mV
Measure the –3 dB bandwidth from
C_SBUx to SBUx. Single ended
measurement, 50-Ω system. Vcm = 0.1
V to 3.6 V.
BWON
On Bandwidth Single Ended (-3dB)
Crosstalk
900
-70
MHz
dB
V
Measure crosstalk at f = 1 MHz from
SBU1 to C_SBU2 or SBU2 to C_SBU1.
Vcm1 = 3.6 V, Vcm2 = 0.3 V. Terminate
open sides to 50 Ω.
XTALK
Hot-Plug C_SBUx with a 1 meter USB
Type C Cable. Put a 100-nF capacitor
in series with a 40-Ω resistor to GND
on SBUx.
Short-to-VBUS tolerance on the SBU
pins
VSTBUS_SBU
24
Hot-Plug C_SBUx with a 1 meter
USB Type C Cable. Hot-Plug voltage
C_SBUx = 24 V. VPWR = 3.3 V. Put a
150-nF capacitor in series with a 40-Ω
resistor to GND on SBUx.
Short-to-VBUS System-Side Clamping
Voltage on the SBU pins (SBUx)
VSTBUS_SBU_CLAMP
8
V
Power Supply and Leakage Currents
Place 1 V on VPWR and raise voltage
until SBU or CC FETs turn-on.
VPWR_UVLO
VPWR Under Voltage Lockout
2.1
2.3
150
90
2.5
V
Place 3 V on VPWR and lower voltage
until SBU or CC FETs turnoff; measure
difference between rising and falling
UVLO to calculate hysteresis.
VPWR_UVLO_HYS
VPWR UVLO Hysteresis
VPWR supply current
100
200
mV
VPWR = 3.3 V (typical), VPWR = 4.5 V
(maximum). –40°C ≤ TJ ≤ +85°C.
IVPWR
135
5
µA
µA
VPWR = 3.3 V, VC_CCx = 3.6 V,
CCx pins are floating, measure leakage
current into C_CCx pins.
Leakage current for C_CCx pins when
device is powered
IC_CC_LEAK
VPWR = 3.3 V, VC_SBUx = 3.6 V, SBUx
pins are floating, measure leakage
Leakage current for C_SBUx pins when current into C_SBUx pins. Result should
IC_SBU_LEAK
3
µA
device is powered
be same if SBUx side is biased and
C_SBUx is left floating.-40°C ≤ TJ ≤
+85°C
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7.6 Electrical Characteristics (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VPWR = 0 V or 3.3 V, VC_CCx = 24
V, CCx pins are set to 0 V, measure
leakage current into C_CCx pins.
Leakage current for C_CCx pins when
device is in OVP
IC_CC_LEAK_OVP
IC_SBU_LEAK_OVP
ICC_LEAK_OVP
1200
µA
VPWR = 0 V or 3.3 V, VC_SBUx = 24
V, SBUx pins are set to 0 V, measure
leakage current into C_SBUx pins.
Leakage current for C_SBUx pins when
device is in OVP
400
30
1
µA
µA
µA
VPWR = 0 V or 3.3 V, VC_CCx = 24
V, CCx pins are set to 0 V, measure
leakage current out of CCx pins.
Leakage current for CC pins when
device is in OVP
VPWR = 0 V, VC_SBUx = 24 V, SBUx
pins are set to 0 V, measure leakage
current into SBUx pins.
Leakage current for SBU pins when
device is in OVP
ISBU_LEAK_OVP
-1
/FLT Pin
IOL = 3 mA. Measure voltage at FLT
pin.
VOL
Low-level output voltage
0.4
V
Over Temperature Protection
The rising over-temperature protection
shutdown threshold
TSD_RISING
TSD_FALLING
TSD_HYST
150
130
175
140
35
°C
°C
°C
The falling over-temperature protection
shutdown threshold
The over-temperature protection
shutdown threshold hysteresis
7.7 Timing Requirements
MIN
NOM
MAX
UNIT
Power-On and Off Timings
tON_FET
Time from Crossing Rising VPWR UVLO until CC and SBU OVP FETs are on.
1.3
5.7
3.5
9.5
ms
ms
Time from Crossing Rising VPWR UVLO until CC and SBU OVP FETs are on
and the dead battery resistors are off.
tON_FET_DB
Minimum slew rate allowed to guarantee CC and FETs turn off during a power
off.
dVPWR_OFF/dt
-0.5
V/µs
Over Voltage Protection
tOVP_RESPONSE_CC
OVP response time on the CCx pins. Time from OVP asserted until OVP FETs
turn off.
70
80
ns
ns
OVP response time on the SBUx pins. Time from OVP asserted until OVP
FETs turn off.
tOVP_RESPONSE_SBU
OVP recovery time on the CCx pins. Once an OVP has occurred, the minimum
time duration until the CC FETs turn back on. OVP must be removed for CC
FETs to turn back on.
tOVP_RECOVERY_CC
0.93
5
ms
ms
ms
OVP recovery time on the CCx pins. Once an OVP has occurred, the minimum
time duration until the CC FETs turn back on and the dead battery resistors
turn off. OVP must be removed for CC FETs to turn back on.
tOVP_RECOVERY_CC_DB
OVP recovery time on the SBUx pins. Once an OVP has occurred, the
minimum time duration until the SBU FETs turn back on. OVP must be
removed for SBU FETs to turn back on.
tOVP_RECOVERY_SBU
0.62
Time from OVP Asserted to /FLT assertion. FLT assertion is 10% of the
maxmimum value. Set C_CCx or C_SBUx above the maxmimum OVP
threshold. Start the time where it passes the typical OVP threshold value.
tOVP_FLT_ASSERTION
20
5
µs
tOVP_FLT_DEASSERTION
Time from CC FET turn on after an OVP to FLT deassertion.
ms
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7.8 Typical Characteristics
0
-10
-15
-20
-25
-30
-35
-40
-45
-50
-55
-60
-65
-70
-1
-2
-3
-4
-5
-6
-7
-8
-9
-10
10
20 30 40 50 70 100
200 300
500 700 1000
2000 3000
D003
10
20 30 40 50 70 100
200 300
500 700 1000
2000 3000
D004
Frequency (MHz)
Frequency (MHz)
Figure 7-1. SBU Bandwidth
Figure 7-2. SBU Crosstalk
32
28
24
20
16
12
8
6.4
5.6
4.8
4
30
27
24
21
18
15
12
9
C_SBU
SBU1
IC_SBU
C_SBU
SBU
/FLT
3.2
2.4
1.6
0.8
0
6
4
3
0
0
-3
-4
-1000
-0.8
D014
-10 -8
-6
-4
-2
0
2
4
6
8
10 12 14 16 18 20
-600
-200
200
600
1000
1400
1800
Time (ms)
D012
Time (ns)
Figure 7-4. SBU Short-to-VBUS 24 V Zoomed Out
Figure 7-3. SBU Short-to-VBUS 24 V Zoomed In
6
5.5
5
6
C_SBU
SBU
/FLT
C_SBU
SBU
/FLT
5.5
5
4.5
4
4.5
4
3.5
3
3.5
3
2.5
2
2.5
2
1.5
1
1.5
1
0.5
0
0.5
0
-0.5
-0.5
-1
-1
-6 -5 -4 -3 -2 -1
0
1
2
3
4
5
6
7
8
9
10
-10
-5
0
5
10
15
20
25
30
35
40
Time (ms)
Time (ms)
D010
D011
Figure 7-5. SBU Short-to-VBUS 5 V Zoomed In
Figure 7-6. SBU Short-to-VBUS 5 V Zoomed Out
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7.8 Typical Characteristics (continued)
7
140
120
100
80
-40èC
25èC
85èC
6
125èC
60
5
40
20
4
3
2
0
-20
-40
-60
-80
C_SBU
SBU
-10
0
10 20 30 40 50 60 70 80 90 100 110
Time (ns)
0
0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7
VSBU1 (V)
3
3.3 3.6
D001
D014
Figure 7-8. SBU IEC 61000-4-2 4-kV Response Waveform
Figure 7-7. SBU RON Flatness
80
60
2.5
C_SBU1
C_SBU2
2
1.5
1
40
20
0
-20
-40
-60
-80
-100
0.5
C_SBU
SBU
0
-10
0
10 20 30 40 50 60 70 80 90 100 110
Time (ns)
-40 -30 -20 -10
0
10 20 30 40 50 60 70 8085
Temperature (èC)
D001
D014
Figure 7-9. SBU IEC 61000-4-2 –4-kV Response Waveform
Figure 7-10. SBU Path Leakage Current vs Ambient
Temperature at 3.6 V
0.000125
500
SBU1: C_SBU1 at 24 V
SBU2: C_SBU2 at 24 V
SBU1: C_SBU1 at 5.5 V
C_SBU1 at 24 V
C_SBU2 at 24 V
C_SBU1 at 5.5 V
450
0.0001
400
SBU2: C_SBU2 at 5.5 V
C_SBU2 at 5.5 V
350
7.5E-5
300
250
200
150
100
50
5E-5
2.5E-5
0
-40 -30 -20 -10
0
10 20 30 40 50 60 70 8085
Temperature (èC)
0
D014
-40 -30 -20 -10
0
10 20 30 40 50 60 70 8085
Temperature (èC)
D014
Figure 7-12. SBU OVP Leakage Current vs Ambient
Temperature at 5.5 V and 24 V
Figure 7-11. C_SBU OVP Leakage Current vs Ambient
Temperature at 5.5 V and 24 V
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7.8 Typical Characteristics (continued)
3.6
3.3
3
30
25
20
15
10
5
C_SBU
2.7
2.4
2.1
1.8
1.5
1.2
0.9
VPWR
C_SBU1
SBU1
0.6
0.3
0
0
-3
-2
-1
0
1
2
Time (ms)
3
4
5
6
7
0
5
10
15
20
Voltage (V)
25
30
35
40
D014
D005
Figure 7-13. SBU FET Turnon Timing
Figure 7-14. C_SBU TLP Curve Unpowered
0
-1
-2
-3
-4
-5
-6
-7
-8
-9
1
0.75
0.5
0.25
0
-0.25
-0.5
-0.75
-1
-10
-11
-12
-13
-14
-15
C_SBU
-5
0
5
10
15
Voltage (V)
20
25
30
35
10
20
30 40 50 6070 100
200
300 400500 700 1000
D001
D003
Frequency (MHz)
Figure 7-15. SBU IV Curve
Figure 7-16. CC Bandwidth
32
28
24
20
16
12
8
6.4
5.6
4.8
4
32
28
24
20
16
12
8
C_CC
CC
/FLT
IC_CC
C_CC
CC
/FLT
3.2
2.4
1.6
0.8
0
4
4
0
0
-4
-1000
-0.8
-4
-600
-200
200
600
1000
1400
1800
-10 -8
-6
-4
-2
0
2
4
6
8
10 12 14 16 18 20
Time (ns)
Time (ms)
Figure 7-17. CC Short-to-VBUS 24 V Zoomed In
Figure 7-18. CC Short-to-VBUS 24 V Zoomed Out
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7.8 Typical Characteristics (continued)
5.5
5.5
5
C_CC
CC
/FLT
C_CC
CC
/FLT
5
4.5
4
4.5
4
3.5
3
3.5
3
2.5
2
2.5
2
1.5
1
1.5
1
0.5
0
0.5
0
-0.5
-0.5
-2
0
2
4
6
8
10
12
14
16
18
20
-2
-1.5
-1
-0.5
0
0.5
1
1.5
2
2.5
Time (ms)
Time (ms)
D009
D008
Figure 7-20. CC Short-to-VBUS 5 V Zoomed Out
Figure 7-19. CC Short-to-VBUS 5 V Zoomed In
140
120
100
80
CC OVP Switches, RON
500
475
450
425
400
375
350
325
300
275
250
60
40
20
0
-20
-40
-60
-80
C_CC
CC
-10
0
10 20 30 40 50 60 70 80 90 100 110
Time (ns)
-45
-30
-15
0
15
30
45
60
75
90
D001
Temperature, èC
CCRO
Figure 7-22. CC IEC 61000-4-2 8-kV Response Waveform
Figure 7-21. CC RON Versus Temperature
80
60
20
C_CC1
19
C_CC2
18
40
17
16
15
14
13
12
11
10
9
20
0
-20
-40
-60
-80
-100
C_CC
CC
8
-10
0
10 20 30 40 50 60 70 80 90 100 110
Time (ns)
-40 -30 -20 -10
0
10 20 30 40 50 60 70 8085
Temperature (èC)
D001
D014
Figure 7-23. CC IEC 61000-4-2 –8-kV Response Waveform
Figure 7-24. C_CC Path Leakage Current vs Ambient
Temperature at C_CC = 5.5 V
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7.8 Typical Characteristics (continued)
1030
4.3E-4
3.8E-4
3.3E-4
2.8E-4
2.3E-4
1.8E-4
1.3E-4
8E-5
C_CC1
C_CC2
1025
CC1: C_CC1 at 24 V
CC2: C_CC2 at 24 V
1020
1015
1010
1005
1000
3E-5
-40 -30 -20 -10
0
10 20 30 40 50 60 70 8085
Temperature (èC)
-40 -30 -20 -10
0
10 20 30 40 50 60 70 8085
Temperature (èC)
D014
D014
Figure 7-26. CC OVP Leakage Current vs Ambient Temperature
at C_CC = 24 V
Figure 7-25. C_CC OVP Leakage Current vs Ambient
Temperature at C_CC = 24 V
5.5
5
30
C_CC
25
20
15
10
5
4.5
4
3.5
3
2.5
2
1.5
1
0.5
0
VPWR
C_CC1
CC1
0
-3
-2
-1
0
1
2
Time (ms)
3
4
5
6
7
0
5
10
15
20 25
Voltage (V)
30
35
40
45
D014
D0035
Figure 7-27. CC FET Turnon Timing
Figure 7-28. C_CC TLP Curve Unpowered
1
100
97.5
95
IVPWR
0.75
0.5
0.25
0
92.5
90
-0.25
-0.5
-0.75
-1
87.5
85
82.5
80
C_CC
-5
0
5
10 15
Voltage (V)
20
25
30
-40 -30 -20 -10
0
10 20 30 40 50 60 70 8085
Temperature (èC)
D003
D014
Figure 7-29. C_CC IV Curve
Figure 7-30. VPWR Supply Leakage vs Ambient Temperature at
3.6 V
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8 Detailed Description
8.1 Overview
The TPD4S311 is a single chip USB Type-C port protection solution that provides 20-V Short-to-VBUS
overvoltage and IEC ESD protection. Due to the small pin pitch of the USB Type-C connector and non-compliant
USB Type-C cables and accessories, the VBUS pins can get shorted to the CC and SBU pins inside the USB
Type-C connector. Because of this short-to-VBUS event, the CC and SBU pins need to be 20-V tolerant, to
support protection on the full USB PD voltage range. Even if a device does not support 20-V operation on VBUS
,
non complaint adaptors can start out with 20-V VBUS condition, making it necessary for any USB Type-C device
to support 20 V protection. The TPD4S311 integrates four channels of 20-V Short-to-VBUS overvoltage protection
for the CC1, CC2, SBU1, and SBU2 pins of the USB Type-C connector.
Additionally, IEC 61000-4-2 system level ESD protection is required in order to protect a USB Type-C port
from ESD strikes generated by end product users. The TPD4S311 integrates four channels of IEC61000-4-2
ESD protection for the CC1, CC2, SBU1, and SBU2 pins of the USB Type-C connector. This means IEC
ESD protection is provided for all of the low-speed pins on the USB Type-C connector in a single chip in the
TPD4S311. Additionally, high-voltage IEC ESD protection that is 22-V DC tolerant is required for the CC and
SBU lines in order to simultaneously support IEC ESD and Short-to-VBUS protection; there are not many discrete
market solutions that can provide this kind of protection. This high-voltage IEC ESD diode is what the TPD4S311
integrates, specifically designed to guarantee it works in conjunction with the overvoltage protection FETs inside
the device. This sort of solution is very hard to generate with discrete components.
8.2 Functional Block Diagram
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8.3 Feature Description
8.3.1 4-Channels of Short-to-VBUS Overvoltage Protection (CC1, CC2, SBU1, SBU2 Pins ): 24-VDC Tolerant
The TPD4S311 provides 4-channels of Short-to-VBUS Overvoltage Protection for the CC1, CC2, SBU1, and
SBU2 pins of the USB Type-C connector. The TPD4S311 is able to handle 24-VDC on its C_CC1, C_CC2,
C_SBU1, and C_SBU2 pins. This is necessary because according to the USB PD specification, with VBUS set for
20-V operation, the VBUS voltage is allowed to legally swing up to 21 V and 21.5 V on voltage transitions from a
different USB PD VBUS voltage. The TPD4S311 builds in tolerance up to 24-VBUS to provide margin above this
21.5-V specification to be able to support USB PD adaptors that may break the USB PD specification.
When a short-to-VBUS event occurs, ringing happens due to the RLC elements in the hot-plug event. With very
low resistance in this RLC circuit, ringing up to twice the settling voltage can appear on the connector. More than
2x ringing can be generated if any capacitor on the line derates in capacitance value during the short-to-VBUS
event. This means that more than 44 V could be seen on a USB Type-C pin during a Short-to-VBUS event. The
TPD4S311 has built in circuit protection to handle this ringing. The diode clamps used for IEC ESD protection
also clamp the ringing voltage during the short-to-VBUS event to limit the peak ringing to approximately 30 V.
Additionally, the overvoltage protection FETs integrated inside the TPD4S311 are 30-V tolerant, therefore being
capable of supporting the high-voltage ringing waveform that is experienced during the short-to-VBUS event. The
well designed combination of voltage clamps and 30-V tolerant OVP FETs insures the TPD4S311 can handle
Short-to-VBUS hot-plug events with hot-plug voltages as high as 24-VDC
.
The TPD4S311 has an extremely fast turnoff time of 70 ns typical. Furthermore, additional voltage clamps are
placed after the OVP FET on the system side (CC1, CC2, SBU1, SBU2) pins of the TPD4S311, to further limit
the voltage and current that are exposed to the USB Type-C CC/PD controller during the 70 ns interval while the
OVP FET is turning off. The combination of connector side voltage clamps, OVP FETs with extremely fast turnoff
time, and system side voltage clamps all work together to insure the level of stress seen on a CC1, CC2, SBU1,
or SBU2 pin during a short-to-VBUS event is less than or equal to an HBM event. This is done by design, as any
USB Type-C CC/PD controller will have built in HBM ESD protection.
Figure 8-1 is an example of the TPD4S311 successfully protecting the TPS65982, the world's first fully
integrated, full-featured USB Type-C and PD controller.
Figure 8-1. TPD4S311 Protecting the TPS65982 During a Short-to-VBUS Event
8.3.2 4-Channels of IEC 61000-4-2 ESD Protection (CC1, CC2, SBU1, SBU2 Pins)
The TPD4S311 integrates 4-Channels of IEC 61000-4-2 system level ESD protection for the CC1, CC2, SBU1,
and SBU2 pins. USB Type-C ports on end-products need system level IEC ESD protection in order to provide
adequate protection for the ESD events that the connector can be exposed to from end users. The TPD4S311
integrates IEC ESD protection for all of the low-speed pins on the USB Type-C connector in a single chip.
Also note, that while the RPD_Gx pins are not individually rated for IEC ESD, when they are shorted to the
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C_CCx pins, the C_CCx pins provide protection for both the C_CCx pins and the RPD_Gx pins. Additionally,
high-voltage IEC ESD protection that is 24-V DC tolerant is required for the CC and SBU lines in order to
simultaneously support IEC ESD and Short-to-VBUS protection; there are not many discrete market solutions
that can provide this kind of protection. The TPD4S311 integrates this type of high-voltage ESD protection so a
system designer can meet both IEC ESD and Short-to-VBUS protection requirements in a single device.
8.3.3 CC1, CC2 Overvoltage Protection FETs 400-mA or 600-mA Capable for Passing VCONN Power
The CC pins on the USB Type-C connector serve many functions; one of the functions is to be a provider of
power to active cables. Active cables are required when desiring to pass greater than 3 A of current on the VBUS
line or when the USB Type-C port uses the super-speed lines (TX1+, TX2–, RX1+, RX1–, TX2+, TX2–, RX2+,
RX2–). When CC is configured to provide power, it is called VCONN. VCONN is a DC voltage source in the
range of 3 V to 5.5 V. If supporting VCONN, a VCONN provider must be able to provide 1 W of power to a cable;
this translates into a current range of 200 mA to 333 mA (depending on your VCONN voltage level). Additionally,
if operating in a USB PD alternate mode, greater power levels are allowed on the VCONN line.
When a USB Type-C port is configured for VCONN and using the TPD4S311, this VCONN current flows
through the OVP FETs of the TPD4S311. Therefore, the TPD4S311 has been designed to handle these currents
and have an RON low enough to provide a specification compliant VCONN voltage to the active cable. The
TPD4S311 is designed to handle up to 400 mA, while the TPD4S311A is designed to handle up to 600 mA of
DC current to allow for alternate mode support in addition to the standard 1 W required by the USB Type-C
specification.
8.3.4 CC Dead Battery Resistors Integrated for Handling the Dead Battery Use Case in Mobile Devices
An important feature of USB Type-C and USB PD is the ability for this connector to serve as the sole power
source to mobile devices. With support up to 100 W, the USB Type-C connector supporting USB PD can be
used to power a whole new range of mobile devices not previously possible with legacy USB connectors.
When the USB Type-C connector is the sole power supply for a battery powered device, the device must be
able to charge from the USB Type-C connector even when its battery is dead. In order for a USB Type-C
power adapter to supply power on VBUS, RD pulldown resistors must be exposed on the CC pins. These RD
resistors are typically included inside a USB Type-C CC/PD controller. However, when the TPD4S311 is used
to protect the USB Type-C port, the OVP FETs inside the device isolate these RD resistors in the CC/PD
controller when the mobile device has no power. This is because when the TPD4S311 has no power, the OVP
FETs are turned off to guarantee overvoltage protection in a dead battery condition. Therefore, the TPD4S311
integrates high-voltage, dead battery RD pull-down resistors to allow dead battery charging simultaneously with
high-voltage OVP protection.
If dead battery support is required, short the RPD_G1 pin to the C_CC1 pin, and short the RPD_G2 pin to
the C_CC2 pin. This connects the dead battery resistors to the connector CC pins. When the TPD4S311 is
unpowered, and the RP pull-up resistor is connected from a power adaptor, this RP pull-up resistor activates
the RD resistor inside the TPD4S311. This enables VBUS to be applied from the power adaptor even in a dead
battery condition. Once power is restored back to the system and back to the TPD4S311 on its VPWR pin, the
TPD4S311 turns ON its OVP FETs in 3.5 ms and then turns OFF its dead battery RD. The TPD4S311 first turns
ON its CC OVP FETs fully, and then removes its dead battery RDs. This is to make sure the PD controller RD is
fully exposed before removing the RD of the TPD4S311. This is to help ensure the USB Type-C source remains
attached because a USB Type-C sink must have an RD present on CC at all times to guarantee according to the
USB Type-C spec that the USB Type-C source remains attached.
If desiring to power the CC/PD controller during dead battery mode and if the CC/PD Controller is configured
as a DRP, it is critical that the TPD4S311 be powered before or at the same time that the CC/PD controller is
powered. It is also critical that when unpowered, the CC/PD controller also expose its dead battery resistors.
When the TPD4S311 gets powered, it exposes the CC pins of the CC/PD controller within 3.5 ms, and then
removes its own RD dead battery resistors. Once the TPD4S311 turns on, the RD pull-down resistors of the
CC/PD controller must be present immediately, in order to guarantee the power adaptor connected to power the
dead battery device keeps its VBUS turned on. If the power adaptor does not see RD present, it can disconnect
VBUS. This removes power from the device with its battery still not sufficiently charged, which consequently
removes power from the CC/PD controller and the TPD4S311. Then the RD resistors of the TPD4S311 are
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exposed again, and connects the power adaptor's VBUS to start the cycle over. This creates an infinite loop,
never or very slowly charging the mobile device.
If the CC/PD Controller is configured for DRP and has started its DRP toggle before the TPD4S311 turns on,
this DRP toggle is unable to guarantee that the power adaptor does not disconnect from the port. Therefore,
it is recommended if the CC/PD controller is configured for DRP, that its dead battery resistors be exposed as
well, and that they remain exposed until the TPD4S311 turns on. This is typically accomplished by powering
the TPD4S311 at the same time as the CC/PD controller when powering the CC/PD controller in dead battery
operation. When protecting the TPS6598x family of PD controllers with TPD4S311, this is accomplished by
powering TPD4S311 from TPS6598x's LDO_3V3 pin (connect TPS6598x's LDO_3V3 pin to TPD4S311's VPWR
pin).
If dead battery charging is not required in your application, connect the RPD_G1 and RPD_G2 pins to ground.
8.3.5 1.69-mm × 1.69-mm DSBGA Package
The TPD4S311 comes in a tiny, 1.69-mm × 1.69-mm DSBGA package, greatly reducing the size of implementing
a similar protection solution discretely. The DSBGA package supports a wide range of PCB designs.
8.4 Device Functional Modes
Table 8-1 describes all of the functional modes for the TPD4S311. The "X" in the below table are "do not
care" conditions, meaning any value can be present within the absolute maximum ratings of the datasheet and
maintain that functional mode.
Table 8-1. Device Mode Table
Device Mode Table
MODE
Inputs
Outputs
CC FETs
VPWR C_CCx
C_SBUx
RPD_Gx
TJ
FLT
SBU FETs
Unpowered,
no dead
battery
<UVLO
X
X
X
X
Grounded
X
High-Z
OFF
OFF
OFF
support
Normal
Operating Unpowered,
Conditions dead battery <UVLO
Shorted to
C_CCx
X
High-Z
High-Z
OFF
support
X, forced
OFF
Powered on >UVLO <OVP
Thermal
<OVP
X
<TSD
>TSD
ON
ON
X, forced
OFF
Low (Fault
Asserted)
>UVLO
X
OFF
OFF
shutdown
CC over
voltage
condition
X, forced
OFF
Low (Fault
Asserted)
Fault
Conditions
>UVLO >OVP
X
<TSD
<TSD
OFF
OFF
OFF
OFF
SBU over
voltage
condition
X, forced
OFF
Low (Fault
Asserted)
>UVLO
>UVLO
X
X
>OVP
IEC ESD
generated
over voltage
condition(1)
RD ON if
RPD_Gx is
shorted to
C_CCx
Low (Fault
Asserted)
X
<TSD
OFF
OFF
(1) This row describes the state of the device while still in OVP after the IEC ESD strike which put the device into OVP is over, and the
voltages on the C_CCx and C_SBUx pins have returned to their normal voltage levels.
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9 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
9.1 Application Information
The TPD4S311 provides 4-channels of Short-to-VBUS overvoltage protection for the CC1, CC2, SBU1, and
SBU2 pins of the USB Type-C connector, and 4-channels of IEC ESD protection for the CC1, CC2, SBU1, and
SBU2 pins of the USB Type-C connector. Care must be taken to insure that the TPD4S311 provides adequate
system protection as well as insuring that proper system operation is maintained. The following application
example explains how to properly design the TPD4S311 into a USB Type-C system.
9.2 Typical Application
DC/DC
Battery
EC
VCONN VBUS_SRC
Battery
Charger
USB_DP
Controller
USB_DP
Controller
VBUS_SINK
DM
DP
AUX_N AUX_P
PP_CABLE
PP_5V
HV_GATE1
HV_GATE2
TPS65982
VBUS
DM_B DP_B
DM_T DP_T C_SBU2
C_SBU1 C_CC2
C_CC1
LDO_3V3
CCC2
CCC1
N.C.
N.C.
CVPWR
CC1
SBU1
CC2
SBU2
VPWR
R/FLT
/FLT
To EC or 82
CVBIAS
TPD4S311
VBIAS
RPD_G2
RPD_G1
C_CC1
C_SBU2 C_SBU1
C_CC2
VBUS
DM_B DP_B DM_T DP_T SBU2 SBU1 CC2
CC1
Figure 9-1. TPD4S311 Typical Application Diagram
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Figure 9-2. TPD4S311 Reference Schematic
9.2.1 Design Requirements
In this application example we study the protection requirements for a full-featured USB Type-C DRP Port,
fully equipped with USB-PD, USB2.0, USB3.0, Display Port, and 100 W charging. The TPS65982 is used to
easily enable a full-featured port with a single chip solution. In this application, all the pins of the USB Type-C
connector are used. Both the CC and SBU pins are susceptible to shorting to the VBUS pin. With 100 W
charging, VBUS operates at 20 V, requiring the CC and SBU pins to tolerate 20-VDC. With these protection
requirements present for the USB Type-C connector, the TPD4S311 is used. The TPD4S311 is a single chip
solution that provides all the required protection for the SBU and CC pins in the USB Type-C connector.
Table 9-1 lists the TPD4S311 design parameters.
Table 9-1. Design Parameters
DESIGN PARAMETER
EXAMPLE VALUE
VBUS nominal operating voltage
20 V
24 V
Short-to-VBUS tolerance for the CC and SBU pins
VBIAS nominal capacitance
0.1 µF
100 W
85°C
Dead battery charging
Maximum ambient temperature requirement
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9.2.2 Detailed Design Procedure
9.2.2.1 VBIAS Capacitor Selection
As noted in the Recommended Operating Conditions table, a minimum of 35-VBUS rated capacitor is required
for the VBIAS pin, and a 50-VBUS capacitor is recommended. The VBIAS capacitor is in parallel with the central
diode clamp integrated inside the TPD4S311. A forward biased hiding diode connects the VBIAS pin to the
C_CCx and C_SBUx pins. Therefore, when a Short-to-VBUS event occurs at 20 V, 20-VBUS minus a forward
biased diode drop is exposed to the VBIAS pin. Additionally, during the short-to-VBUS event, ringing can occur
almost double the settling voltage of 20 V, allowing a potential 40 V to be exposed to the C_CCx and C_SBUx
pins. However, the internal diode clamps limit the voltage exposed to the C_CCx and C_SBUx pins to around 30
V. Therefore, at least 35-VBUS capacitor is required to insure the VBIAS capacitor does not get destroyed during
Short-to-VBUS events.
A 50-V, X7R capacitor is recommended to further improve the derating performance of the capacitors. When the
voltage across a real capacitor is increased, its capacitance value derates. The more the capacitor derates, the
greater than 2x ringing can occur in the short-to-VBUS RLC circuit. The 50-V X7R capacitors have great derating
performance, allowing for the best short-to-VBUS performance of the TPD4S311.
Additionally, the VBIAS capacitor helps pass IEC 61000-4-2 ESD strikes. The more capacitance present, the
better the IEC performance. So the less the VBIAS capacitor derates, the better the IEC performance. Table 9-2
shows real capacitors recommended to achieve the best performance with the TPD4S311.
Table 9-2. Design Parameters
CAPACITOR SIZE
PART NUMBER
0402
0603
CC0402KRX7R9BB104
GRM188R71H104KA93D
9.2.2.2 Dead Battery Operation
For this application, we want to support 100-W dead battery operation; when the laptop is out of battery, we
still want to charge the laptop at 20 V and 5 A. This means that the USB PD Controller must receive power in
dead battery mode. The TPS65982 has its own built in LDO in order to supply the TPS65982 power from VBUS
in a dead battery condition. The TPS65982 can also provide power to its flash during this condition through its
LDO_3V3 pin.
The OVP FETs of the TPD4S311 remain OFF when it is unpowered in order to insure in a dead battery situation
proper protection is still provided to the PD controller in the system, in this case the TPS65982. However, when
the OVP FETs are OFF, this isolates the TPS65982s dead battery resistors from the USB Type-C ports CC
pins. A USB Type-C power adaptor must see the RD pull-down dead battery resistors on the CC pins or it does
not provide power on VBUS. Since the TPS65982s dead battery resistors are isolated from the USB Type-C
connector's CC pins, the built-in, dead battery resistors of the TPD4S311 must be connected. Short the RPD_G1
pin to the C_CC1 pin, and short the RPD_G2 pin to the C_CC2 pin.
Once the power adaptor sees the dead battery resistors of the TPD4S311, it applies 5 V on the VBUS pin. This
provides power to the TPS65982, turning the PD controller on, and allowing the battery to begin to charge.
However, this application requires 100 W charging in dead battery mode, so VBUS at 20 V and 5 A is required.
USB PD negotiation is required to accomplish this, so the TPS65982 needs to be able to communicate on the
CC pins. This means the TPD4S311 needs to be turned on in dead battery mode as well so the TPS65982s
PD controller can be exposed to the CC lines. To accomplish this, it is critical that the TPD4S311 is powered
by the TPS65982s internal LDO, the LDO_3V3 pin. This way, when the TPS65982 receives power on VBUS, the
TPD4S311 is turned on simultaneously.
It is critical that the TPS65982's dead battery resistors are also connected to its CC pins for dead battery
operation. Short the TPS65982s RPD_G1 pin to its C_CC1 pin, and its RPD_G2 pin to its C_CC2 pin. It is
critical that the TPS65982s dead battery resistors are present; once the TPD4S311 receives power, turns on its
OVP FETs and then removes its dead battery RD resistor, TPS65982's RD pull-down resistors must be present
on the CC line in order to guarantee the power adaptor stays connected. If RD is not present the power adaptor
will eventually interpret this as a disconnect and remove VBUS
.
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Also, it is important that the TPS65982's dead battery resistors are present so it properly boots up in dead
battery operation with the correct voltages on its CC pins.
Once this process has occurred, the TPS65982 can start negotiating with the power adaptor through USB PD for
higher power levels, allowing 100-W operation in dead battery mode.
For more information on the TPD4S311 dead battery operation, see the CC Dead Battery Resistors Integrated
for Handling the Dead Battery Use Case in Mobile Devices section of the datasheet.
9.2.2.3 CC Line Capacitance
USB PD has a specification for the total amount of capacitance that is required for proper USB PD BMC
operation on the CC lines. The specification from section 5.8.6 of the USB PD Specification is given below in
Table 9-3.
Table 9-3. USB PD cReceiver Specification
NAME
DESCRIPTION
MIN
MAX
UNIT
COMMENT
The DFP or UFP system shall have
capacitance within this range when
not transmitting on the line
cReceiver
CC receiver capacitance
200
600
pF
Therefore, the capacitance on the CC lines must stay in between 200 pF and 600 pF when USB PD is being
used. Therefore, the combination of capacitances added to the system by the TPS65982, the TPD4S311, and
any external capacitor must fall within these limits. Table 9-4 shows the analysis involved in choosing the correct
external CC capacitor for this system, and shows that an external CC capacitor is required.
Table 9-4. CC Line Capacitor Calculation
CC CAPACITANCE
CC line target capacitance
TPS65982 capacitance
TPD4S311 capacitance
MIN
200
70
MAX UNIT
COMMENT
600
120
120
pF
pF
pF
From the USB PD Specification section
From the TPS65982 data sheet
From the Electrical Characteristics table
45
CAP, CERM, 220 pF, 25 V, ±10%, X7R,
0201 (for min and max, assume ±50%
capacitance change with temperature and
voltage derating to be overly conservative)
Proposed capacitor GRM033R71E221KA01D
110
225
330
570
pF
pF
TPS65982 + TPD4S311 + GRM033R71E221KA01D
Meets USB PD cReceiver specification
9.2.2.4 Additional ESD Protection on CC and SBU Lines
If additional IEC ESD protection is desired to be placed on either the CC or SBU lines, it is important that
high-voltage ESD protection diodes be used. The maximum DC voltage that can be seen in USB PD is 21-VBUS
,
with 21.5 V allowed during voltage transitions. Therefore, an ESD protection diode must have a reverse stand off
voltage higher than 21.5 V in order to guarantee the diode does not breakdown during a short-to-VBUS event and
have large amounts of current flowing through it indefinitely, destroying the diode. A reverse stand off voltage
of 24 V is recommended to give margin above 21.5 V in case USB Type-C power adaptors are released in the
market which break the USB Type-C specification.
Furthermore, due to the fact that the Short-to-VBUS event applies a DC voltage to the CC and SBU pins, a
deep-snap-back diode cannot be used unless its minimum trigger voltage is above 42 V. During a Short-to-VBUS
event, RLC ringing of up to 2x the settling voltage can be exposed to CC and SBU, allowing for up to 42 V to be
exposed. Furthermore, if any capacitor derates on the CC or SBU line, greater than 2x ringing can occur. Since
this ringing is hard to bound, it is recommended to not use deep-snap-back diodes. If the deep-snap-back diode
triggers during the short-to-VBUS hot-plug event, it begins to operate in its conduction region. With a 20-VBUS
source present on the CC or SBU line, this allows the diode to conduct indefinitely, destroying the diode.
9.2.2.5 FLT Pin Operation
Once a Short-to-VBUS occurs on the C_CCx or C_SBUx pins, the FLT pin is asserted in 20 µs (typical) so the
PD controller can be notified quickly. If VBUS is being shorted to CC or SBU, it is recommended to respond to the
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event by forcing a detach in the USB PD controller to remove VBUS from the port. Although the USB Type-C port
using the TPD4S311 is not damaged, as the TPD4S311 provides protection from these events, the other device
connected through the USB Type-C Cable or any active circuitry in the cable can be damaged. Although shutting
the VBUS off through a detach does not guarantee it stops the other device or cable from being damaged, it can
mitigate any high current paths from causing further damage after the initial damage takes place. Additionally,
even if the active cable or other device does have proper protection, the short-to-VBUS event may corrupt a
configuration in an active cable or in the other PD controller, so it is best to detach and reconfigure the port.
9.2.2.6 How to Connect Unused Pins
If either the RPD_Gx pins are unused in a design, they must be connected to GND.
9.2.3 Application Curves
Figure 9-4. TPD4S311 Protecting the TPS65982
During a Short-to-VBUS Event
Figure 9-3. TPD4S311 Turning On in Dead Battery
Mode with RD on CC1
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10 Power Supply Recommendations
The VPWR pin provides power to all the circuitry in the TPD4S311. It is recommended a 1-µF decoupling
capacitor is placed as close as possible to the VPWR pin. If USB PD is desired to be operated in dead battery
conditions, it is critical that the TPD4S311 share the same power supply as the PD controller in dead battery
boot-up (such as sharing the same dead battery LDO). See the CC Dead Battery Resistors Integrated for
Handling the Dead Battery Use Case in Mobile Devices section for more details.
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11 Layout
11.1 Layout Guidelines
Proper routing and placement is important to maintain the signal integrity the SBU and CC line signals. The
following guidelines apply to the TPD4S311:
•
Place the bypass capacitors as close as possible to the VPWR pin, and ESD protection capacitor as close as
possible to the VBIAS pin. Capacitors must be attached to a solid ground. This minimizes voltage disturbances
during transient events such as short-to-VBUS and ESD strikes.
•
The SBU lines must be routed as straight as possible and any sharp bends must be minimized.
Standard ESD recommendations apply to the C_CC1, C_CC2, C_SBU1, C_SBU2:
•
The optimum placement for the device is as close to the connector as possible:
– EMI during an ESD event can couple from the trace being struck to other nearby unprotected traces,
resulting in early system failures.
– The PCB designer must minimize the possibility of EMI coupling by keeping any unprotected traces away
from the protected traces which are between the TPD4S311 and the connector.
Route the protected traces as straight as possible.
Eliminate any sharp corners on the protected traces between the TVS and the connector by using rounded
corners with the largest radii possible.
•
•
– Electric fields tend to build up on corners, increasing EMI coupling.
11.2 Layout Example
Figure 11-2. TPD4S311 Bottom Layer Routing
Figure 11-1. TPD4S311 Top Layer Routing
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12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation see the following:
TPD6S300 Evaluation Module User's Guide
TPS65982 USB Type-C and USB PD Controller, Power Switch, and High-Speed Multiplexer
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
12.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.4 Trademarks
USB Type-C™ are trademarks of USB Implementers Forum.
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.6 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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10-Mar-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPD4S311AYBFR
TPD4S311YBFR
ACTIVE
DSBGA
DSBGA
YBF
16
16
3000 RoHS & Green
3000 RoHS & Green
Call TI
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 85
-40 to 85
4S311
A1
ACTIVE
YBF
SAC396
4S311
A0
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Mar-2021
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Mar-2021
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPD4S311AYBFR
TPD4S311YBFR
DSBGA
DSBGA
YBF
YBF
16
16
3000
3000
180.0
180.0
8.4
8.4
1.86
1.86
1.86
1.86
0.62
0.62
4.0
4.0
8.0
8.0
Q1
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Mar-2021
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPD4S311AYBFR
TPD4S311YBFR
DSBGA
DSBGA
YBF
YBF
16
16
3000
3000
182.0
182.0
182.0
182.0
20.0
20.0
Pack Materials-Page 2
PACKAGE OUTLINE
YBF0016
DSBGA - 0.55 mm max height
SCALE 8.000
DIE SIZE BALL GRID ARRAY
A
B
E
BALL A1
CORNER
D
C
0.55 MAX
SEATING PLANE
0.05 C
0.20
0.14
1.2
TYP
D
C
1.2
TYP
SYMM
D: Max = 1.72 mm, Min = 1.66 mm
E: Max = 1.72 mm, Min = 1.66 mm
B
A
0.4 TYP
1
2
3
4
0.27
0.23
16X
SYMM
0.015
C A B
4225494/A 11/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
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EXAMPLE BOARD LAYOUT
YBF0016
DSBGA - 0.55 mm max height
DIE SIZE BALL GRID ARRAY
(0.4) TYP
16X ( 0.23)
3
1
2
4
A
(0.4) TYP
B
C
SYMM
D
SYMM
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 50X
0.05 MIN
0.05 MAX
METAL UNDER
SOLDER MASK
(
0.23)
METAL
(
0.23)
EXPOSED
METAL
SOLDER MASK
OPENING
EXPOSED
METAL
SOLDER MASK
OPENING
SOLDER MASK
DEFINED
NON-SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
NOT TO SCALE
4225494/A 11/2019
NOTES: (continued)
3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.
See Texas Instruments Literature No. SNVA009 (www.ti.com/lit/snva009).
www.ti.com
EXAMPLE STENCIL DESIGN
YBF0016
DSBGA - 0.55 mm max height
DIE SIZE BALL GRID ARRAY
(0.4) TYP
(R0.05) TYP
16X ( 0.25)
1
2
3
4
A
B
(0.4) TYP
SYMM
METAL
TYP
C
D
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
SCALE: 50X
4225494/A 11/2019
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
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