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TPIC1021D

更新时间：2025-07-06 12:27:08

品牌：TI

描述：LIN Physical Interface

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TPIC1021D 概述

LIN Physical Interface LIN物理接口接口芯片网络接口

TPIC1021D 规格参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Not Recommended	零件包装代码：	SOIC
包装说明：	SOIC-8	针数：	8
Reach Compliance Code：	compliant	HTS代码：	8542.39.00.01
Factory Lead Time：	1 week	风险等级：	7.35
Samacsys Confidence：		Samacsys Status：	Released
Samacsys PartID：	292844	Samacsys Pin Count：	8
Samacsys Part Category：	Integrated Circuit	Samacsys Package Category：	Other
Samacsys Footprint Name：	SOIC127P600X175-8N	Samacsys Released Date：	2017-01-12 12:59:53
Is Samacsys：	N	JESD-30 代码：	R-PDSO-G8
JESD-609代码：	e4	长度：	4.9 mm
湿度敏感等级：	1	功能数量：	1
端子数量：	8	收发器数量：	1
最高工作温度：	125 °C	最低工作温度：	-40 °C
封装主体材料：	PLASTIC/EPOXY	封装代码：	SOP
封装形状：	RECTANGULAR	封装形式：	SMALL OUTLINE
峰值回流温度（摄氏度）：	260	认证状态：	Not Qualified
座面最大高度：	1.75 mm	最大压摆率：	2.5 mA
标称供电电压：	14 V	表面贴装：	YES
电信集成电路类型：	INTERFACE CIRCUIT	温度等级：	AUTOMOTIVE
端子面层：	Nickel/Palladium/Gold (Ni/Pd/Au)	端子形式：	GULL WING
端子节距：	1.27 mm	端子位置：	DUAL
处于峰值回流温度下的最长时间：	NOT SPECIFIED	宽度：	3.9 mm
Base Number Matches：	1

TPIC1021D 数据手册

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TPIC1021

LIN Physical Interface

www.ti.com

SLIS113C–OCTOBER 2004–REVISED JULY 2005

FEATURES

•

Dominant State Timeout Protection on TXD

•

LIN Physical Layer Specification Revision 2.0

compliant. Conforms to SAEJ2602

Recommended Practice for LIN

•

Wake-Up Request on RXD Pin

Control of External Voltage Regulator (INH

Pin)

•

LIN Bus Speed up to 20 kbps

ESD Protection to 12 kV (Human Body Model)

on LIN Pin

•

Integrated Pull-Up Resistor and Series Diode

for LIN Slave Applications

•

LIN Pin Handles Voltage from -40 V to +40 V

Low EME (Electromagnetic Emissions), High

EMI (Electromagnetic Immunity)

Survives Transient Damage in Automotive

Environment (ISO 7637)

Bus Terminal Short-Circuit Protected for

Short to Battery or Short to Ground

•

Operation with Supply from 7 V to 27 V DC

•

Thermally Protected

Two Operation Modes: Normal and Low

Power (Sleep) Mode

Ground Disconnection Fail Safe at System

Level

•

Low Current Consumption in Low Power

Mode

•

Ground Shift Operation at System Level

Wake-Up Available from LIN Bus, Wake-Up

Input (External Switch) or Host MCU

Unpowered Node Does Not Disturb the

Network

Interfaces to MCU with 5 V or 3.3 V I/O Pins

D PACKAGE

(TOP VIEW)

RXD

NWake

TXD

INH

SUP

LIN

GND

DESCRIPTION

The TPIC1021 is the LIN (Local Interconnect Network) physical interface, which integrates the serial transceiver

with wake up and protection features. The LIN bus is a single wire, bi-directional bus typically used for low-speed

in-vehicle networks using baud rates between 2.4 kbps and 20 kbps.

The LIN bus has two logical values: the dominant state (voltage near ground) represents a logic ‘0’ and the

recessive state (voltage near battery) and represents logic ‘1’.

In the recessive state the LIN bus is pulled high by the TPIC1021’s internal pull-up resistor (30kΩ) and series

diode, so no external pull-up components are required for slave applications. Master applications require an

external pull-up resistor (1kΩ) plus a series diode.

The LIN Protocol output data stream on the TXD pin is converted by the TPIC1021 into the LIN bus signal

through a current limited, wave-shaping low-side driver with control as outlined by the LIN Physical Layer

Specification Revision 2.0. The receiver converts the data stream from the LIN bus and outputs the data stream

via the RXD pin.

In Low Power mode, the TPIC1021 requires very low quiescent current even though the wake-up circuits remain

active allowing for remote wake up via the LIN bus or local wake ups via NWake or EN pins.

The TPIC1021 has been designed for operation in the harsh automotive environment. The device can handle LIN

bus voltage swing from +40 V down to ground and survive -40 V. The device also prevents back feed current

through the LIN pin to the supply input in case of a ground shift or supply voltage disconnection. It also features

under-voltage, over temperature, and loss of ground protection. In the event of a fault condition the output is

immediately switched off and remains off until the fault condition is removed.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

TPIC1021

LIN Physical Interface

www.ti.com

SLIS113C–OCTOBER 2004–REVISED JULY 2005

TERMINAL FUNCTIONS

Terminal Assignments

PIN NAME

RXD

PIN NO.

PIN TYPE

DESCRIPTION

RXD output (open drain) pin interface reporting state of LIN bus voltage

Enable input pin

NWake

TXD

GND

LIN

High voltage input pin for device wake up

TXD input pin interface to control state of LIN output

Ground connection

I/O

LIN bus pin single wire transmitter and receiver

V_SUP

INH

Supply

Device supply pin (connected to battery in series with external reverse blocking diode)

Inhibit pin controls external voltage regulator with inhibit input

LIN Bus Pin

This I/O pin is the single-wire LIN bus transmitter and receiver.

Transmitter Characteristics

The driver is a low side transistor with internal current limitation and thermal shutdown. There is an internal

30-kΩ pull-up resistor with a serial diode structure to V_supso no external pull-up components are required for LIN

slave mode applications. An external pull-up resistor of 1 kΩ plus a series diode to V_supmust be added when the

device is used for master node applications.

Voltage on the LIN pin can go from -40 V to +40 V DC without any currents other than through the pull-up

resistance. There are no reverse currents from the LIN bus to supply (V_sup), even in the event of a ground shift or

loss of supply (V_sup).

The LIN thresholds and ac parameters are compatible LIN Protocol Specification Revision 2.0.

During a thermal shut down condition the driver is disabled.

Receiver Characteristics

The receiver’s characteristic thresholds are ratio-metric with the device supply pin. Typical thresholds are 50%,

with a hysteresis between 5% and 17.5% of supply.

Transmit Input Pin (TXD)

This pin is the interface to the MCU’s LIN Protocol Controller or SCI/UART used to control the state of the LIN

output. When TXD is low, LIN output is dominant (near ground). When TXD is high, LIN output is recessive (near

battery). TXD input structure is compatible with microcontrollers with 3.3 V and 5.0 V I/O. This pin has an internal

pull-down resistor.

TXD Dominant State Timeout

If the TXD pin is inadvertently driven permanently low by a hardware or software application failure, the LIN bus

is protected by TPIC1021’s Dominant State Timeout Timer. This timer is triggered by a falling edge on the TXD

pin. If the low signal remains on the TXD pin for longer than t_DST, the transmitter is disabled thus allowing the LIN

bus to return to the recessive state and communication to resume on the bus. The timer is reset by a rising edge

on TXD pin.

Receive Output Pin (RXD)

This pin is the interface to the MCU’s LIN Protocol Controller or SCI/UART, which reports the state of the LIN

bus voltage. LIN recessive (near battery) is represented by a high level on RXD and LIN dominant (near ground)

is represented by a low level on RXD. The RXD output structure is an open-drain output stage. This allows the

TPIC1021 to be used with 3.3 V and 5 V I/O microcontrollers. If the microcontroller’s RXD pin does not have an

integrated pull-up, an external pull-up resistor to the microcontroller I/O supply voltage is required.

TPIC1021

LIN Physical Interface

www.ti.com

SLIS113C–OCTOBER 2004–REVISED JULY 2005

RXD Wake-up Request

When the TPIC1021 has been in low power mode and encounters a wake-up event from the LIN bus or NWake

pin the RXD pin will go LOW while the device enters and remains in Standby Mode (until EN is re-asserted high

and the device enters Normal Mode).

Supply Voltage (V_SUP

)

The TPIC1021 device power supply pin. This pin is connected to the battery through an external reverse battery

blocking diode. The continuous DC operating voltage range for the TPIC1021 is from 7 V to +27 V. The V_SUPis

protected to for harsh automotive conditions of up to + 40 V.

The device contains a reset circuit to avoid false bus messages during under-voltage conditions when V_SUPis

less than V_{SUP_UNDER}

Ground (GND)

TPIC1021 device ground connection. The TPIC1021 can operate with a ground shift as long as the ground shift

does not reduce V_SUPbelow the minimum operating voltage. If there is a loss of ground at the ECU level, the

TPIC1021 will not have a significant current consumption on the LIN pin while in the recessive state (<100 µA

sourced via the LIN pin) and for the dominant state the pull-up resistor should be active.

Enable Input Pin (EN)

The enable input pin controls the operation mode of the TPIC1021 (Normal or Low Power Mode). When enable

is high, the TPIC1021 is in normal mode allowing a transmission path from TXD to LIN and from LIN to RXD.

When the enable input is low, the device is put into low power (sleep) mode and there are no transmission paths.

The device can enter normal operating mode only after being woken up. The enable pin has an internal

pull-down resistor to ensure the device remains in low power mode even if the enable pin floats.

NWake Input Pin (NWake)

The NWake input pin is a high-voltage input used to wake up the TPIC1021 from low power mode. NWake is

usually connected to an external switch in the application. A falling edge on NWake with a low that is asserted

longer than the filter time (t_NWAKE) results in a local wake-up. The NWake pin provides an internal pull-up current

source to V_SUP

Inhibit Output Pin (INH)

The inhibit output pin is used to control an external voltage regulator that has an inhibit input. When the

TPIC1021 is in normal operating mode, the inhibit high-side switch is enabled and the external voltage regulator

is activated. When TPIC1021 is in low power mode, the inhibit switch is turned off, which disables the voltage

regulator. A wake-up event on for the TPIC1021 will return the INH pin to V_SUPlevel. The INH pin output current

is limited to 2 mA. The INH pin can also drive an external transistor connected to an MCU interrupt input.

TPIC1021

LIN Physical Interface

www.ti.com

SLIS113C–OCTOBER 2004–REVISED JULY 2005

Functional Block Diagram

INH

V_SUP

RXD

V_SUP/2

Receiver

Wake−Up

and

Filter

Vreg Control

Filter

NWake

Fault

Detection and

Protection

Dominant

State

Timeout

LIN

GND

Driver

TXD

with

Slope Control

OPERATING STATES

Unpowered

System

A: V

B: V

C:V

< V

> V

SUP

SUP_under

, EN = 0

SUP_unde

< V

SUP_under

SUP

> V

, EN = 1

SUP_unde

Standby

Mode

TXD: off

RXD: LOW

IHN: HIGH (high

side switched on)

Term: 30 kW

EN = 1

LIN Bus Wake−UP

NWake Pin Wake−Up

Low Power

Normal Mode

TXD: on

Mode

TXD: off

RXD: LIN bus data

IHN: HIGH (high

side switched on)

Term: 30 kW

RXD: floating

IHN: high

impedance (high

side switched off)

Term: highW

EN = 0

EN = 1

Figure 1. Operating States Diagram

TPIC1021

LIN Physical Interface

www.ti.com

SLIS113C–OCTOBER 2004–REVISED JULY 2005

OPERATING STATES (continued)

Operating Modes

MODE

RXD

Floating

LIN BUS

INH

TRANSMITTER

Off

COMMENTS

TERMINATION

High impedance

30 kΩ (typical)

Low Power

Standby

High impedance

High

Low

Off

Wake-up event detected,

waiting on MCU to set EN

Normal

LIN bus data

30 kΩ (typical)

High

Normal Mode

This is the normal operational mode where the receiver and driver are active. The receiver detects the data

stream on the LIN bus and outputs it on the RXD pin for the LIN controller where recessive on the LIN bus is a

digital high and dominate on the LIN bus is digital low. The driver will transmit input data on the TXD pin to the

LIN bus.

Low Power Mode

The power saving mode for the TPIC1021 and the default state after power-up (assuming EN=0). Even with the

extremely low current consumption in this mode, the TPIC1021 can still wake-up from LIN bus activity, a falling

edge on the NWake pin or if EN is set high. The LIN bus and NWake pins are filtered to prevent false wake-up

events. The wake-up events must be active for their respective time periods: t_LINBUS, t_NWake

The low power mode is entered by setting the EN pin low.

While the device is in low power mode the following conditions exist:

•

The LIN bus driver is disabled and the internal LIN bus termination is switched off (to minimize power loss if

LIN is short-circuited to ground).

•

The normal receiver is disabled.

The INH pin is high impedance.

EN input, NWake input and the LIN wake-up receiver are active.

Wake-Up Events

There are three ways to wake-up the TPIC1021 from Low Power Mode.

•

Remote wake-up via recessive (high) to dominant (low) state transition on LIN Bus where dominant bus state

of 50% threshold is detected. The dominant state must be held for t_LINBUSfilter time (to eliminate false wake

ups from disturbances on the LIN Bus).

•

Local wake-up via falling edge on NWake pin which is held low for filter time t_NWake(to eliminate false wake

ups from disturbances on NWake).

Local wake-up via EN being set high

Standby Mode

This mode is entered whenever a wake-up event occurs via the LIN bus or NWake pin while the TPIC1021 is in

low power mode. The LIN bus slave termination circuit and the INH pin are turned on when standby mode is

entered. The application system will power up once the INH pin is turn assuming it is using a voltage regulator

connected via INH pin. Standby Mode is signaled via a low level on RXD pin.

When EN pin is set high while the TPIC1021 is in Standby Mode the device returns to Normal Mode and the

normal transmission paths from TXD to LIN bus and LIN bus to RXD are turned on.

TPIC1021

LIN Physical Interface

www.ti.com

SLIS113C–OCTOBER 2004–REVISED JULY 2005

LIN

LINBUS

SUP

INH

High Impedance

System Wake−Up Time (Vreg + MCU)

Floating

RXD

Low Power

Standby

Normal

MODE

Figure 2. Wake-Up Via LIN Bus Timing Diagram

Falling Edge on NWake

NWake

SUP

INH

High Impedance

System Wake−Up Time (Vreg + MCU)

Floating

RXD

Low Power

Standby

Normal

MODE

Figure 3. Wake-Up Via NWake Timing Diagram

TPIC1021

LIN Physical Interface

www.ti.com

SLIS113C–OCTOBER 2004–REVISED JULY 2005

ABSOLUTE MAXIMUM RATINGS⁽¹⁾

over operating free-air temperature range (unless otherwise noted)

PARAMETER

RATING

0 to 27

UNIT

(2)

V_SUP

Supply line supply voltage (continuous)

Supply line supply voltage (transient)

0 to 40

NWake DC and transient input voltage (through 33-kΩ serial resistor)

Logic pin input voltage (RXD, TXD, EN)

LIN DC input voltage

Electrostatic discharge: Human Body Model: LIN pin⁽³⁾

Electrostatic discharge: Human Body Model: NWake pin⁽³⁾

Electrostatic discharge: Human Body Model: All other pins⁽³⁾

Electrostatic discharge: Machine Model: LIN and NWake pins⁽⁴⁾

Electrostatic discharge: Machine Model: All other pins⁽⁴⁾

Operational free-air temperature

-1 to 40

-0.3 to 5.5

-40 to 40

-12 to 12

-9 to 9

-3 to 3

-400 to 400

-200 to 200

-40 to 125

-40 to 150

-40 to 165

145

T_A

°C

°C/W

°C

T_J

Junction temperature

T_stg

R_θJA

Storage temperature

Thermal resistance, junction-to-ambient

Thermal shutdown

200

Thermal shutdown hysteresis

(1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings

only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating

conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltage values are with respect to GND.

(3) The human body model is a 100-pF capacitor discharged through a 1.5-kΩ resistor into each pin.

(4) The machine model is a 200-pF capacitor through a 10-Ω resistor and a 0.75-µH coil.

TPIC1021

LIN Physical Interface

www.ti.com

SLIS113C–OCTOBER 2004–REVISED JULY 2005

ELECTRICAL CHARACTERISTICS

V_SUP= 7 V to 27 V, T_A= -40°C to 125°C (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP⁽¹⁾

MAX

UNIT

SUPPLY

Operational supply voltage⁽²⁾

Nominal supply line voltage⁽²⁾

V_SUPundervoltage threshold⁽²⁾

Supply Current

4.5

1.2

I_CC

Normal Mode, EN = 1, Bus domi-

2.5

2.1

500

nant (total bus load > 500 Ω)⁽³⁾

Standby Mode, EN = 0, Bus domi-

300

µA

nant (total bus load > 500 Ω)⁽³⁾

Normal Mode, EN = 1, Bus recess-

ive

Standby Mode, EN = 0, Bus recess-

ive

Low Power Mode, EN = 0, V_SUP

14 V, NWake = V_SUP, LIN = V_SUP

Low Power Mode, EN = 0, 14 V <

V_SUP< 27 V, NWake = V_SUP, LIN =

V_SUP

100

RXD OUTPUT PIN

V_O

I_OL

I_IKG

Output voltage

Low-level output current, open drain LIN = 0 V, RXD = 0.4 V

Leakage current, high-level LIN = V_SUP, RXD = 5 V

-0.3

3.5

-5

5.5

µA

TXD INPUT PIN

V_IL

V_IH

V_IT

Low-level input voltage⁽²⁾

-0.3

0.8

5.5

500

800

High-level input voltage⁽²⁾

Input threshold hysteresis voltage⁽²⁾

Pull-down resistor

125

-5

kΩ

µA

350

I_IL

Low-level input current

TXD = 0

LIN PIN (Referenced to V_SUP

)

V_OH

High-level output voltage⁽²⁾

LIN recessive, TXD = High, I_O= 0

V_SUP-1V

V_OL

Low-level output voltage⁽²⁾

LIN dominant, TXD = Low, I_O= 40

0.2×V_SUP

Pull-up resistor to V_SUP

Limiting current

150

250

kΩ

µA

I_L

TXD = Low

LIN = V_SUP

I_IKG

V_IL

V_IH

V_IT

V_hys

V_IL

Leakage current

-5

Low-level input voltage⁽²⁾

High-level input voltage⁽²⁾

Input threshold voltage⁽²⁾

Hysteresis voltage⁽²⁾

LIN dominant

LIN recessive

0×V_SUP

0.6×V_SUP

0.4×V_SUP

0.05×V_SUP

0.4×V_SUP

V_SUP

0.5×V_SUP

0.6×V_SUP

0.175×V_SUP

0.4×V_SUP

Low-level input voltage for

wake-up⁽²⁾

EN PIN

V_IL

Low-level input voltage⁽²⁾

High-level input voltage⁽²⁾

Hysteresis voltage⁽²⁾

-0.3

0.8

5.5

V_IH

V_hys

500

(1) Typical values are give for V_SUP= 14 V at 25°C.

(2) All voltages are defined with respect to ground; positive currents flow into the TPIC1021 device.

(3) In the dominant state the supply current increases as the supply voltage increases due to the integrated LIN slave termination

resistance. At higher voltages the majority of supply current is through the termination resistance. The minimum resistance of the LIN

slave termination is 20 kΩ so the maximum supply current attributed to the termination is: I_{SUP (dom) max termination}≈ (V_SUP

(V_{LIN_Dominant}+0.7V) / 20 kΩ.

–

TPIC1021

LIN Physical Interface

www.ti.com

SLIS113C–OCTOBER 2004–REVISED JULY 2005

ELECTRICAL CHARACTERISTICS (continued)

V_SUP= 7 V to 27 V, T_A= -40°C to 125°C (unless otherwise noted)

PARAMETER

Pull-down resistor

TEST CONDITIONS

MIN

125

-5

TYP⁽¹⁾

350

MAX

800

UNIT

kΩ

I_IL

Low-level input current

EN = 0 V

µA

INH PIN

V_o

DC output voltage

Ouptut current

Transient voltage

-0.3

-50

V_SUP+0.3

Ω

I_O

R_on

On state resistance

Between V_SUPand INH, INH = 2 mA

drive, Normal or Standby Mode

100

I_IKG

Leakage current

Low Power mode, 0 < INH < V_SUP

-5

µA

NWake PIN

(4)

V_IL

V_IH

Low-level input voltage

-0.3

V_SUP-1

-40

V_SUP-3.3

High-level input voltage⁽⁴⁾

V_SUP+0.3

Pull-up current

NWake = 0 V

-10

-4

µA

I_IKG

Leakage current

V_SUP= NWake

-5

THERMAL SHUTDOWN

Shutdown junction thermal tempera-

185

°C

ture

AC CHARACTERISTICS

Duty cycle 1⁽⁵⁾⁽⁶⁾

TH_REC(max)= 0.744×V_SUP

TH_DOM(max)= 0.581×V_SUP, V_SUP

7.0 V to 18 V, t_BIT= 50 µs (20 kbps),

See Figure 4

0.396

0.417

Duty cycle 2⁽⁵⁾⁽⁶⁾

Duty cycle 3⁽⁵⁾⁽⁶⁾

Duty cycle 4⁽⁵⁾⁽⁶⁾

TH_REC(max)= 0.284×V_SUP

TH_DOM(max)= 0.422×V_SUP, V_SUP

7.6 V to 18 V, t_BIT= 50 µs (20 kbps),

See Figure 4

0.581

0.590

TH_REC(max)= 0.778×V_SUP

TH_DOM(max)= 0.616×V_SUP, V_SUP

7.0 V to 18 V, t_BIT= 96 µs (10.4

kbps), See Figure 4

TH_REC(max)= 0.251×V_SUP

TH_DOM(max)= 0.389×V_SUP, V_SUP

7.6 V to 18 V, t_BIT= 96 µs (10.4

kbps), See Figure 4

t_{rx_pdr}

t_{rx_pdf}

t_{rx_sym}

Receiver rising propagation delay

time

R_L= 2.4 kΩ, C_L= 20 pF, See

Figure 4

µs

Receiver falling propagation delay

time

R_L= 2.4 kΩ, C_L= 20 pF, See

Figure 4

Symmetry of receiver propagation

delay time (rising edge)

wrt falling edge, See Figure 4

-2

t_NWake

t_LINBUS

NWake filter time for local wake-up

See Figure 4

100

µs

LIN wake-up filter time (dominant

time for wake-up via LIN bus)

t_DST

Dominant state timeout⁽⁷⁾

See Figure 4

(4) All voltages are defined with respect to ground; positive currents flow into the TPIC1021 device.

(5) Duty cycle = t_{BUS_rec(min)}/ (2×t_BIT

)

(6) Duty Cycles: LIN Driver bus load conditions (CLINBUS, RLINBUS): Load1 = 1 nF, 1 kΩ; Load2 = 6.8 nF, 660 Ω; Load3 = 10 nF, 500 Ω.

Duty Cycles 3 and 4 are defined for 10.4 kbps operation. The TPIC1021 also meets these lower speed requirements, while it is capable

of of the higher speed 20.0 kbps operation as specified by Duty Cycles 1 and 2. SAEJ2602 derives propagation delay equations from

the LIN 2.0 duty cycle definitions, for details please refer to the SAEJ2602 specification.

(7) Dominant state timeout will limit the minimum data rate to 2.4 kbps.

TPIC1021

LIN Physical Interface

www.ti.com

SLIS113C–OCTOBER 2004–REVISED JULY 2005

TIMING DIAGRAMS

t_Bit

RECESSIVE

DOMINANT

TXD (Input)

t_{Bus_dom(max)}

t_{Bus_rec(min)}

TH_Rec(max)

Thresholds of

receiving node 1

TH_Dom(max)

V_SUP

(Transceiver supply

of transmitting node)

LIN Bus Signal

Thresholds of

receiving node 2

TH_Rec(min)

TH_Dom(min)

t_{Bus_dom(min)}

t_{Bus_rec(max)}

RXD

(Output of receiving node 1)

t_{rx_pdf(1)}

t_{rx_pdr(1)}

RXD

(Output of receiving node 2)

t_{rx_pdf(2)}

t_{rx_pdr(2)}

Figure 4. Definition of Bus Timing Parameters

TPIC1021

LIN Physical Interface

www.ti.com

SLIS113C–OCTOBER 2004–REVISED JULY 2005

APPLICATION INFORMATION

BAT

SUP

TPIC7xxxx

MASTER

NODE

SUP

NWake

INH

Master Node

Pull−Up

SUP

MCU w/o

pull−up

1 kΩ

I/O

MCU

TPIC1021

TMS430

TMS470

LIN

Controller

LIN

RXD

TXD

220 pF

SCI/UART

bat

GND

SLAVE

NODE

SUP

TPIC7xxxx

SUP

NWake

INH

SUP

MCU w/o

pull−up

I/O

MCU

TPIC1021

TMS430

TMS470

LIN

Controller

LIN

RXD

TXD

220 pF

SCI/UART

GND

(1) RXD on MCU or LIN Slave has internal pull-up, no external pull-up resistor is needed.

(2) RXD on MCU or LIN Slave without internal pull-up, requires external pull-up resistor.

(3) Master Node applications require an external 1-kΩ pull-up resistor and serial diode.

Figure 5.

PACKAGE OPTION ADDENDUM

www.ti.com

24-Jan-2013

PACKAGING INFORMATION

Orderable Device

TPIC1021D

Status Package Type Package Pins Package Qty

Eco Plan Lead/Ball Finish

MSL Peak Temp

Op Temp (°C)

Top-Side Markings

Samples

Drawing

(1)

(2)

(3)

(4)

ACTIVE

SOIC

Green (RoHS

& no Sb/Br)

CU NIPDAU

Level-1-260C-UNLIM

-40 to 125 T1021

T1021

TPIC1021DG4

TPIC1021DR

ACTIVE

Green (RoHS

& no Sb/Br)

2500

Green (RoHS

& no Sb/Br)

-40 to 125 T1021

T1021

TPIC1021DRG4

Green (RoHS

& no Sb/Br)

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that

lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between

the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight

in homogeneous material)

⁽³⁾MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾Only one of markings shown within the brackets will appear on the physical device.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

24-Jan-2013

Addendum-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

14-Mar-2013

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

TPIC1021DR

SOIC

2500

330.0

12.4

6.4

5.2

2.1

8.0

12.0

TPIC1021DRG4

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

14-Mar-2013

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

TPIC1021DR

SOIC

2500

367.0

35.0

TPIC1021DRG4

Pack Materials-Page 2

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TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms

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TPIC1021D CAD模型

原理图符号

PCB 封装图

TPIC1021D 替代型号

型号	制造商	描述	替代类型	文档
TPIC1021DR	TI	LIN Physical Interface	完全替代
TPIC1021DRG4	TI	LIN Physical Interface	完全替代
TPIC1021AQDRQ1	TI	LIN PHYSICAL INTERFACE	完全替代

TPIC1021D 相关器件

型号	制造商	描述	价格	文档
TPIC1021DG4	TI	LIN Physical Interface	获取价格
TPIC1021DR	TI	LIN Physical Interface	获取价格
TPIC1021DRG4	TI	LIN Physical Interface	获取价格
TPIC1301	TI	3-HALF H-BRIDGE GATE-PROTECTED POWER DMOS ARRAY	获取价格
TPIC1301DW	TI	3-HALF H-BRIDGE GATE-PROTECTED POWER DMOS ARRAY	获取价格
TPIC1301DWR	TI	2.25A, 60V, 0.275ohm, 6 CHANNEL, N-CHANNEL, Si, POWER, MOSFET, MS-013AD, PLASTIC, SOIC-24	获取价格
TPIC1310	TI	3-HALF H-BRIDGE GATE PROTECTED POWER DMOS ARRAY	获取价格
TPIC1310KTR	TI	3-HALF H-BRIDGE GATE PROTECTED POWER DMOS ARRAY	获取价格
TPIC1310KTS	TI	3-HALF H-BRIDGE GATE PROTECTED POWER DMOS ARRAY	获取价格
TPIC1321L	TI	3-HALF H-BRIDGE GATE-PROTECTED LOGIC-LEVEL POWER DMOS ARRAY	获取价格