TPIC1021D

更新时间:2025-07-06 12:27:08
品牌:TI
描述:LIN Physical Interface

TPIC1021D 概述

LIN Physical Interface LIN物理接口 接口芯片 网络接口

TPIC1021D 规格参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Not Recommended零件包装代码:SOIC
包装说明:SOIC-8针数:8
Reach Compliance Code:compliantHTS代码:8542.39.00.01
Factory Lead Time:1 week风险等级:7.35
Samacsys Confidence:Samacsys Status:Released
Samacsys PartID:292844Samacsys Pin Count:8
Samacsys Part Category:Integrated CircuitSamacsys Package Category:Other
Samacsys Footprint Name:SOIC127P600X175-8NSamacsys Released Date:2017-01-12 12:59:53
Is Samacsys:NJESD-30 代码:R-PDSO-G8
JESD-609代码:e4长度:4.9 mm
湿度敏感等级:1功能数量:1
端子数量:8收发器数量:1
最高工作温度:125 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
峰值回流温度(摄氏度):260认证状态:Not Qualified
座面最大高度:1.75 mm最大压摆率:2.5 mA
标称供电电压:14 V表面贴装:YES
电信集成电路类型:INTERFACE CIRCUIT温度等级:AUTOMOTIVE
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:3.9 mm
Base Number Matches:1

TPIC1021D 数据手册

通过下载TPIC1021D数据手册来全面了解它。这个PDF文档包含了所有必要的细节,如产品概述、功能特性、引脚定义、引脚排列图等信息。

PDF下载
TPIC1021  
LIN Physical Interface  
www.ti.com  
SLIS113COCTOBER 2004REVISED JULY 2005  
FEATURES  
Dominant State Timeout Protection on TXD  
Pin  
LIN Physical Layer Specification Revision 2.0  
compliant. Conforms to SAEJ2602  
Recommended Practice for LIN  
Wake-Up Request on RXD Pin  
Control of External Voltage Regulator (INH  
Pin)  
LIN Bus Speed up to 20 kbps  
ESD Protection to 12 kV (Human Body Model)  
on LIN Pin  
Integrated Pull-Up Resistor and Series Diode  
for LIN Slave Applications  
LIN Pin Handles Voltage from -40 V to +40 V  
Low EME (Electromagnetic Emissions), High  
EMI (Electromagnetic Immunity)  
Survives Transient Damage in Automotive  
Environment (ISO 7637)  
Bus Terminal Short-Circuit Protected for  
Short to Battery or Short to Ground  
Operation with Supply from 7 V to 27 V DC  
Thermally Protected  
Two Operation Modes: Normal and Low  
Power (Sleep) Mode  
Ground Disconnection Fail Safe at System  
Level  
Low Current Consumption in Low Power  
Mode  
Ground Shift Operation at System Level  
Wake-Up Available from LIN Bus, Wake-Up  
Input (External Switch) or Host MCU  
Unpowered Node Does Not Disturb the  
Network  
Interfaces to MCU with 5 V or 3.3 V I/O Pins  
D PACKAGE  
(TOP VIEW)  
RXD  
EN  
NWake  
TXD  
INH  
1
2
3
4
8
7
6
5
V
SUP  
LIN  
GND  
DESCRIPTION  
The TPIC1021 is the LIN (Local Interconnect Network) physical interface, which integrates the serial transceiver  
with wake up and protection features. The LIN bus is a single wire, bi-directional bus typically used for low-speed  
in-vehicle networks using baud rates between 2.4 kbps and 20 kbps.  
The LIN bus has two logical values: the dominant state (voltage near ground) represents a logic ‘0’ and the  
recessive state (voltage near battery) and represents logic ‘1’.  
In the recessive state the LIN bus is pulled high by the TPIC1021’s internal pull-up resistor (30k) and series  
diode, so no external pull-up components are required for slave applications. Master applications require an  
external pull-up resistor (1k) plus a series diode.  
The LIN Protocol output data stream on the TXD pin is converted by the TPIC1021 into the LIN bus signal  
through a current limited, wave-shaping low-side driver with control as outlined by the LIN Physical Layer  
Specification Revision 2.0. The receiver converts the data stream from the LIN bus and outputs the data stream  
via the RXD pin.  
In Low Power mode, the TPIC1021 requires very low quiescent current even though the wake-up circuits remain  
active allowing for remote wake up via the LIN bus or local wake ups via NWake or EN pins.  
The TPIC1021 has been designed for operation in the harsh automotive environment. The device can handle LIN  
bus voltage swing from +40 V down to ground and survive -40 V. The device also prevents back feed current  
through the LIN pin to the supply input in case of a ground shift or supply voltage disconnection. It also features  
under-voltage, over temperature, and loss of ground protection. In the event of a fault condition the output is  
immediately switched off and remains off until the fault condition is removed.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
PRODUCTION DATA information is current as of publication date.  
Copyright © 2004–2005, Texas Instruments Incorporated  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
TPIC1021  
LIN Physical Interface  
www.ti.com  
SLIS113COCTOBER 2004REVISED JULY 2005  
TERMINAL FUNCTIONS  
Terminal Assignments  
PIN NAME  
RXD  
PIN NO.  
PIN TYPE  
DESCRIPTION  
1
2
3
4
5
6
7
8
O
RXD output (open drain) pin interface reporting state of LIN bus voltage  
Enable input pin  
EN  
I
NWake  
TXD  
GND  
LIN  
I
High voltage input pin for device wake up  
TXD input pin interface to control state of LIN output  
Ground connection  
I
I
I/O  
LIN bus pin single wire transmitter and receiver  
VSUP  
INH  
Supply  
O
Device supply pin (connected to battery in series with external reverse blocking diode)  
Inhibit pin controls external voltage regulator with inhibit input  
LIN Bus Pin  
This I/O pin is the single-wire LIN bus transmitter and receiver.  
Transmitter Characteristics  
The driver is a low side transistor with internal current limitation and thermal shutdown. There is an internal  
30-kpull-up resistor with a serial diode structure to Vsup so no external pull-up components are required for LIN  
slave mode applications. An external pull-up resistor of 1 kplus a series diode to Vsup must be added when the  
device is used for master node applications.  
Voltage on the LIN pin can go from -40 V to +40 V DC without any currents other than through the pull-up  
resistance. There are no reverse currents from the LIN bus to supply (Vsup), even in the event of a ground shift or  
loss of supply (Vsup).  
The LIN thresholds and ac parameters are compatible LIN Protocol Specification Revision 2.0.  
During a thermal shut down condition the driver is disabled.  
Receiver Characteristics  
The receiver’s characteristic thresholds are ratio-metric with the device supply pin. Typical thresholds are 50%,  
with a hysteresis between 5% and 17.5% of supply.  
Transmit Input Pin (TXD)  
This pin is the interface to the MCU’s LIN Protocol Controller or SCI/UART used to control the state of the LIN  
output. When TXD is low, LIN output is dominant (near ground). When TXD is high, LIN output is recessive (near  
battery). TXD input structure is compatible with microcontrollers with 3.3 V and 5.0 V I/O. This pin has an internal  
pull-down resistor.  
TXD Dominant State Timeout  
If the TXD pin is inadvertently driven permanently low by a hardware or software application failure, the LIN bus  
is protected by TPIC1021’s Dominant State Timeout Timer. This timer is triggered by a falling edge on the TXD  
pin. If the low signal remains on the TXD pin for longer than tDST, the transmitter is disabled thus allowing the LIN  
bus to return to the recessive state and communication to resume on the bus. The timer is reset by a rising edge  
on TXD pin.  
Receive Output Pin (RXD)  
This pin is the interface to the MCU’s LIN Protocol Controller or SCI/UART, which reports the state of the LIN  
bus voltage. LIN recessive (near battery) is represented by a high level on RXD and LIN dominant (near ground)  
is represented by a low level on RXD. The RXD output structure is an open-drain output stage. This allows the  
TPIC1021 to be used with 3.3 V and 5 V I/O microcontrollers. If the microcontroller’s RXD pin does not have an  
integrated pull-up, an external pull-up resistor to the microcontroller I/O supply voltage is required.  
2
TPIC1021  
LIN Physical Interface  
www.ti.com  
SLIS113COCTOBER 2004REVISED JULY 2005  
RXD Wake-up Request  
When the TPIC1021 has been in low power mode and encounters a wake-up event from the LIN bus or NWake  
pin the RXD pin will go LOW while the device enters and remains in Standby Mode (until EN is re-asserted high  
and the device enters Normal Mode).  
Supply Voltage (VSUP  
)
The TPIC1021 device power supply pin. This pin is connected to the battery through an external reverse battery  
blocking diode. The continuous DC operating voltage range for the TPIC1021 is from 7 V to +27 V. The VSUP is  
protected to for harsh automotive conditions of up to + 40 V.  
The device contains a reset circuit to avoid false bus messages during under-voltage conditions when VSUP is  
less than VSUP_UNDER  
.
Ground (GND)  
TPIC1021 device ground connection. The TPIC1021 can operate with a ground shift as long as the ground shift  
does not reduce VSUP below the minimum operating voltage. If there is a loss of ground at the ECU level, the  
TPIC1021 will not have a significant current consumption on the LIN pin while in the recessive state (<100 µA  
sourced via the LIN pin) and for the dominant state the pull-up resistor should be active.  
Enable Input Pin (EN)  
The enable input pin controls the operation mode of the TPIC1021 (Normal or Low Power Mode). When enable  
is high, the TPIC1021 is in normal mode allowing a transmission path from TXD to LIN and from LIN to RXD.  
When the enable input is low, the device is put into low power (sleep) mode and there are no transmission paths.  
The device can enter normal operating mode only after being woken up. The enable pin has an internal  
pull-down resistor to ensure the device remains in low power mode even if the enable pin floats.  
NWake Input Pin (NWake)  
The NWake input pin is a high-voltage input used to wake up the TPIC1021 from low power mode. NWake is  
usually connected to an external switch in the application. A falling edge on NWake with a low that is asserted  
longer than the filter time (tNWAKE) results in a local wake-up. The NWake pin provides an internal pull-up current  
source to VSUP  
.
Inhibit Output Pin (INH)  
The inhibit output pin is used to control an external voltage regulator that has an inhibit input. When the  
TPIC1021 is in normal operating mode, the inhibit high-side switch is enabled and the external voltage regulator  
is activated. When TPIC1021 is in low power mode, the inhibit switch is turned off, which disables the voltage  
regulator. A wake-up event on for the TPIC1021 will return the INH pin to VSUP level. The INH pin output current  
is limited to 2 mA. The INH pin can also drive an external transistor connected to an MCU interrupt input.  
3
TPIC1021  
LIN Physical Interface  
www.ti.com  
SLIS113COCTOBER 2004REVISED JULY 2005  
Functional Block Diagram  
8
7
INH  
VSUP  
1
RXD  
VSUP/2  
Receiver  
2
EN  
Wake−Up  
and  
Filter  
Vreg Control  
3
Filter  
NWake  
Fault  
Detection and  
Protection  
6
5
Dominant  
State  
Timeout  
LIN  
GND  
4
Driver  
TXD  
with  
Slope Control  
OPERATING STATES  
Unpowered  
System  
A: V  
B: V  
C:V  
< V  
> V  
SUP  
SUP  
SUP  
SUP_under  
, EN = 0  
SUP_unde  
V
< V  
SUP_under  
SUP  
> V  
, EN = 1  
SUP_unde  
A
A
A
Standby  
Mode  
TXD: off  
C
B
RXD: LOW  
IHN: HIGH (high  
side switched on)  
Term: 30 kW  
EN = 1  
LIN Bus Wake−UP  
or  
NWake Pin Wake−Up  
Low Power  
Normal Mode  
TXD: on  
Mode  
TXD: off  
RXD: LIN bus data  
IHN: HIGH (high  
side switched on)  
Term: 30 kW  
RXD: floating  
IHN: high  
impedance (high  
side switched off)  
Term: highW  
EN = 0  
EN = 1  
Figure 1. Operating States Diagram  
4
TPIC1021  
LIN Physical Interface  
www.ti.com  
SLIS113COCTOBER 2004REVISED JULY 2005  
OPERATING STATES (continued)  
Operating Modes  
MODE  
EN  
RXD  
Floating  
LIN BUS  
INH  
TRANSMITTER  
Off  
COMMENTS  
TERMINATION  
High impedance  
30 k(typical)  
Low Power  
Standby  
0
0
High impedance  
High  
Low  
Off  
Wake-up event detected,  
waiting on MCU to set EN  
Normal  
1
LIN bus data  
30 k(typical)  
High  
On  
Normal Mode  
This is the normal operational mode where the receiver and driver are active. The receiver detects the data  
stream on the LIN bus and outputs it on the RXD pin for the LIN controller where recessive on the LIN bus is a  
digital high and dominate on the LIN bus is digital low. The driver will transmit input data on the TXD pin to the  
LIN bus.  
Low Power Mode  
The power saving mode for the TPIC1021 and the default state after power-up (assuming EN=0). Even with the  
extremely low current consumption in this mode, the TPIC1021 can still wake-up from LIN bus activity, a falling  
edge on the NWake pin or if EN is set high. The LIN bus and NWake pins are filtered to prevent false wake-up  
events. The wake-up events must be active for their respective time periods: tLINBUS, tNWake  
.
The low power mode is entered by setting the EN pin low.  
While the device is in low power mode the following conditions exist:  
The LIN bus driver is disabled and the internal LIN bus termination is switched off (to minimize power loss if  
LIN is short-circuited to ground).  
The normal receiver is disabled.  
The INH pin is high impedance.  
EN input, NWake input and the LIN wake-up receiver are active.  
Wake-Up Events  
There are three ways to wake-up the TPIC1021 from Low Power Mode.  
Remote wake-up via recessive (high) to dominant (low) state transition on LIN Bus where dominant bus state  
of 50% threshold is detected. The dominant state must be held for tLINBUS filter time (to eliminate false wake  
ups from disturbances on the LIN Bus).  
Local wake-up via falling edge on NWake pin which is held low for filter time tNWake (to eliminate false wake  
ups from disturbances on NWake).  
Local wake-up via EN being set high  
Standby Mode  
This mode is entered whenever a wake-up event occurs via the LIN bus or NWake pin while the TPIC1021 is in  
low power mode. The LIN bus slave termination circuit and the INH pin are turned on when standby mode is  
entered. The application system will power up once the INH pin is turn assuming it is using a voltage regulator  
connected via INH pin. Standby Mode is signaled via a low level on RXD pin.  
When EN pin is set high while the TPIC1021 is in Standby Mode the device returns to Normal Mode and the  
normal transmission paths from TXD to LIN bus and LIN bus to RXD are turned on.  
5
TPIC1021  
LIN Physical Interface  
www.ti.com  
SLIS113COCTOBER 2004REVISED JULY 2005  
LIN  
t
LINBUS  
V
SUP  
INH  
EN  
High Impedance  
System Wake−Up Time (Vreg + MCU)  
Floating  
RXD  
Low Power  
Standby  
Normal  
MODE  
Figure 2. Wake-Up Via LIN Bus Timing Diagram  
Falling Edge on NWake  
NWake  
t
NWake  
V
SUP  
INH  
EN  
High Impedance  
System Wake−Up Time (Vreg + MCU)  
Floating  
RXD  
Low Power  
Standby  
Normal  
MODE  
Figure 3. Wake-Up Via NWake Timing Diagram  
6
TPIC1021  
LIN Physical Interface  
www.ti.com  
SLIS113COCTOBER 2004REVISED JULY 2005  
ABSOLUTE MAXIMUM RATINGS(1)  
over operating free-air temperature range (unless otherwise noted)  
PARAMETER  
RATING  
0 to 27  
UNIT  
V
(2)  
VSUP  
Supply line supply voltage (continuous)  
Supply line supply voltage (transient)  
0 to 40  
V
NWake DC and transient input voltage (through 33-kserial resistor)  
Logic pin input voltage (RXD, TXD, EN)  
LIN DC input voltage  
Electrostatic discharge: Human Body Model: LIN pin(3)  
Electrostatic discharge: Human Body Model: NWake pin(3)  
Electrostatic discharge: Human Body Model: All other pins(3)  
Electrostatic discharge: Machine Model: LIN and NWake pins(4)  
Electrostatic discharge: Machine Model: All other pins(4)  
Operational free-air temperature  
-1 to 40  
-0.3 to 5.5  
-40 to 40  
-12 to 12  
-9 to 9  
V
V
V
kV  
kV  
kV  
V
-3 to 3  
-400 to 400  
-200 to 200  
-40 to 125  
-40 to 150  
-40 to 165  
145  
V
TA  
°C  
°C  
°C  
°C/W  
°C  
°C  
TJ  
Junction temperature  
Tstg  
RθJA  
Storage temperature  
Thermal resistance, junction-to-ambient  
Thermal shutdown  
200  
Thermal shutdown hysteresis  
25  
(1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings  
only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating  
conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.  
(2) All voltage values are with respect to GND.  
(3) The human body model is a 100-pF capacitor discharged through a 1.5-kresistor into each pin.  
(4) The machine model is a 200-pF capacitor through a 10-resistor and a 0.75-µH coil.  
7
TPIC1021  
LIN Physical Interface  
www.ti.com  
SLIS113COCTOBER 2004REVISED JULY 2005  
ELECTRICAL CHARACTERISTICS  
VSUP = 7 V to 27 V, TA = -40°C to 125°C (unless otherwise noted)  
PARAMETER  
TEST CONDITIONS  
MIN  
TYP(1)  
MAX  
UNIT  
SUPPLY  
Operational supply voltage(2)  
Nominal supply line voltage(2)  
VSUP undervoltage threshold(2)  
Supply Current  
7
7
14  
14  
27  
V
18  
V
V
4.5  
1.2  
ICC  
Normal Mode, EN = 1, Bus domi-  
2.5  
2.1  
500  
500  
50  
mA  
nant (total bus load > 500 )(3)  
Standby Mode, EN = 0, Bus domi-  
1
300  
300  
20  
mA  
µA  
µA  
µA  
µA  
nant (total bus load > 500 )(3)  
Normal Mode, EN = 1, Bus recess-  
ive  
Standby Mode, EN = 0, Bus recess-  
ive  
Low Power Mode, EN = 0, VSUP  
<
14 V, NWake = VSUP, LIN = VSUP  
Low Power Mode, EN = 0, 14 V <  
VSUP < 27 V, NWake = VSUP, LIN =  
VSUP  
50  
100  
RXD OUTPUT PIN  
VO  
IOL  
IIKG  
Output voltage  
Low-level output current, open drain LIN = 0 V, RXD = 0.4 V  
Leakage current, high-level LIN = VSUP, RXD = 5 V  
-0.3  
3.5  
-5  
5.5  
5
V
mA  
µA  
0
TXD INPUT PIN  
VIL  
VIH  
VIT  
Low-level input voltage(2)  
-0.3  
2
0.8  
5.5  
500  
800  
5
V
V
High-level input voltage(2)  
Input threshold hysteresis voltage(2)  
Pull-down resistor  
30  
125  
-5  
mV  
kΩ  
µA  
350  
0
IIL  
Low-level input current  
TXD = 0  
LIN PIN (Referenced to VSUP  
)
VOH  
High-level output voltage(2)  
LIN recessive, TXD = High, IO = 0  
mA  
VSUP-1V  
0
V
V
VOL  
Low-level output voltage(2)  
LIN dominant, TXD = Low, IO = 40  
mA  
0.2×VSUP  
Pull-up resistor to VSUP  
Limiting current  
20  
50  
30  
150  
0
60  
250  
kΩ  
mA  
µA  
V
IL  
TXD = Low  
LIN = VSUP  
IIKG  
VIL  
VIH  
VIT  
Vhys  
VIL  
Leakage current  
-5  
5
Low-level input voltage(2)  
High-level input voltage(2)  
Input threshold voltage(2)  
Hysteresis voltage(2)  
LIN dominant  
LIN recessive  
0×VSUP  
0.6×VSUP  
0.4×VSUP  
0.05×VSUP  
0
0.4×VSUP  
VSUP  
V
0.5×VSUP  
0.6×VSUP  
0.175×VSUP  
0.4×VSUP  
V
V
Low-level input voltage for  
wake-up(2)  
V
EN PIN  
VIL  
Low-level input voltage(2)  
High-level input voltage(2)  
Hysteresis voltage(2)  
-0.3  
2
0.8  
5.5  
V
V
VIH  
Vhys  
30  
500  
mV  
(1) Typical values are give for VSUP = 14 V at 25°C.  
(2) All voltages are defined with respect to ground; positive currents flow into the TPIC1021 device.  
(3) In the dominant state the supply current increases as the supply voltage increases due to the integrated LIN slave termination  
resistance. At higher voltages the majority of supply current is through the termination resistance. The minimum resistance of the LIN  
slave termination is 20 kso the maximum supply current attributed to the termination is: ISUP (dom) max termination (VSUP  
(VLIN_Dominant+0.7V) / 20 k.  
8
TPIC1021  
LIN Physical Interface  
www.ti.com  
SLIS113COCTOBER 2004REVISED JULY 2005  
ELECTRICAL CHARACTERISTICS (continued)  
VSUP = 7 V to 27 V, TA = -40°C to 125°C (unless otherwise noted)  
PARAMETER  
Pull-down resistor  
TEST CONDITIONS  
MIN  
125  
-5  
TYP(1)  
350  
0
MAX  
800  
5
UNIT  
kΩ  
IIL  
Low-level input current  
EN = 0 V  
µA  
INH PIN  
Vo  
DC output voltage  
Ouptut current  
Transient voltage  
-0.3  
-50  
25  
VSUP+0.3  
V
mA  
IO  
2
Ron  
On state resistance  
Between VSUP and INH, INH = 2 mA  
drive, Normal or Standby Mode  
40  
0
100  
IIKG  
Leakage current  
Low Power mode, 0 < INH < VSUP  
-5  
5
µA  
NWake PIN  
(4)  
VIL  
VIH  
Low-level input voltage  
-0.3  
VSUP-1  
-40  
VSUP-3.3  
V
V
High-level input voltage(4)  
VSUP+0.3  
Pull-up current  
NWake = 0 V  
-10  
0
-4  
5
µA  
µA  
IIKG  
Leakage current  
VSUP = NWake  
-5  
THERMAL SHUTDOWN  
Shutdown junction thermal tempera-  
185  
°C  
ture  
AC CHARACTERISTICS  
D1  
D2  
D3  
D4  
Duty cycle 1(5)(6)  
THREC(max) = 0.744×VSUP  
THDOM(max) = 0.581×VSUP, VSUP  
7.0 V to 18 V, tBIT = 50 µs (20 kbps),  
See Figure 4  
,
0.396  
0.417  
=
Duty cycle 2(5)(6)  
Duty cycle 3(5)(6)  
Duty cycle 4(5)(6)  
THREC(max) = 0.284×VSUP  
THDOM(max) = 0.422×VSUP, VSUP  
7.6 V to 18 V, tBIT = 50 µs (20 kbps),  
See Figure 4  
,
0.581  
0.590  
=
THREC(max) = 0.778×VSUP  
,
THDOM(max) = 0.616×VSUP, VSUP  
7.0 V to 18 V, tBIT = 96 µs (10.4  
kbps), See Figure 4  
=
=
THREC(max) = 0.251×VSUP  
,
THDOM(max) = 0.389×VSUP, VSUP  
7.6 V to 18 V, tBIT = 96 µs (10.4  
kbps), See Figure 4  
trx_pdr  
trx_pdf  
trx_sym  
Receiver rising propagation delay  
time  
RL = 2.4 k, CL = 20 pF, See  
Figure 4  
6
6
2
µs  
µs  
µs  
Receiver falling propagation delay  
time  
RL = 2.4 k, CL = 20 pF, See  
Figure 4  
Symmetry of receiver propagation  
delay time (rising edge)  
wrt falling edge, See Figure 4  
-2  
tNWake  
tLINBUS  
NWake filter time for local wake-up  
See Figure 4  
See Figure 4  
25  
25  
50  
50  
100  
100  
µs  
µs  
LIN wake-up filter time (dominant  
time for wake-up via LIN bus)  
tDST  
Dominant state timeout(7)  
See Figure 4  
6
9
14  
ms  
(4) All voltages are defined with respect to ground; positive currents flow into the TPIC1021 device.  
(5) Duty cycle = tBUS_rec(min)/ (2×tBIT  
)
(6) Duty Cycles: LIN Driver bus load conditions (CLINBUS, RLINBUS): Load1 = 1 nF, 1 k; Load2 = 6.8 nF, 660 ; Load3 = 10 nF, 500 .  
Duty Cycles 3 and 4 are defined for 10.4 kbps operation. The TPIC1021 also meets these lower speed requirements, while it is capable  
of of the higher speed 20.0 kbps operation as specified by Duty Cycles 1 and 2. SAEJ2602 derives propagation delay equations from  
the LIN 2.0 duty cycle definitions, for details please refer to the SAEJ2602 specification.  
(7) Dominant state timeout will limit the minimum data rate to 2.4 kbps.  
9
TPIC1021  
LIN Physical Interface  
www.ti.com  
SLIS113COCTOBER 2004REVISED JULY 2005  
TIMING DIAGRAMS  
tBit  
tBit  
tBit  
RECESSIVE  
DOMINANT  
TXD (Input)  
tBus_dom(max)  
tBus_rec(min)  
THRec(max)  
Thresholds of  
receiving node 1  
THDom(max)  
VSUP  
(Transceiver supply  
of transmitting node)  
LIN Bus Signal  
Thresholds of  
receiving node 2  
THRec(min)  
THDom(min)  
tBus_dom(min)  
tBus_rec(max)  
RXD  
(Output of receiving node 1)  
trx_pdf(1)  
trx_pdr(1)  
RXD  
(Output of receiving node 2)  
trx_pdf(2)  
trx_pdr(2)  
Figure 4. Definition of Bus Timing Parameters  
10  
TPIC1021  
LIN Physical Interface  
www.ti.com  
SLIS113COCTOBER 2004REVISED JULY 2005  
APPLICATION INFORMATION  
V
BAT  
V
SUP  
TPIC7xxxx  
MASTER  
NODE  
V
SUP  
V
DD  
NWake  
INH  
V
DD  
Master Node  
Pull−Up  
V
SUP  
3
V
DD  
EN  
8
3
7
2
MCU w/o  
pull−up  
2
1 k  
V
DD  
I/O  
MCU  
V
TPIC1021  
TMS430  
TMS470  
LIN  
Controller  
or  
LIN  
1
4
RXD  
TXD  
6
220 pF  
5
1
SCI/UART  
GND  
SLAVE  
NODE  
V
SUP  
TPIC7xxxx  
V
SUP  
V
DD  
NWake  
INH  
V
SUP  
V
DD  
EN  
8
2
3
7
MCU w/o  
2
pull−up  
V
DD  
I/O  
MCU  
TPIC1021  
TMS430  
TMS470  
LIN  
Controller  
or  
LIN  
1
4
RXD  
TXD  
6
220 pF  
5
1
SCI/UART  
GND  
(1) RXD on MCU or LIN Slave has internal pull-up, no external pull-up resistor is needed.  
(2) RXD on MCU or LIN Slave without internal pull-up, requires external pull-up resistor.  
(3) Master Node applications require an external 1-kpull-up resistor and serial diode.  
Figure 5.  
11  
PACKAGE OPTION ADDENDUM  
www.ti.com  
24-Jan-2013  
PACKAGING INFORMATION  
Orderable Device  
TPIC1021D  
Status Package Type Package Pins Package Qty  
Eco Plan Lead/Ball Finish  
MSL Peak Temp  
Op Temp (°C)  
Top-Side Markings  
Samples  
Drawing  
(1)  
(2)  
(3)  
(4)  
ACTIVE  
SOIC  
SOIC  
SOIC  
SOIC  
D
8
8
8
8
75  
75  
Green (RoHS  
& no Sb/Br)  
CU NIPDAU  
CU NIPDAU  
CU NIPDAU  
CU NIPDAU  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
-40 to 125 T1021  
T1021  
TPIC1021DG4  
TPIC1021DR  
ACTIVE  
ACTIVE  
ACTIVE  
D
D
D
Green (RoHS  
& no Sb/Br)  
2500  
2500  
Green (RoHS  
& no Sb/Br)  
-40 to 125 T1021  
T1021  
TPIC1021DRG4  
Green (RoHS  
& no Sb/Br)  
(1) The marketing status values are defined as follows:  
ACTIVE: Product device recommended for new designs.  
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.  
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.  
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.  
OBSOLETE: TI has discontinued the production of the device.  
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability  
information and additional product content details.  
TBD: The Pb-Free/Green conversion plan has not been defined.  
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that  
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.  
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between  
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.  
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight  
in homogeneous material)  
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.  
(4) Only one of markings shown within the brackets will appear on the physical device.  
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information  
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and  
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.  
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.  
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.  
Addendum-Page 1  
PACKAGE OPTION ADDENDUM  
www.ti.com  
24-Jan-2013  
Addendum-Page 2  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
14-Mar-2013  
TAPE AND REEL INFORMATION  
*All dimensions are nominal  
Device  
Package Package Pins  
Type Drawing  
SPQ  
Reel  
Reel  
A0  
B0  
K0  
P1  
W
Pin1  
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant  
(mm) W1 (mm)  
TPIC1021DR  
TPIC1021DR  
SOIC  
SOIC  
SOIC  
D
D
D
8
8
8
2500  
2500  
2500  
330.0  
330.0  
330.0  
12.4  
12.4  
12.4  
6.4  
6.4  
6.4  
5.2  
5.2  
5.2  
2.1  
2.1  
2.1  
8.0  
8.0  
8.0  
12.0  
12.0  
12.0  
Q1  
Q1  
Q1  
TPIC1021DRG4  
Pack Materials-Page 1  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
14-Mar-2013  
*All dimensions are nominal  
Device  
Package Type Package Drawing Pins  
SPQ  
Length (mm) Width (mm) Height (mm)  
TPIC1021DR  
TPIC1021DR  
SOIC  
SOIC  
SOIC  
D
D
D
8
8
8
2500  
2500  
2500  
367.0  
367.0  
367.0  
367.0  
367.0  
367.0  
35.0  
35.0  
35.0  
TPIC1021DRG4  
Pack Materials-Page 2  
IMPORTANT NOTICE  
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other  
changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest  
issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and  
complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale  
supplied at the time of order acknowledgment.  
TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms  
and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary  
to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily  
performed.  
TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and  
applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide  
adequate design and operating safeguards.  
TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or  
other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information  
published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or  
endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the  
third party, or a license from TI under the patents or other intellectual property of TI.  
Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration  
and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered  
documentation. Information of third parties may be subject to additional restrictions.  
Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service  
voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice.  
TI is not responsible or liable for any such statements.  
Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements  
concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support  
that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which  
anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause  
harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use  
of any TI components in safety-critical applications.  
In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is to  
help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and  
requirements. Nonetheless, such components are subject to these terms.  
No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties  
have executed a special agreement specifically governing such use.  
Only those TI components which TI has specifically designated as military grade or “enhanced plastic” are designed and intended for use in  
military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components  
which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and  
regulatory requirements in connection with such use.  
TI has specifically designated certain components as meeting ISO/TS16949 requirements, mainly for automotive use. In any case of use of  
non-designated products, TI will not be responsible for any failure to meet ISO/TS16949.  
Products  
Applications  
Audio  
www.ti.com/audio  
amplifier.ti.com  
dataconverter.ti.com  
www.dlp.com  
Automotive and Transportation www.ti.com/automotive  
Communications and Telecom www.ti.com/communications  
Amplifiers  
Data Converters  
DLP® Products  
DSP  
Computers and Peripherals  
Consumer Electronics  
Energy and Lighting  
Industrial  
www.ti.com/computers  
www.ti.com/consumer-apps  
www.ti.com/energy  
dsp.ti.com  
Clocks and Timers  
Interface  
www.ti.com/clocks  
interface.ti.com  
logic.ti.com  
www.ti.com/industrial  
www.ti.com/medical  
Medical  
Logic  
Security  
www.ti.com/security  
Power Mgmt  
Microcontrollers  
RFID  
power.ti.com  
Space, Avionics and Defense  
Video and Imaging  
www.ti.com/space-avionics-defense  
www.ti.com/video  
microcontroller.ti.com  
www.ti-rfid.com  
www.ti.com/omap  
OMAP Applications Processors  
Wireless Connectivity  
TI E2E Community  
e2e.ti.com  
www.ti.com/wirelessconnectivity  
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265  
Copyright © 2013, Texas Instruments Incorporated  

TPIC1021D CAD模型

原理图符号

PCB 封装图

TPIC1021D 替代型号

型号 制造商 描述 替代类型 文档
TPIC1021DR TI LIN Physical Interface 完全替代
TPIC1021DRG4 TI LIN Physical Interface 完全替代
TPIC1021AQDRQ1 TI LIN PHYSICAL INTERFACE 完全替代

TPIC1021D 相关器件

型号 制造商 描述 价格 文档
TPIC1021DG4 TI LIN Physical Interface 获取价格
TPIC1021DR TI LIN Physical Interface 获取价格
TPIC1021DRG4 TI LIN Physical Interface 获取价格
TPIC1301 TI 3-HALF H-BRIDGE GATE-PROTECTED POWER DMOS ARRAY 获取价格
TPIC1301DW TI 3-HALF H-BRIDGE GATE-PROTECTED POWER DMOS ARRAY 获取价格
TPIC1301DWR TI 2.25A, 60V, 0.275ohm, 6 CHANNEL, N-CHANNEL, Si, POWER, MOSFET, MS-013AD, PLASTIC, SOIC-24 获取价格
TPIC1310 TI 3-HALF H-BRIDGE GATE PROTECTED POWER DMOS ARRAY 获取价格
TPIC1310KTR TI 3-HALF H-BRIDGE GATE PROTECTED POWER DMOS ARRAY 获取价格
TPIC1310KTS TI 3-HALF H-BRIDGE GATE PROTECTED POWER DMOS ARRAY 获取价格
TPIC1321L TI 3-HALF H-BRIDGE GATE-PROTECTED LOGIC-LEVEL POWER DMOS ARRAY 获取价格
Hi,有什么可以帮您? 在线客服 或 微信扫码咨询