TPIC2060ADFDRG4 [TI]
TPIC2060A 用于 ODD 的串行 I/F 控制的 9 通道电机驱动器 | DFD | 56 | -20 to 75;
| 型号： | TPIC2060ADFDRG4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | TPIC2060A 用于 ODD 的串行 I/F 控制的 9 通道电机驱动器 | DFD | 56 | -20 to 75 电动机控制 电机 驱动 光电二极管 驱动器 |
| 文件： | 总63页 (文件大小：1323K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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TPIC2060A
ZHCSEQ4 –JULY 2015
TPIC2060A 用于 ODD、由串行接口控制的 9 通道电机驱动器
1 特性
•
负载机制支持：
–
滑动电机和步进电机通道中具有独立的端点检测
机制
1
•
串行端口数字接口
–
–
–
–
串行外设接口 (SPI)
–
–
托盘锁定检测
4 线接口：SSZ、SCLK、SIMO、SOMI
最大读写频率 35MHz
检测托盘推事件
3.3V 数字输入输出 (I/O)
2 应用
•
执行器和电机驱动器
光盘驱动器（Blu-ray™、数字化视频光盘 (DVD)、
光盘 (CD)）
–
–
具有 H 桥输出的脉冲宽度调制 (PWM) 控制
具有 12 位数模转换器 (DAC) 控制的聚焦/跟踪/
倾斜执行器驱动器
3 说明
–
具有电流模式、10 位 DAC 控制的滑动电机驱
动器
TPIC2060A 是一款适用于 12V ODD 的超低噪声电机
驱动器集成电路 (IC)。该驱动器 IC 有 9 条通道且由串
行接口控制，非常适用于驱动主轴电机、滑动电机（适
用的步进电机）、负载电机以及针对准直透镜的聚焦/
跟踪/倾斜执行器和步进电机。
–
–
具有 12 位 DAC 控制的负载驱动器
具有 8 位 PWM 控制的步进电机驱动器
•
主轴电机驱动器
–
–
–
集成有电流感测电阻
器件信息(1)
可通过寄存器集更改电流限值
器件型号
TPIC2060A
封装
封装尺寸（标称值）
无传感器：通过电机反电动势 (BEMF) 感测转
子位置
HTSSOP (56)
6.10mm x 14.00mm
(1) 要了解所有可用封装，请见数据表末尾的可订购产品附录。
–
–
–
–
–
通过串行端口编程设定的 12 位主轴 DAC
独立的感应位置感测和启动
简化电路原理图
通过自动控制制动实现急停：主动制动和短制动
最大持续电流为 1.5A，不存在散热问题
MCOM
TPIC2060A
U
12 V
V
SPM
0.35Ω 低导通电阻、典型金属氧化物半导体场效
应晶体管 (MOSFET) 输出
Driver
12 V
W
5 V
SLED1+
12 V
3.3 V
•
•
实用功能
SLED1œ
SLED1
SLED2+
–
状态锁存器：执行器定时器、SIF 错误、电源监
视器、热保护和短路保护 (SCP) 故障
12 V
SLED2
SLED2œ
TLT+
TLTœ
FCS+
SPI
5 V
–
片上温度计（15°C 至 165°C/1.2°C）
Controller
TLT
9V LDO
5 V
FCSœ
FCS
–
–
9V LDO 集成有前置驱动器
TRK+
TRKœ
5 V
5 V
5 V
5 V
根据电流要求选择外部 N 沟道场效应晶体管
(NFET)
TRK
LOAD
STP1
STP2
12 V
LOAD+
LIN9VG
LOADœ
STP1+
STP1œ
STP2+
–
通过串行控制使能
LDO
Control
9 Vout
•
保护
–
同步永磁电机 (SPM)、滑动电机、步进准直透
镜和执行器上均配有独立热保护电路
LINFB
STP2œ
–
–
两个警报级别：热保护中的预检测和检测
ACTTEMP：监视由过去累积的 DAC 值计算得
出的执行器温度
–
SPM、滑动电机、负载、步进驱动器和执行器
通道中具有短路保护
–
–
硬件器件禁用引脚 XRSTIN
具有欠压锁定 (UVLO) 和过压保护 (OVP) 的电
源监视器
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SLIS166
TPIC2060A
ZHCSEQ4 –JULY 2015
www.ti.com.cn
目录
8.3 Feature Description................................................. 15
8.4 Device Functional Modes........................................ 18
8.5 Programming........................................................... 19
8.6 Register Maps......................................................... 21
Application and Implementation ........................ 42
9.1 Application Information............................................ 42
9.2 Typical Application ................................................. 54
1
2
3
4
5
6
7
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
说明 （续）.............................................................. 3
Pin Configuration and Functions......................... 3
Specifications......................................................... 5
7.1 Absolute Maximum Ratings ...................................... 5
7.2 ESD Ratings.............................................................. 5
7.3 Recommended Operating Conditions....................... 6
7.4 Thermal Information.................................................. 6
7.5 Electrical Characteristics........................................... 7
7.6 Serial I/F Write Timing Requirements..................... 10
7.7 Serial I/F Read Timing Requirements..................... 11
7.8 Typical Characteristics............................................ 12
Detailed Description ............................................ 13
8.1 Overview ................................................................. 13
8.2 Functional Block Diagram ....................................... 14
9
10 Power Supply Recommendations ..................... 55
11 Layout................................................................... 56
11.1 Layout Guidelines ................................................. 56
11.2 Layout Example .................................................... 56
12 器件和文档支持 ..................................................... 57
12.1 社区资源................................................................ 57
12.2 商标....................................................................... 57
12.3 静电放电警告......................................................... 57
12.4 Glossary................................................................ 57
13 机械、封装和可订购信息....................................... 57
8
4 修订历史记录
日期
修订版本
注释
2015 年 7 月
*
最初发布。
2
版权 © 2015, Texas Instruments Incorporated
TPIC2060A
www.ti.com.cn
ZHCSEQ4 –JULY 2015
5 说明 （续）
该 IC 集成有电流感测电阻，能够测量 SPM 电流并降低驱动系统成本。主轴电机驱动器部分内置无传感器逻辑，可
确保以低噪声启动和运行。用户无需使用启动电路使器件自启动或者通过电机或传感器（例如霍尔器件）的 BEMF
执行位置检测。由于所有通道的输出级均在高效的 PWM 驱动下工作，用户可通过 PWM 控制实现低功率运行。可
以对聚焦/跟踪/倾斜执行器驱动器进行无死区控制。此外，该器件还内置有主轴部件输出电流限制电路、热关断电
路、滑动结束位置检测电路、准直透镜结束检测电路、执行器保护和 9V LDO 的前置驱动器。新增的内置温度计可
测量 IC 温度。
6 Pin Configuration and Functions
DFD Package
56-Pin HTSSOP
Top View
1
2
3
4
5
6
7
8
9
SLED1_ P
SLED1_ N
P12V_ SLD
SLED2_ P
SLED2_ N
PGND_ 2
C10V
(N.C) 56
LINFB 55
LIN9VG 54
IDCHG(TEST) 53
(N.C) 52
AGND
51
(N.C) 50
CP1
MCOM 49
PGND_ SPM2
W
CP2
48
47
46
45
44
43
10 CP3
P12V_ SPM2
11 GPOUT
12 XFG
V
PGND_ SPM1
U
13 RDY
14 SSZ
15 SCLK
P12V_ SPM1 42
PGND_ 1 41
FCS_ N 40
FCS_ P 39
TRK_ N 38
TRK_ P 37
TLT_ P 36
TLT_ N 35
P5V 34
16 SIMO
17 SOMI
18 SIOV
19 XRSTIN
20 (N.C)
21 (N.C)
22 CV3P3A
23 AGND/DGND
24 (N.C)
33
STP1_ P
25 P5V12L
26 LOAD_ N
27 LOAD_ P
28 CA5V
STP1_ N 32
STP2_ P 31
STP2_ N 30
(N.C) 29
Copyright © 2015, Texas Instruments Incorporated
3
TPIC2060A
ZHCSEQ4 –JULY 2015
www.ti.com.cn
Pin Functions
PIN
NAME
I/O
DESCRIPTION
NO.
51
AGND
PS
PS
Ground terminal for internal analog
AGND/DGND
23
Ground terminal for internal digital and analog
The capacitance connection terminal for control system power supply. Connect a 0.1-µF or
lager decoupling capacitor.
CA5V
28
MISC
CP1
8
CP2
9
MISC
Capacitance connections for charge pump
CP3
10
22
39
40
11
53
54
55
26
27
49
CV3P3
FCS_P
FCS_N
GPOUT
IDCHG(TEST)
LIN9VG
LINFB
MISC
OUT
OUT
OUT
—
Capacitance terminal for internal 3.3-V core (typ 0.1 µF)
Focus positive output terminal
Focus negative output terminal
General-purpose output (test monitor)
Test pin (leave open)
—
9-V predriver output control signal for external NFET
Voltage feedback of 9-V pre-driver (controlled to LINFB = 1.215 V)
Load negative output terminal
—
LOAD_N
LOAD_P
MCOM
OUT
OUT
IN
Load positive output terminal
Motor center tap connection
20, 21, 24, 29,
50, 52, 56
(N.C)
—
Leave open
P12V_SLD
P12V_SPM1
P12V_SPM2
P5V
3
PS
PS
Power supply terminal for SLED drivers
Power supply terminal for SPM driver output stage
Power supply terminal for SPM driver output stage
Power supply terminal for 5-V driver output
Power supply terminal (5 or 12 V) for load driver output stages
GND terminal
42
46
34
25
41
6
PS
PS
P5V12L
PGND_1
PGND_2
PGND_SPM1
PGND_SPM2
RDY
PS
PS
PS
GND terminal
44
48
13
15
16
18
2
PS
Ground terminal for spindle driver
PS
Ground terminal for spindle driver
OUT
IN
Device ready signal internally pulled up to SIOV
SIO Serial clock input terminal
SCLK
SIMO
IN
SIO slave input master output terminal
Power supply terminal for serial port 3.3 V typical
Sled1 negative output terminal
SIOV
PS
SLED1_N
SLED1_P
SLED2_N
SLED2_P
SOMI
OUT
OUT
OUT
OUT
OUT
IN
1
Sled1 positive output terminal
5
Sled2 negative output terminal
4
Sled2 positive output terminal
17
14
32
33
30
31
35
36
37
38
43
SIO slave output master input terminal
SIO slave select active-low input terminal
STP1 negative output terminal for collimator lens motor
STP1 positive output terminal for collimator lens motor
STP2 negative output terminal for collimator lens motor
STP2 positive output terminal for collimator lens motor
Tilt negative output terminal
SSZ
STP1_N
STP1_P
STP2_N
STP2_P
TLT_N
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
TLT_P
Tilt positive output terminal
TRK_P
Tracking positive output terminal
TRK_N
Tracking negative output terminal
U
U phase output terminal for spindle motor
4
Copyright © 2015, Texas Instruments Incorporated
TPIC2060A
www.ti.com.cn
ZHCSEQ4 –JULY 2015
Pin Functions (continued)
PIN
I/O
DESCRIPTION
NAME
NO.
45
V
OUT
OUT
OUT
IN
V phase output terminal for spindle motor
W
47
W phase output terminal for spindle motor
XFG
XRSTIN
12
Motor speed signal output, internally pulled up to SIOV
RESET input terminal to reset the driver IC (optional)
19
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature (unless otherwise noted)
(1)
MIN
MAX
6
UNIT
5-V supply voltage P5V
12-V supply voltage P12V
15
V
Load supply P5V12 voltage
15
Spindle output peak voltage
Spindle output current
15
2.5
3.5
1.0
1.0
1.0
Spindle output peak current、(PW ≤ 2 ms、Duty ≤ 30%)
Sled output peak current
A
Focus/tracking/tilt driver output peak current
Load driver output peak current
Input/output voltage
–0.3
–20
–60
VCC + 0.3
1344
75
V
(2)
Power dissipation
mW
Operating temperature
Lead temperature 1.6 mm from case for 10 s
260
°C
Tstg
Storage temperature
150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) A lower RθJC is attainable if the exposed pad is connected to a large copper ground plane. RθJC and RθJA are values for 56-pin TSSOP
without a exposed heat slug (HSL) on bottom. ꢀActual thermal resistance would be better than the above values.
7.2 ESD Ratings
VALUE
±2000
±500
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
Electrostatic
discharge
V(ESD)
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
Copyright © 2015, Texas Instruments Incorporated
5
TPIC2060A
ZHCSEQ4 –JULY 2015
www.ti.com.cn
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
4.5
NOM
5.0
MAX
5.5
UNIT
Operating supply voltage (apply for P5V)
Driver 12-V supply voltage (apply for P12V)(1)
10.8
4.5
12.0
5.0
13.2
5.5
V
Load operating supply voltage (apply for P5V12L)
10.8
3.0
12.0
3.3
13.2
3.6
SIOV voltage
Operating temperature range
–20
30
25
75
°C
SCLK frequency
33.8688
35
MHz
SIMO, SSZ, SCLK pin 'H' level input voltage range
SIMO, SSZ, SCLK pin 'L' level input voltage range
XRSTIN pin 'H' level input voltage
2.2
SIOV + 0.2
0.8
–0.2
2.2
V
P5V + 0.1
0.8
XRSTIN pin 'L' level input voltage range
Spindle output current (U, V, W average total)
Spindle output current [peak]
–0.1
1.7
3.0
A
Focus / tracking / tilt / loading / sled output current [average]
Focus / tracking / tilt / loading / sled output current [peak]
STP output average current
0.4
0.8
300
mA
(1) (P5V = 4.5 to 5.5 V, P12V = 10.8 to 13.2 V, CATA ≈ –20℃ to 75℃, unless otherwise noted)
7.4 Thermal Information
TPIC2060A
THERMAL METRIC(1)
DFD (HTSSOP)
UNIT
56 PINS
16.9
0.8
RθJA
RθJC
RθJB
ψJT
Junction-to-ambient thermal resistance
Junction-to-case thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
Junction-to-board thermal resistance
5.2
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
1
ψJB
5.2
RθJC(bot)
0.9
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
6
Copyright © 2015, Texas Instruments Incorporated
TPIC2060A
www.ti.com.cn
ZHCSEQ4 –JULY 2015
7.5 Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
COMMON PART
ISTBY
VCV3
RXM
Stand by supply current
CV3P3 output voltage
XRSTIN pulldown resistor
RDY pullup resistor
Standby mode (XSLEEP = 0)
Iload = 25 mA
0.6
3.3
200
33
1.2
3.5
mA
V
3.1
80
320
52.8
0.3
kΩ
RRDY
VRDY
RXFG
13.2
RDY low level output voltage
XFG output resistor
SIOV = 3.3 V, IOL = –100 µA
V
100
200
300
Ω
SIOV = 3.3 V, XSLEEP = 1, IOH =
100 µA
VXFGH
XFG high-level output voltage
SIOV – 0.3
V
SIOV = 3.3 V, XSLEEP = 1, IOL = -
100 µA
VSFGL
RGPO
VGPOH
XFG low-level output voltage
GPOUT output resistor
0.3
100
200
300
Ω
SIOV = 3.3 V, XSLEEP = 1,
GPOUT high-level output voltage GPOUT_ENA = 1,GPOUT_HL = 1,
IOH = 100 µA
SIOV – 0.3
V
SIOV = 3.3 V, XSLEEP = 1,
VGPOL
GPOUT low-level output voltage
GPOUT_ENA = 1,GPOUT_HL = 0,
IOH = 100 µA
0.3
V
Thermal protection on
temperature
TTSD
Design value
135
5
150
15
165
25
°C
Thermal protection hysteresis
temperature
TTSDhys
Vonvcc
P5V reset on voltage
P5V reset off voltage
P12V reset on voltage
P12V reset off voltage
CV3P3 reset on voltage
CV3P3 reset off voltage
3.6
3.6
3.7
3.8
8.4
8.8
2.7
2,8
2
3.8
4.0
Voffvcc
Vonvcc
7.9
8.9
Voffvcc
8.3
9.3
VonCV3
VoffCV3
VonSIOV
VoffSIOV
VovpspmOn
VovpspmOff
2.55
2,65
1.9
2.85
2,95
2.1
(1)
SIOV reset on voltage
V
(1)
SIOV reset off voltage
2
2.1
14.9
14.5
2.2
OVP detection voltage (spindle)(1)
OVP release voltage (spindle)(1)
OVP detection voltage (except
14.2
13.8
15.6
15.2
VovpOn
VovpOff
5.9
5.7
6.2
6.0
6.5
6.3
(1)
spindle)
OVP release voltage (except
(1)
spindle)
CHARGE PUMP PART
FCHGP Frequency
VCHGP Output voltage
SPINDLE MOTOR DRIVER PART
XSLEEP = 1
132.6
15.6
156
179.4
21.4
kHz
V
Ccp1 = Ccp3 = 0.1 µF Io = –1 mA
18.5
Total output resistance high side
+ low side
RttlSPM
IOUT = 500 mA
0.4
0.7
Ω
ResSPM
VoutSPM
Resolution
Spindle grain
12
14.0
52h
bit
Magnification to 1.0 inputs
Forward
12.4
12h
15.6
92h
times
WidDZSPM
Spindle dead band
Reverse
–92h
–52h
–12h
(1) These values are protection functions only, and stress beyond those listed under Recommended Operating Conditions may cause
permanent damage to the device.
Copyright © 2015, Texas Instruments Incorporated
7
TPIC2060A
ZHCSEQ4 –JULY 2015
www.ti.com.cn
Electrical Characteristics (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SPM_RCOM_SEL = 00
SPM_TQAJST = 00
1019.7
1133
1246.3
849.2
1557.6
1870.0
–6%
SPM_RCOM_SEL = 01
SPM_TQAJST = 00
694.8
1274.4
1530.0
–4%
772
1416
1700
–5%
SPMClim
Current limit
mA
SPM_RCOM_SEL = 10
SPM_TQAJST = 00
SPM_RCOM_SEL = 11
SPM_TQAJST = 00
SPM_RCOM_SEL = xx
SPM_TQAJST = 01
SPM_RCOM_SEL = xx
SPM_TQAJST = 10
SPMClimF
Current limit fine adjust
–8%
–10%
–15%
–12%
–18%
SPM_RCOM_SEL = xx
SPM_TQAJST = 11
–12%
SLED MOTOR DRIVER PART
Total output resistance high side P12 V = 10.8 to 13.2 V, IO = 500
RttlSLD
1.6
2.5
Ω
+ low side
mA
ResSLD
Resolution
10
+1Fh
–20h
bit
Forward
Reverse
WidDZSLD
GnSLD
input dead band
Sled current gain
P5V = 5 V,P12V = 12 V VSLED =
7FFh
760
62
880
124
1000
186
mA
mV
SLD_ENA = 1, SLD_ENDDET_ENA
= 1, SLEDENDTH <1:0> = 00
END_DET BEMF threshold
voltage
VthEdetSLD
SLEDENDTH<1:0> = 01
SLEDENDTH<1:0> = 11
35
80
72
105
250
168
FOCUS/TILT/TRACKING DRIVER PART
Each channel total output
RttlAct
P5V = 4.5 to 5.5 V、IO = 500 mA
0.7
12
0
1.1
Ω
bit
resistance high side + low side
ResACT
VOfstACT
GnAct
Resolution
Each channel output offset
voltage
DAC_code = 000h
–20
5
20
7
mV
times
mV
Each channel voltage gain
Magnification to 1.0 inputs
DIFF_TLT = 1, FCS-TLT
DIFF_TLT = 1, FCS-TLT (Typ = 1)
6
FCS, TLT differential output offset
voltage
DifOff
–40
0.89
0
40
GnDAct
FCS, TLT differential gain ratio
1
1.13
LOAD DRIVER PART
P5V12L = 4.5 V to 5.5 V、IO = 500
mA
Total output resistance high side
+ low side
RttlLOD
1.2
1.9
Ω
P5V12L = 10.8 V to 13.2 V、IO =
500 mA
ResLOD
GnLOD
Resolution
12
6.0
bit
P5V12L = 4.5 to 5.5 V
P5V12L = 10.8 to 13.2 V
Forward
5.1
6.9
Voltage gain
times
12.6
14.0
20h
15.4
WidDZLOD
Dead band
Reverse
–21h
8
Copyright © 2015, Texas Instruments Incorporated
TPIC2060A
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ZHCSEQ4 –JULY 2015
Electrical Characteristics (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
P5V12L = 5 V,
TRAY_LOCKDET[2:0] = 1
80
100
120
P5V12L = 12 V,
TRAY_LOCKDET[2:0] = 1
80
120
120
160
160
212
212
255
255
297
297
340
340
0.8
100
150
150
200
200
250
250
300
300
350
350
400
400
1.0
120
180
180
240
240
287
287
345
345
402
402
460
460
1.2
P5V12L = 5 V,
TRAY_LOCKDET[2:0] = 2
P5V12L = 12 V,
TRAY_LOCKDET[2:0] = 2
P5V12L = 5 V,
TRAY_LOCKDET[2:0] = 3
P5V12L = 12 V,
TRAY_LOCKDET[2:0] = 3
P5V12L = 5 V,
TRAY_LOCKDET[2:0] = 4
LockDth
Tray lock detect threshold current
mA
P5V12L = 12 V,
TRAY_LOCKDET[2:0] = 4
P5V12L = 5 V,
TRAY_LOCKDET[2:0] = 5
P5V12L = 12 V,
TRAY_LOCKDET[2:0] = 5
P5V12L = 5 V,
TRAY_LOCKDET[2:0] = 6
P5V12L = 12 V,
TRAY_LOCKDET[2:0] = 6
P5V12L = 5 V,
TRAY_LOCKDET[2:0] = 7
P5V12L = 12 V,
TRAY_LOCKDET[2:0] = 7
LOAD_ENA = 0, P5V12L = 12V,
PUSHDETTH[1:0] = 01
Tray push detect voltage
threshold
LOAD_ENA = 0, P5V12L = 12V,
PUSHDETTH[1:0] = 10
PushDVth
PushDTth
0.52
0.27
78
0.75
0.5
0.96
0.63
130
260
520
25
V
LOAD_ENA = 0, P5V12L = 12V,
PUSHDETTH[1:0] = 11
LOAD_ENA = 0, P5V12L = 12V,
PUSHDETTH_TIME[1:0] = 00
104
208
416
0
LOAD_ENA = 0, P5V12L = 12V,
PUSHDETTH_TIME[1:0] = 01
156
312
Tray push detect time threshold
ms
LOAD_ENA = 0, P5V12L = 12V,
PUSHDETTH_TIME[1:0] = 10
LOAD_ENA = 0, P5V12L = 12V,
PUSHDETTH_TIME[1:0] = 11
STEPPING MOTOR DRIVER PART
Total output resistance high side
+ low side
RttlSTP
IO = 100 mA
1.0
8
1.5
Ω
bit
ResSTP
VthEdetSTP
Resolution
STP_ENA = 1, STP_ENDDET_ENA
= 1, STPDENDTH<1:0> = 00
END_DET threshold level
19
39
59
mV
9-V LDO DRIVER PART
LINFBVth
LINFB threshold voltage
1.165
1.215
7
1.265
V
THERMOMETER PART
ResTEMP
Resolution
bit
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ZHCSEQ4 –JULY 2015
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Electrical Characteristics (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
Temperature range
Update cycle
TEST CONDITIONS
MIN
8
TYP
15
MAX
UNIT
°C
CHIPTEMP[6:0] = 00
CHIPTEMP[6:0] = 7Fh
22
Trng
155
165
10
175
FTEMP
kHz
ACTUATOR PROTECTION
tintACTTEMP Update cycle
SERIAL PORT VOLTAGE LEVELS
26
ms
SOMI
SOMI
SIMO
SIMO
tSIMO
High-level output voltage, VOH
IOH = 1 mA
IOL = 1 mA
80% SIOV
70% SIOV
Low-level output voltage, VOL
High-level input voltage, VIH
Low level input voltage, VIL
Input rise/fall time
20% SIOV
V
20% SIOV
3.5
20% to 80% of SIOV
ns
tSOMI
Output rise/fall time
Cload = 30 pF, 20% to 80% of SIOV
10
RSCLK
RSSZ
Internal pulldown resistance
Internal pullup resistance
Internal pulldown resistance
80
80
80
200
200
200
320
320
kΩ
RSIMO
320
7.6 Serial I/F Write Timing Requirements
MIN
NOM
MAX
UNIT
MHz
ns
ƒck
tckl
SCLK clock frequency (SIOV = 3.3 V)
SCLK low time
35
11
11
7
tckh
tsens
tsenh
tsl
SCLK high time
ns
SSZ setup time
ns
SSZ hold time
7
ns
SSZ disable high time
SIMO setup time (Write)
SIMO hold time (Write)
11
7
ns
tds
ns
tdh
7
ns
Tsl
SSZ
Fck
Tsens
Tsenh
SCLK
Tckl
Tckh
SIMO
Tds
Tdh
SOMI
Hi-Z
Figure 1. Serial Port Write Timing
10
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ZHCSEQ4 –JULY 2015
7.7 Serial I/F Read Timing Requirements
MIN
NOM
MAX
UNIT
MHz
ns
ƒck
tckl
SCLK clock frequency (SIOV = 3.3 V)
SCLK low time
35
11
11
7
tckh
tsens
tsenh
tsl
SCLK high time
ns
SSZ setup time
ns
SSZ hold time
7
ns
SSZ disable high time
11
7
ns
tds
SIMO setup time (Write)
ns
tdh
SIMO hold time (Write)
7
ns
trdly
tsendl
trls
SOMI delay time (Read) - (CLOAD = 10 pF, SIOV = 3.3 V)
SOMI hold time (Read) - (CLOAD = 10 pF, SIOV = 3.3 V)
2
9
9
9
ns
2
ns
SOMI release time (Read) - (CLOAD = 10 pF, SIOV = 3.3 V) From SSZ
rise to SOMI HIZ
0
ns
Tsl
SSZ
Tsenh
Fck
Tsens
Trls
SCLK
Tdh
Tds
Tckh Tckl
SIMO
SOMI
R
Hi-Z
Figure 2. Serial Port Read Timings
Tsl
SSZ
Tsenh
Fck
Tsens
SCLK
Tdh
Tds
Tckh Tck l
SIMO
SOMI
R
Trls
Hi-Z
Trdly
Tsendl
Figure 3. Serial Port Read Timings (Advanced Read Mode)
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7.8 Typical Characteristics
100%
90%
80%
70%
60%
50%
40%
30%
20%
10%
0
100%
90%
80%
70%
60%
50%
40%
30%
20%
10%
0
STP1+
STP1-
STP2+
STP2-
-2047 -1547 -1047 -547
-47
453
953 1453 1953
-2047 -1547 -1047 -547
-47
453
953 1453 1953
DAC Code
DAC Code
D003
D004
Figure 4. STP1 Driver: DAC Code vs Output On Duty
Figure 5. STP2 Driver: DAC Code vs Output On Duty
12
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ZHCSEQ4 –JULY 2015
8 Detailed Description
8.1 Overview
The TPIC2060A is a low-noise motor driver IC suitable for 12-V ODD. The 9-channel driver IC controlled by a
serial interface is optimized for driving a spindle motor, a sled motor (stepping motor applicable), a load motor,
focus / tracking / tilt actuators, and stepping motor for collimator lens. This IC has an integrated current sense
resistance that measures SPM current, which reduces drive system costs. The spindle motor driver part builds in
sensorless logic, which attains low-noise operation at the start and run times. The user does not need to self-
start the device using the starting circuit or perform position detection by BEMF of a motor or sensors such as a
Hall device. As the output stage of all channels works in efficient PWM driving, the user can attain low-power
operation by PWM control. Dead-zone-less control is possible for a focus / tracking / tilt actuator driver. In
addition, the spindle part output current limiting circuit, the thermal shutdown circuit, the sled-end detection
circuit, collimator-lens-end detection circuit, actuator protection, and pre-driver for a 9-V LDO are built in. The
newly added, built-in thermometer measures IC temperature.
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8.2 Functional Block Diagram
12V
12V
5V
12V
12V
0.1u
0.1u
PGND_ SPM1
analog
SPM_ RCOM
PGND_ SPM 2
Charge
pum p
19V
XSLEEP
3.3V
SPM
Current lim it
SPM_ ENA
MCOM
U
BEMF
SPM Logic
DAC PWM
SIOV
detector
XFG
XFG
XSLEEP
V
SIOV
pre
-driver
pwrFET
3.3V
W
SSZ
SSZ
Digital core
SLED1+
SLED1-
SCLK
SCLK
DACPWM
pre
-driver
SIMO
SIMO
pwrFET
pwrFET
I-F/B
SIOV
SLD_ ENA
SOMI
SOMI
SLED2+
SLED2-
pre
3.3V
-driver
SIOV
SLD_ E_ ENA
I-F/B
GPOUT
GPOUT
On chip
therm ometer
GPOUTENA
TLT+
TLT-
XRSTIN
InterLock
DACPWM
DACPWWM
pre
pwrFET
-driver
TLT_ ENA
FCS_ ENA
F/B
FCS+
FCS-
CV3P3V
int3.3V
Regulator
pre
pwrFET
-driver
0.1u
F/B
P5V
SIOV
P12V
SIOV
P5V
TRK+
TRK-
Power
ACTTEMPTH>0
pre
pwrFET
monitor
RDY
-driver
RDY
TRK_ ENA
F/B
P5V12L
12V
DACPWWM
5V
CA5V
LOAD+
5VAnalog
pre
0.1u
pwrFET
-driver
LOAD-
12V
F/B
TRAY_ E_ ENA
DACPWM
LIN9VG
LINFB
LDO
LIN9V_ DIS
LOAD_ ENA
control
STP1+
9V
pre
pwrFET
pwrFET
-driver
STP1-
STP2+
F/B
pre
-driver
STP_ ENA STEP_E_ENA
STP2-
F/B
C10V
int10V
Regulator
TPIC2060A
0.1u
14
Copyright © 2015, Texas Instruments Incorporated
TPIC2060A
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ZHCSEQ4 –JULY 2015
8.3 Feature Description
8.3.1 Protection Functions
The TPIC2060A has four protection features to protect target equipment: overvoltage protection (OVP), short-
circuit protection (SCP), thermal protection (TSD), and actuator temperature protection (ACTTIMER).
8.3.1.1 OVP
The OVP function protects the unit from the supplying high voltage. When the supply voltage exceeds 6.2 V (for
P5V), all driver output goes Hi-Z. SPM, sled, and load channels put Hi-Z when P12V is over 14.9 V. Regardless
of the input voltage of P5V12L, the load channel become Hi-Z at the time of OVP_P5V or OVP_P12V. When the
supply voltage falls below a typical 6.0 V, all outputs start to operate again. (14.5 V for 12-V driver channel) The
OVP and POR (RDY) function is not interlocking.
OVP is intended to protect the device in evaluation stage as temporary and back-up solution.
8.3.1.2 SCP
SCP protects the device from breakdown by large current. Each behavior is indicated on Table 1.
Table 1. Protection Threshold Table
BLOCK
STEP driver
FUNCTION
DETECTION CURRENT
DETECT TIME
HI-Z HOLD TIME
SPM driver
Sled driver
Monitor driver output voltage
SCP
0.8 to 1.6 µs
1.6 ms
Hi side FET output V = GND
Load driver
Actuator driver
Lo side FET output V = Supply voltage
When the large current is detected on each block, the device puts the output FET to Hi-Z.
When SCP occurs, it returns automatically after expiring set Hi-Z hold time. The OCPSCPERR (REG7F) and
SCP flag (REG7B) are set at detection.
The SCP function always monitors the output voltage of the high-side and low-side FET of the output driver.
When the setting voltage is not outputted, the device recognizes it as SCP and changes output Hi-Z. The device
returns to the original state automatically after 1.6 ms.
VDAC set
Driver current
Hi-Z
Hi-Z
detect1.6us
Drivervoltage
1.6m s
RDY
Figure 6. Example of SCP (Driver Short to GND)
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8.3.1.3 Temperature Shutdown (TSD)
TSD is a protection function which intercepts an output and suspends an operation when the IC temperature
exceeds a maximum permissible on a safety. TSD makes an output Hi-Z when the temperature rises up and a
threshold value is exceeded. There are two levels for threshold: Alert and Trip. An alarm is given by status
register TSD_FAULT_ on Alert level with 135°C. If it the temperature continues to rise, the register TSD_ is set at
150°C, and the driver output changes HI-Z. If the temperature falls and reaches 135°C, it will output again. The
TPIC2060A has 11 temperature sensors in each circuit block. Particular sensors are assigned to the appropriate
status flags in Table 2.
Table 2. Thermal Sensor Assignment
CIRCUIT
U
ALERT (°C)
135
TRIP (°C)
150
RELEASE (°C)
ALERT FLAG
TSD_FAULT_SPM
TSD_FAULT_SPM
TSD_FAULT_SPM
TSD_FAULT_ACT
TSD_FAULT_ACT
TSD_FAULT_ACT
TSD_FAULT_ACT
TSD_FAULT_ACT
TSD_FAULT_ACT
TSD_FAULT_ACT
TSD_FAULT_P12DCHG
TRIP FLAG
TSD_SPM
TSD_SPM
TSD_SPM
TSD_ACT
TSD_ACT
TSD_ACT
TSD_ACT
TSD_ACT
TSD_ACT
TSD_ACT
TSD_P12DCHG
135
135
135
135
135
135
135
135
135
135
135
V
135
150
W
135
150
TLT
135
150
FCS
135
150
TRK
135
150
SLED1
SLED2
STP
135
150
135
150
135
150
LOAD
P12DCHG
135
150
135
150
8.3.1.4 ACTTIMER
The TPIC2060A has an actuator protection function named ACTTIMER. This function sets the actuator channel
output to Hi-Z when the actuator coil current exceeds a specific value. Some other devices use a simple actuator
protection function that detects if max current is exceeded with time; however, this other type of actuator
protection function lacks accuracy. This new protection calculates heat accumulation and judges accordingly.
When this function operates, the load driver channel output will be Hi-Z, the spindle channel is forced to “Auto
short brake” and the disc motor stops.
Observe if the protection has occurred by checking the Fault register ACTTIMER_FAULT and
ACT_TIMER_PROT. ACTTIMER_FAULT has
a character for advance notice, set before detecting
ACT_TIMER_PROT. After an ACT_TIMER_PROT is set, even if the temperature falls, it will not release the
protection automatically. It is necessary to clear the flag by setting RST_ERR_FLAG or setting 0 to
ACTTEMPTH. The ACTTIMER function is disabled by setting H to ACTPROT_OFF or setting 0 to ACTTEMPTH.
To acquire the optimal value for ACTTEMPTH, set the device into the condition of the detection level, and read
the value of ACTTEMP. The present value can be read from ACTTEMP. The ACTTEMP data is updated in the
register in ACTPROT_OFF = 0 and ACTTEMPTH > 0.
16
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ZHCSEQ4 –JULY 2015
RST_ ERR_ FLAG
ACTTIMER_ FAULT
ACT_ TIMER_ PROT
ACTTEMPTH
ACTTEMPTH-1
ACTTEMPcount
Hi-Z
Hi-Z
FCS+ , TRK+ , TLT+
FCS-, TRK-, TLT-
Sled1+ , Sled2+
Sled1-, Sled2-
Step1+ ,Step2+
Step1-,Step2-
Load+
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Load-
Motor rpm
0
auto short brake
XFG
disable 300m s
Figure 7. Actuator Temperature Protections
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8.4 Device Functional Modes
8.4.1 Differential Tilt Mode
The TPIC2060A supports differential tilt mode, which outputs the value calculated from focus and tilt. Focus and
tilt can be set in differential mode by DIFF_TLT (REG74) = 1. Because focus and tilt are updated at the same
time, the update interval of tilt can be thinned out. Output data changes at after writing VFCS data. Therefore, it
is necessary to write VFCS data when setting VTLT. In differential mode, the output value is calculated as
follows.
FCS_OUT = (VFCS + VTLT) × 6
TLT_OUT = (VFCS – VTLT) × 6
(1)
(2)
8.4.2 Power-On Reset (POR)
8.4.2.1 RDY (Power Ready)
The TPIC2060A prepares the RDY pin to show a power status to the host controller. A device sets RDY output
to high (= POR), if the supply voltage and internal regulator voltage reach a rated value. All registers are
initialized at the time of POR operation. Figure 8 shows the behavior of RDY.
RDY: High
(Write data)
Register reset
Register valid data
XRSTIN = L (*1)
or RST_REGS = 1
P5V > 3.8 V
P5V < 3.7 V
and CV3P3 > 2.8 V
and SIOV > 2.1 V
and P12V > 8.8 V
or CV3P3 < 2.7 V
or SIOV < 2.0 V
or P12V < 8.4 V
RDY: Low
A. *1 = The period of XRSTIN cannot be communicated with the device.
Figure 8. 10 RDY Pin Behavior
8.4.2.2 Voltage Monitoring
Power faults are reported in the UVLOMon register. Each UVLOMon bit is initialized to 0 upon a cold power-up.
After a fault is detected, the appropriate fault bit is latched high. Writing to the RST_ERR_FLG (REG77) clears
all UVLOMon bits. Table 3 summarizes the power device faults and actions.
Table 3. Power Fault Monitor
DRIVER OUTPUT AT DETECTION
FAULT TYPE
LATCHED REGISTER
POR
CRITERIA
SPM SLED LOAD STEP
ACT
P5V under voltage
UVLO_P5V
Yes
Yes
Yes(1)
<3.7 V
<2.7 V
<8.4 V
<2.0 V
>6.2 V
>14.9 V
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Internal 3.3 V under voltage UVLO_INT3P3
P12V under voltage
SIOV under voltage
P5V over voltage
P12V over voltage
UVLO_P12V
UVLO_SIOV
OVP_P5V
Yes
OVP_P12V
Hi-Z
—
—
(1) P12VMUTE_NORST = 0: force POR, P12VMUTE_NORST = 1: no POR
18
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ZHCSEQ4 –JULY 2015
8.5 Programming
8.5.1 Serial Port Functional Description
The serial communication of the TPIC2060A is based on a SPI communications protocol. TPIC2060A is put on
the slave side. All 16-bit transmission data is effective in SSZ = L period.
The bit stream sent through SIMO from a master (DSP) is latched to an internal shift register by the rising edge
of SCLK. All data is transmitted in a 16-bit format of a command and data. A format has two types of data, 8 bits
and 12 bits in length. To access specific registers, an address and R/W flag are specified as a command part. In
addition, 12-bit data types do not have a R/W flag in the packet, as the DAC registerꢀ(= 12-bit data form) is
Write only. A transfer packet, command and data, is transmitted sequentially from MSB to LSB. A packet is
distinguished in MSB 2 bits of command. In the case of 11, it handles a packet for control register access, and
the other processed as a packet for a DAC data setting.
These are the four kinds of serial-data communication packets:
•
•
•
•
Write 12 bits DAC data (MSB two bit ≠ 11)
Write 8 bits control register (MSB two bit = 11)
Read 8 bits control register (MSB two bit = 11)
Write 12 bits Focus DAC data＋Read 8 bits status register at the same time (MSB two bit ≠ 11)
8.5.2 Write Operation
For write operations, DSP transmits 16-bit (command + address + data) data in an order from MSB. Only the 16-
bit data, 16 SCLK sent from the master during SSZ = L, is effective. If >17 or <15 SCLK pulses are received
during the time that SSZ is low, the whole packet is ignored. For all valid write operations, the data of the shift
register is latched into its designated internal register at the rising edge of the 16th SCLK. All internal register bits,
except as indicated otherwise, are reset to their default states upon power-on reset.
SSZ
SCLK
SIMO
C3
C2
C1
C0
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
SOMI
Hi-Z
Figure 9. Write 12 Bits DAC Data
SSZ
SCLK
SIMO
SOMI
A6
A5
A4
A3
A2
A1
A0
W
D7
D6
D5
D4
D3
D2
D1
D0
Hi-Z
Figure 10. Write 8 Bits Control Register
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Programming (continued)
8.5.3 Read Operation
DSP sends an 8-bit header through SIMO to perform the Read operation. The TPIC2060A starts to drive the
SOMI line upon the eighth falling edge of SCLK and shifts out eight data bits. The master DSP inputs 8 bits of
data from SOMI after the ninth rising edge of SCLK. ꢀ
SSZ
SCLK
SIMO
SOMI
A6
A5
A4
A3
A2
A1
A0
R
D7
D6
D5
D4
D3
D2
D1
D0
Hi-Z
Figure 11. Read 8 Bits Control Register
8.5.4 Write and Read Operation
Optionally, the master DSP can read the Status register during writing a 12 bits DAC (Focus DAC) packet. It is
enabled by setting bit RDSTAT_ON_VFCS (REG74) = H.
SSZ
SCLK
SIMO
C3
C2
C1
C0
D11
D10
D9
D8
D7
D7
D6
D6
D5
D5
D4
D4
D3
D3
D2
D2
D1
D1
D0
D0
SOMI
Hi-Z
Figure 12. Write 12 Bits Focus DAC Data + Read 8 Bits Status Data
20
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ZHCSEQ4 –JULY 2015
8.6 Register Maps
All registers are in WRITE-protect mode after XRSTIN release. WRITE_ENA bit (REG76) = 1 is required before
writing data in register.
8.6.1 Register State Transition
Device Pow er On
version data
(REG7E)
POR
Register initialized
P5V < 2.0V
P5V < 3.7V
or C V3P3 < 2.0V
or CV3P3 < 2.7V
or RST_ ERR_ FLAG= 1
orSIOV< 2.0V
orP12V< 8.4V
or SIF_ TIMEOUT_ ERR= 1
or RST_ REGS= 1
orXRSTIN= L
W RITE_ ENABLE= 0
orXSLEEP= 0
XRSTIN= H
P5V < 3.7V
or CV3P3 < 2.7V
orSIOV< 2.0V
orP12V< 8.4V
or P5V > 6.3V
orP12V> 14.5V
orXRSTIN= L
VDAC Reg data
(REG01-09)
Control Reg data
REG70-77,7C
REG78[4:0]
REG6B-6F
or SIF_ TIMEOUT_ ERR= 1
orRST_ REGS= 1
Initial(000)
Vxxx W rite
RST_ INDAC= 1
orXXX_ ENA= 0
Error latched Reg data
(REG78[5],79,7A,7B,7F[7:1])
set Value
(error occur)
Register valid data
The register contentsare not affected.
Figure 13. Register Behavior
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Register Maps (continued)
8.6.2 DAC Register (12-Bit Write Only)
Two different forms are prepared in the 12-bit DAC register. The forms are selected by setting VDAC_MAPSW
(REG74h).
Table 4. List 2 DAC Register (VDAC_MAPSW = 0)
REG NAME
11
10
9
8
7
6
5
4
3
2
1
0
00h
01h
N/A
N/A
VTLT
[11]
VTLT VTLT[9 VTLT[8 VTLT[7
[10]
VTLT
VTLT[6] VTLT[5] VTLT[4]
VFCS[6] VFCS[5] VFCS[4]
VTRK[6] VTRK[5] VTRK[4]
VTLT[3]
VFCS[3]
VTLT[2]
VFCS[2]
VTLT[1]
VFCS[1]
VTLT[0]
VFCS[0]
]
]
]
VFCS
[11]
VFCS VFCS[ VFCS[ VFCS[
[10] 9] 8] 7]
02h
03h
VFCS
VTRK
VTRK
[11]
VTRK VTRK[ VTRK[ VTRK[
[10] 9] 8] 7]
VTRK[3]
VTRK[2]
VTRK[1]
VTRK[0]
VSLD1 VSLD1 VSLD1 VSLD1 VSLD1 VSLD1
[11] [10] [9] [8] [7] [6]
VSLD1
[5]
VSLD1
[4]
04h VSLD1
05h VSLD2
06h VSTP1
07h VSTP2
VSLD1[3]
VSLD2[3]
VSTP1[3](1)
VSTP2[3](1)
VSPM[3]
VSLD1[2]
VSLD2[2]
VSTP1[2](1)
VSTP2[2](1)
VSPM[2]
VSLD1[1](1)
VSLD2[1](1)
VSTP1[1](1)
VSTP2[1](1)
VSPM[1]
VSLD1[0](1)
VSLD2[0](1)
VSTP1[0](1)
VSTP2[0](1)
VSPM[0]
VSLD2 VSLD2 VSLD2 VSLD2 VSLD2 VSLD2
[11] [10] [9] [8] [7] [6]
VSLD2
[5]
VSLD2
[4]
VSTP1 VSTP1 VSTP1 VSTP1 VSTP1 VSTP1
[11] [10] [9] [8] [7] [6]
VSTP1
[5]
VSTP1
[4]
VSTP2 VSTP2 VSTP2 VSTP2 VSTP2 VSTP2
[11] [10] [9] [8] [7] [6]
VSTP2
[5]
VSTP2
[4]
VSPM VSPM VSPM[ VSPM[ VSPM[
08h
09h
VSPM
VSPM[6] VSPM[5] VSPM[4]
[11]
[10]
9]
8]
7]
VLOA
D
[11]
VLOA
D
[10]
VLOA
D
VLOA
D[9]
VLOA
D[8]
VLOA VLOAD[ VLOAD[ VLOAD[
D[7] 6] 5] 4]
VLOAD[3]
VLOAD[2]
VLOAD[1]
VLOAD[0]
0Ah
0Bh
N/A
N/A
N/A
N/A
(1) TPIC2060A process as 0 even if set as 1.
Table 5. List 3 DAC Register (VDAC_MAPSW=1)
REG
NAME
11
10
9
8
7
6
5
4
3
2
1
0
00h
N/A
N/A
VTRK
[11]
VTRK
[10]
01h
02h
03h
04h
05h
06h
VTRK
VFCS
VTLT
VTRK[9] VTRK[8] VTRK[7] VTRK[6] VTRK[5] VTRK[4] VTRK[3] VTRK[2] VTRK[1]
VFCS[9] VFCS[8] VFCS[7] VFCS[6] VFCS[5] VFCS[4] VFCS[3] VFCS[2] VFCS[1]
VTRK[0]
VFCS[0]
VTLT[0]
VFCS
[11]
VFCS
[10]
VTLT
[11]
VTLT
[10]
VTLT[9]
VTLT[8]
VTLT[7]
VTLT[6]
VTLT[5]
VTLT[4]
VTLT[3]
VTLT[2]
VTLT[1]
VSLD1
[11]
VSLD1
[10]
VSLD1
[9]
VSLD1
[8]
VSLD1
[7]
VSLD1
[6]
VSLD1
[5]
VSLD1
[4]
VSLD1
[3]
VSLD1
[2]
VSLD1
[1](1)
VSLD1
[0](1)
VSLD1
VSLD2
VSPM
VSLD2
[11]
VSLD2
[10]
VSLD2
[9]
VSLD2
[8]
VSLD2
[7]
VSLD2
[6]
VSLD2
[5]
VSLD2
[4]
VSLD2
[3]
VSLD2
[2]
VSLD2
[1](1)
VSLD2
[0](1)
VSPM
[11]
VSPM
[10]
VSPM[9] VSPM[8] VSPM[7] VSPM[6] VSPM[5] VSPM[4] VSPM[3] VSPM[2] VSPM[1]
VSPM[0]
07h
08h
N/A
N/A
N/A
N/A
VLOAD
[11]
VLOAD
[10]
VLOAD
[9]
VLOAD
[8]
VLOAD
[7]
VLOAD
[6]
VLOAD
[5]
VLOAD
[4]
09h
0Ah
0Bh
VLOAD
VSTP1
VSTP2
N/A
N/A
N/A
VSTP1
[11]
VSTP1
[10]
VSTP1
[9]
VSTP1
[8]
VSTP1
[7]
VSTP1
[6]
VSTP1
[5]
VSTP1
[4]
VSTP2
[11]
VSTP2
[10]
VSTP2
[9]
VSTP2
[8]
VSTP2
[7]
VSTP2
[6]
VSTP2
[5]
VSTP2
[4]
(1) TPIC2060A process as 0 even if set as 1.
22
Copyright © 2015, Texas Instruments Incorporated
TPIC2060A
www.ti.com.cn
ZHCSEQ4 –JULY 2015
8.6.3 Control Register (8-Bit Read/Write)
Table 6. List 4 Control Register (8-Bit Read/Write)
REG
NAME
F
7
6
5
4
3
2
1
0
70h
DriverEna
R/W
TLT_ENA
FCS_ENA
TRK_ENA
SPM_ENA
SLD_ENA
STP_ENA
LOAD_ENA
XSLEEP
SLD
_ENDDET
_ENA
STP
_ENDDET
_ENA
LIN9V
_DISABLE
TEMPMON
_ENA
71h
FuncEna
R/W
TI Rsvd
TI Rsvd
SPM_RCOM_SEL
P12VMUTE
_NORST
ACTPROT
_OFF
72h
73h
74h
75h
76h
77h
78h
79h
ACTCfg
Parm0
R/W
R/W
R/W
R/W
R/W
W
RSTIN_OFF
ACTTEMPTH
SLEDEND
_HZTIME
STPEND
_HZTIME
SIF_TIMEOUT_TH
SLDENDTH
STPENDTH
STATUS
_ON_VFCS
VSLD2
_POL
VSTP2
_POL
ADVANCE
_RD
VDAC
_MAPSW
SIFCfg
DIFF_TLT
TI Rsvd
SOMI_HIZ
SPM_FAST SPM_SLNT
_BRK
SPM
Parm1
TRAY_LOCKDET
TI Reserved
_BRK
_HIZMODE
WRITE
_ENABLE
REG6X
_Write
WriteEna
ClrReg
TI Reserved
TI Rsvd
RST_ERR
_FLAG
RST_INDAC RST_REGS
TI Reserved
TI Reserved
ACTTEMP
ACT_TIMER
_PROT
ActTemp
UVLOMon
R
UVLO
UVLO
R
LIN9V_RDY
TI Rsvd
TI Rsvd
UVLO_P5V
UVLO_SIOV OVP_P5V
OVP_P12V
_INT3P3
_P12V
TSD
_FAULT
_SPM
TSD
_FAULT
_ACT
TSD
TSD
_P12DCHG
7Ah
TSDMon
R
_FAULT
TI Rsvd
TSD_SPM
TSD_ACT
SCP_ACT
_P12DCHG
7Bh
7Ch
SCPMon
R
R
TI Reserved
SCP_SPM
SCP_SLED SCP_LOAD
CHIPTEMP
SCP_STP
CHIPTEMP
_STATUS
TempMon
SIF_TIMEO
UTERR
XRSTIN
_DET
TRAY_LOC TRAY_PUS TRAY_PUS
STP
_ENDDET
SLD
_ENDDET
7Dh
7Eh
7Fh
Monitor
Version
Status
R
R
R
TI Rsvd
TI Rsvd
KDETECT
HDETP
HDETN
Version
ACTTIMER
_FAULT
MONITOR
PWRERR
TSDERR
SCPERR
TSDFAULT
FG
FG_SBRK
_OFF
IS_NZONE
_OFF
60h
61h
SPMCfg
SPMCfg
R/W
R/W
TI Rsvd
TI Reserved
TI Rsvd
TI Rsvd
PWMmaxDu
ty_R_SEL
TI Reserved
62h
63h
64h
65h
66h
67h
68h
SPMCfg
Protect
Protect
SPMCfg
Protect
Protect
Protect
R/W
R/W
R/W
R/W
R/W
R/W
R/W
TI Reserved
TIME_BASE_SEL
TI Reserved
FG5M_OFF
TI Reserved
TI Reserved
TI Reserved
TI Reserved
TI Reserved
HZSVR_SEL
TI Reserved
TI Reserved
TI Reserved
SCP_SLED SCP_LOAD SCP_ACT
SPM_TQAJST
TI Reserved
SCP_SPM
_OFF
SCP_STP
_OFF
SPM
_RCDDIS
6Bh
DisProt
R/W
_OFF
_OFF
_OFF
6Ch
6Dh
ENDCfg
Protect
R/W
R/W
PUSHDETTH
PUSHDET_TIME
TI Reserved
TI Reserved
GPOUT
_ENA
6Eh
6Fh
UtilCfg
R/W
R/W
GPOUT_HL
TI Reserved
ACTTIMER
_FLT_MON
MONITOR
_MON
PWRERR
_MON
TSDERR
_MON
OCPSCPER TSDFAULT
R_MON _MON
SPMRCD
_BRK_MON
GPOUTSet
TI Rsvd
VTRK and VLOAD is exclusive, using the same DAC circuit block.
Copyright © 2015, Texas Instruments Incorporated
23
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ZHCSEQ4 –JULY 2015
www.ti.com.cn
8.6.4 Detailed Register Description
8.6.4.1 REG01 12-Bit DAC for Tilt (offset = 01h)
(VDAC_MAPSW = 0)
Figure 14. REG01 12-Bit DAC for Tilt
11
10
9
8
VTLT
w-0
3
w-0
2
w-0
1
w-0
0
7
6
5
4
VTLT
w-0
w-0
w-0
w-0
w-0
w-0
w-0
w-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 7. REG01 12-Bit DAC for Tilt Field Descriptions
BIT
FIELD
TYPE
RESET
DESCRIPTION
11-0
VTLT
W
0h
Digital input code for tilt.
2’s complement format 0x800(-2048) to 0x7ff(+2047)
Output is changed by “differential tilt mode (REG74[7])”
TLT_OUT = VTLT × (6.0/2048) (DIFF_TLT = 0)
TLT_OUT = (VFCS-VTLT) × (6.0/2048) (DIFF_TLT = 1)
TLT_OUT should be changed after writing VFCS. In DIFF_TLT
mode (DIFF_TLT = 1), TLT_OUT should be changed after
writing VFCS.
8.6.4.2 REG02 12-Bit DAC for Focus (offset = 02h)
(VDAC_MAPSW = 0)
Figure 15. REG02 12-Bit DAC for Focus
11
10
9
8
VFCS
w-0
3
w-0
2
w-0
1
w-0
0
7
6
5
4
VFCS
w-0
w-0
w-0
w-0
w-0
w-0
w-0
w-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 8. REG02 12-Bit DAC for Focus Field Descriptions
BIT
FIELD
TYPE
RESET
DESCRIPTION
11-0
VFCS
W
0h
Digital input code for focus.
2’s complement format 0x800(-2048) to 0x7ff(+2047)
Output is changed by differential tilt mode (REG74[7])
FCS_OUT = VFCS × (6.0/2048) (DIFF_TLT = 0)
FCS_OUT = (VFCS + VTLT) × (6.0 / 2048) (DIFF_TLT = 1)
24
Copyright © 2015, Texas Instruments Incorporated
TPIC2060A
www.ti.com.cn
ZHCSEQ4 –JULY 2015
8.6.4.3 REG03 12-Bit DAC for Tracking (offset = 03h)
(VDAC_MAPSW = 0)
Figure 16. REG03 12-Bit DAC for Tracking
11
10
9
8
VTRK
w-0
3
w-0
2
w-0
1
w-0
0
7
6
5
4
VTRK
w-0
w-0
w-0
w-0
w-0
w-0
w-0
w-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 9. REG03 12-Bit DAC for Tracking Field Descriptions
BIT
FIELD
TYPE
RESET
DESCRIPTION
11-0
VTRK
W
0h
Digital input code for tracking.
2’s complement format 0x800(-2048) to 0x7ff(+2047)
TRK_OUT = VTRK × (6.0 / 2048)
8.6.4.4 REG04 12-Bit DAC for Sled1 (offset = 04h)
(VDAC_MAPSW = 0)
Figure 17. REG04 12-Bit DAC for Sled1
11
10
9
8
VSLD1
w-0
3
w-0
2
w-0
1
w-0
0
7
6
5
4
VSLD1
w-0
w-0
w-0
w-0
w-0
w-0
w-0
w-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 10. REG04 12-Bit DAC for Sled1 Field Descriptions
BIT
FIELD
TYPE
RESET
DESCRIPTION
11-0
VSLD1
W
0h
Digital input code for sled1.
2’s complement format 0x800(-2048) to 0x7ff(+2047)
Two bits on LSB, VSLD1[1:0], will be handled with 0.
SLD1_OUT = VSLD1 × (880 mA / 2048)
Copyright © 2015, Texas Instruments Incorporated
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TPIC2060A
ZHCSEQ4 –JULY 2015
www.ti.com.cn
8.6.4.5 REG05 12-Bit DAC for Sled2 (offset = 05h)
(VDAC_MAPSW = 0)
Figure 18. REG05 12-Bit DAC for Sled2
11
10
9
8
VSLD2
w-0
3
w-0
2
w-0
1
w-0
0
7
6
5
4
VSLD2
w-0
w-0
w-0
w-0
w-0
w-0
w-0
w-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 11. REG05 12-Bit DAC for Sled2 Field Descriptions
BIT
FIELD
TYPE
RESET
DESCRIPTION
11-0
VSLD2
W
0h
Digital input code for sled2.
2’s complement format 0x800(-2048) to 0x7ff(+2047)
Two bits on LSB, VSLD2[1:0], will be handled with 0.
SLD2_OUT = VSLD2 × (880 mA / 2048)
8.6.4.6 REG06 12-Bit DAC for Stepping1 (offset = 06h)
(VDAC_MAPSW = 0)
Figure 19. REG06 12-Bit DAC for Stepping1
11
10
9
8
VSTP1
w-0
w-0
w-0
1
w-0
0
7
6
5
4
3
2
VSTP1
w-0
w-0
w-0
w-0
w-0
w-0
w-0
w-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 12. REG06 12-Bit DAC for Stepping1 Field Descriptions
BIT
FIELD
TYPE
RESET
DESCRIPTION
11-0
VSTP1
W
0h
Digital input code for stepping1.
2’s complement format 0x800(-2048) to 0x7ff(+2047)
Although VSTP1 is 12-bit width, MSB 8 bits is effective.
Four bits on LSB, VSTP1[3:0], will be handled with 0.
VSTP1_OUT = VSTP1 × (P5V/2048)
26
Copyright © 2015, Texas Instruments Incorporated
TPIC2060A
www.ti.com.cn
ZHCSEQ4 –JULY 2015
8.6.4.7 REG07 12-Bit DAC for Stepping2 (offset = 07h)
(VDAC_MAPSW = 0)
Figure 20. REG07 12-Bit DAC for Stepping2
11
10
9
8
VSTP2
w-0
3
w-0
2
w-0
1
w-0
0
7
6
5
4
VSTP2
w-0
w-0
w-0
w-0
w-0
w-0
w-0
w-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 13. REG07 12-Bit DAC for Stepping2 Field Descriptions
BIT
FIELD
TYPE
RESET
DESCRIPTION
11-0
VSTP2
W
0h
Digital input code for stepping2.
2’s complement format 0x800(-2048) to 0x7ff(+2047)
Although VSTP2 is 12-bit width, MSB 8 bits is effective.
Four bits on LSB, VSTP2[3:0], will be handled with 0.
VSTP2_OUT = VSTP2 × (P5V/2048)
8.6.4.8 REG08 12-Bit DAC for Spindle (offset = 08h)
(VDAC_MAPSW = 0)
Figure 21. REG08 12-Bit DAC for Spindle
11
10
9
8
VSPM
w-0
w-0
w-0
1
w-0
0
7
6
5
4
3
2
VSPM
w-0
w-0
w-0
w-0
w-0
w-0
w-0
w-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 14. REG08 12-Bit DAC for Spindle Field Descriptions
BIT
FIELD
TYPE
RESET
DESCRIPTION
11-0
VSPM
W
0h
Digital input code for spindle.
2’s complement format 0x800(-2048) to 0x7ff(+2047)
SPM_OUT = VSPM × (14.0/2048)
Copyright © 2015, Texas Instruments Incorporated
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TPIC2060A
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8.6.4.9 REG09 12-Bit DAC for Load (offset = 09h)
(VDAC_MAPSW = 0)
Figure 22. REG09 12-Bit DAC for Load
11
10
9
8
VLOAD
w-0
3
w-0
2
w-0
1
w-0
0
7
6
5
4
VLOAD
w-0
w-0
w-0
w-0
w-0
w-0
w-0
w-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 15. REG09 12-Bit DAC for Load Field Descriptions
BIT
FIELD
TYPE
RESET
DESCRIPTION
11-0
VLOAD
W
0h
Digital input code for load.
2’s complement format 0x800(-2048) to 0x7ff(+2047)
LOAD_OUT = VLOAD × (6.0 / 2048) at P5V12L = 5.0 V
LOAD_OUT = VLOAD × (14.0 / 2048) at P5V12L = 12.0 V
8.6.4.10 REG70 8-Bit Control Register for DriverEna (offset = 70h)
Figure 23. REG70 8-Bit Control Register for DriverEna
7
6
5
4
3
2
1
0
TLT_ENA
rw-0
FCS_ENA
rw-0
TRK_ENA
rw-0
SPM_ENA
rw-0
SLD_ENA
rw-0
STP_ENA
rw-0
LOAD_ENA
rw-0
XSLEEP
rw-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 16. REG70 8-Bit Control Register for DriverEna Field Descriptions
BIT
7
FIELD
TYPE
RW
RW
RW
RW
RW
RW
RW
RESET
0h
DESCRIPTION
TLT_ENA
FCS_ENA
TRK_ENA
SPM_ENA
SLD_ENA
STP_ENA
LOAD_ENA
1h = Tilt enable (with XSLEEP = 1)
1h = Focus enable (with XSLEEP = 1)
1h = Track enable (with XSLEEP = 1)
1h = Spindle enable (with XSLEEP = 1)
1h = Sled enable (with XSLEEP = 1)
1h = Step enable (with XSLEEP = 1)
6
0h
5
0h
4
0h
3
0h
2
0h
1
0h
1h = LOAD enable (with XSLEEP = 1)
Track (bit5:TRK_ENA) will be disabled at LOAD_ENA = 1 because of sharing
the DAC PWM module. Load priority is higher than TRK_ENA.
0
XSLEEP
RW
0h
1h = Operation mode (need 1 ms)
0h = Standby mode
Charge pump enable bit.
All driver enable bit (Bit[7:1]) change disabled and output change to Hi-Z
(regardless of setting xxx_ENA bit is 1) when setting XSLEEP to 0. Therefore,
set 1 to XSLEEP before setting each enable bit.
28
Copyright © 2015, Texas Instruments Incorporated
TPIC2060A
www.ti.com.cn
ZHCSEQ4 –JULY 2015
8.6.4.11 REG71 8-Bit Control Register for FuncEna (offset = 71h)
Figure 24. REG71 8-Bit Control Register for FuncEna
7
6
5
4
3
2
1
0
Reserved
SLD_ENDDET STP_ENDDET
Reserved
LIN9V
_DISABLE
SPM_RCOM_SEL
TEMPMON
_ENA
_ENA
_ENA
rw-0
rw-0
rw-0
rw-0
rw-0
rw-0
rw-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 17. REG71 8-Bit Control Register for FuncEna Field Descriptions
BIT
7
FIELD
TYPE
RW
RESET
0h
DESCRIPTION
Reserved
6
SLD_ENDDET_ENA
RW
0h
1h = Enable SLED channel end position detection (with XSLEEP = 1,
SLD_ENA)
5
STP_ENDDET_ENA
RW
0h
1h = Enable STEP channel end position detection (with XSLEEP = 1,
STP_ENA)
4
3
Reserved
RW
RW
RW
0h
0h
0h
LIN9V_DISABLE
SPM_RCOM_SEL
1h = Disable LDO predriver
2-1
Select resistor value of spindle current sense resistor. Current limit is
set as following current (with SPM_TQAJST = 00)
00: 1133 mA
01: 772 mA
10: 1416 mA
11: 1700 mA
0
TEMPMON_ENA
RW
0h
1h = Enable chip temperature monitoring (with XSLEEP = 1)
8.6.4.12 REG72 8-Bit Control Register for ACTCfg (offset = 72h)
Figure 25. REG72 8-Bit Control Register for ACTCfg
7
6
5
4
3
2
1
0
P12VMUTE
_NORST
RSTIN_OFF
ACTPROT
_OFF
ACTTEMPTH
rw-0
rw-0
rw-0
rw-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 18. REG72 8-Bit Control Register for ACTCfg Field Descriptions
BIT
FIELD
TYPE
RESET
DESCRIPTION
7
P12VMUTE_NORST
RW
0h
0h = System reset at P12V low voltage
1h = Output High-Z only at P12V low-voltage detection
6
5
RSTIN_OFF
RW
RW
RW
0h
0h
0h
0h = XRSTIN input enable
1h = Ignored XRSTIN pin input (do not reset device when XRSTIN = L)
ACTPROT_OFF
ACTTEMPTH
0h = Actuator protection ON
1h = Actuator fault monitor disable (no protection for ACT channel)
4-0
Actuator thermal protection (= ACT Timer) threshold level
ACT Timer Protection enable except ACTTEMPTH[4:0] = 0x00
ACTTEMPTH = 0x00 equal to ACTPROT_OFF = 1
By writing value 0x00, ACTTIMER_PROT flag is cleared.
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8.6.4.13 REG73 8-Bit Control Register for Parm0 (offset = 73h)
Figure 26. REG73 8-Bit Control Register for Parm0
7
6
5
4
3
2
1
0
SIF_TIMEOUT_TH
SLEDEND
_HZTIME
SLDENDTH
rw-0
STPEND
_HZTIME
STPENDTH
rw-0
rw-0
rw-0
rw-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 19. REG73 8-Bit Control Register for Parm0 Field Descriptions
BIT
FIELD
TYPE
RESET
DESCRIPTION
7-6
SIF_TIMEOUT_TH
RW
0h
Watch dog timer for Serial communication
0h = Disable
1h = 1 ms
2h = 100 µs
3h = 10 µs
Set SIF_TIMEOUTERR (REG7D) if communication is suspended for this
time period. Reset register processing is performed if a SIF_TIMEOUTERR
occurs.
5
SLEDEND_HZTIME
SLDENDTH
RW
RW
0h
0h
Time window for sled end detection.
0h = 400 µs
1h = 200 µs
Note: The user must recycle SLD_ENDDET_ENA = 0 → 1 after writing this
bit.
4-3
Sled end detection sensibility setting. Detection threshold for motor BEMF
00: 124 mV
01: 168 mV
11: 72 mVꢀ
10: 0 mV (use for test purpose)
2
STPEND_HZTIME
STPENDTH
RW
RW
0h
0h
Step High-Z detection period in end detection
0h = 400 µs
1h = 200 µs
Note: The user must recycle STP_ENDDET_ENA = 0→1 after writing this
bit.
1-0
Step end detection sensibility setting
00: 39 mV
01: 61 mV
11: 19 mV
10: 0 mV (use for test purpose)
30
Copyright © 2015, Texas Instruments Incorporated
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ZHCSEQ4 –JULY 2015
8.6.4.14 REG74 8-Bit Control Register for SIFCfg (offset = 74h)
Figure 27. REG74 8-Bit Control Register for SIFCfg
7
6
5
4
3
2
1
0
DIFF_TLT
Reserved
STATUS_ON
_VFCS
VSLD2_POL
VSTP2_POL
ADVANCE_RD
SOMI_HIZ
VDAC_MAPSW
rw-0
rw-0
rw-0
rw-0
rw-0
rw-0
rw-0
rw-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 20. REG74 8-Bit Control Register for SIFCfg Field Descriptions
BIT
FIELD
TYPE
RESET
DESCRIPTION
7
DIFF_TLT
RW
0h
1h = Differential tilt mode enable (with TLT_ENA = FCS_ENA = 1)
Differential tilt mode (DIFF_TLT = 1), DAC value setting as follows
FCS_OUT = (VFCS + VTLT) × 6 / 2048
TLT_OUT = (VFCS – VTLT) × 6 / 2048
In DIFF_TLT mode (DIFF_TLT = 1), TLT_OUT should be changed after
writing VFCS.
6
5
Reserved
RW
RW
0h
0h
STATUS_ON_VFCS
Set Read status data (REG7F) at VFCS write command (REG02)
1h = enable Write and Read mode
(Write 12 bits Focus DAC data + Read 8 bits status data)
Change direction of SLED rotation
4
3
2
VSLD2_POL
VSTP2_POL
ADVANCE_RD
RW
RW
RW
0h
0h
0h
Change direction of STEP rotation
0h = Normal read timing
1h = Read timing is advanced half clock cycle
1
0
SOMI_HIZ
RW
RW
0h
0h
0h = SOMI line High-Z at bus idling time.
1h = SOMI line Pull down at bus idling time.
VDAC_MAPSW
1h = Change channel assignments of DAC register (REG01~0A)
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8.6.4.15 REG75 8-Bit Control Register for Parm1 (offset = 75h)
Figure 28. REG75 8-Bit Control Register for Parm1
7
6
5
4
3
2
1
0
TRAY_LOCKDET
Reserved
rw-0
SPM_FAST
_BRK
SPM_SLNT
_BRK
SPM
_HIZMODE
rw-0
rw-0
rw-0
rw-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 21. REG75 8-Bit Control Register for Parm1 Field Descriptions
BIT
FIELD
TYPE
RESET
DESCRIPTION
7-5
TRAY_LOCKDET
RW
0H
Load tray locking detection control
0h = Disable detection
1-7: Detection threshold
1h = 100 mA
2h = 150 mA
3h = 200 mA
4h = 250 mA
5h = 300 mA
6h = 350 mA
7h = 400 mA
4-3
2
Reserved
RW
RW
0h
0h
SPM_FAST_BRK
Fast brake mode selection
0h = Normal brake mode perform auto short brake sequence in
specific speed
1h = No short brake under 5500 rpm
1
0
SPM_SLNT_BRK
SPM_HIZMODE
RW
RW
0h
0h
Silent brake mode selection
0h = Normal brake mode
1h = No active brake under 5500 rpm
Active brake mode is not performed inputting any value into
VSPIN.
Spindle output Hi-Z mode
0h = Normal operation
1h = Spindle output (UVW) put Hi-Z (use for test purpose)
8.6.4.16 REG76 8-Bit Control Register for WriteEna (offset = 76h)
Figure 29. REG76 8-Bit Control Register for WriteEna
7
6
5
4
3
2
1
0
WRITE_ENABLE
rw-0
Reserved
rw-0
REG6X_Write
rw-0
Reserved
rw-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 22. REG76 8-Bit Control Register for WriteEna Field Descriptions
BIT
FIELD
TYPE
RESET
DESCRIPTION
7
WRITE_ENABLE
RW
0h
0h = Register Write disable except REG76
1h = Write enable for registers REG01~09, REG70~7F
6-2
1
Reserved
RW
RW
0h
0h
REG6X_Write
0h = Disable Write access REG6X bank
1h = Enable Write access REG6X bank
32
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ZHCSEQ4 –JULY 2015
8.6.4.17 REG77 8-Bit Control Register for ClrReg (offset = 77h)
Figure 30. REG77 8-Bit Control Register for ClrReg
7
6
5
RST_ERR_FLAG
w-0
4
3
2
1
0
RST_INDAC
w-0
RST_REGS
w-0
Reserved
w-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 23. REG77 8-Bit Control Register for ClrReg Field Descriptions
BIT
FIELD
TYPE
RESET
DESCRIPTION
7
RST_INDAC
W
0h
1h = Reset all 12-bit input DAC register (REG01~09)
*Self clear bit
6
5
RST_REGS
RST_ERR_FLAG
Reserved
W
W
W
0h
0h
0h
1h = Reset all 8-bit R/W registers (REG70h~77h, 60h-6Fh)
*Self clear bit
1h = Reset fault flag latch (REG7F, REG79~REG7D)
*Self clear bit
4-0
8.6.4.18 REG78 8-Bit Control Register for ActTemp (offset = 78h)
Figure 31. REG78 8-Bit Control Register for ActTemp
7
6
5
4
3
2
1
0
Reserved
r-0
ACT_TIMER
_PROT
ACTTEMP
r-0
r-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 24. REG78 8-Bit Control Register for ActTemp Field Descriptions
BIT
7-6
5
FIELD
TYPE
RESET
0h
DESCRIPTION
Reserved
R
R
ACT_TIMER_PROT
0h
ACT timer protection flag
1h = ACT Timer Protection has detected and latched.
(ACTTEMP > ACTTEMPTH)
This bit holds data after temperature change to low since this is a latch bit.
Also driver output keep Hi-Z until setting RST_ERR_FLAG or ACTTEMPTH
= 0.
4-0
ACTTEMP
R
0h
An integrated value of ACT_TIMER counters at present.
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8.6.4.19 REG79 8-Bit Control Register for UVLOMon (offset = 79h)
Figure 32. REG79 8-Bit Control Register for UVLOMon
7
LIN9V_RDY
r-0
6
RCD_BRK
r-0
5
UVLO_P5V
r-0
4
UVLO_INT3P3
r-0
3
UVLO_P12V
r-0
2
UVLO_SIOV
r-0
1
OVP_P5V
r-0
0
OVP_P12V
r-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 25. REG79 8-Bit Control Register for UVLOMon Field Descriptions
BIT
7
FIELD
TYPE
R
RESET
0h
DESCRIPTION
LIN9V_RDY
RCD_BRK
UVLO_P5V
UVLO_INT3P3
UVLO_P12V
UVLO_SIOV
OVP_P5V
LIN9V output status. LINFB voltage over 92% (typical) of target voltage.
6
R
0h
(1)
5
R
0h
UVLO flag for detection Low P5V supply
UVLO flag for detection Low internal 3.3-V regulator(1)
4
R
0h
(1)
3
R
0h
UVLO flag for detection Low P12V supply
(1)
2
R
0h
UVLO flag for detection Low SIOV supply
(1)
1
R
0h
OVP flag for P5V supply
(1)
0
OVP_P12V
R
0h
OVP flag for P12V supply
(1) Latched first reset event only. Cleared by RST_ERR_FLG (REG77)
8.6.4.20 REG7A 8-Bit Control Register for TSDMon (offset = 7Ah)
Figure 33. REG7A 8-Bit Control Register for TSDMon
7
6
5
4
3
2
1
0
Reserved
TSD_FAULT
_SPM
TSD_FAULT
_ACT
TSD_FAULT
_P12DCHG
Reserved
TSD_SPM
TSD_ACT
TSD_
P12DCHG
r-0
r-0
r-0
r-0
r-0
r-0
r-0
r-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 26. REG7A 8-Bit Control Register for TSDMon Field Descriptions
BIT
7
FIELD
TYPE
RESET
0h
DESCRIPTION
Reserved
R
R
R
6
TSD_FAULT_SPM
TSD_FAULT_ACT
0h
Prealert of thermal protection of Spindle block(1)
5
0h
Prealert of thermal protection of focus /track /tilt sled1 /sled2 /step1
/step2 /load(1)
(1)
4
3
2
TSD_FAULT_P12DCHG
Reserved
R
R
R
0h
0h
0h
Prealert of thermal protection of P12V discharge block
Thermal protection flag for spindle(1)
SPM output Hi-Z until temperature falls on release level
1h = Detect (latch)
TSD_SPM
1
0
TSD_ACT
R
R
0h
0h
Thermal protection flag for focus /track /tilt sled1 /sled2 /step1 /step2
/load(1)
Actuator output Hi-Z until temperature falls on release level
1h = Detect (latch)
Thermal protection flag for P12V discharge block(1)
IDCHG output Hi-Z until temperature falls on release level
1h = Detect (latch)
TSD_ P12DCHG
(1) Cleared by RST_ERR_FLAG bit (REG77)
34
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ZHCSEQ4 –JULY 2015
8.6.4.21 REG7B 8-Bit Control Register for SCPMon (offset = 7Bh)
Figure 34. REG7B 8-Bit Control Register for SCPMon
7
6
Reserved
r-0
5
4
SCP_SPM
r-0
3
SCP_SLED
r-0
2
SCP_LOAD
r-0
1
SCP_ACT
r-0
0
SCP_STP
r-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 27. REG7B 8-Bit Control Register for SCPMon Field Descriptions
BIT
7-5
4
FIELD
TYPE
RESET
0h
DESCRIPTION
Reserved
SCP_SPM
SCP_SLED
SCP_LOAD
SCP_ACT
SCP_STP
R
R
R
R
R
R
0h
Short protection flag bit for spindle block(1)
Short protection flag bit for sled block(1)
Short protection flag bit for load block(1)
Short protection flag bit for Actuator block(1)
Short protection flag bit for step block(1)
3
0h
2
0h
1
0h
0
0h
(1) Cleared by RST_ERR_FLAG bit (REG77)
8.6.4.22 REG7C 8-Bit Control Register for TempMon (offset = 7Ch)
Figure 35. REG7C 8-Bit Control Register for TempMon
7
6
5
4
3
2
1
0
CHIPTEMP
_STATUS
CHIPTEMP
r-0
r-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 28. REG7C 8-Bit Control Register for TempMon Field Descriptions
BIT
FIELD
TYPE
RESET
DESCRIPTION
7
CHIPTEMP_STATUS
R
0h
1h = New data CHIPTEMP[6:0] is updated It will be cleared after reading.
6-0
CHIPTEMP
R
0h
Chip temperature monitor (1.2°/LSB)
15° (0) to 165° (127)
For monitoring, TEMPMON_ENA = 1 and XSLEEP = 1 is required
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8.6.4.23 REG7D 8-Bit Control Register for Status Monitor (offset = 7Dh)
Figure 36. REG7D 8-Bit Control Register for Status Monitor
7
6
5
4
3
2
1
0
SIF
_TIMEOUTER
R
XRSTIN_DET
Reserved
TRAY
_LOCKDETEC
T
TRAY
_PUSHDETP
TRAY
_PUSHDETN
STP_ENDDET SLD_ENDDET
r-0
r-0
r-0
r-0
r-0
r-0
r-0
r-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 29. REG7D 8-Bit Control Register for Status Monitor Field Descriptions
BIT
FIELD
TYPE
RESET
DESCRIPTION
7
SIF_TIMEOUTERR
R
0h
Error flag of serial I/F watch dog timer
1h = SIF communication was interrupted, expired watch dog timer
6
XRSTIN_DET
R
0h
XRSTIN event flag
1h = Detect low event in XRSTIN pin
5
4
Reserved
R
R
0h
0h
TRAY_LOCKDETECT
TRAY lock detection flag
1h = Detect tray lock detection
3
2
1
0
TRAY_PUSHDETP
TRAY_PUSHDETN
STP_ENDDET
R
R
R
R
0h
0h
0h
0h
TRAY push event detection flag in LOAD_P pin
1h = Detect tray push event in LOAD_P pin
TRAY push event detection flag in LOAD_N pin
1h = Detect tray push event in LOAD_N pin
Step end event flag
1h = Detect step end event
SLD_ENDDET
Sled end event flag
1h = Detect sled end event
8.6.4.24 REG7E 8-Bit Control Register for Version (offset = 7Eh)
Figure 37. REG7E 8-Bit Control Register for Version
7
6
5
4
3
2
1
0
Version
r-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 30. REG7E 8-Bit Control Register for Version Field Descriptions
BIT
FIELD
TYPE
RESET
DESCRIPTION
7-0
Version
R
0h
Version[7:4] = revision number of TPIC2060A
Version[3:0] = option
36
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ZHCSEQ4 –JULY 2015
8.6.4.25 REG7F 8-Bit Control Register for Status (offset = 7Fh)
Figure 38. REG7F 8-Bit Control Register for Status
7
6
5
4
3
2
1
0
ACTTIMER
_FAULT
MONITOR
Reserved
PWRERR
TSDERR
SCPERR
TSDFAULT
FG
r-0
r-0
r-0
r-0
r-0
r-0
r-0
r-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 31. REG7F 8-Bit Control Register for Status Field Descriptions
BIT
FIELD
TYPE
RESET
DESCRIPTION
7
ACTTIMER_FAULT
R
0h
Status flag of ACTTIMER protection
1h = Prealert of ACTTIMER protection. It is close to the threshold level.
The user can get current ACTTIMER value in REG78.
Both this bit and ACT_TIMER_PROT (REG78) will be set when over the
threshold.
6
MONITOR
R
0h
Event flag of any monitor event in REG7D
1h = Event occurred, details in REG7Dh
5
4
Reserved
PWRERR
R
R
0h
0h
Error flag of power
1h = Voltage problem occurred, details in REG79
3
2
1
0
TSDERR
SCPERR
TSDFAULT
FG
R
R
R
R
0h
0h
0h
0h
Error flag of any overthermal protections
1h = Dispatched thermal protection, details in REG7A
Error flag of any SCP
1h = Dispatched SCP, details in REG7Bh
Warning of TSD of any thermal protection
1h = Detect pre-thermal protection, details in REG7A
FG signal. Spindle rotation pulse for speed monitor
8.6.4.26 REG60 8-Bit Control Register for SPMCfg (offset = 60h)
Figure 39. REG60 8-Bit Control Register for SPMCfg
7
6
5
4
3
2
1
0
Reserved
FG_SBRK
_OFF
Reserved
rw-0
IS_NZONE
_OFF
Reserved
rw-0
rw-0
rw-0
rw-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 32. REG60 8-Bit Control Register for SPMCfg Field Descriptions
BIT
7
FIELD
TYPE
RW
RW
RW
RW
RW
RESET
0h
DESCRIPTION
Reserved
6
FG_SBRK_OFF
Reserved
0h
FG Jitter setting in short brake period. Should be set to 1
Inductive position sense (IS) timing control. Should be set to 1
5-2
1
0h
IS_NZONE_OFF
Reserved
0h
0
0h
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8.6.4.27 REG61 8-Bit Control Register for SPMCfg (offset = 61h)
Figure 40. REG61 8-Bit Control Register for SPMCfg
7
6
5
4
3
2
1
0
Reserved
rw-0
PWMmaxDuty
_R_SEL
Reserved
rw-0
rw-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 33. REG61 8-Bit Control Register for SPMCfg Field Descriptions
BIT
7-2
1
FIELD
TYPE
RW
RESET
0h
DESCRIPTION
Reserved
PWMmaxDuty_R_SEL
RW
0h
PWM duty maximum setting in active brake mode
0h = Maximum PWM duty 12.5%
1h = Maximum PWM duty 25%
(Recommend to set 0 if using in no-disk because it may not stop in a
specific motor setting 25%.)
0
Reserved
RW
0h
8.6.4.28 REG62 8-Bit Control Register for SPMCfg (offset = 62h)
Figure 41. REG62 8-Bit Control Register for SPMCfg
7
6
5
4
3
2
1
0
Reserved
rw-0
TIME_BASE_SEL
rw-0
Reserved
rw-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 34. REG62 8-Bit Control Register for SPMCfg Field Descriptions
BIT
7-4
3-2
1-0
FIELD
TYPE
RW
RESET
0h
DESCRIPTION
Reserved
TIME_BASE_SEL
Reserved
RW
0h
Spindle waveform selection. Should be set to 11
RW
0h
8.6.4.29 REG64 8-Bit Control Register for Protect (offset = 64h)
Figure 42. REG64 8-Bit Control Register for Protect
7
6
5
4
3
2
1
0
Reserved
rw-0
FG5M_OFF
rw-0
Reserved
rw-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 35. REG64 8-Bit Control Register for Protect Field Descriptions
BIT
7-4
3
FIELD
TYPE
RW
RESET
0h
DESCRIPTION
Reserved
FG5M_OFF
Reserved
RW
0h
Spindle FG filter selection. Should be set to 1
2-0
RW
0h
38
Copyright © 2015, Texas Instruments Incorporated
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ZHCSEQ4 –JULY 2015
8.6.4.30 REG65 8-Bit Control Register for SPMCfg (offset = 65h)
Figure 43. REG65 8-Bit Control Register for SPMCfg
7
6
5
4
3
2
1
0
Reserved
rw-0
HZSVR_SEL
rw-0
Reserved
rw-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 36. REG65 8-Bit Control Register for SPMCfg Field Descriptions
BIT
7-5
4-3
2-0
FIELD
TYPE
RW
RESET
0h
DESCRIPTION
Reserved
HZSVR_SEL
Reserved
RW
0h
Spindle waveform silent mode selection. Should be set to 11
RW
0h
8.6.4.31 REG68 8-Bit Control Register for Protect (offset = 68h)
Figure 44. REG68 8-Bit Control Register for Protect
7
6
5
4
3
2
1
0
Reserved
rw-0
SPM_TQAJST
rw-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 37. REG68 8-Bit Control Register for Protect Field Descriptions
BIT
7-2
1-0
FIELD
TYPE
RW
RESET
0h
DESCRIPTION
Reserved
SPM_TQAJST
RW
0h
Select fine adjust value of spindle limit current which is set by
SPM_RCOM_SEL
00: No adjust
01: –5%
10: –10%
11: –15%
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8.6.4.32 REG6B 8-Bit Control Register for DisProt (offset = 6Bh)
Figure 45. REG6B 8-Bit Control Register for DisProt
7
6
5
4
3
2
1
0
SCP_SPM
_OFF
SCP_SLED
_OFF
SCP_LOAD
_OFF
SCP_ACT
_OFF
SCP_STP_OFF SPM_RCDDIS
Reserved
rw-0
rw-0
rw-0
rw-0
rw-0
rw-0 rw-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 38. REG6B 8-Bit Control Register for DisProt Field Descriptions
BIT
FIELD
TYPE
RESET
DESCRIPTION
7
SCP_SPM_OFF
RW
0h
Control bit of SCP function for spindle block.
0h = Enable SCP function
1h = Disable SCP function
Caution(1) TI recommends using it only for test purposes.
6
5
4
3
2
SCP_SLED_OFF
SCP_LOAD_OFF
SCP_ACT_OFF
SCP_STP_OFF
SPM_RCDDIS
RW
RW
RW
RW
RW
0h
0h
0h
0h
0h
For Sled driver block.
Caution(1) TI recommends using it only for test purposes.
For Load driver block
Caution(1) TI recommends using it only for test purposes.
For Actuator driver block
Caution(1) TI recommends using it only for test purposes.
For Step driver block
Caution(1) TI recommends using it only for test purposes.
Spindle block reverse current detect function.
0h = Enable
1h = Disable
1-0
Reserved
RW
0h
(1) Caution: Device will be fatally damaged if short circuit occurs in the xxx_OFF = 1.
8.6.4.33 REG6C 8-Bit Control Register for ENDCfg (offset = 6Ch)
Figure 46. REG6C 8-Bit Control Register for ENDCfg
7
6
5
4
3
2
1
0
PUSHDETTH
rw-0
PUSHDET_TIME
rw-0
Reserved
rw-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 39. REG6C 8-Bit Control Register for ENDCfg Field Descriptions
BIT
FIELD
TYPE
RESET
DESCRIPTION
7-6
PUSHDETTH
RW
0h
Detection voltage threshold for PUSH detection
00: Disable function
01: 1 V
10: 0.75 V
11: 0.5 V
5-4
3-0
PUSHDET_TIME
RW
RW
0h
0h
Duration of PUSH detection
00: 104 ms
01: 208 ms
10: 416 ms
11: 0 ms (immediately at the exceeding threshold)
Reserved
40
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8.6.4.34 REG6E 8-Bit Control Register for UtilCfg (offset = 6Eh)
Figure 47. REG6E 8-Bit Control Register for UtilCfg
7
6
5
4
3
2
1
0
GPOUT_HL
rw-0
GPOUT_ENA
rw-0
Reserved
rw-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 40. REG6E 8-Bit Control Register for UtilCfg Field Descriptions
BIT
FIELD
TYPE
RESET
DESCRIPTION
7
GPOUT_HL
RW
0h
General-purpose output (GPOUT) pin output selection
0h = Low output
1h = High output
Valid only if REG6F = 00h
6
GPOUT_ENA
Reserved
RW
RW
0h
0h
Enable monitor signal output to GPOUT pin
0h = No signal output, Hi-Z
1h = Output signal selected in REG6F with CMOS output
Output is logical OR when selected two more signals
5-0
8.6.4.35 REG6F 8-Bit Control Register for GPOUTSet (offset = 6Fh)
Figure 48. REG6F 8-Bit Control Register for GPOUTSet
7
6
5
4
3
2
1
0
ACTTIMER
_FLT_MON
MONITOR
_MON
Reserved
PWRERR
_MON
TSDERR_MON SCPERR_MON
TSDFAULT
_MON
SPMRCD
_BRK_MON
rw-0
rw-0
rw-0
rw-0
rw-0 rw-0
rw-0
rw-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 41. REG6F 8-Bit Control Register for GPOUTSet Field Descriptions
BIT
7
FIELD
TYPE
RW
RW
RW
RW
RW
RW
RW
RW
RESET
0h
DESCRIPTION
ACTTIMER_FLT_MON
MONITOR_MON
Reserved
1h = ACTTIMER fault output to GPOUT pin
1h = ENDDET monitor output to GPOUT pin
6
0h
5
0h
4
PWRERR_MON
TSDERR_MON
SCPERR_MON
TSDFAULT_MON
SPMRCD_BRK_MON
0h
1h = PWRERR monitor output to GPOUT pin
1h = TSDERR fault output to GPOUT pin
1h = SCPERR fault output to GPOUT pin
1h = TSDFAULT fault output to GPOUT pin
1h = SPMRCD_BRK fault output to GPOUT pin
3
0h
2
0h
1
0h
0
0h
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
9.1.1 DAC Type
The TPIC2060A has nine-channel drivers and each channel is assigned to the most suitable DAC engine with a
different type. ACT (FCS/TRK/TLT) has a 12-bit DAC. The upper 8 (MSB sign bit) are sampled in 5 MHz, and
LSB 4 bits are output in sequence with 1.25-MHz PWM. SPIN and load DAC have the same types and sampling
rate with 312 kHz. The SPM channel has 14× gain, and other channels (except SLED and STP) have 6× gain.
The DAC for STP is 8-bit resolution output with 40-kHz PWM, and no feedback. The gain for STP is 5× relative
to P5V voltage. Table 42 shows the configuration of each driver.
Table 42. DAC Type
FCS/TRK/TLT
12 bit
SLED
SPIN
LOAD
STP
Resolution
Type
10 bit
12 bit
12 bit
8 bit
8-bit oversampling
10-bit voltage DAC
8-bit oversampling
8-bit oversampling
1-bit direct duty PWM
1.25M / 10 bit
312K / 12 bit
Sampling
312K
312K
40 kHz
About 156 kHz
(variable)
PWM frequency
Out range
312 kHz
±6 V
156 kHz
±14 V
312 kHz
±6V
40 kHz
±880 mA
±(P5V*1)
Power supply
compensation
Voltage F/B shared
with TRK
Feedback
Voltage F/B
Current F/B
Direct PWM No F/B
9.1.2 Example of 12-Bit DAC Sampling Rate for FCS/TRK/TLT
The input data is separated in the upper 8 bits and the lower 4 bits. Upper 8 bits (MSB sign 1 bit) are put into 8-
bit current DAC in every 5 MHz. The lower 4 bits are put into one bit current DAC in sequence from upper to
lower bit. This is a one-bit DAC output with PWM in 1.25 MHz. Any PWM duty, 100%, 75%, 50%, 25%, or 0%, is
summed in 8-bit current DAC every 1.25 MHz. Thus, it takes 3.2 µs for all lower 4 bits summing to the PWM
output. As a result, 12-bit data is sampled in every PWM cycle. Figure 49 shows an example of the sampling rate
for FCS/TRK/TLT.
42
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WriteDAC
5 MHz
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
1.25 MHz
625 KHz
10bit
10bit
10bit
10bit
11bit
11bit
312 KHz
12bit
LSB 4bit width
PWM duty
12bit DAC(8bit DAC+ 4bit PWM DAC) output
one PWM cycle (312 KHz = 3.2us)
Figure 49. Example of 12-Bit DAC Conversion Time (FCS/TRK/TLT)
9.1.3 Digital Input Coding
The output voltage (current) is commanded through programming to the DAC. All of the DAC input format is 12
bit in complements of 2's, though some DAC has a low resolution. When 12 bits of data is input as 8-bits DAC,
the TPIC2060A recognizes four subordinate position bits (LSB) as 0. To arrange for 12-bit DAC format, DSP
should shift 8-bit or 10-bit data to an appropriate bit position. The full scale is ±1.0 V and driver gain is set to 6 or
14. The output voltage (Vout) is given by the following equation:
6.0
Vout = DACcode ì
2048
14.0
VSPMout = DACcode ì
2048
Calculation by fixed point number :
Vdac = 1.0 ì bit[10] ì 0.51 + bit[9] ì 0.52 + bit[8] ì 0.53 + ... + bit[0] ì 0.511
(
)
Vdac = (œ1.0) ì bit[10] ì 0.51 + bit[9] ì 0.52 + bit[8] ì 0.53 + ... + bit[0] ì 0.511 + 0.512
(
)
Vout = Vdac ì 6.0 (V)
VSPMout = Vdac ì 14.0 (V)
STPVout = Vdac ì (P5V) (V)
SLEDIout = Vdac ì 0.88 (A)
where bit[11:0] is the digital input value, range 000000000000b to 111111111111b
(3)
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Table 43. DAC Format
MSB Digital input (BIN) LSB
1000_0000_0000
1000_0000_0001
1111_1111_1111
0000_0000_0000
0000_0000_0001
0111_1111_1110
0111_1111_1111
Hex
Dec
–2048
–2047
–1
Vdac
–0.9995
–0.9995
–0.0005
0
Analog Output (5 V)
–5.997
Analog Output (12 V)
–13.993
–13.993
–0.007
0x800
0x801
0xFFF
0x000
0x001
0x7FE
0x7FF
–5.997
–0.003
0
0.000
0.000
1
0.0005
0.9990
0.9995
0.003
0.007
2046
2047
5.994
13.986
5.997
13.993
Analog output(V)
VDAC
+ 1.000
+6.0 / + 14.0
+5.0 / + 12.0
*
800h
7FFh
DACcode
000
-5.0 / -12.0
-6.0 / -14.0
*
-1.000
* follow ing P5V, P12V inp u t voltag e
Figure 50. Output Voltage vs DAC Code
9.1.4 Example Timing of Target Control System
The TPIC2060A is designed to meet the requirements for updating control data in 400 kHz. Table 44 lists an
example of a control system parameter. It takes 0.51 µs to transmit a 16-bit data packet to the TPIC2060A with a
35-MHz SCLK. Therefore, DSP can be sent four packets at 400-kHz intervals. If the SCLK is lower than 28.8
MHz, the user must reduce packet quantity to less than three. For example, the Focus/Truck command updates
every 2.5 µs (400 kHz), and can send another two kinds of packets during this time. Figure 51 shows an
example of the control timing when using the TPIC2060A.
Table 44. Example Timing of Target Control System
UPDATE CYCLE
SIGNAL
BIT
(kHz)
400
400
100
100
100
100
—
Focus
Track
Tilt
12
12
12
10
10
12
12
8
Sled1
Sled2
Spindle
Load
Step1
Step2
40
8
40
44
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312 kHz /3.2 µs (PW M 1 cycle)
Track
Focus
Tilt
R
R
R
R
R
Sled1
Sled2
SPM
Load
Step1
Step2
400 kHz / 2.5 µs
Control
register
100KHz /10us (1control cycle)
PWM cycle
DACcommand
R
DACcommand with statusread
Control register command
0.51 µs (SCLK: 35 MHz) for data transmit
Figure 51. Example DAC Control
9.1.5 Spindle Motor Driver Operating Sequence
When the VSPM is set to a positive DAC code, it goes into acceleration mode. Initial position sense (IS) mode
then operates, the start-up circuits offer a start-up pattern sequence to the driver, and then switch to spin-up
mode by detecting the rotor position through BEMF signal from the spindle motor coil.
The spin-down and brake functions are also controlled by the DAC value, VSPM. When the brake command to
VSPM is set, the driver goes into active-brake mode, switches to short-brake mode in slow revolution speed, and
then stops automatically. The FG signal is composed from EXOR of a three-phase signal and is output from XFG
pin shown in Figure 52.
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RDY
XRSTIN
WRITE_ENABLE
XSLEEP
SPM_ENA
VSPM
XFG
VSPM[11:0] > 0
VSPM[11:0] < 0
0
brake
speed
>15ms
release
300ms
260rpm
time
Figure 52. Spindle Operating Sequence
Use the down-edge of the FG signal for monitoring the FG frequency.
Short brake mode is asserted after 300 ms of FG signal stays L-level in deceleration.
This value is the nominal number of using a 12-pole motor.
9.1.6 Auto Short Brake Function
The TPIC2060A provides an auto short brake function that selects the brake mode automatically by motor speed.
The auto short brake is an intelligent brake function that includes two modes, short brake and active brake. If a
value of 0xF90 or less is set to VSPM, brake mode automatically changes at rotation speed. This function
enables low-power consumption and silent braking. Table 45 shows the relation between brake mode and speed.
The overspeed protection function suspends the SPM driver output at 15000 or more revolutions.
Table 45. Brake Mode
ROTATION SPEED (RPM)(1)
VSPM[11:0]
MODE
ABOUT 11500
ABOUT 11500 TO 5600 ABOUT 5600 TO 4000
2-phase short brake
ABOUT 4000 TO 0
0x000 - 0xFDD
0xFDC - 0xF90
0xF8F - 0xADB
0xADA - 0x800
Manual
Manual
Active brake
Auto short
Auto short
Free run
Free run
3-phase short brake(2)
3-phase short brake(3)
Active brake
Active brake
(1) Typical value using 12-pole motor.
(2) Active brake is chosen when it does not exceed 6400 rpm once from a rotation start.
(3) Active brake is chosen when it does not exceed 4600 rpm once from a rotation start.
46
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rpm
Hi-Z (overspeed protection)
Free run
15600
*1
11500
3-phase short
2-phase
short
auto
5600
4000
*1
auto
Active
(selectable 3-phase short)
0
800h
ADBh
F90h FDDh000
VSPM[11:0]
A. 1* = Each threshold value has hysteresis. Brake mode changes to a specific mode at the threshold speed when it
reaches a speed about 15% higher than the threshold speed. These speed values are the nominal number of using a
12-pole motor. In applying to the 16-pole motor, the rotations speed becomes 75% of indicated rpm values.
Figure 53. Brake Mode
9.1.7 Spindle PWM Control
The output PWM duty of the spindle is controlled by DAC code (VSPM). The gain in acceleration setting is
always 14 times, while the maximum output is restricted to P12V voltage. A dead band which outputs = 0 exists
in the width of plus or minus 0x52, focusing on zero.
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PW M outputduty
100%
output (V)
P12V
(PWMmax
Duty_R_SEL)
dead band
duty= 0%
25.0%
12.5%
speed up
slow down
0%
800h
FAEh
000
52h
7FFh
VSPM[11:0]
Figure 54. Spindle PWM Control
9.1.8 Spindle Driver Current Limit Circuit
This IC builds in the SPM current sense resistor, which can select the resistor value. The spindle current limit
circuit monitors motor current (which flows through this resistance) and limits the output current by reducing
PWM duty when detecting overcurrent conditions. Table 46 shows resistor value. A limit current value can be
calculated from following formula, where the resistor value is the equivalent resistance for a current limit
calculation:
Limit current = 160 mV / resistor value
(4)
Table 46. SPM Current Sense Resistor
RESISTANCE
LIMIT CURRENT
SPM_RCOM_SEL[1:0]
VALUE (Ω)(1)
(mA)
1133
772
00
01
10
11
0.15
0.22
0.12
0.10
1416
1700
(1) The equivalent resistance for current limit calculation.
48
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9.1.9 Sled Driver Part
The sled driver outputs the PWM pulse set as DAC code (VSLDx) with current feedback. The maximum output is
restricted to 880 mA at 0x7FF and 0x800. A dead band with output = 0 exists in the width of plus or minus 0x1F
focusing on zero.
outputcurrent
reverse
forw ard
880m A
dead band
ISLEDxP
= ISLEDxN
ISLEDxP < ISLEDxN
ISLEDxP > ISLEDxN
0
FE0h
1Fh
800h
000
7FFh
VSLDx[11:0]
Figure 55. Sled Output Current
Both outputs of SLED1/2 are 'L' when the input code is in the dead band.
9.1.10 Stepping Driver Part
The step driver outputs the PWM pulse set as 8-bit DAC code (VSTPx) using VSTP[11:4]. There is no feedback
monitor for output. The pulse duration according to the P5V power supply voltage is outputted.
outputPW M duty
flow STPxN→STPxP
flow STPxP→STPxN
100%
dutySTPxN
dutySTPxP
0%
FF0h
020h
800h
000
VSTPx[11:4]
Figure 56. Step Output Duty
7F0h
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9.1.11 Focus/Track/Tilt Driver Part
9.1.11.1 Input VS Output Duty
PW M output duty
100%
P5V
reverse
forw ard
ACT+ < ACT-
ACT+ > ACT-
0%
800h
000
7FFh
ACT(FCS/TRK/TLT)[11:0]
Figure 57. FCS/TRK/TLT Output Duty
9.1.12 Load Driver Part
The load driver outputs the voltage, with voltage feedback corresponding to the input DAC value. This channel
has power voltage compensation and therefore is suited for slot-in type load control. This channel becomes
active exclusively to other actuator channels. The load driver is shared with the TRK driver.
PW M output duty
reverse
forw ard
P5V/P12V
100%
deadband
LOAD+
= LOAD-
LOAD+<LOAD-
LOAD+>LOAD-
0%
800h
FE0h 000 01Fh
VLOAD[11:0]
7FFh
Figure 58. Load Output Duty
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9.1.13 End Detect Function
This device has the function of end position detection for sled and collimator lens. This function eliminates the
position switch at the PUH inner and collimator lens end position. Sled channel and step channel can be used
independently by setting XXX_ENDDET_ENA = 1. When this function is enabled, internal logic detects the sled
out zero-cross point, then the internal BEMF detect circuit measures the BEMF level of the stepping motor. There
are four threshold levels. If the BEMF is lower than the selected threshold, the device causes the motor to stop
and sets the XXX_ENDDET bit to 1. The ENDDET bit is then cleared at the BEMF voltage exceed threshold.
SLD_ ENA= 1, SLD_ ENDDET_ ENA= 1
I-SLED1
I-SLED2
BEMF1
BEMF2
motorstop
SLD_ ENDDET
1
Figure 59. Timing of Sled End Detection
STP_ ENA= 1, STP_ ENDDET_ ENA= 1
1
STP_ ENDDET
STP1
STP2
Step m otor
BEMF1
BEMF2
deadend
Figure 60. Timing of Step End Detection
9.1.14 Load Tray Lock Detect Function
The tray lock detect function detects inserted obstacles at the time of tray opening and closing, using the load
motor BEMF. The user must adjust the TRAY_LOCKDET [2:0] for the optimal threshold level by the
characteristics of the motor. By setting TRAY_LOCKDET, the user can select a threshold level from 100 to 400
mA, with a 50-mA step. Observe the lock detection by reading the TRAY_LOCKDETECT flag where LOAD_ENA
= 1 is set.
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LOAD_ ENA= 1, TRAY_ LOCKDET> 00
1
TRAY_ LOCKDETECT
threshold
(TRAY_ LOCKDET)
(forward)
(reverse)
Load motor
current(filtered)
stop
Figure 61. Load Tray Lock Detect
9.1.15 Load Tray Push Detect Function
The load tray can detect the event of push or pull using the TRAY_PUSHDETx flag. The push detect function
monitors the motor BEMF voltage of LOAD_P and LOAD_N in the LOAD_ENA = 0. If the motor BEMF voltage
exceeds the threshold level, the detection terminal flag is set where the voltage appeared. A detection threshold
is determined by voltage (PUSHDETTH) and time (PUSHDET_TIME). Observe the push event by reading the
TRAY_PUSHDETP or TRAY_PUSHDETN flags, where LOAD_ENA = 0 is set. Because TRAY_PUSHDETx is a
latch flag, it is necessary to reset by RST_ERR_FLAG = 1.
LOAD_ ENA= 0, PUSHD ETTH> 00, PUSHDET_ TIME= xx
1 (latch)
TRAY_ PUSHDETP
threshold
(RST_ERR_FLAG)
(PUSHDETTH)
PUSHDET_TIME
Load m otor BEMF
(reverse)
TRAY_ PUSHDETN
Figure 62. Load Tray Push Detect
9.1.16 Monitor Signal on GPOUT
The device can output a specific signal to the GPOUT pin. To output a signal, choose a signal from REG6F by
enabling first, then enable GPOUT_ENA. When two or more signals are set for GPOUT, an output is a logical
sum.
52
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9.1.17 9-V LDO
The TPIC2060A has a built-in predriver for 9-V LDO. An arbitrary current can be supplied to the LDO by
selecting the external NFET according to required current capacity. LIN9VG output (= NFET gate control) is
controlled to the feedback voltage and LINFB is set as 1.215 V. The 220-nF capacitor for phase compensation is
installed, and the division resistance for FB is chosen so that it may total less than 11 kΩ. Figure 63 shows an
example of external components. The accuracy of the output voltage depends on the tolerance of the resistance.
When not using the LDO, open both LIN9VG and LINFB with LIN9V_DISABLE = 1.
P12V
NFET
ZXMN2A14F
1.215V
LIN9VG
9V
com pensation
220nF(10% 25V)
Storage
0.1 .... 10.1uF(10% 25V)
8.66K(1% )
LINFB
total resistance < 11kohm
1.37K(1% )
Figure 63. Example Circuit of 9-V LDO
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9.2 Typical Application
P5V
10uF
0.1uF
P12V
10uF
0.1uF
1
2
3
4
5
6
7
8
9
SLED1_ P
SLED1_ N
P12V_ SLD
SLED2_ P
SLED2_ N
PGND_ 2
C10V
56 (open)
LINFB 55
LIN9VG 54
SLED COIL1
220nF
9V
IDCHG(TEST) 53 (open)
52 (open)
8.66K
1.37K
10uF 0.1uF
SLED COIL2
0.1uF
AGND
51
50 (open)
MCOM 49
CP1
0.1uF
0.1uF
PGND_ SPM2
CP2
48
47
46
45
44
43
Rdump 1K
Rdump 1K
Rdump 1K
W
10 CP3
GPOUT
XFG
P12V_ SPM2
11 GPOUT
12 XFG
V
PGND_ SPM1
U
READY
13 RDY
14 SSZ
0.1uF
SSZ
SCLK
SIM O
15 SCLK
16 SIMO
17 SOMI
18 SIOV
19 XRSTIN
P12V_ SPM1 42
PGND_ 1 41
FCS_ N 40
FCS_ P 39
TRK_ N 38
TRK_ P 37
TLT_ P 36
SOMI
FOCUS COIL
3.3V
RESETIN
TRACKING COIL
TILT COIL
(open) 20
(open) 21
22 CV3P3
23 AGND/DGND
(open) 24
TLT_ N 35
P5V 34
0.1uF
STP1_ P 33
STP1_ N 32
STP2_ P 31
STP2_ N 30
25 P5V12L
26 LOAD_ N
27 LOAD_ P
28 CA5V
Step COIL1
Step COIL2
0.1uF
10000pF
Load COIL
10000pF
29 (open)
0.1uF
Figure 64. Example of Application Circuit
9.2.1 Design Requirements
To begin the design process, determine the following:
1. Motor configuration. Can use all motor channels or part of them.
2. Usage for 9V LDO predriver. Can be disabled.
3. RDY pin can be connected to Host CPU. Then Host CPU can know the power supply status of TPIC2060A
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Typical Application (continued)
9.2.2 Detailed Design Procedure
After power up on 5V and 12V supply, register can be changed following way and enabling motors.
1. Set WRITE_ENABLE=1 on REG76 via SPI.
2. Set XSLEEP=1 at REG70
3. Enable motor channel by ENA_XXX bits on REG70
4. Change the DAC settings for the motor on REG01-0B. Then output channels start driving load.
9.2.3 Application Curves
100%
90%
80%
70%
60%
50%
40%
30%
20%
10%
0
14
12
10
8
6
4
2
FCS+
FCS-
0
-2047 -1547 -1047 -547
-47
DAC Code
453
953 1453 1953
1.1 1.12 1.14 1.16 1.18 1.2 1.22 1.24 1.26 1.28
LINFB (V)
D001
D002
Figure 65. FCS Driver: DAC Code vs Output On Duty
Figure 66. LDO Control: LINFB vs LIN9VG Output
10 Power Supply Recommendations
All driver channels should be operated after the required power is supplied and stable.
The appropriate capacity of the decoupling capacitor requires a value over 10 μF to reduce the influence of PWM
switching noise. The P5V pin must connect to a 1-μF filter. Place a bypass capacitor (about 0.1 µF) near the
power pin (P5V, P5V12L, P12V_SPM, P12V_SLD) for PWM switching noise reduction on the power and GND
lines.
Current flow to the driver circuits takes both pattern-layout, line-impedance, and noise influence from the supply
line into consideration.
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55
TPIC2060A
ZHCSEQ4 –JULY 2015
www.ti.com.cn
11 Layout
11.1 Layout Guidelines
1. CV3P3V, CA5V, and C10V requires external capacitor. Because these are reference voltage for device,
locate the capacitor as close to device as possible. Keep away from noise source.
2. TI recommends SCLK ground shielding.
3. LINFB is feedback pin for LDO. External divided resistors should be located closer to LINFB pin.
11.2 Layout Example
To MPU
To 3.3-V supply
To MPU
GPOUT
To MPU
XFG
RDY
SSZ
GND Shield
SCLK
To MPU
GND Shield
SIMO
SOMI
To MPU
SIOV
XRTIN
To MPU
To 3.3-V supply
To MPU
GND
A. GND shield is recommend for SCLK.
Figure 67. Layout Example between TPIC2060A and MPU
56
版权 © 2015, Texas Instruments Incorporated
TPIC2060A
www.ti.com.cn
ZHCSEQ4 –JULY 2015
12 器件和文档支持
12.1 社区资源
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.2 商标
E2E is a trademark of Texas Instruments.
Blu-ray is a trademark of Blue-ray Disc Association.
All other trademarks are the property of their respective owners.
12.3 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
12.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 机械、封装和可订购信息
以下页中包括机械、封装和可订购信息。这些信息是针对指定器件可提供的最新数据。这些数据会在无通知且不对
本文档进行修订的情况下发生改变。欲获得该数据表的浏览器版本，请查阅左侧的导航栏。
版权 © 2015, Texas Instruments Incorporated
57
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPIC2060ADFDRG4
ACTIVE
HTSSOP
DFD
56
2000 RoHS & Green
NIPDAU
Level-3-260C-168 HR
-20 to 75
2060A
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
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Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
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Addendum-Page 1
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