TPIC3302_11 [TI]

3-CHANNEL COMMON-DRAIN POWER DMOS ARRAY;
TPIC3302_11
型号: TPIC3302_11
厂家: TEXAS INSTRUMENTS    TEXAS INSTRUMENTS
描述:

3-CHANNEL COMMON-DRAIN POWER DMOS ARRAY

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TPIC3302  
3-CHANNEL COMMON-DRAIN POWER DMOS ARRAY  
SLIS021B – APRIL 1994 – REVISED JULY 1995  
D PACKAGE  
(TOP VIEW)  
Low r  
. . . 0.4 Typ  
DS(on)  
High-Voltage Outputs . . . 60 V  
Pulsed Current . . . 5 A Per Channel  
Fast Commutation Speed  
SOURCE1  
GATE2  
GATE1  
GND  
1
2
3
4
8
7
6
5
SOURCE2  
SOURCE3  
DRAIN  
GATE3  
description  
The TPIC3302 is a monolithic power DMOS array that consists of three electrically isolated N-channel  
enhancement-mode DMOS transistors configured with a common drain and open sources. The TPIC3302 is  
offered in a standard eight-pin small-outline surface-mount (D) package.  
The TPIC3302 is characterized for operation over the case temperature range of 40°C to 125°C.  
schematic  
DRAIN  
6
D1  
Q1  
Q2  
Q3  
8
2
5
Z1  
Z2  
Z3  
GATE1  
GATE2  
GATE3  
7
GND  
1
3
4
SOURCE1  
SOURCE2  
SOURCE3  
absolute maximum ratings over operating case temperature range (unless otherwise noted)  
Drain-to-source voltage, V  
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 V  
DS  
Source-to-GND voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 V  
Drain-to-GND voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 V  
Gate-to-source voltage, V  
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 V  
GS  
Continuous drain current, each output, all outputs on, T = 25°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 A  
Continuous source-to-drain diode current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 A  
C
Pulsed drain current, each output, T = 25°C (see Note 1 and Figure 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 A  
C
Single-pulse avalanche energy, T = 25°C, E (see Figure 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 mJ  
C
AS  
Continuous total power dissipation at (or below) T = 25°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.95 W  
C
Operating virtual junction temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40°C to 150°C  
J
Operating case temperature range, T  
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40°C to 125°C  
C
Storage temperature range, T  
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65°C to 150°C  
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C  
stg  
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and  
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not  
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.  
NOTE 1: Pulse duration = 10 ms, duty cycle = 2%  
Copyright 1995, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
2–1  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
TPIC3302  
3-CHANNEL COMMON-DRAIN POWER DMOS ARRAY  
SLIS021B – APRIL 1994 – REVISED JULY 1995  
electrical characteristics, T = 25°C (unless otherwise noted)  
C
PARAMETER  
TEST CONDITIONS  
MIN  
60  
TYP  
MAX  
UNIT  
V
V
V
Drain-to-source breakdown voltage  
Gate-to-source threshold voltage  
I
I
= 250 µA,  
V
V
= 0  
= V  
(BR)DSX  
D
GS  
= 1 mA,  
1.5  
1.85  
2.2  
V
GS(th)  
D
DS  
GS  
Reverse drain-to-GND breakdown voltage  
(across D1)  
V
V
V
V
Drain-to-GND current = 250 µA  
100  
V
V
V
V
(BR)  
DS(on)  
F
I
= 1 A,  
V
GS  
= 10 V,  
D
Drain-to-source on-state voltage  
0.4 0.475  
2
See Notes 2 and 3  
I
= 1 A,  
D
Forward on-state voltage, GND-to-drain  
Forward on-state voltage, source-to-drain  
See Notes 2 and 3  
I
= 1 A,  
V
= 0,  
S
GS  
0.9  
1.1  
F(SD)  
See Notes 2 and 3  
T
T
= 25°C  
0.05  
0.5  
10  
1
10  
V
V
= 48 V,  
= 0  
C
DS  
GS  
I
Zero-gate-voltage drain current  
µA  
DSS  
= 125°C  
C
I
I
Forward gate current, drain short circuited to source  
Reverse gate current, drain short circuited to source  
V
= 16 V,  
= 16 V,  
V
V
= 0  
= 0  
100  
100  
1
nA  
nA  
GSSF  
GS  
SG  
DS  
V
10  
GSSR  
DS  
T
= 25°C  
0.05  
0.5  
C
C
I
Leakage current, drain-to-GND  
V
R
= 48 V  
µA  
lkg  
T
= 125°C  
10  
V
= 10 V,  
= 1 A,  
GS  
T
= 25°C  
0.4 0.475  
C
C
I
D
r
Static drain-to-source on-state resistance  
Forward transconductance  
DS(on)  
See Notes 2 and 3  
and Figures 6 and 7  
T
= 125°C  
0.63  
0.7  
V
= 10 V,  
I = 0.5 A,  
D
DS  
See Notes 2 and 3  
g
0.85  
1.02  
S
fs  
C
C
Short-circuit input capacitance, common source  
Short-circuit output capacitance, common source  
115  
60  
145  
75  
iss  
V
= 25 V,  
V
GS  
= 0,  
oss  
DS  
f = 1 MHz  
pF  
Short-circuit reverse-transfer capacitance,  
common source  
C
30  
40  
rss  
NOTES: 2. Technique should limit T – T to 10°C maximum, pulse duration 5 ms.  
J
C
3. These parameters are measured with voltage-sensing contacts separate from the current-carrying contacts.  
source-to-drain diode characteristics, T = 25°C  
C
PARAMETER  
TEST CONDITIONS  
= 0.5 A, = 0, = 48 V,  
MIN  
MIN  
TYP  
35  
MAX  
UNIT  
ns  
t
Reverse-recovery time  
Total diode charge  
I
V
GS  
V
rr(SD)  
S
DS  
See Figure 1  
di/dt = 100 A/µs,  
Q
0.03  
µC  
RR  
GND-to-drain diode characteristics, T = 25°C (see schematic, D1)  
C
PARAMETER  
Reverse-recovery time  
Total diode charge  
TEST CONDITIONS  
TYP  
90  
MAX  
UNIT  
ns  
t
rr  
I
F
= 0.5 A,  
di/dt = 100 A/µs,  
V
= 48 V,  
DS  
See Figure 1  
Q
0.2  
µC  
RR  
2–2  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
TPIC3302  
3-CHANNEL COMMON-DRAIN POWER DMOS ARRAY  
SLIS021B – APRIL 1994 – REVISED JULY 1995  
resistive-load switching characteristics, T = 25°C  
C
PARAMETER  
Turn-on delay time  
TEST CONDITIONS  
MIN  
TYP  
21  
20  
5
MAX  
42  
UNIT  
t
t
t
t
d(on)  
Turn-off delay time  
Rise time  
40  
d(off)  
V
t
= 25 V,  
= 10 ns,  
R
= 50 ,  
t
en  
= 10 ns,  
DD  
dis  
L
ns  
See Figure 2  
10  
r
f
Fall time  
13  
3.1  
0.4  
1.3  
5
26  
Q
Q
Q
Total gate charge  
3.8  
0.5  
1.6  
g
V
= 48 V,  
I
D
= 0.5 A,  
V
= 10 V,  
DS  
See Figure 3  
GS  
Threshold gate-to-source charge  
Gate-to-drain charge  
Internal drain inductance  
Internal source inductance  
Internal gate resistance  
nC  
gs(th)  
gd  
L
L
D
nH  
5
S
R
0.25  
g
thermal resistance  
PARAMETER  
TEST CONDITIONS  
All outputs with equal power, See Note 4  
MIN  
TYP  
130  
44  
MAX  
UNIT  
R
R
Junction-to-ambient thermal resistance  
Junction-to-pin thermal resistance  
θJA  
θJP  
°C/W  
NOTE 4: Package mounted on an FR4 printed-circuit board with no heat sink  
PARAMETER MEASUREMENT INFORMATION  
1
T
J
= 25°C  
Reverse di/dt = 100 A/µs  
0.5  
0
25% of I  
RM  
– 0.5  
– 1  
– 1.5  
– 2  
I
RM  
– 2.5  
– 3  
t
rr(SD)  
0
25  
50  
75 100 125 150 175 200 225 250  
Time – ns  
I
= maximum recovery current  
RM  
Figure 1. Reverse-Recovery-Current Waveform of Source-to-Drain Diode  
2–3  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
TPIC3302  
3-CHANNEL COMMON-DRAIN POWER DMOS ARRAY  
SLIS021B – APRIL 1994 – REVISED JULY 1995  
PARAMETER MEASUREMENT INFORMATION  
V
DD  
= 25 V  
t
dis  
t
en  
R
10 V  
L
V
DS  
V
GS  
0 V  
Pulse Generator  
V
GS  
t
d(off)  
t
d(on)  
DUT  
t
r
t
f
C
= 30 pF  
R
50 Ω  
L
gen  
V
V
DD  
(see Note A)  
50 Ω  
V
DS  
DS(on)  
VOLTAGE WAVEFORMS  
TEST CIRCUIT  
NOTE A: C includes probe and jig capacitance.  
L
Figure 2. Resistive-Switching Test Circuit and Voltage Waveforms  
V
DS  
Current  
Regulator  
Q
g
Same Type  
as DUT  
12-V  
Battery  
0.2 µF  
50 kΩ  
10 V  
0.3 µF  
Q
Q
gd  
gs(th)  
V
DD  
V
GS  
DUT  
Gate Voltage  
Time  
I
G
= 1 µA  
0
I
Current-  
I Current-  
D
Sampling Resistor  
Q
= Q – Q  
g gd  
G
gs  
Sampling Resistor  
VOLTAGE WAVEFORM  
TEST CIRCUIT  
Figure 3. Gate-Charge Test Circuit and Voltage Waveform  
2–4  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
TPIC3302  
3-CHANNEL COMMON-DRAIN POWER DMOS ARRAY  
SLIS021B – APRIL 1994 – REVISED JULY 1995  
PARAMETER MEASUREMENT INFORMATION  
V
DD  
= 25 V  
t
av  
t
w
420 µH  
15 V  
0 V  
V
GS  
V
DS  
Pulse Generator  
(see Note A)  
I
D
I
AS  
V
GS  
(see Note B)  
I
D
DUT  
50 Ω  
0 V  
R
gen  
V
= 60 V Min  
(BR)DSX  
50 Ω  
V
DS  
0 V  
VOLTAGE AND CURRENT WAVEFORMS  
TEST CIRCUIT  
NOTES: A. The pulse generator has the following characteristics: t 10 ns, t 10 ns, Z = 50 .  
r
f
O
B. Input pulse duration (t ) is increased until peak current I  
AS  
= 5 A.  
w
I
V
t
av  
AS  
(BR)DSX  
2
Energy test level is defined as E  
9 mJ.  
AS  
Figure 4. Single-Pulse Avalanche-Energy Test Circuit and Waveforms  
TYPICAL CHARACTERISTICS  
GATE-TO-SOURCE THRESHOLD VOLTAGE  
STATIC DRAIN-TO-SOURCE ON-STATE RESISTANCE  
vs  
vs  
JUNCTION TEMPERATURE  
JUNCTION TEMPERATURE  
1
2.5  
2
I
D
= 1 A  
0.8  
0.6  
0.4  
I
= 1 mA  
D
1.5  
1
I
D
= 100 µA  
V
GS  
= 10 V  
V
GS  
= 15 V  
0.2  
0
0.5  
0
40 20  
0
20 40 60 80 100 120 140 160  
40 20  
0
20 40 60 80 100 120 140 160  
T
J
– Junction Temperature – °C  
T
J
– Junction Temperature – °C  
Figure 5  
Figure 6  
2–5  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
TPIC3302  
3-CHANNEL COMMON-DRAIN POWER DMOS ARRAY  
SLIS021B – APRIL 1994 – REVISED JULY 1995  
TYPICAL CHARACTERISTICS  
STATIC DRAIN-TO-SOURCE ON-STATE RESISTANCE  
DRAIN CURRENT  
vs  
vs  
DRAIN CURRENT  
DRAIN-TO-SOURCE VOLTAGE  
1
5
4
3
2
1
0
T
J
= 25°C  
15 V  
10 V  
V
= 0.2 V  
GS  
T
= 25°C  
J
Unless Otherwise  
Noted  
V
GS  
= 10 V  
V
GS  
= 5 V  
V
GS  
= 15 V  
V
GS  
= 4 V  
V
GS  
= 3 V  
0.1  
0.01  
0.1  
1
10  
0
1
2
3
4
5
6
7
8
9
10  
I
D
– Drain Current – A  
V
DS  
– Drain-to-Source Voltage – V  
Figure 7  
Figure 8  
DRAIN CURRENT  
vs  
DISTRIBUTION OF  
FORWARD TRANSCONDUCTANCE  
GATE-TO-SOURCE VOLTAGE  
0.5  
5
Total Number of Units = 639  
= 25°C  
T
J
= 40°C  
T
J
0.45  
4.5  
4
T
= 25°C  
= 75°C  
J
J
0.4  
T
T
= 125°C  
= 150°C  
J
T
3.5  
3
0.35  
J
0.3  
0.25  
2.5  
2
0.2  
0.15  
0.1  
1.5  
1
0.5  
0
0.05  
0
0
1
2
3
4
5
6
7
8
9
10  
V
GS  
– Gate-to-Source Voltage – V  
g
fs  
– Forward Transconductance – S  
Figure 9  
Figure 10  
2–6  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
TPIC3302  
3-CHANNEL COMMON-DRAIN POWER DMOS ARRAY  
SLIS021B – APRIL 1994 – REVISED JULY 1995  
TYPICAL CHARACTERISTICS  
SOURCE-TO-DRAIN DIODE CURRENT  
CAPACITANCE  
vs  
vs  
SOURCE-TO-DRAIN VOLTAGE  
DRAIN-TO-SOURCE VOLTAGE  
10  
400  
360  
320  
280  
240  
200  
160  
120  
f = 1 MHz  
T
J
= 25°C  
C
C
C
(0) = 158 pF  
iss  
(0) = 400 pF  
(0) = 78 pF  
oss  
rss  
1
T
J
= 40°C  
T
J
= 125°C  
T
J
= 150°C  
T
T
= 25°C  
= 75°C  
J
0.1  
C
iss  
J
C
80  
40  
0
oss  
C
rss  
0.01  
0.1  
1
10  
0
4
8
12 16 20 24 28 32 36 40  
– Drain-to-Source Voltage – V  
V
SD  
– Source-to-Drain Voltage – V  
V
DS  
Figure 11  
Figure 12  
DRAIN-TO-SOURCE VOLTAGE AND  
GATE-TO-SOURCE VOLTAGE  
vs  
REVERSE-RECOVERY TIME  
vs  
REVERSE di/dt  
GATE CHARGE  
150  
14  
12  
70  
I
T
= 0.5 A  
= 25°C  
I
T
= 0.5 A  
= 25°C  
D
J
S
J
60  
See Figure 3  
125 See Figure 1  
V
DD  
= 20 V  
10  
8
50  
40  
30  
20  
10  
0
100  
75  
V
DD  
= 30 V  
6
D1  
50  
4
V
= 48 V  
DD  
Q1, Q2, and Q3  
25  
0
2
V
DD  
= 20 V  
0
3.5  
0
100  
200  
300  
400  
500  
600  
0
0.5  
1
1.5  
2
2.5  
3
Reverse di/dt – A/µs  
Q
– Gate Charge – nC  
g
Figure 13  
Figure 14  
2–7  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
TPIC3302  
3-CHANNEL COMMON-DRAIN POWER DMOS ARRAY  
SLIS021B – APRIL 1994 – REVISED JULY 1995  
THERMAL INFORMATION  
MAXIMUM PEAK-AVALANCHE CURRENT  
MAXIMUM DRAIN CURRENT  
vs  
vs  
DRAIN-TO-SOURCE VOLTAGE  
TIME DURATION OF AVALANCHE  
10  
10  
See Figure 4  
T
C
= 25°C  
1 µs  
10 ms  
1 ms  
T
C
= 25°C  
1
500 µs  
T
C
= 125°C  
DC Conditions  
1
0.01  
0.1  
0.1  
0.1  
1
10  
1
10  
100  
t
av  
– Time Duration of Avalanche – ms  
V
DS  
– Drain-to-Source Voltage – V  
Figure 16  
Less than 0.1 duty cycle  
Figure 15  
2–8  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
TPIC3302  
3-CHANNEL COMMON-DRAIN POWER DMOS ARRAY  
SLIS021B – APRIL 1994 – REVISED JULY 1995  
THERMAL INFORMATION  
D PACKAGE  
NORMALIZED JUNCTION-TO-AMBIENT THERMAL RESISTANCE  
vs  
PULSE DURATION  
10  
DC Conditions  
d = 0.5  
1
d = 0.2  
d = 0.1  
d = 0.05  
0.1  
d = 0.02  
d = 0.01  
0.01  
0.001  
Single Pulse  
t
c
t
w
I
D
0
0.0001  
0.0001  
0.001  
0.01  
0.1  
– Pulse Duration – s  
1
10  
t
w
Device mounted on FR4 printed-circuit board with no heat sink  
NOTES: (t) = r(t) R  
Z
θA θJA  
t
w
= pulse duration  
t = cycle time  
c
d = duty cycle = t /t  
w c  
Figure 17  
2–9  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
2–10  
IMPORTANT NOTICE  
Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue  
any product or service without notice, and advise customers to obtain the latest version of relevant information  
to verify, before placing orders, that information being relied on is current and complete. All products are sold  
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those  
pertaining to warranty, patent infringement, and limitation of liability.  
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in  
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent  
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily  
performed, except those mandated by government requirements.  
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF  
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL  
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR  
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER  
CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO  
BE FULLY AT THE CUSTOMER’S RISK.  
In order to minimize risks associated with the customer’s applications, adequate design and operating  
safeguards must be provided by the customer to minimize inherent or procedural hazards.  
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent  
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other  
intellectual property right of TI covering or relating to any combination, machine, or process in which such  
semiconductor products or services might be or are used. TI’s publication of information regarding any third  
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.  
Copyright 1998, Texas Instruments Incorporated  

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