TPIC44H01DAG4 [TI]
具有故障模式选择的 1.2mA/1.2mA 4 通道栅极驱动器 | DA | 32;
| 型号： | TPIC44H01DAG4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有故障模式选择的 1.2mA/1.2mA 4 通道栅极驱动器 | DA | 32 栅极驱动 光电二极管 接口集成电路 驱动器 MOSFET驱动器 驱动程序和接口 |
| 文件： | 总28页 (文件大小：402K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPIC44H01
4-CHANNEL SERIAL AND PARALLEL HIGH-SIDE PRE-FET DRIVER
SLIS088 – SEPTEMBER 1998
DA PACKAGE
(TOP VIEW)
Serial or Parallel Control of Gate Outputs
Sleep State for Low Quiescent Current
1
32
CS
SD0
SDI
PGND
Independent On-State Source
Short-to-Ground (Shorted-Load)
Detection/Protection
2
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
V
(PWR)
3
CP1
CP2
4
SCLK
AR_ENBL
GND
IN1
Independent On-State Over-Current
Detection/Protection With Dynamic Fault
Threshold
5
V
(CP)
6
GATE1
SRC1
GATE2
SRC2
GATE3
SRC3
GATE4
SRC4
FLT
7
Independent Off-State Open-Load
Detection
8
IN2
IN3
IN4
9
10
11
12
13
14
15
16
Supply Over-Voltage Lockout Protection
V
CC
Asynchronous Open-Drain Fault Interrupt
Terminal to Flag Fault Conditions. Output
Can be OR’ed With Multiple Devices
V
V
(PK_A)
(PK_B)
V
V
V
(COMP1)
(COMP2)
(COMP3)
Encoded Fault Status Reporting Through
Serial Output Terminal (2-Bits Per Channel)
RESET
V
(COMP4)
Programmable On-State Fault Deglitch
Timers
High Impedance CMOS Compatible Inputs
With Hysteresis
Fault Mode Selection: Outputs Latched Off
or Switched at Low Duty Cycle
Device Can be Cascaded With Serial
Interface
description
The TPIC44H01 is a four channel high-side pre-FET driver which provides serial or parallel input interface to
control four external NMOS power FETs. It is designed for use in low frequency switching applications for
resistive or inductive loads, including solenoids and incandescent bulbs.
Each channel has over-current, short-to-ground, and open-load detection that is flagged through the FLT pin
and distinguished through the serial interface. Over-current thresholds are set through the V
and
(PK_x)
V
pins. Short-to-ground and open-load thresholds are set internally to approximately 2.5 V. The
(COMP1-4)
AR_ENBL pin is used to define the operation of the device during a fault condition, allowing the outputs to either
latch off or to enter a low duty cycle, auto-retry mode. An over-voltage lockout circuit on V protects the
(PWR)
device and the external FETs. A low current sleep state mode is provided to allow the TPIC44H01 to be used
in applications where V is connected directly to the battery. An internal charge pump allows the use of
(PWR)
N-channel FETs for high-side drive applications, while current-limit gate drive provides slope control for reduced
RFI.
By having the unique ability to develop a dynamic over-current threshold, the TPIC44H01 can be used to drive
incandescent bulbs with long inrush currents without falsely flagging a fault. Likewise, the user can select an
internally set over-current threshold of ~1.25 V by pulling the respective V
pin to V
.
(COMP1-4)
CC
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
TI is a trademark of Texas Instruments Incorporated.
Copyright 1998, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPIC44H01
4-CHANNEL SERIAL AND PARALLEL HIGH-SIDE PRE-FET DRIVER
SLIS088 – SEPTEMBER 1998
description (continued)
The 8-bit serial peripheral interface (SPI) allows the user to command any of the four outputs on or off, to
program one of eight possible open-load, over-current, and short-load fault deglitch timer settings, and to
engage the sleep state. Data is clocked into the SDI pin on the rising edge of SCLK and clocked out of the SDO
pinontheSCLKfallingedge. TheserialinputbitsarelogicOR’edwiththeIN1-IN4parallelinputspins. Theserial
interface is also used to read normal-load, open-load, over-current, and short-to-ground conditions for each
channel. Over-voltage lockout can be detected when the FLT pin is low and no bits are set in the SDO register.
MultipleTPIC44H01devicesmaybecascadedtogetherusingtheserialinterfacetofurtherreduceI/Olinesfrom
the host controller.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPIC44H01
4-CHANNEL SERIAL AND PARALLEL HIGH-SIDE PRE-FET DRIVER
SLIS088 – SEPTEMBER 1998
schematic/block diagram
0.01 µF
CP
0.1 µF
CS
V
AR_ENBL PGND
(PK_B)
CP2
V
CP1
(CP)
OVLO
OVLO
5-V Int
5-V
V
Buffer
peak
V
Buffer
peak
V
V
peakA
(PK_A)
V
peakB
V
Charge
Pump
reg
OSC
OVDS V
OVDS V
thres
Generation
V
thres1
thres2
V
(COMP1)
(PWR)
V
V
V
V
OVLO
bg
bg
bg
bg
+
–
V
peakA
+
OVDS
V
OVDS V
thres
Generation
OVDS V
V
(COMP2)
V
thres
0.1 µF 1 µF
OVDS t
DG
Comp
V
peakB
+
–
Over-V
Detect
DS
OVDS V
OVDS V
OVDS V
V
thres
thres3
(COMP3)
5-V Int
Generation
V
peakB
GATE1
HS Gate
Drive
Gate
Control
thres4
OVDS V
V
thres
(COMP4)
FLT
Generation
7-V Int
+
Channel 1
Output
100 Ω
I
SRC1
PS
Q
D
–
On-State Short-
Load Detect
CLK
Comp
+
IN1
IN2
IN3
–
2 V
bg
Off-State Open-
Load Detect
GATE2
SRC2
Channel 2 Output
Channel 3 Output
Channel 4 Output
IN4
GATE3
SRC3
V
CC
GATE4
SRC4
t
t
RESET
DG
AR
Parallel Reg
V
CC
Sleep
I
bias
Control Reg
Sleep
8
CS
2 V
V
bg
bg
Global
Ibias
Fault Logic
8
Band Gap
V
CC
SCLK
4
4
Charge Pump
Digital Deglitch
UVLO/
POR
OSC
Serial Shift Register
SDI
Tri-State Buffer
SDO
GND
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPIC44H01
4-CHANNEL SERIAL AND PARALLEL HIGH-SIDE PRE-FET DRIVER
SLIS088 – SEPTEMBER 1998
Terminal Functions
PIN
NO.
PIN
NAME
I/O
DESCRIPTION
1
2
3
4
5
CS
I
Chip Select. CS is an active low, logic level input with internal pullup. A logic level low on CS enables the
serial interface and refreshes the fault interrupt (FLT). A high on CS enables the serial register to serve as
the fault data register.
SDO
O
I
Serial Data Output. SDO is a logic level, tri-state output that transfers fault data to the host controller. Serial
input data passes to the next stage for cascade operation. SDO is forced into a high impendance state when
CS terminal is in a high state. When CS is in a low state, data is clocked out on each falling edge of SCLK.
SDI
Serial Data Input. SDI is a logic level input with hysteresis and internal pulldown. Gate drive output control
data is clocked into the serial register using SDI. A high SDI bit programs a particular gate output on, and a
low turns it off, as long as the parallel input is off (OR function).
SCLK
AR_ENBL
I
Serial Clock. SCLK is a logic level input with hysteresis and internal pulldown. SCLK clocks data at the SDI
terminal into the input serial shift register on each rising edge, and shifts out fault data (and serial input data
for cascaded operation) to the SDO pin on each falling edge.
I
Auto-Retry Enable. AR_ENBL is a logic level input with hysteresis and internal pulldown. When
AR_ENBL=0, an over-current/short-to-ground fault latches the channel off. When AR_ENBL = 1, an
over-current/short-to-ground fault engages a low duty cycle operation.
6
GND
I
I
Analog ground and substrate connection
7–10
IN1-4
Parallel Inputs. IN1-4 are logic level inputs with hysteresis and internal pulldown. IN1–4 provide real-time
control of gate pre-drive circuitry. A high on IN1-4 will turn on corresponding gate drive outputs (GATE1-4).
Gate output status is a logic OR function of the parallel inputs and the serial input bits.
11
12
V
V
V
V
I
I
I
I
5-V logic supply voltage
CC
Dynamic over-current fault threshold peak voltage that is shared by channels 1 and 2
Dynamic over-current fault threshold peak voltage that is shared by channels 3 and 4
(PK_A)
(PK_B)
(COMP1-4)
13
14–17
Fault Reference Voltage. V are used to provide an external fault reference voltage for the
(COMP1–4)
over-currentfaultdetectioncircuitry. Itisalsousedtogenerateadynamicthresholdwhenusedinconjunction
with V . To guarantee V stability, a minimum of 100 pF capacitance should be placed from
(PK_x) (COMP)
(COMP)
V
to ground.
18
19
RESET
FLT
I
Reset. RESET is an active low, logic level input with hysteresis and internal pullup. A low on RESET clears
all registers and fault bits. All gate outputs are turned off and a latched FLT interrupt is cleared.
O
Fault Interrupt. FLT is an active low, logic level, open-drain output providing real-time latched fault interrupts
for fault detection. A latched FLT is cleared only by a low on CS. The FLT terminal can be OR’ed with other
devices for fault interrupt handling. An external pullup is required.
20, 22, SRC1-4
24, 26
I
FET Source Inputs. These inputs are used for both open-load and over-current fault detection at the source
of the external FETs.
21, 23, GATE1-4
25, 27
O
GateDriveOutputs. OutputvoltageisderivedfromV
on these nodes, with respect to SRC1-4, from exceeding the V
GS
supplyvoltage.Internalclampspreventthevoltage
rating of most FETs.
(CP)
28
29
30
31
32
V
O
O
O
I
Charge pump voltage storage capacitor and supply pin to high-side gate drives
Charge pump capacitor terminal
(CP)
CP2
CP1
Charge pump capacitor terminal
V
Power supply voltage input
(PWR)
PGND
I
Power ground for charge pump
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPIC44H01
4-CHANNEL SERIAL AND PARALLEL HIGH-SIDE PRE-FET DRIVER
SLIS088 – SEPTEMBER 1998
†
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
Logic supply voltage range, V
Power supply voltage range, V
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 7 V
CC
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 40 V
(PWR)
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 7 V
I
Output voltage range, V (SDO and FLT, see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 7 V
O
Source input voltage, V
Output voltage, V
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –3 V to 40 V
I(SRCx)
O(GATEx)
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 45 V
Logic input current, I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 µA
I
Operating case temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 125°C
C
Operating virtual junction temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 150°C
J
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to GND.
recommended operating conditions
MIN
4.5
8
TYP
MAX
5.5
UNIT
V
Logic supply voltage, V
5
CC
Power supply voltage, V
24
V
(PWR)
High level logic input voltage, V (all logic inputs except RESET)
0.7×V
0
V
V
IH
Low level logic input voltage, V (all logic inputs except RESET)
CC
CC
0.3×V
V
IL
Setup time, SDI high before SCLK rising edge, t (see Figure 5)
CC
10
ns
ns
°C
su
Hold time, SDI high after SCLK rising edge, t (see Figure 5)
10
h
Operating case temperature, T
–40
125
C
thermal resistance
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
°C/W
°C/W
R
R
Junction-to-ambient thermal resistance
Junction-to-case thermal resistance
Using JEDEC, low K, board configuration
86.04
7.32
θJA
θJC
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPIC44H01
4-CHANNEL SERIAL AND PARALLEL HIGH-SIDE PRE-FET DRIVER
SLIS088 – SEPTEMBER 1998
electrical characteristics over recommended operating case temperature and supply voltage
†
range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
= 12 V
MIN
TYP
MAX
UNIT
mA
I
I
V
supplycurrent All outputs off, V
2
4
6
(PWR)
(PWR)
(PWR)
All outputs off, V = 5.5 V
5-V supply current
3
4
5
mA
CCH
CC
Sleep state (all outputs off),
V = 5.5 V, V = 12 V, T = 25°C
Sleep state current
I
I
15
40
µA
(PWR-sleep)
(I
PWR
)
CC
(PWR)
C
Sleep state current
(I
Sleep state (all outputs off),
30
40
µA
CCL(sleep)
)
V
V
= 5.5 V, V
= 12 V, T = 25°C
CCL
Power-on reset
threshold, V
CC
(PWR)
C
V
= 5.5 V, V
increasing
decreasing
3.4
3.9
4.4
V
IT(POR)
(PWR)
CC
CC
CC
Power-on reset
threshold hysteresis,
V
V
V
= 5.5 V, V
100
300
40
500
mV
V
hys(POR)
(PWR)
V
CC
> 24 V, CP = 0.01 µF, CS = 0.1 µF,
= –2 mA, See Figure 8
(PWR)
44
42
I
(CP)
V
= 24 V, CP = 0.01 µF, CS = 0.1 µF,
(PWR)
= –2 mA, See Figure 8
38
11.5
6.8
40
13.5
7.5
30
V
V
I
(CP)
V
Charge pump voltage
(CP)
V
= 8 V, CP = 0.01 µF, CS = 0.1 µF,
(PWR)
= –2 mA, See Figure 8
I
(CP)
V
= 5.5 V, CP = 0.01 µF,
(PWR)
CS = 0.1 µF, I
V
= –2 mA, See Figure 8
(CP)
Over-supply voltage
lockout
V
V
Gate disabled, See Figure 10
See Figure 10
27.5
0.5
32.5
2
V
(OVLO)
Over-supply voltage
reset hysteresis
1
V
hys(OV)
8 V < V
(PWR)
< 24 V, I = –100 µA,
O
V +4
(PWR)
V +18
(PWR)
V
All channels on, See Note 2
V
G
Gate drive voltage
5.5 V < V < 8 V, I = –100 µA,
All channels on, See Note 2
(PWR)
O
V +1.5
(PWR)
V +3.5
(PWR)
V
External gate sleep
state voltage
V
V
V
I
= 100 µA, RESET = CS = 0 V
0
100
300
19.5
9.5
mV
V
G(sleep)
O
Gate-to-source clamp
voltage
SRCx = 0 V, Output on
Output off, I = 100 µA
15
17
8
GS(clamp)
SG(clamp)
Source-to-gate clamp
voltage
6.5
V
I
V
G
V
G
V
G
V
G
= 0 V, V
= 12 V
–2.3
–1.4
1
–3
–2
1.5
2.6
–3.7
–2.6
2
Gate drive source
current
(PWR)
= 10 V, V
I
mA
mA
G(SRCx)
G(SNKx)
= 12 V
(PWR)
= 12 V
= 2 V, V
Gate drive sink
current
(PWR)
= 12 V
I
= V
(PWR)
2
3.2
SRCx pin off-state
open-load detection
threshold
V
All outputs off, See Figure 11
All outputs off
1.9
2.4
2.6
V
(open)
Off-state open-load
hysteresis
V
–50
–150
–300
mV
hys(open)
†
Device will function with degraded performance for a power supply voltage between 5.5 V and 8 V.
NOTE 2: For characterization purposes only, not implemented in production testing.
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPIC44H01
4-CHANNEL SERIAL AND PARALLEL HIGH-SIDE PRE-FET DRIVER
SLIS088 – SEPTEMBER 1998
electrical characteristics over recommended operating case temperature and supply voltage
†
range (unless otherwise noted) (continued)
PARAMETER
TEST CONDITIONS
All outputs off
MIN
TYP
–50
1.25
MAX
UNIT
µA
V
Off-state open-load
detection current
I
–20
1
–70
1.5
(open)
V
> V
– 250 mV
< 2.5 V,
(COMPx)
CC
Drain-to-source
V
(OVDS)
0.1 V < V
0.95×V
–15
1.05×V
+15
(COMPx)
(COMPx)
mV
(COMPx)
mV
V
See Figures 12 and 13
On-state
V
V
short-to-ground
detection voltage
See Figure 17
1.9
–50
–5
2.35
–150
–20
20
2.6
V
(STG)
On-state
short-to-ground
hysteresis
–300
–50
50
mV
µA
µA
hys(STG)
(pullup)
Logic input pullup
current
(CS, RESET)
I
V
V
= 5 V, V = 0 V
IN
CC
Logic input pulldown
current (IN1–4, SCLK,
SDI, AR_ENBL)
I
= 5 V, V = 5 V
IN
5
(pulldown)
CC
Logic input voltage
hysteresis (IN1–4,
SCLK, SDI, AR_ENBL,
CS)
V
hys
V
CC
= 5 V
0.5
0.8
1.2
V
High level serial output
voltage
V
V
I
I
= –1 mA
0.8×V
CC
4.96
100
1
V
OH
O
Low level serial output
voltage
= 1 mA
0
400
35
mV
µA
OL
O
Serial data output
tri-state current
V
V
= 5.5 V to 0 V,
(SDO)
= 5.5 V
I
–35
OZ
CC
FLT low level output
voltage
V
I
= 220 µA
0
0
30
1
350
20
mV
µA
V
OL(FLT)
O
I
FLT leakage current
R
= 25 K, V
= 5.5 V
CC
lkg(FLT)
(pullup)
RESET high level logic
input voltage
V
V
V
1.9
2.2
V
IH(RESET)
IL(RESET)
hys(RESET)
CC
1.4
RESET low level logic
input voltage
0
1.2
1
V
V
Logic input voltage
hysteresis (RESET)
V
= 5 V
0.6
1.4
CC
†
Device will function with degraded performance for a power supply voltage between 5.5 V and 8 V.
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPIC44H01
4-CHANNEL SERIAL AND PARALLEL HIGH-SIDE PRE-FET DRIVER
SLIS088 – SEPTEMBER 1998
switching characteristics, V
= 5 V, V
= 12 V, T = 25°C
CC
(PWR)
C
PARAMETER
TEST CONDITIONS
MIN
TYP
16
MAX
UNIT
µs
t
t
t
t
Short-to-ground deglitch time
(STG)
Over-current deglitch time
Open-load deglitch time
Auto-retry time
120
120
15
µs
(OC)
SDI bits DG1–3 = 0 (default after POR),
See Figures 11, 12, and 17 and Table 4
µs
(OL)
ms
(retry)
Propagation turn-on delay, CS or IN1–4 to
GATE1–4
t
5
µs
PLH
C
= 400 pF, See Figures 1 and 2
G
Propagation turn-off delay, CS or IN1–4 to
GATE1–4
t
f
t
5
1
µs
MHz
ns
PHL
Serial clock frequency
t
= t
= 0.5/f
, See Figure 5
(SCLK)
5
(SCLK)
su(lead)
(WH) (WL)
Setup from the falling edge of CS to the
rising edge of SCLK
100
See Figure 5
Setup from the falling edge of SCLK to
rising edge of CS
t
t
t
100
50
ns
ns
ns
su(lag)
Propagation delay from falling edge of CS
to SDO valid
pd(SDOEN)
pd(valid)
Propagation delay from falling edge of
SCLK to SDO valid
50
R
R
= 10 kΩ, C = 200 pF, See Figure 5
L
L
L
Propagation delay from rising edge of CS
to SDO Hi-Z state
t
t
t
150
12
ns
ns
µs
pd(SDODIS)
Fall time of FLT output
= 10 kΩ, C = 200 pF, See Figure 3
L
f(FLT)
POR-to-active status delay, sleep-to-active
status delay
See Figure 4
512
(active)
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPIC44H01
4-CHANNEL SERIAL AND PARALLEL HIGH-SIDE PRE-FET DRIVER
SLIS088 – SEPTEMBER 1998
PARAMETER MEASUREMENT INFORMATION
V
CC
50%
50%
V
CS or IN1–4
CC
0 V
50%
CS or IN1–4
GATE1–4
0 V
V
CC
t
PLH
0 V
V
(CP)
V
(PWR)
90%
t
PHL
0 V
V
(CP)
GATE1–4
10%
0 V
Figure 1. Gate Control Turn-On
Figure 2. Gate Control Turn-Off
POR Threshold
V
CC
Input
t
f (FLT)
V
CC
Internal
90%
10%
Sleep Bit
FLT
0 V
t
t
(active)
(active)
GATEx
Figure 3. Fault Interrupt Fall Time
Figure 4. Power-Up Waveforms
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPIC44H01
4-CHANNEL SERIAL AND PARALLEL HIGH-SIDE PRE-FET DRIVER
SLIS088 – SEPTEMBER 1998
PARAMETER MEASUREMENT INFORMATION
FLT
t
t
su(lag)
su(lead)
CS
t
t
t
(WL)
(SCLK)
(WH)
50%
SCLK
1
2
7
8
t
su
t
pd(SDOEN)
t
pd(SDODIS)
t
pd(valid)
Hi-Z
Hi-Z
90%
10%
90%
10%
SDO
SDI
t
h
90%
10%
Fault Data
Register Latch
(Internal)
Fault Data
Register Refresh
(Internal)
SDO
R
C
L
L
SDO Output Test Schematic
Figure 5. Serial Interface Timing Diagram
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPIC44H01
4-CHANNEL SERIAL AND PARALLEL HIGH-SIDE PRE-FET DRIVER
SLIS088 – SEPTEMBER 1998
PRINCIPLES OF OPERATION
serial data operation
The TPIC44H01 offers a serial interface to a host microcontroller to receive control data and to return fault data
to the host controller. For the serial interface operation, it is assumed that all parallel inputs, IN1–4, are low. The
serial interface consists of:
SCLK
CS
SDI
Serial clock
Chip select (active low)
Serial data input
Serial data output
SDO
After a CS transition from high to low, serial data at the SDI pin is shifted, MSB first, into the serial input shift
register on the low-to-high transition of SCLK. Eight SCLK cycles are required (see Table 1) to shift the first data
bit from LSB to MSB of the shift register. Eight SCLK cycles must occur before a transition from low to high on
CS to insure proper control of the outputs. Less than eight clock cycles will result in fault data being latched into
the output control buffer. Sixteen bits of data can be shifted into the device, but the first eight bits shifted out are
always the fault data and the last eight bits shifted in are always the output control data. A low-to-high transition
on CS will latch bits 1–4 of the serial shift register into the output control buffer, bits 5–7 into the deglitch timer
control register, and bit 8 into the sleep state latch. A logic 0 in SDI bit1–4 will turn the corresponding gate drive
output off (providing the parallel input for that channel is at a logic low state); likewise, a logic 1 will turn the output
on. Functionality of bits 5–7 is detailed in Table 4. A logic 1 in SDI bit 8 will enable sleep state and a logic 0 will
maintain normal operation.
Table 1. Serial Data Input Shift Register Bit Assignment
SDI, Normal Protocol (8–SCLKs)
LSB
(Last In)
MSB
(First In)
Shift Direction
B5
SDI
B1
B2
B3
B4
IN4
B6
B7
B8
IN1
IN2
IN3
DG1
DG2
DG3
SLEEP
Table 2. Serial Data Output Shift Register Bit Assignment
SDO, Fault Bit Protocol (8–SCLKs)
MSB
(First Out)
LSB
(Last Out)
Shift Direction
B4
SDO
B8
B7
B6
B5
F3A
B3
B2
B1
F4B
F4A
F3B
F2B
F2A
F1B
F1A
Table 3. Fault Bit Encoding
FAULT CONDITION
Normal – no faults
Over-voltage
FxB
X
FxA
X
FLT
1
0
0
0
Open-load
0
1
0
Over-current
1
0
0
Short-to-ground
1
1
0
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPIC44H01
4-CHANNEL SERIAL AND PARALLEL HIGH-SIDE PRE-FET DRIVER
SLIS088 – SEPTEMBER 1998
PRINCIPLES OF OPERATION
Table 4. Deglitch Time Encoding
SHORT-TO-GND
DEGLITCH TIME,
SHORT-TO-GND OVER-CURRENT OVER-CURRENT AUTO-RETRY OPEN-LOAD
DG1 DG2 DG3
SDI SDI SDI
BIT5 BIT6 BIT7
DUTY CYCLE
WITH:
DEGLITCH TIME,
DUTY CYCLE
WITH:
TIME,
DEGLITCH
t
t
t
TIME, t
)
(STG)
(OC)
(retry)
(ms)
(OL
(µs)
(µs)
AR_ENBL=1
(µs)
AR_ENBL=1
†
†
†
†
†
†
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
16
4
0.1%
120
0.75%
16
4
120
30
0.1%
0.1%
0.1%
0.1%
0.1%
0.1%
0.1%
30
60
0.75%
0.75%
0.75%
0.75%
0.75%
0.75%
0.75%
8
8
60
32
120
30
240
120
30
32
16
4
240
120
30
60
60
8
60
240
240
32
240
†
Indicated default conditions after power up.
SDO MSB fault data is setup on the SDO pin by the high-to-low transition of CS prior to the first low-to-high
transition of SCLK. Thus, there must be a lead time, t (see Figure 5), in the host controller from CS
su(lead)
high-to-low transition to the first rising edge of SCLK to allow the SDO tri-state output to enable and to setup
the fault data MSB on the SDO pin. The remaining 7 bits of fault data are shifted out by the falling edge of the
next 7 SCLK cycles. To prevent data from prematurely shifting out of SDO on a low transition of CS while SCLK
is high, the device requires a low-to-high transition on SCLK after a low transition on CS before the second fault
bit is shifted out. One SCLK cycle is required to clear the serial data register and latch in fault data. If a low
transition on CS occurs without a low-to-high transition on SCLK, then fault data remains in the SDO register
and the device will not latch data into the control register.
The serial register serves as the fault register while CS is high. Thus, a fault occurring any time after the end
ofthepreviousserialinterfaceprotocol(low-to-hightransitionofCS)willbelatchedasafaultintheserialregister
and will be reported via SDO during the next serial protocol. The FLT interrupt will refresh on the high-to-low
transition of CS. The CS input must be driven to a high state after the last bit of serial data has been clocked
into the device. The rising edge of CS will inhibit the SDI input port, put the SDO output port into a high
impedance state, latch the 4 bits of SDI data into the output buffer, and clear/re-enable the serial fault registers
(see Figure 6).
1
2
3
4
5
6
7
8
SCLK
CS
Hi-Z
Hi-Z
FLT4B
Bit 8
FLT4A
Bit 7
FLT3B
Bit 6
FLT3A
Bit 5
FLT2B
Bit 4
FLT2A
Bit 3
FLT1B
Bit 2
FLT1A
Bit 1
SDO
Figure 6. SDO Timing Diagram
The TPIC44H01 serial data interface allows multiple devices to be cascaded together to reduce I/O from the
host controller by using a single CS line. In this configuration, 8 bits of data for every cascaded TPIC44H01 must
be sent during the time that CS is low for proper operation (see Figure 7 for an example of two cascaded
TPIC44H01s). If less than 8 bits of data per cascaded device is sent during the time CS is low, the wrong output
may be enabled or disabled, and some fault data will be latched to the output(s) once CS returns high.
12
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPIC44H01
4-CHANNEL SERIAL AND PARALLEL HIGH-SIDE PRE-FET DRIVER
SLIS088 – SEPTEMBER 1998
PRINCIPLES OF OPERATION
CS
SCLK
1st
TPIC44H01
SDI
SDO
CS
SCLK
µC
MOSI
MISO
MISO = Master In Slave Out
MOSI = Master Out Slave In
CS
SCLK
SDI
2nd
TPIC44H01
SDO
LAST IN
LSB
FIRST IN
MSB
SDI Shift Direction
B1
1st
IN1
B2
1st
IN2
B3
1st
IN3
B4
1st
B5
1st
B6
1st
B7
1st
B8
1st
B1
2nd
B2
B3
B4
B5
B6
2nd
B7
2nd 2nd
B8
2nd 2nd 2nd 2nd
IN2
IN4 DG1 DG2 DG3 SLEEP IN1
IN3
IN4 DG1 DG2 DG3 SLEEP
FIRST OUT
MSB
LAST OUT
LSB
SDO Shift Direction
B8
B7
B6
B5
B4
B3
B2
B1
B8
B7
B6
B5
B4
B3
B2
B1
2nd 2nd
2nd 2nd 2nd
2nd 2nd
2nd 1st
1st
1st
1st
1st
1st
1st
1st
F4B F4A F3B F3A F2B F2A F1B F1A F4B F4A F3B F3A F2B F2A F1B F1A
Figure 7. Cascading Multiple TIPC44H01s
13
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPIC44H01
4-CHANNEL SERIAL AND PARALLEL HIGH-SIDE PRE-FET DRIVER
SLIS088 – SEPTEMBER 1998
PRINCIPLES OF OPERATION
parallel input data operation
In addition to the serial interface, the TPIC44H01 also provides a parallel interface to control gate drive outputs.
Parallel input is OR’ed with the serial interface control bit. Thus, the parallel inputs provide direct, real-time
control of the output drivers. SCLK and CS are not required to transfer parallel input data to the output buffer.
Fault detection/protection is provided during parallel operation (see performance under fault conditions
section).
WithAR_ENBLpinlow, detectionofanover-currentorshort-to-groundfaultconditionwilldisabledthegatedrive
until the auto-retry timer clears and re-enables the output.
CAUTION:
If a parallel input is cycled low then high during auto-retry time, the timer is reset and the gate drive
re-enable. The device will not prevent the user from switching at a higher duty cycle than the
auto-retry function provides.
Serial fault data can be read over the serial data bus as described in the serial data operation section. If the FLT
pin is latched low due to a fault detection, it cannot be cleared by cycling the parallel input. It can only be cleared
by a low level on CS.
In applications where the serial interface and FLT interrupt are unused, CS should be tied high to disable the
serial interface.
In applications where the serial interface or FLT interrupt are used only to retrieve fault data, care should be
taken to program the SDI input low to prevent accidental activation of a gate drive output using a serial input
control bit.
charge pump operation
TheTPIC44H01providesachargepumpcircuittogeneratethehigh-sidegatedrivevoltage. Itisadoublerusing
external pump and storage capacitors, CP and CS respectively (refer to the schematic/block diagram). For
V
V
voltage levels above 16 V, the charge pump voltage, V
, is internally regulated to approximately
(PWR)
(CP)
+ 15 V. However, when V
voltage rises to higher than 27 V, V
is limited to approximately 42 V
(PWR)
(PWR)
(CP)
from ground (see Figure 8).
Voltage
42 V
30 V
V
(CP)
15 V
42 V
V
(PWR)
14 V
Time
Figure 8. Charge Pump Voltage With Respect to V
(PWR)
14
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPIC44H01
4-CHANNEL SERIAL AND PARALLEL HIGH-SIDE PRE-FET DRIVER
SLIS088 – SEPTEMBER 1998
PRINCIPLES OF OPERATION
gate drive operation
The TPIC44H01 uses a 2-mA source/sink method for external FET gate drive. This gate drive method limits the
current drain from the charge pump so that when one channel is shorted to ground, the device will maintain
sufficient gate drive for the remaining three channels. This benefit allows the user to add an external Miller
capacitor between the FET’s drain and gate pins to reduce the slew rate minimizing radiated emissions (see
Figure 9).
In order to prevent the external FETs from turning on when V
is not applied to the TPIC44H01, an internal
CC
regulator powered from V
to be used in switched V
supplies voltage to the gate drive input control circuitry. This allows the device
applications without the concern of one of the outputs turning on when V
(PWR)
is low.
CC
CC
An internal zener clamp (15 V – 17 V) from SRCx to GATEx protects the external FET from excessive V
GS
voltages. During the flyback event when turning off an inductive load, the diode from GATEx to ground protects
the TPIC44H01 and external FETs from overstress. The voltage at SRCx during flyback will be V – V
(GND)
(F)
– V , where V
is ground potential, V is the forward voltage drop of the internal diode from GATEx to
is the voltage drop from gate to source of the external FET.
GS
(GND)
(F)
ground, and V
GS
CP
0.01 µF
PGND CP1
CS
0.1 µF
CP2
V
(CP)
V
reg
Charge
Pump
V
(PWR)
C
HS Gate
Drive
(Miller)
2 mA
HV
+
Level-Shift
GATEx
SRCx
5-V Int
Gate
LS
Logic
100 Ω
Control
2 mA
Channel x
Output
Figure 9. Gate Drive Block Diagram
15
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPIC44H01
4-CHANNEL SERIAL AND PARALLEL HIGH-SIDE PRE-FET DRIVER
SLIS088 – SEPTEMBER 1998
PRINCIPLES OF OPERATION
performance under fault conditions
The TPIC44H01 is designed for normal operation over a supply voltage range of 8 V to 24 V with over-voltage
fault detection typically at 30 V. The device offers on board fault detection to handle a variety of faults which may
occur within a system. The primary function of the circuitry is to prevent damage to the load and the external
power FETs in the event that a fault occurs, but off-state, open-load detection and reporting is also provided for
diagnostics. Note that unused SRC1–4 inputs must be connected to their respective GATE1–4 pins to prevent
false reporting of open-load fault conditions. Unused outputs with a SRC-to-GATE short should not be
commanded on. For on-state faults, the circuitry detects the fault, shuts off the output to the FET, and reports
the fault to the microcontroller. The primary faults monitored are:
1. V
2. Open-load
over-voltage lockout (OVLO)
(PWR)
3. Over-current
4. Short-to-ground
FLT, fault interrupt operation
The FLT pin provides a real-time fault interrupt to signal a host controller that a fault has been detected. Any
of the four fault conditions listed above causes the FLT pin to be latched low immediately upon fault detection.
NOTE:
Once FLT is latched low from a fault occurrence, it can only be cleared by a high-to-low transition
on CS.
V
over-voltage lockout
(PWR)
The TPIC44H01 monitors V
supply voltage and responds in the event of supply voltage exceeding OVLO.
(PWR)
This condition may occur due to voltage transients resulting from a loose battery connection. If V
supply
(PWR)
voltage is detected above 30 V, the device will turn off all gate drive outputs to prevent possible damage to the
internalchargepump, theexternalFET, andtheload. AnOVLOfaultwillbeflaggedtothecontrollerbyFLTbeing
latched low. The FLT interrupt will be reset by a high-to-low transition of CS, provided that the OVLO condition
is corrected, and no other faults have been detected with internal fault bits set. Thus, the user will detect an
OVLO fault by a low transition on FLT with no fault bit read from SDO (see Table 3). The gate outputs will return
to normal operation immediately after the OVLO condition is removed (the outputs are not latched off). Figure
10 illustrates the operation of the over-supply voltage detection circuit.
V
(PWR)
+
_
OVLO Output Disable
30 V
30 V
29 V
V
(PWR)
12 V
GATE (1–4)
Figure 10. Over-Voltage Lockout Waveform
16
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPIC44H01
4-CHANNEL SERIAL AND PARALLEL HIGH-SIDE PRE-FET DRIVER
SLIS088 – SEPTEMBER 1998
PRINCIPLES OF OPERATION
open load
An off-state, open-load condition is implemented in the TPIC44H01 by monitoring the SRCx terminal voltage
when the FET is turned off by both the parallel input and the SDI bit being a logic 0. Figure 11 illustrates the
operation of the open-load detection circuit. When the GATEx output is low, thus turning off the FET (see
Figure 11), a 50-µA current is internally sourced from V
to pull up the SRCx pin for open-load fault detection.
CC
If the load is open, or if the impedance is substantially high, the 50-µA current source will cause the SRCx pin
to rise above the ~2.4 V reference threshold of the open-load comparator. Unused SRC1–4 inputs must be
connected to their respective GATE1–4 pins to prevent false reporting of open-load fault conditions. An on
board deglitch timer starts when the open-load comparator detects a SRCx voltage greater than ~2.4 V,
providing time for the SRCx voltage to stabilize after the power FET has been turned off. The SRCx voltage must
remain above the open-load detection threshold for the entire deglitch time, t
, (programmable, see Table 4)
(OL)
forthefaulttoberecognizedasvalid. Ifavalidfaultisrecognized, areal-timefaultisflaggedtothehostcontroller
by latching the FLT pin low, and the appropriate fault bit is set. The host controller can read the serial SDO bits
to determine which channel reported the fault. Fault bits (1:8) distinguish faults for each of the output channels
(see Table 2 and Table 3). This feature provides useful diagnostic information to the host controller to
troubleshoot system failures and warn the operator that a problem exists.
If an open-load fault is detected by the TPIC44H01 while an output is off, the gate drive will be disabled the next
time the output is commanded on either through the serial interface or the parallel inputs. In order to re-enable
the gate drive, the load must return to a normal condition and the user must toggle the input to the previously
faulted channel on then off then back on again.
NOTE:
If an open-load fault is detected by the TPIC44H01 while an output is off and AR_ENBL = 0, the
gate drive will be disabled the next time the output is commanded on either through the serial
interface or the parallel inputs. In order to re-enable the gate drive, the load must return to a normal
condition and the user must toggle the input to the previously faulted channel on then off then back
on again.
NOTE:
If an open-load fault is detected by the TPIC44H01 while an output is off and AR_ENBL = 1, the
auto-retry timer will be initiated. This will cause the gate drive output to be delayed by t
from
(retry)
the input signal. If more than one channel has detected an open-load fault, the delay from the input
signal to the gate drive output signal will depend on which output detected the fault first. This
happens because there is a single auto-retry timer used for all four channels. Normal operation will
return once the fault condition is removed.
17
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPIC44H01
4-CHANNEL SERIAL AND PARALLEL HIGH-SIDE PRE-FET DRIVER
SLIS088 – SEPTEMBER 1998
PRINCIPLES OF OPERATION
V
(PWR)
+
V
(CP)
GATEx
HS Gate
Drive
V
CC
I
50 µA
100 Ω
Deglitch
Timer
SRCx
2 Vbg
Comp
OSC
Normal Load
Open Load
Input
GATEx
SRCx
Input
GATEx
SRCx
V
(open)
V
(open)
t
<t
(deglitch)
SRCx Rises to
With Open
Load Due to 50-µA
(deglitch)
V
CC
Open
Load
FLT
FLT
Current Source
Occurs
Figure 11. Open-Load Fault Detection
18
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPIC44H01
4-CHANNEL SERIAL AND PARALLEL HIGH-SIDE PRE-FET DRIVER
SLIS088 – SEPTEMBER 1998
PRINCIPLES OF OPERATION
over-current detection/protection
On-state, over-current detection is implemented in TPIC44H01 by monitoring SRCx voltage with respect to
. Figure 12 shows the functionality of the over-current detection circuitry. When a channel is on (see
V
(PWR)
Figure 12), theexternalFETV iscomparedtotheV
faultthresholdtodetectanover-currentcondition.
DS
(OVDS)
IftheFETV exceedsV
timer provides programmable deglitch time, t
isturnedon.ThedeglitchtimerstartsonlywhenV >V
, thecomparatordetectsanover-currenteventandadeglitchtimerbegins. The
DS
(OVDS)
(see Table 4), to allow V
voltage to stabilize after the FET
OC
DS
,andresetswhenV <V
.IftheV
(OVDS) (OVDS)
DS
(OVDS)
DS
threshold is exceeded for the entire deglitch time, a valid over-current shutdown fault (OCSD) is recognized.
If an over-current fault is detected with AR_ENBL = 0, a real-time fault condition is flagged to the host controller
by latching FLT low, the appropriate internal fault bit is set, and the GATEx output is latched off. GATEx will
remain off until the error condition has been corrected and the input bit or parallel input is cycled off then on.
An over-heating condition of the FET can occur if the host controller continually re-enables the output under
short-to-ground conditions.
If an over-current fault is detected with AR_ENBL = 1, FLT is latched low, the appropriate internal fault bit is set,
and the gate output is disabled until an auto-retry timer re-enables it. If the over-current remains, auto-retry
provides a low duty cycle PWM (≈ 0.75%) function to protect the FET from over heating. The PWM period is
defined as t
+ t
, while the duty cycle is defined as t
/ (t
+ t
). The auto-retry cycle is
(OC)
(retry)
(OC)
(OC)
(retry)
maintained until the fault has been eliminated and/or until the channel is turned off by both the INx parallel input
and the serial control bit. The host controller can read the serial port of the device to determine which channel
reported the fault condition. Fault bits (1:8) distinguish faults for each of the output channels (see Table 3).
V
(PWR)
+
–
V
V
(OVDS)
V
DS
+
Comp
–
Deglitch
Timer
100 Ω
SRCx
OSC
Over-Current
AR_ENBL = 0
Over-Current
AR_ENBL = 1
Normal Load
Input
Input
Input
t
(retry)
GATEx
GATEx
GATEx
V
V
V
(OVDS)
(OVDS)
(OVDS)
V
DS
V
DS
V
DS
<t
(deglitch)
t
t
(deglitch)
(deglitch)
FLT
FLT
FLT
Figure 12. Over-Current Fault Detection
19
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPIC44H01
4-CHANNEL SERIAL AND PARALLEL HIGH-SIDE PRE-FET DRIVER
SLIS088 – SEPTEMBER 1998
PRINCIPLES OF OPERATION
external over-current threshold generation
The TPIC44H01 device provides several means for setting V
, the threshold voltage used to detect
(OVDS)
over-current. Figure 13 shows operation of the V
generation circuitry. Any voltage appearing at the
(OVDS)
MUXOUT node (see Figure 13) will be forced across R1A, setting up a current equal to V
current is passed through R1B, a resistor matched to R1A, thereby generating an IR drop, V
/R1A. This
, down from
(MUXOUT)
(OVDS)
V
, which is identical to V
. The user can select either an internally generated ~1.25-V band-gap
(PWR)
(MUXOUT)
reference or can provide an external reference voltage using the V
pin to control V
. The internal
(COMPx)
(OV)
reference is selected by connecting the V
pin to V . This forces a comparator with a threshold of V
(COMPx)
CC CC
– V to a state where it controls the analog AMUX block to connect MUXOUT to internal V
.
(F)
ref
A user adjustable V
threshold can be set by supplying a voltage to the V
pin in the range of 0.1
(COMPx)
(OVDS)
to 2.5 V. With V
voltage in this range, the comparator controlling AMUX is in the state where V
(COMPx)
(COMPx)
voltage is connected to MUXOUT. Proper layout techniques should be used in the grounding network for the
V
circuit on the TPIC44H01. Ground for the pre-driver and V network should be connected to a
(COMP)
(COMPx)
Kelvin ground, if available. Otherwise, there should be a single point contact back to PGND of the FET array.
Improper grounding techniques may result in inaccurate fault detection.
V
CC
V
(PWR)
Shared by Channels
1 and 2 or 3 and 4
V
CC
R1B/R1A Matching ± 5%
R1B
V
(OVDS)
R2
R3
V
= ± 10 mV
1X
Buffer
V
IO
(PK_x)
+
Switched by
Serial Input
Bit or by
OVDS
Detection
Comp
_
SRCx
Parallel Input
Internal
V –V
CC (F)
MUXOUT
V
ref(Vbg)
V
CC
V
CC
_
R4
+
Comp
AMUX
V
(COMPx)
+
Op-Amp
_
I
R5
V
IO
= ± 5 mV
C1
R1A
NOTES: A.
V
should have at least 100 pF to ground to assure stability of the V
amplifier.
(COMPx)
(COMPx)
B. Equation for dynamic fault threshold voltage at V
:
(COMP)
– t RC
(1)
V
(t)
V
e
V
(0)
(COMPx)
(PK_x)
(COMPx)
WhereV
(t)isthevoltageatV
attimet,V
isthevoltageatV
setbytheR2andR3resistor
(COMPx)
(COMPx)
(PK_x)
(PK_x)
(0)isthevoltagesetupbytheR4
divider, CisthevalueofC1, RistheparallelcombinationofR4andR5, andV
and R5 resistor divider.
(COMPx)
Figure 13. Over-Current Fault Threshold Generation
20
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPIC44H01
4-CHANNEL SERIAL AND PARALLEL HIGH-SIDE PRE-FET DRIVER
SLIS088 – SEPTEMBER 1998
PRINCIPLES OF OPERATION
dynamic over-current threshold generation
Figure 13 shows the internal circuitry associated with V
and the external resistor divider and capacitor
(PK_x)
connectedtoV
.TheintentofthisimplementationistoallowadynamicV
voltagetobegenerated
(COMPx)
(COMPx)
which begins at the voltage referenced to the V
pin and decays as an RC discharge to the resistor divider
(PK_x)
voltagesetupbythenetworkontheV
pin.Figure14showsanexampleofthedynamicV
voltage
(COMPx)
(COMPx)
waveform. This waveform will be generated each time a channel is switched from off to on by either a serial bit
or parallel input. The V threshold begins at a high value to allow the high in-rush current associated with
(OVDS)
cold lamp filament resistance and decays at an RC time constant to emulate the current decrease in the lamp
as the filament warms up. The steady-state threshold after the RC decay provides protection against soft-short
conditions that could cause the FET to over heat after a long period of time. Selection of V
voltage and
(PK_x)
V
resistor divider and capacitor provides the user with the flexibility to accommodate a wide variety of
(COMPx)
lamp types. The TPIC44H01 thus provides a wide dynamic range of the over-current detection function, and
a time-dependent variation in the threshold that are user adjustable by the selection of external components.
3
Dynamic V
,
(COMPx)
= 2.5 V,
2.5
2
V
V
(peak)
(sustained)
= 0.2 V
1.5
1
0.5
0
–20
0
20
40
60
80 100 120 140 160 180 200 220 240
t – Time – ms
Figure 14. Dynamic Fault Threshold Voltage
21
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPIC44H01
4-CHANNEL SERIAL AND PARALLEL HIGH-SIDE PRE-FET DRIVER
SLIS088 – SEPTEMBER 1998
PRINCIPLES OF OPERATION
To demonstrate how V
threshold, Figure 15 shows both waveforms. Figure 16 illustrates a typical V
voltage is reflected down from V
to establish the high-side V
(COMPx)
(PWR) (OVDS)
voltage waveform as
(SRCx)
compared to V
during a normal turn-on transition.
(OVDS)
8
V
V
Voltage,
(OVDS)
= 8 V
(PWR)
6
4
2
Dynamic V
,
(COMPx)
= 2.5 V,
V
V
(peak)
(sustained)
= 0.2 V
0
–20
20
60
100
140
180
220
t – Time – ms
Figure 15. V
Mirrored From V
to Generate V
Threshold
(OVDS)
(COMPx)
(PWR)
8
V
V
Voltage,
(OVDS)
= 8 V
(PWR)
6
4
2
Typical V
Voltage Waveform
(SRCx)
Parallel Input or SDI Bit
0
–20
20
60
100
140
180
220
t – Time – ms
Figure 16. V
Compared to V
(SRCx)
(OVDS)
22
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPIC44H01
4-CHANNEL SERIAL AND PARALLEL HIGH-SIDE PRE-FET DRIVER
SLIS088 – SEPTEMBER 1998
PRINCIPLES OF OPERATION
short-to-ground detection/protection
The TPIC44H01 provides short-to-ground detection to protect the external FET from a more severe condition
than an over-current condition. This is accomplished by engaging a reduced deglitch time should a
short-to-ground be detected, thereby turning off the FET faster than in an over-current condition. Figure 17
illustrates operation of the short-to-ground detection scheme. A short-to-ground is detected during on-state by
monitoring the condition of the low-side comparator in addition to the V
comparator. If the low-side
(OVDS)
comparator indicates SRCx voltage is below the V
fault threshold voltage (2-V referenced to ground),
(STG)
bg
a short-to-ground condition is detected. Should this condition exist for the entire duration of t
, a valid fault
(STG)
is registered, causing the associated gate drive output to turn off, the FLT pin to latch low, and the appropriate
serial data fault bits to be set. Deglitch of short-to-ground detection relies on the over-current deglitch timer,
whichbeginsiftheFETV exceedsV
(thatisover-currentevent).However,detectionofshort-to-ground
DS
(OVDS)
reduces the deglitch time from t
to t
, as shown in Table 4. The deglitch time allows V
voltage to
(OC)
(STG)
(SRCx)
stabilize after the FET is turned on, and to distinguish between normal and shorted loads.
As shown in Figure 17, three short-to-ground cases can occur.
Case 1: SRCx is shorted to ground prior to gate drive turn on. GATEx is shut off when t
is reached.
(STG)
Case 2: SRCx is shorted to ground after gate drive is turned on and V
falls beneath V
before
(SRCx)
(STG)
t
isexceeded.Thus,t
isinitiatedonceV
fallsbeneathV
andGATExisshut
(OVDS)
(STG)
(STG)
(SRCx)
off when t
is reached.
(STG)
Case 3: Aftergatedriveisturnedon,SRCxispulledbeneathV
,thenfallsbeneathV
aftert
(OVDS)
(STG) (STG)
isreached. GATExisnotshutoffwhent
isreached,butshutsoffimmediatelywhenSRCxfall
(STG)
beneath V
.
(STG)
23
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPIC44H01
4-CHANNEL SERIAL AND PARALLEL HIGH-SIDE PRE-FET DRIVER
SLIS088 – SEPTEMBER 1998
PRINCIPLES OF OPERATION
V
(PWR)
+
–
V
CM
+
+
Deglitch
Timer and
Logic
V
(OVDS)
Comp
V
CC
–
GATEx
I
OSC
50 µA
100 Ω
+
SRCx
Comp
–
V
= 2 Vbg
(STG)
Normal Load
Shorted Load
Case 2
Case 1
Case 3
Input
GATEx
SRCx
Input
GATEx
V
V
V
V
(OVDS)
(STG)
(OVDS)
(STG)
SRCx
FLT
t
(STG)
<t
(STG)
t
(OC)
t
(STG)
(STG)
<t
(STG)
<t
FLT
Figure 17. Short-to-Ground Fault Detection
24
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPIC44H01
4-CHANNEL SERIAL AND PARALLEL HIGH-SIDE PRE-FET DRIVER
SLIS088 – SEPTEMBER 1998
PRINCIPLES OF OPERATION
sleep state
TheTPIC44H01providesasleepstateinwhichminimalcurrentisdrawnfromV andV
. Sleepstatecan
CC
(PWR)
be engaged using the serial interface by programming the SDI MSB to a logic 1 and latching the sleep bit with
a low-to-high transition of CS. For parallel operation, sleep state can also be engaged immediately by
simultaneously forcing a logic low on CS and RESET. When sleep state is engaged, the charge pump is
disabled, I
timers are cleared.
toallanalogcircuitsisdisabled, allgatedriveoutputsareturnedoff, andallregistersanddeglitch
(bias)
Sleep state is terminated, returning the device to normal operation, by the next high-to-low transition of CS, or
by the next low-to-high transition of any parallel input, IN1–4 (providing all other non-transition INx inputs are
held low). Since sleep state disables the charge pump shared by all high-side gate drives, a delay time, t
,
(active)
of approximately 512 µs is implemented after sleep state is terminated (see Figure 18) to allow sufficient time
for V to charge and all analog circuits to power up and stabilized before any gate drive outputs can be
(CP)
re-engaged.
Input
Sleep State
Internal
Sleep Bit
t
(active)
GATEx
Figure 18. Sleep State Timing Diagram
gate drive control and sleep state
Refer to the schematic/block diagram and note the internal regulator block, 5-V Vreg, near V
pin. The
(PWR)
internal regulator provides power to gate control input logic of gate drives any time an external voltage is applied
toV pin. Gate control block inputs have a passive pulldown which must be overcome with a high level from
(PWR)
the core logic to turn on gate drives. This scheme ensures external FETs are actively held off when V
(PWR)
pin while V
(PWR)
voltage is applied while sleep state is induced, and/or if voltage is not supplied to the V
CC
voltage is present. This eliminates the risk of external FET turn-on from drain-to-gate leakage current of theFET,
allows the user to switch off V as another option to disable the device and gate drives for system sleep state,
CC
and maintains voltage applied to the V
pin.
(PWR)
25
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPIC44H01
4-CHANNEL SERIAL AND PARALLEL HIGH-SIDE PRE-FET DRIVER
SLIS088 – SEPTEMBER 1998
PRINCIPLES OF OPERATION
inductive voltage transients
A typical application for the TPIC44H01 is to switch inductive loads. Whenever an inductive load is switched
off, the inductive flyback can cause a large voltage spike to occur at the FET source, or SRCx pin. These spikes
can also capacitively couple to the FET gate. The voltages at the GATEx and SRCx pins must be limited from
extendingsignificantlybelowdevicegroundtopreventpotentialinternallatchupandtoavoiddamagetotheFET
by exceeding the maximum BV
. To address this concern, the TPIC44H01 provides an internal diode
DSS
connected between device GND and GATEx to limit the gate voltage from exceeding more than a diode drop
negative below ground. If no additional external component is provided to limit V and to recirculate the
(source)
inductive energy, the FET source will fly negative due to the load inductive flyback during turn-off. The FET
source will thus extend as negative as V – V . Since the GATEx pin is clamped V beneath GND,
G
GS
(diode)
V
=V
–V
–V .Duringthiscondition,theFETisoperatinginahighpowerdissipationregion
(source)
(GND)
(diode) GS
because V is large while I is flowing. Design of the FET thermal system must consider this power to avoid
DS
DS
excessive junction temperature.
For high current applications where the FET power dissipation is a concern, an external recirculation diode
connected between the source of the FET (diode cathode) and ground (diode anode) can be implemented to
limitthesourcevoltageto–V ofthediode. Damagetothedevicecanoccurifproperprotectionisnotprovided.
(F)
5 V
INx
0 V
GATEx
V
–V
(GND) (F)
V
– V
DS
(PWR)
SRCx
0 V
V –V – V
(GND) (F) GS
Figure 19. Inductive Load Waveforms
26
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPIC44H01
4-CHANNEL SERIAL AND PARALLEL HIGH-SIDE PRE-FET DRIVER
SLIS088 – SEPTEMBER 1998
MECHANICAL DATA
DA (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
38 PIN SHOWN
0,30
0,19
M
0,13
0,65
38
20
6,20
8,40
NOM 7,80
0,15 NOM
Gage Plane
1
19
0,25
A
0°–8°
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
30
32
38
DIM
11,10
10,90
11,10
10,90
12,60
12,40
A MAX
A MIN
4040066/D 4/98
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions include mold flash or protrusion.
D. Falls within JEDEC MO-153
27
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
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TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
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Copyright 1998, Texas Instruments Incorporated
相关型号：
TPIC44L01DBR
1.2-mA/1.2-mA 4-channel gate driver with disable in Short-Load, Open-Load, Over-Bat-voltage 24-SSOP -40 to 125
TI
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