TPIC6B273DWR [TI]
Eight Power DMOS-Transistor Outputs of 150-mA Continuous Current;
| 型号： | TPIC6B273DWR |
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TEXAS INSTRUMENTS |
| 描述： | Eight Power DMOS-Transistor Outputs of 150-mA Continuous Current 光电二极管 逻辑集成电路 触发器 |
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TPIC6B273
POWER LOGIC OCTAL D-TYPE LATCH
SLIS031 – APRIL 1994 – REVISED JULY 1995
Low r
. . . 5 Ω Typical
DS(on)
DW OR N PACKAGE
(TOP VIEW)
Avalanche Energy . . . 30 mJ
Eight Power DMOS-Transistor Outputs of
150-mA Continuous Current
CLR
D1
V
CC
D8
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
500-mA Typical Current-Limiting Capability
Output Clamp Voltage . . . 50 V
Low Power Consumption
D2
D7
DRAIN1
DRAIN2
DRAIN3
DRAIN4
D3
DRAIN8
DRAIN7
15 DRAIN6
14
13
12
11
DRAIN5
D6
description
The TPIC6B273 is a monolithic, high-voltage,
medium-current, power logic octal D-type latch
with DMOS-transistor outputs designed for use in
systems that require relatively high load power.
The device contains a built-in voltage clamp on
the outputs for inductive transient protection.
Power driver applications include relays, sole-
noids, and other medium-current or high-voltage
loads.
D4
D5
GND
CLK
†
logic symbol
1
CLR
CLK
R
11
C1
2
4
5
6
7
The TPIC6B273 contains eight positive-edge-
triggered D-type flip-flops with a direct clear input.
Each flip-flop features an open-drain power
DMOS-transistor output.
D1
D2
D3
D4
D5
D6
D7
D8
1D
DRAIN1
DRAIN2
DRAIN3
DRAIN4
DRAIN5
DRAIN6
DRAIN7
DRAIN8
3
8
9
12
13
18
19
14
15
16
17
When clear (CLR) is high, information at the D
inputs meeting the setup time requirements is
transferred to the DRAIN outputs on the positive-
going edge of the clock (CLK) pulse. Clock
triggering occurs at a particular voltage level and
is not directly related to the transition time of the
positive-going pulse. When the clock input (CLK)
is at either the high or low level, the D input signal
has no effect at the output. An asynchronous CLR
is provided to turn all eight DMOS-transistor
outputs off. When data is low for a given output,
the DMOS-transistor output is off. When data is
high, theDMOS-transistoroutputhassink-current
capability.
†
This symbol is in accordance with ANSI/IEEE Standard 91-1984
and IEC Publication 617-12.
FUNCTION TABLE
(each channel)
INPUTS
CLK
OUTPUT
DRAIN
CLR
D
L
H
H
H
X
↑
↑
X
H
L
H
L
H
Outputs are low-side, open-drain DMOS
transistors with output ratings of 50 V and 150-mA
continuous sink-current capability. Each output
provides a 500-mA typical current limit at
L
X
Latched
H = high level, L = low level, X = irrelevant
T
= 25°C. The current limit decreases as the
C
junction temperature increases for additional
device protection.
The TPIC6B273 is characterized for operation over the operating case temperature range of –40°C to 125°C.
Copyright 1997, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPIC6B273
POWER LOGIC OCTAL D-TYPE LATCH
SLIS031 – APRIL 1994 – REVISED JULY 1995
logic diagram (positive logic)
4
5
6
DRAIN1
DRAIN2
DRAIN3
1
CLR
1D
CLR
2
D1
11
C1
CLK
CLR
1D
3
D2
C1
CLR
1D
8
D3
C1
7
DRAIN4
DRAIN5
CLR
1D
9
D4
C1
14
15
16
CLR
1D
12
D5
C1
DRAIN6
DRAIN7
CLR
13
D6
1D
C1
CLR
18
D7
1D
C1
17
10
DRAIN8
GND
CLR
19
D8
1D
C1
2
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TPIC6B273
POWER LOGIC OCTAL D-TYPE LATCH
SLIS031 – APRIL 1994 – REVISED JULY 1995
schematic of inputs and outputs
EQUIVALENT OF EACH INPUT
TYPICAL OF ALL DRAIN OUTPUTS
V
CC
DRAIN
50 V
Input
25 V
20 V
12 V
GND
GND
absolute maximum ratings over recommended operating case temperature range (unless
†
otherwise noted)
Logic supply voltage, V
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
CC
Logic input voltage range, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 7 V
Power DMOS drain-to-source voltage, V
I
(see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 V
DS
Continuous source-to-drain diode anode current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500 mA
Pulsed source-to-drain diode anode current (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 A
Pulsed drain current, each output, all outputs on, I , T = 25°C (see Note 3) . . . . . . . . . . . . . . . . . . . 500 mA
D
C
Continuous drain current, each output, all outputs on, I , T = 25°C . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 mA
D
C
Peak drain current single output, I ,T = 25°C (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500 mA
DM
C
Single-pulse avalanche energy, E (see Figure 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 mJ
AS
Avalanche current, I (see Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500 mA
AS
Continuous total dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table
Operating virtual junction temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 150°C
J
Operating case temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 125°C
C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values are with respect to GND.
2. Each power DMOS source is internally connected to GND.
3. Pulse duration ≤ 100 µs and duty cycle ≤ 2%.
4. DRAIN supply voltage = 15 V, starting junction temperature (T ) = 25°C, L = 200 mH, I
= 0.5 A (see Figure 4).
AS
JS
DISSIPATION RATING TABLE
T
≤ 25°C
DERATING FACTOR
T = 125°C
C
POWER RATING
C
PACKAGE
POWER RATING
ABOVE T = 25°C
C
DW
N
1389 mW
11.1 mW/°C
10.5 mW/°C
278 mW
1050 mW
263 mW
3
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TPIC6B273
POWER LOGIC OCTAL D-TYPE LATCH
SLIS031 – APRIL 1994 – REVISED JULY 1995
recommended operating conditions
MIN
MAX
UNIT
V
Logic supply voltage, V
CC
4.5
5.5
High-level input voltage, V
IH
0.85 V
V
CC
Low-level input voltage, V
0.15 V
V
IL
Pulsed drain output current, T = 25°C, V
CC
= 5 V (see Notes 3 and 5)
CC
–500
20
500
mA
ns
ns
ns
°C
C
Setup time, D high before CLK↑, t (see Figure 2)
su
Hold time, D high after CLK↑, t (see Figure 2)
20
h
Pulse duration, t (see Figure 2)
40
w
Operating case temperature, T
–40
125
C
electrical characteristics, V
= 5 V, T = 25°C (unless otherwise noted)
CC
C
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Drain-to-source breakdown
voltage
V
V
I
I
= 1 mA
50
V
(BR)DSX
D
Source-to-drain diode forward
voltage
= 100 mA
0.85
1
V
SD
F
I
I
High-level input current
Low-level input current
V
V
= 5.5 V,
= 5.5 V,
V = V
CC
1
–1
µA
µA
IH
CC
I
V = 0
I
IL
CC
All outputs off
All outputs on
20
100
300
I
I
I
Logic supply current
Nominal current
V
= 5.5 V
µA
mA
µA
CC
CC
150
V
= 0.5 V, I = I ,
T
T
= 85°C,
= 125°C
DS(on)
N
D
C
90
N
See Notes 5, 6, and 7
V
V
= 40 V,
= 40 V,
V
CC
V
CC
V
CC
V
CC
= 5.5 V
= 5.5 V,
= 4.5 V
= 4.5 V,
0.1
0.15
4.2
5
8
DS
Off-state drain current
DSX
DS
C
I
I
= 100 mA,
= 100 mA,
5.7
D
Static drain-to-source on-state
resistance
See Notes 5 and 6
and Figures 6 and 7
D
C
r
Ω
6.8
5.5
9.5
8
DS(on)
T
= 125°C
I
D
= 350 mA,
V
CC
= 4.5 V
switching characteristics, V
= 5 V, T = 25°C
C
CC
PARAMETER
TEST CONDITIONS
MIN
TYP
150
90
MAX
UNIT
ns
t
t
t
t
t
t
Propagation delay time, low-to-high-level output from CLK
Propagation delay time, high-to-low-level output from CLK
Rise time, drain output
PLH
ns
PHL
C
= 30 pF,
See Figures 1, 2, and 8
I = 100 mA,
D
L
200
200
100
300
ns
r
Fall time, drain output
ns
f
Reverse-recovery-current rise time
Reverse-recovery time
I
F
= 100 mA,
di/dt = 20 A/µs,
a
rr
ns
See Notes 5 and 6 and Figure 3
NOTES: 3. Pulse duration ≤ 100 µs and duty cycle ≤ 2%.
5. Technique should limit T – T to 10°C maximum.
J
C
6. These parameters are measured with voltage-sensing contacts separate from the current-carrying contacts.
7. Nominal current is defined for a consistent comparison between devices from different sources. It is the current that produces a
voltage drop of 0.5 V at T = 85°C.
C
4
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TPIC6B273
POWER LOGIC OCTAL D-TYPE LATCH
SLIS031 – APRIL 1994 – REVISED JULY 1995
thermal resistance
PARAMETER
TEST CONDITIONS
MIN
MAX
90
UNIT
DW package
N package
R
Thermal resistance, junction-to-ambient
All 8 outputs with equal power
°C/W
θJA
95
PARAMETER MEASUREMENT INFORMATION
24 V
5 V
20
5 V
I
D
CLK
D
V
CC
0 V
5 V
235 Ω
Output
DUT
11
1
4–7,
14–17
CLK
0 V
5 V
Word
Generator
(see Note A)
DRAIN
D
C
= 30 pF
L
CLR
CLR
(see Note B)
0 V
GND
10
24 V
Output
0.5 V
TEST CIRCUIT
VOLTAGE WAVEFORMS
Figure 1. Resistive-Load Test Circuit and Voltage Waveforms
5 V
D
5 V
0 V
5 V
CLK
50%
50%
24 V
1
20
CC
0 V
V
CLR
t
t
PHL
PLH
Word
I
D
Generator
(see Note A)
D
24 V
235 Ω
DUT
90%
90%
Output
10%
10%
4–7,
14–17
Output
0.5 V
Word
Generator
(see Note A)
11
t
t
f
r
DRAIN
CLK
SWITCHING TIMES
C
= 30 pF
L
GND
10
(see Note B)
5 V
0 V
50%
CLK
t
su
TEST CIRCUIT
t
h
5 V
0 V
D
50%
50%
t
w
INPUT SETUP AND HOLD WAVEFORMS
Figure 2. Test Circuit, Switching Times, and Voltage Waveforms
NOTES: A. The word generator has the following characteristics: t ≤ 10 ns, t ≤ 10 ns, t = 300 ns, pulsed repetition rate (PRR) = 5 KHz,
r
f
w
Z
C
= 50 Ω.
O
L
B.
includes probe and jig capacitance.
5
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TPIC6B273
POWER LOGIC OCTAL D-TYPE LATCH
SLIS031 – APRIL 1994 – REVISED JULY 1995
PARAMETER MEASUREMENT INFORMATION
TP K
DRAIN
0.1 A
Circuit
Under
Test
2500 µF
250 V
di/dt = 20 A/µs
+
–
I
F
25 V
L = 1 mH
I
F
(see Note A)
0
TP A
25% of I
RM
t
2
t
1
t
3
Driver
I
RM
R
G
t
V
a
GG
(see Note B)
50 Ω
t
rr
CURRENT WAVEFORM
TEST CIRCUIT
NOTES: A. The DRAIN terminal under test is connected to the TP K test point. All other terminals are connected together and connected to the
TP A test point.
B. The V
amplitude and R are adjusted for di/dt = 20 A/µs. A V
double-pulse train is used to set I = 0.1 A, where t = 10 µs,
GG F 1
GG
= 7 µs, and t = 3 µs.
G
t
2
3
Figure 3. Reverse-Recovery-Current Test Circuit and Waveforms of Source-to-Drain Diode
5 V
15 V
t
w
t
av
20
5 V
Input
V
CC
10.5 Ω
1
See Note B
0 V
CLR
I
D
I
= 0.5 A
AS
200 mH
11
DUT
I
D
Word
Generator
(see Note A)
CLK
D
4–7,
14–17
V
DS
DRAIN
V
= 50 V
(BR)DSX
MIN
GND
V
DS
10
VOLTAGE AND CURRENT WAVEFORMS
TEST CIRCUIT
NOTES: A. The word generator has the following characteristics: t 10 ns, t ≤ 10 ns, Z = 50 Ω.
r ≤
AS
f
O
B. Input pulse duration, t , is increased until peak current I
= 0.5 A.
w
Energy test is defined as E = I
AS AS
x V
x t /2 = 30 mJ.
(BR)DSX av
Figure 4. Single-Pulse Avalanche Energy Test Circuit and Waveforms
6
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TPIC6B273
POWER LOGIC OCTAL D-TYPE LATCH
SLIS031 – APRIL 1994 – REVISED JULY 1995
TYPICAL CHARACTERISTICS
PEAK AVALANCHE CURRENT
vs
DRAIN-TO-SOURCE ON-STATE RESISTANCE
vs
TIME DURATION OF AVALANCHE
DRAIN CURRENT
10
4
18
V
= 5 V
CC
See Note A
T
C
= 25°C
16
14
12
10
T
C
= 125°C
2
1
8
6
4
0.4
T
C
= 25°C
0.2
0.1
T
= –40°C
C
2
0
0
100
200
300
400
500
600
700
0.1
0.2
0.4
1
2
4
10
I – Drain Current – mA
D
t
– Time Duration of Avalanche – ms
av
Figure 5
Figure 6
STATIC DRAIN-TO-SOURCE ON-STATE RESISTANCE
SWITCHING TIME
vs
vs
LOGIC SUPPLY VOLTAGE
CASE TEMPERATURE
8
300
250
200
I
= 100 mA
I
= 100 mA
D
D
See Note A
See Note A
7
6
t
f
T
= 125°C
C
t
r
5
4
T
= 25°C
C
t
t
PLH
PHL
150
100
50
3
2
T
C
= – 40°C
1
0
–50 –25
0
25
50
75
100
125
4
4.5
5
5.5
6
6.5
7
T
C
– Case Temperature – °C
V
CC
– Logic Supply Voltage – V
Figure 7
Figure 8
NOTE C: Technique should limit T – T to 10°C maximum.
J
C
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPIC6B273
POWER LOGIC OCTAL D-TYPE LATCH
SLIS031 – APRIL 1994 – REVISED JULY 1995
THERMAL INFORMATION
MAXIMUM CONTINUOUS
DRAIN CURRENT OF EACH OUTPUT
vs
MAXIMUM PEAK DRAIN CURRENT
OF EACH OUTPUT
vs
NUMBER OF OUTPUTS CONDUCTING
SIMULTANEOUSLY
NUMBER OF OUTPUTS CONDUCTING
SIMULTANEOUSLY
0.5
0.45
0.4
V
CC
= 5 V
d = 10%
d = 20%
0.45
0.4
0.35
0.3
0.35
d = 50%
0.3
0.25
0.2
T
C
= 25°C
0.25
d = 80%
0.2
0.15
0.1
0.15
0.1
T
C
= 100°C
V
T
= 5 V
CC
= 25°C
T
C
= 125°C
C
d = t /t
w period
0.05
0.05
0
= 1 ms/t
period
0
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
N – Number of Outputs Conducting Simultaneously
N – Number of Outputs Conducting Simultaneously
Figure 9
Figure 10
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
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