TPL0401A-10-Q1 [TI]
具有 I2C 接口（地址 0101110）的汽车类 128 抽头单通道数字电位器;
| 型号： | TPL0401A-10-Q1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有 I2C 接口（地址 0101110）的汽车类 128 抽头单通道数字电位器 电位器 |
| 文件： | 总32页 (文件大小：713K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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TPL0401A-10-Q1
TPL0401B-10-Q1
ZHCSFW3 –NOVEMBER 2016
TPL0401x-10-Q1 具有 I2C 接口的 128 抽头单通道数字电位计
1 特性
3 说明
1
•
单通道 128 位置分辨率
10kΩ 端到端电阻选项
TPL0401x-10-Q1 器件是一款具有 128 个抽头位置的
单通道线性抽头数字电位计。TPL0401x-10-Q1 的低电
平端子内部连接至 GND。可使用 I2C 接口来调节抽头
位置。TPL0401x-10-Q1 采用 6 引脚 SC70 封装，额
定温度范围为 -40°C 至 +125°C。此部件有一个 10kΩ
端到端电阻，工作电源电压范围为 2.7V 至 5.5V。这
类产品广泛用于为低功耗 DDR3 存储器设定电压基
准。
•
•
•
•
•
•
•
•
•
•
低温度系数：22ppm/°C
I2C 串行接口
2.7V 至 5.5V 单电源运行
±20% 电阻容差
A 和 B 版本具有不同的 I2C 地址
L 端子内部连接至 GND
工作温度：-40°C 至 +125°C
采用行业标准 SC70 封装
根据 JESD 22 测试得出的静电放电 (ESD) 性能
TPL0401x-10-Q1 的低电平端子内部连接至 GND。
器件信息(1)
器件型号
封装
封装尺寸（标称值）
–
2000V 人体放电模型（A114-B，II 类）
TPL0401A-10-Q1
TPL0401B-10-Q1
SC70 (6)
2.00mm × 1.25mm
2 应用
(1) 要了解所有可用封装，请参见数据表末尾的可订购产品附录。
•
•
•
•
•
机械电位计的替代产品
可调电源
可调增益放大器和偏移修剪
设定点阈值精密校准
传感器微调和校准
简化电路原理图
I
ë55
Çt[0401!/.-10-v1
{ꢀ[
WIPER
REGISTER
I2C INTERFACE
í
{5!
Db5 Copyright © 2016, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SLIS182
TPL0401A-10-Q1
TPL0401B-10-Q1
ZHCSFW3 –NOVEMBER 2016
www.ti.com.cn
目录
9.6 Register Maps ........................................................ 19
10 Application and Implementation........................ 21
10.1 Application Information.......................................... 21
10.2 Typical Application ............................................... 21
11 Power Supply Recommendations ..................... 23
11.1 Power Sequence................................................... 23
11.2 Power-On Reset Requirements ........................... 23
11.3 I2C Communication After Power Up ..................... 23
1
2
3
4
5
6
7
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Device Comparison Table..................................... 3
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
7.1 Absolute Maximum Ratings ...................................... 4
7.2 ESD Ratings.............................................................. 4
7.3 Recommended Operating Conditions....................... 4
7.4 Thermal Information ................................................. 4
7.5 Electrical Characteristics........................................... 4
7.6 Timing Requirements................................................ 5
7.7 Typical Characteristics.............................................. 7
Parameter Measurement Information .................. 9
Detailed Description ............................................ 11
9.1 Overview ................................................................. 11
9.2 Functional Block Diagram ....................................... 11
9.3 Feature Description................................................. 11
9.4 Device Functional Modes........................................ 11
9.5 Programming........................................................... 15
11.4 Wiper Position While Unpowered and After Power
Up............................................................................. 24
12 Layout................................................................... 25
12.1 Layout Guidelines ................................................. 25
12.2 Layout Example .................................................... 25
13 器件和文档支持 ..................................................... 26
13.1 文档支持................................................................ 26
13.2 相关链接................................................................ 26
13.3 接收文档更新通知 ................................................. 26
13.4 社区资源................................................................ 26
13.5 商标....................................................................... 26
13.6 静电放电警告......................................................... 26
13.7 Glossary................................................................ 26
14 机械、封装和可订购信息....................................... 27
8
9
4 修订历史记录
日期
修订版本
注释
2016 年 11 月
*
首次发布。
2
Copyright © 2016, Texas Instruments Incorporated
TPL0401A-10-Q1
TPL0401B-10-Q1
www.ti.com.cn
ZHCSFW3 –NOVEMBER 2016
5 Device Comparison Table
PART NUMBER
TPL0401A-10-Q1
TPL0401B-10-Q1
END-TO-END RESISTANCE
I2C ADDRESS
010 1110 (0×2E)
011 1110 (0×3E)
10 kΩ
10 kΩ
6 Pin Configuration and Functions
DCK Package
6-Pin SC70
Top View
1
2
6
VDD
GND
SCL
H
5
W
SDA
L
3
4
Pin Functions
PIN
TYPE
DESCRIPTION
NO.
NAME
VDD
GND
SCL
SDA
W
1
Power
—
Positive supply voltage
2
Ground
3
I
I2C Clock
4
I/O
I/O
I/O
I/O
I2C Data
5
Wiper terminal
High terminal
6
H
—
L
Low terminal (Internally connected to GND)
Copyright © 2016, Texas Instruments Incorporated
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TPL0401B-10-Q1
ZHCSFW3 –NOVEMBER 2016
www.ti.com.cn
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
(1)
MIN
MAX
7
UNIT
V
VDD
Supply voltage
VDD to GND
–0.3
IH, IL, IW
Continuous current
±5
mA
Digital input pins (SDA, SCL)
Potentiometer pins (H, W)
Maximum junction temperature
Storage temperature
–0.3
–0.3
VDD + 0.3
VDD + 0.3
130
VI
V
TJ(MAX)
Tstg
°C
°C
–65
150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
7.2 ESD Ratings
VALUE
±2500
±1000
UNIT
Human-body model (HBM), per AEC Q100-002(1)
Charged-device model (CDM), per AEC Q100-011
V(ESD)
Electrostatic discharge
V
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
5.5
UNIT
VDD
Supply voltage
2.7
V
V
VW,VH, SDA, SCL Terminal voltage
0
VDD
VIH
VIL
IW
Voltage input high ( SCL, SDA )
0.7 × VDD
VDD
V
Voltage input low ( SCL, SDA )
Wiper current
0
–2
0.3 × VDD
2
V
mA
°C
TA
Ambient operating temperature
–40
125
7.4 Thermal Information
TPL0401x-10-Q1
THERMAL METRIC(1)
DCK (SC70)
6 PINS
234
UNIT
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
110.5
79
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
7.2
ψJB
77
RθJC(bot)
N/A
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
7.5 Electrical Characteristics
Typical values are specified at 25°C and VDD = 3.3 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
10
MAX
12
UNIT
kΩ
Ω
RTOTAL
RH
End-to-end resistance
Terminal resistance
Wiper resistance
8
100
35
200
100
RW
Ω
4
Copyright © 2016, Texas Instruments Incorporated
TPL0401A-10-Q1
TPL0401B-10-Q1
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ZHCSFW3 –NOVEMBER 2016
Electrical Characteristics (continued)
Typical values are specified at 25°C and VDD = 3.3 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
10
MAX
UNIT
pF
CH
Terminal capacitance
Wiper capacitance
CW
TCR
11
pF
Resistance temperature coefficient
22
ppm/°C
–40°C to +105°C
0.5
1.5
IDD(STBY)
IIN-DIG
VDD standby current
µA
µA
–40°C to +125°C
Digital pins leakage current (SCL,
SDA Inputs)
–2.5
2.5
SERIAL INTERFACE SPECS (SDA, SCL)
0.7 ×
VDD
VIH
VIL
Input high voltage
Input low voltage
VDD
V
V
0.3 ×
VDD
0
VOL
CIN
Output low voltage
Pin capacitance
SDA Pin, IOL = 4 mA
SCL, SDA Inputs
0.4
V
7
pF
VOLTAGE DIVIDER MODE (VH = VDD, VW = Not Loaded)
INL(1)(2)
DNL(3)(2)
ZSERROR
FSERROR
TCV
Integral non-linearity
–0.5
–0.25
0
0.5
0.25
1.5
0
LSB
LSB
Differential non-linearity
(4)(5)
(6)(5)
Zero-scale error
0.75
LSB
Full-scale error
–1.5 –0.75
4
LSB
Ratiometric temperature coefficient Wiper set at mid-scale
ppm/°C
Wiper set at mid-scale,
CLOAD = 10 pF
BW
Bandwidth
2862
0.152
0.03
kHz
µs
TSW
Wiper settling time
See Figure 10
VH = 1 VRMS at 1 kHz,
measurement at W
THD+N
Total harmonic distortion
%
RHEOSTAT MODE (VH = VDD, VW = Not Loaded)
Rheostat mode integral non-
linearity
RINL(7)(8)
–1
1
0.5
2
LSB
LSB
LSB
Rheostat mode differential non-
linearity
RDNL(9)(8)
0.5
(10)(1
ROFFSET
Rheostat-mode zero-scale error
0
0.75
1)
(1) INL = ((VMEAS[code x] – VMEAS[code 0]) / LSB) – [code x]
(2) LSB = (VMEAS[code 127] – VMEAS[code 0]) / 127
(3) DNL = ((VMEAS[code x] – VMEAS[code x-1]) / LSB) – 1
(4) ZSERROR = VMEAS[code 0] / IDEAL_LSB
(5) IDEAL_LSB = VH/ 128
(6) FSERROR = [(VMEAS[code 127] – VH) / IDEAL_LSB] + 1
(7) RINL = ( (RMEAS[code x] – RMEAS[code 0]) / RLSB) – [code x]
(8) RLSB = (RMEAS[code 127] – RMEAS[code 0]) / 127
(9) RDNL = ( (RMEAS[code x] – RMEAS[code x–1]) / RLSB ) – 1
(10) ROFFSET = RMEAS[code 0] / IDEAL_RLSB
(11) IDEAL_RLSB = RTOT / 128
7.6 Timing Requirements
MIN
MAX
UNIT
STANDARD MODE
I2C Clock frequency
fSCL
0
4
100
50
kHz
µs
I2C Clock high time
tSCH
I2C Clock low time
tSCL
4.7
0
µs
I2C Spike time
tsp
ns
I2C Serial data setup time
tSDS
250
ns
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TPL0401B-10-Q1
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Timing Requirements (continued)
MIN
MAX
UNIT
ns
I2C Serial data hold time
tSDH
0
I2C Input rise time
tICR
1000
300
ns
I2C Input fall time
tICF
ns
I2C Output fall time, 10 pF to 400 pF bus
tOCF
300
ns
I2C Bus free time between stop and start
tBUF
4.7
4.7
4
µs
I2C Start or repeater start condition setup time
tSTS
µs
I2C Start or repeater start condition hold time
tSTH
µs
I2C Stop condition setup time
tSPS
4
µs
tVD(DATA)
tVD(ACK)
FAST MODE
fSCL
Valid data time, SCL low to SDA output valid
1
1
µs
Valid data time of ACK condition, ACK signal from SCL low to SDA (out) low
µs
I2C Clock frequency
0
400
50
kHz
µs
µs
ns
ns
ns
ns
ns
ns
µs
µs
µs
µs
µs
µs
I2C Clock high time
tSCH
0.6
I2C Clock low time
tSCL
1.3
I2C Spike time
tsp
0
I2C Serial data setup time
tSDS
100
I2C Serial data hold time
tSDH
0
I2C Input rise time
tICR
20
300
300
300
I2C Input fall time
tICF
20 × (VDD / 5.5)
I2C Output fall time, 10 pF to 400 pF bus
I2C Bus free time between stop and start
I2C Start or repeater start condition setup time
I2C Start or repeater start condition hold time
I2C Stop condition setup time
Valid data time, SCL low to SDA output valid
Valid data time of ACK condition, ACK signal from SCL low to SDA (out) low
tOCF
(VDD / 5.5) × 20
tBUF
1.3
1.3
0.6
0.6
tSTS
tSTH
tSPS
tVD(DATA)
tVD(ACK)
1
1
6
Copyright © 2016, Texas Instruments Incorporated
TPL0401A-10-Q1
TPL0401B-10-Q1
www.ti.com.cn
ZHCSFW3 –NOVEMBER 2016
7.7 Typical Characteristics
0.15
0.1
0.15
0.1
2.7 V
3.3 V
5.5 V
2.7 V
3.3 V
5.5 V
0.05
0
0.05
0
-0.05
-0.1
-0.15
-0.05
-0.1
-0.15
0
18
36
54
72
90
108
126
0
18
36
54
72
90
108
126
Digital Code
Digital Code
D001
D002
Figure 1. INL vs Tap Position (Potentiometer Mode)
Figure 2. DNL vs Tap Position (Potentiometer Mode)
1
0.5
0
0
2.7 V
3.3 V
5.5 V
2.7 V
3.3 V
5.5 V
-0.1
-0.2
-0.3
-0.4
-0.5
-0.6
-0.7
-0.8
-0.9
-1
-0.5
-1
0
16
32
48
64
80
96
112
128
-40
-20
0
20
40
60
80
100
120
Digital Code
Temperature (èC)
D003
D004
Figure 3. INL vs Tap Position (Rheostat Mode)
Figure 4. Full Scale Error vs Temperature
300
270
240
210
180
150
120
90
1
0.5
0
2.7 V
3.3 V
5.5 V
2.7 V
3.3 V
5.5 V
-0.5
60
30
-1
0
-40
-10
20
50
80
110
130
0
16
32
48
64
80
96
112
128
Temperature (èC)
Digital Code
D005
D006
Figure 5. End-to-End RTOTAL Change vs Temperature
Figure 6. Temperature Coefficient vs TAP Position
(Potentiometer Mode)
Copyright © 2016, Texas Instruments Incorporated
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TPL0401B-10-Q1
ZHCSFW3 –NOVEMBER 2016
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Typical Characteristics (continued)
300
270
240
210
180
150
120
90
0
-6
2.7 V
3.3 V
5.5 V
-12
-18
-24
-30
-36
-42
-48
-54
-60
Code 08
Code 10
Code 20
Code 40
60
30
0
0
16
32
48
64
80
96
112
128
103
104
105
106
107
Digital Code
Frequency (Hz)
D007
D008
Figure 7. Temperature Coefficient vs TAP Position
(Rheostat Mode)
Figure 8. Frequency Response
8
Copyright © 2016, Texas Instruments Incorporated
TPL0401A-10-Q1
TPL0401B-10-Q1
www.ti.com.cn
ZHCSFW3 –NOVEMBER 2016
8 Parameter Measurement Information
V
DD
R
= 1 kΏ
L
SDA
DUT
C
= 50 pF
L
(see Note A)
SDA LOAD CONFIGURATION
Two Bytes for READ Wiper Position Register
Stop
Condition Condition
(P) (S)
Start
Address
Bit 7
(MSB)
Data
Bit 7
(MSB)
Data
Bit 0
(LSB)
Stop
Condition
(P)
R/W
Bit 0
(LSB)
ACK
(A)
Address
Bit 1
t
t
sch
scl
0.7 x V
CCI
SCL
SDA
0.3 x V
CCI
t
t
icr
vd
t
t
sts
sp
t
t
icf
t
buf
vd
t
t
sps
ocf
0.7 x V
0.3 x V
CCI
CCI
t
t
vd(ack)
icr
t
sdh
t
t
icf
sds
t
sth
Repeat Start
Condition
Stop
Condition
VOLTAGE WAVEFORMS
BYTE
DESCRIPTION
I2C address
1
2
Wiper Position Data
A. CL includes probe and jig capacitance. tocf is measured with CL of 10 pF or 400 pF.
B. All inputs are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr/tf ≤ 30 ns.
C. All parameters and waveforms are not applicable to all devices.
Figure 9. I2C Interface Load Circuit and Voltage Waveforms
Copyright © 2016, Texas Instruments Incorporated
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TPL0401B-10-Q1
ZHCSFW3 –NOVEMBER 2016
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Parameter Measurement Information (continued)
50% VDD
SCL
DATA
ACK
tswx
VW
5% VH
A. Code change is from 0×40 to 0×00
B. All inputs are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr/tf ≤ 30 ns.
Figure 10. Switch Time Waveform (tSW
)
10
Copyright © 2016, Texas Instruments Incorporated
TPL0401A-10-Q1
TPL0401B-10-Q1
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ZHCSFW3 –NOVEMBER 2016
9 Detailed Description
9.1 Overview
The TPL0401x-10-Q1 has a single linear-taper digital potentiometer with 128 wiper positions and an end-to-end
resistance of 10 kΩ. The potentiometer can be used as a three-terminal potentiometer. The main operation of
TPL0401x-10-Q1 is in voltage divider mode.
The low (L) terminal of the TPL0401x-10-Q1 is tied directly to GND. The high (H) and low (GND) terminals of
TPL0401-10-Q1 are equivalent to the fixed terminals of a mechanical potentiometer. The H terminal must have a
higher voltage than the low terminal (GND). The position of the wiper (W) terminal is controlled by the value in
the Wiper Resistance (WR) 8-bit register. When the WR register contains all zeroes (zero-scale), the wiper
terminal is closest to its L terminal. As the value of the WR register increases from all zeroes to all ones (full-
scale), the wiper moves from the position closest to the GND terminal to the position closest to the H terminal. At
the same time, the resistance between W and GND increases, whereas the resistance between W and H
decreases.
9.2 Functional Block Diagram
I
ë55
Çt[0401!/.-10-v1
{ꢀ[
WIPER
REGISTER
I2C INTERFACE
í
{5!
Db5 Copyright © 2016, Texas Instruments Incorporated
9.3 Feature Description
The TPL0401x-10-Q1 device is a single-channel, linear taper digital potentiometer with 128 wiper positions.
Default power up state for the TPL0401x-10-Q1 is mid code (0×40). The TPL0401x-10-Q1 has the low terminal
connected to GND internally. The position of the wiper can be adjusted using an I2C interface. The TPL0401x-10-
Q1 is available in a 6-pin SOT package with a specified temperature range of –40°C to +125°C. The part has a
10-kΩ end-to-end resistance and can operate with a supply voltage range of 2.7 V to 5.5 V. This kind of product
is widely used in setting the voltage reference for low power DDR3 memory. The TPL0401x-10-Q1 has the low
terminal internal and connected to GND.
9.4 Device Functional Modes
9.4.1 Voltage Divider Mode
The digital potentiometer generates a voltage divider when all three terminals are used. The voltage divider at
wiper-to-H and wiper-to-GND is proportional to the input voltage at H to L (see Figure 11).
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Device Functional Modes (continued)
H
VHW
VH - VL
W
VWL
L
Figure 11. Equivalent Circuit for Voltage Divider Mode
For example, connecting terminal H to 5 V, the output voltage at terminal W can range from 0 V to 5 V.
Equation 1 is the general equation defining the output voltage at terminal W for any valid input voltage applied to
terminal H and terminal L (GND).
D
VW = VWL = (VH - VL)ì
128
(1)
The voltage difference between terminal H and terminal W can also be calculated in Equation 2.
≈
D
’
≈
’
VHW = (VH - VL)ì 1-
∆
÷
◊
∆
«
÷
◊
128
«
where
•
D is the decimal value of the wiper code
(2)
Table 1 shows the ideal values for DPOT with end-to end resistance of 10 kΩ. The absolute values of resistance
can vary significantly but the Ratio (RWL/RTOT) is extremely accurate.
The linearity values are relative linearity values (that is, linearity after zero-scale and full-scale offset errors are
removed). Consider this when expecting a certain absolute accuracy because some error is introduced when the
device gets close in magnitude to the offset errors.
Note that the MSB is always discarded during a write to the wiper position register. For example, if 0×80 is
written to the wiper position register, a read returns 0×00. Another similar example is if 0×FF is written, then
0×7F is read.
Table 1. Resistance Values Table
STEP
HEX
0×00
0×01
0×02
0×03
0×04
0×05
0×06
0×07
0×08
0×09
0×0A
RWL (KΩ)
0.00
RHW (KΩ)
10.00
9.92
RWL/RTOT
0.0%
0.8%
1.6%
2.3%
3.1%
3.9%
4.7%
5.5%
6.3%
7.0%
7.8%
0
1
0.08
2
0.16
9.84
3
0.23
9.77
4
0.31
9.69
5
0.39
9.61
6
0.47
9.53
7
0.55
9.45
8
0.63
9.38
9
0.70
9.30
10
0.78
9.22
12
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Table 1. Resistance Values Table (continued)
STEP
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
HEX
0×0B
0×0C
0×0D
0×0E
0×0F
0×10
0×11
0×12
0×13
0×14
0×15
0×16
0×17
0×18
0×19
0×1A
0×1B
0×1C
0×1D
0×1E
0×1F
0×20
0×21
0×22
0×23
0×24
0×25
0×26
0×27
0×28
0×29
0×2A
0×2B
0×2C
0×2D
0×2E
0×2F
0×30
0×31
0×32
0×33
0×34
0×35
0×36
0×37
0×38
0×39
RWL (KΩ)
0.86
0.94
1.02
1.09
1.17
1.25
1.33
1.41
1.48
1.56
1.64
1.72
1.80
1.88
1.95
2.03
2.11
2.19
2.27
2.34
2.42
2.50
2.58
2.66
2.73
2.81
2.89
2.97
3.05
3.13
3.20
3.28
3.36
3.44
3.52
3.59
3.67
3.75
3.83
3.91
3.98
4.06
4.14
4.22
4.30
4.38
4.45
RHW (KΩ)
9.14
9.06
8.98
8.91
8.83
8.75
8.67
8.59
8.52
8.44
8.36
8.28
8.20
8.13
8.05
7.97
7.89
7.81
7.73
7.66
7.58
7.50
7.42
7.34
7.27
7.19
7.11
7.03
6.95
6.88
6.80
6.72
6.64
6.56
6.48
6.41
6.33
6.25
6.17
6.09
6.02
5.94
5.86
5.78
5.70
5.63
5.55
RWL/RTOT
8.6%
9.4%
10.2%
10.9%
11.7%
12.5%
13.3%
14.1%
14.8%
15.6%
16.4%
17.2%
18.0%
18.8%
19.5%
20.3%
21.1%
21.9%
22.7%
23.4%
24.2%
25.0%
25.8%
26.6%
27.3%
28.1%
28.9%
29.7%
30.5%
31.3%
32.0%
32.8%
33.6%
34.4%
35.2%
35.9%
36.7%
37.5%
38.3%
39.1%
39.8%
40.6%
41.4%
42.2%
43.0%
43.8%
44.5%
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Table 1. Resistance Values Table (continued)
STEP
HEX
0×3A
0×3B
0×3C
0×3D
0×3E
0×3F
0×40
0×41
0×42
0×43
0×44
0×45
0×46
0×47
0×48
0×49
0×4A
0×4B
0×4C
0×4D
0×4E
0×4F
0×50
0×51
0×52
0×53
0×54
0×55
0×56
0×57
0×58
0×59
0×5A
0×5B
0×5C
0×5D
0×5E
0×5F
0×60
0×61
0×62
0×63
0×64
0×65
0×66
0×67
0×68
RWL (KΩ)
4.53
4.61
4.69
4.77
4.84
4.92
5.00
5.08
5.16
5.23
5.31
5.39
5.47
5.55
5.63
5.70
5.78
5.86
5.94
6.02
6.09
6.17
6.25
6.33
6.41
6.48
6.56
6.64
6.72
6.80
6.88
6.95
7.03
7.11
7.19
7.27
7.34
7.42
7.50
7.58
7.66
7.73
7.81
7.89
7.97
8.05
8.13
RHW (KΩ)
5.47
5.39
5.31
5.23
5.16
5.08
5.00
4.92
4.84
4.77
4.69
4.61
4.53
4.45
4.38
4.30
4.22
4.14
4.06
3.98
3.91
3.83
3.75
3.67
3.59
3.52
3.44
3.36
3.28
3.20
3.13
3.05
2.97
2.89
2.81
2.73
2.66
2.58
2.50
2.42
2.34
2.27
2.19
2.11
2.03
1.95
1.88
RWL/RTOT
45.3%
46.1%
46.9%
47.7%
48.4%
49.2%
50.0%
50.8%
51.6%
52.3%
53.1%
53.9%
54.7%
55.5%
56.3%
57.0%
57.8%
58.6%
59.4%
60.2%
60.9%
61.7%
62.5%
63.3%
64.1%
64.8%
65.6%
66.4%
67.2%
68.0%
68.8%
69.5%
70.3%
71.1%
71.9%
72.7%
73.4%
74.2%
75.0%
75.8%
76.6%
77.3%
78.1%
78.9%
79.7%
80.5%
81.3%
58
59
60
61
62
63
64 (POR Default)
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
14
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Table 1. Resistance Values Table (continued)
STEP
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
HEX
0×69
0×6A
0×6B
0×6C
0×6D
0×6E
0×6F
0×70
0×71
0×72
0×73
0×74
0×75
0×76
0×77
0×78
0×79
0×7A
0×7B
0×7C
0×7D
0×7E
0×7F
RWL (KΩ)
8.20
8.28
8.36
8.44
8.52
8.59
8.67
8.75
8.83
8.91
8.98
9.06
9.14
9.22
9.30
9.38
9.45
9.53
9.61
9.69
9.77
9.84
9.92
RHW (KΩ)
1.80
1.72
1.64
1.56
1.48
1.41
1.33
1.25
1.17
1.09
1.02
0.94
0.86
0.78
0.70
0.63
0.55
0.47
0.39
0.31
0.23
0.16
0.08
RWL/RTOT
82.0%
82.8%
83.6%
84.4%
85.2%
85.9%
86.7%
87.5%
88.3%
89.1%
89.8%
90.6%
91.4%
92.2%
93.0%
93.8%
94.5%
95.3%
96.1%
96.9%
97.7%
98.4%
99.2%
9.5 Programming
9.5.1 I2C General Operation and Overview
9.5.1.1 START and STOP Conditions
I2C communication with this device is initiated by the master sending a START condition and terminated by the
master sending a STOP condition. A high-to-low transition on the SDA line while the SCL is high defines a
START condition. A low-to-high transition on the SDA line while the SCL is high defines a STOP condition. See
Figure 12.
{/[
{5!
5ata Çransfer
{Ç!wÇ
/ondition
{Çhꢀ
/ondition
Figure 12. Definition of START and STOP Conditions
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Programming (continued)
9.5.1.2 Data Validity and Byte Formation
One data bit is transferred during each clock pulse of the SCL. One byte is comprised of eight bits on the SDA
line. See Figure 13. A byte may either be a device address, register address, or data written to or read from a
slave.
Data is transferred Most Significant Bit (MSB) first. Any number of data bytes can be transferred from the master
to slave between the START and STOP conditions. Data on the SDA line must remain stable during the high
phase of the clock period, as changes in the data line when the SCL is high are interpreted as control commands
(START or STOP).
SDA line stable while SCL line is high
SCL
1
0
1
1
1
ACK
0
0
0
SDA
MSB
Bit
Bit
Bit
Bit
Bit
Bit
LSB
ACK
Byte: 1010 1010 ( 0xAAh )
Figure 13. Definition of Byte Formation
9.5.1.3 Acknowledge (ACK) and Not Acknowledge (NACK)
Each byte is followed by one ACK bit from the receiver. The ACK bit allows the receiver to communicate to the
transmitter that the byte was successfully received and another byte may be sent.
The transmitter must release the SDA line before the receiver can send the ACK bit. To send an ACK bit, the
receiver shall pull down the SDA line during the low phase of the ACK/NACK-related clock period (period 9), so
that the SDA line is stable low during the high phase of the ACK/NACK-related clock period. Consider setup and
hold times. Figure 14 shows an example use of ACK.
16
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Programming (continued)
1
2
3
4
5
6
7
8
9
SCL
SDA
LSB
R/W
START
Condition
MSB
A6
A5
A4
A3
A2
A1
A0
ACK
Device Address
Figure 14. Example Use of ACK
When the SDA line remains high during the ACK/NACK-related clock period, this is a NACK signal. There are
several conditions that lead to the generation of a NACK:
•
The receiver is unable to receive or transmit because it is performing some real-time function and is not ready
to start communication with the master.
•
•
•
During the transfer, the receiver gets data or commands that it does not understand.
During the transfer, the receiver cannot receive any more data bytes.
A master-receiver is done reading data and indicates this to the slave through a NACK.
Figure 15 shows an example use of NACK.
1
2
3
4
5
6
7
8
9
SCL
SDA
LSB
D0
MSB
D7
STOP
Condition
D6
D5
D4
D3
D2
D1
NACK
Data Byte N
Figure 15. Example Use of NACK
9.5.1.4 Repeated Start
A repeated START condition may be used in place of a complete STOP condition follow by another START
condition when performing a read function. The advantage of this is that the I2C bus does not become available
after the stop and therefore prevents other devices from grabbing the bus between transfers.
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Programming (continued)
9.5.2 Programing With I2C
9.5.2.1 Write Operation
To write on the I2C bus, the master sends a START condition on the bus with the address of the slave, as well
as the last bit (the R/W bit) set to 0, which signifies a write. After the slave responds with an acknowledge, the
master then sends the register address of the register to which it wishes to write. The slave acknowledges again,
letting the master know that it is ready. After this, the master starts sending the register data to the slave until the
master has sent all the data necessary (which is sometimes only a single byte), and the master terminates the
transmission with a STOP condition. See Figure 16.
ꢄaster controls {ꢀ! line
{lave controls {ꢀ! line
írite to one register in a device
wegister !ddress ꢁ (8 bits)
ꢀata .yte to wegister ꢁ (8 bits)
ꢀevice ({lave) !ddress (7 bits)
{
!6 !5 !4 !3 !2 !1 !0
0
!
.7 .6 .5 .4 .3 .2 .1 .0
!
ꢀ7 ꢀ6 ꢀ5 ꢀ4 ꢀ3 ꢀ2 ꢀ1 ꢀ0
!
ꢂ
{Ç!wÇ
w/í=0 !ꢃY
!ꢃY
!ꢃY {Çhꢂ
Figure 16. Write Operation
9.5.2.2 Read Operation
Reading from a slave is very similar to writing, but requires some additional steps. in order to read from a slave,
the master must first instruct the slave which register it wishes to read from. This is done by the master starting
off the transmission in a similar fashion as the write, by sending the address with the R/W bit equal to 0
(signifying a write), followed by the register address it wishes to read from. When the slave acknowledges this
register address, the master sends a START condition again, followed by the slave address with the R/W bit set
to 1 (Signifying a read). This time, the slave acknowledges the read request, and the master releases the SDA
bus but continues supplying the clock to the slave. During this part of the transaction, the master becomes the
master-receiver, and the slave becomes the slave-transmission.
The master continues to send out the clock pulses, for each byte of data that it wishes to receive. At the end of
every byte of data, the master sends an ACK to the slave, letting the slave know that it is ready for more data.
When the master has received the number of bytes it was expecting (or needs to stop communication), it sends
a NACK, signaling to the slave to halt communications and release the bus. The master follows this up with a
STOP condition. Figure 17 shows the read operation from one register.
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Programming (continued)
wead from one register in a device
wegister !ddress ꢃ (8 bits)
ꢀevice ({lave) !ddress (7 bits)
!6 !5 !4 !3 !2 !1 !0
ꢀata .yte from wegister ꢃ (8 bits)
ꢀevice ({lave) !ddress (7 bits)
!6 !5 !4 !3 !2 !1 !0
{
0
!
.7 .6 .5 .4 .3 .2 .1 .0
!
ꢂ
{
1
!
ꢀ7 ꢀ6 ꢀ5 ꢀ4 ꢀ3 ꢀ2 ꢀ1 ꢀ0 ꢃ!
ꢂ
{Ç!wÇ
w/í=0 !ꢁY
!ꢁY {Çhꢂ {Ç!wÇ
w/í=1 !ꢁY
ꢃ!ꢁY {Çhꢂ
wead from one register in a device (wepeated {tart)
ꢀevice ({lave) !ddress (7 bits)
!6 !5 !4 !3 !2 !1 !0
wegister !ddress ꢃ (8 bits)
ꢀevice ({lave) !ddress (7 bits)
ꢀata .yte from wegister ꢃ (8 bits)
{
0
!
.7 .6 .5 .4 .3 .2 .1 .0
!
{r !6 !5 !4 !3 !2 !1 !0
1
!
ꢀ7 ꢀ6 ꢀ5 ꢀ4 ꢀ3 ꢀ2 ꢀ1 ꢀ0 ꢃ!
ꢂ
{Ç!wÇ
w/í=0
!ꢁY
!ꢁY wepeated {Ç!wÇ
!ꢁY
w/í=1
ꢃ!ꢁY {Çhꢂ
Figure 17. Read Operation from One Register
wead from one register in a device ꢀith single register
ꢁevice ({lave) !ddress (7 bits)
ꢁata .yte from wegister (8 bits)
{
!6 !5 !4 !3 !2 !1 !0
1
!
ꢁ7 ꢁ6 ꢁ5 ꢁ4 ꢁ3 ꢁ2 ꢁ1 ꢁ0 ꢂ!
ꢃ
{Ç!wÇ
wꢅí=1 !/Y
ꢂ!/Y {Çꢄꢃ
Figure 18. Short Read Operation
The TPL0401x-10-Q1 has 1 register, and it is not a requirement that the register address be sent before a read.
A shorter read allows the user to simply send a read request to the device address as shown in Figure 18.
9.6 Register Maps
9.6.1 Slave Address
Table 2 and Table 3 show the TPL0401A-10-Q1 and TPL0401B-10-Q1 bit address repectively.
Table 2. TPL0401A-10-Q1 Bit Address
BIT 7
(MSB)
BIT 6
1
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
0
BIT 0
(LSB)
0
0
1
1
1
R/W
Table 3. TPL0401B-10-Q1 Bit Address
BIT 7
(MSB)
BIT 6
1
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
0
BIT 0
(LSB)
0
1
1
1
1
R/W
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9.6.2 Register Address
Following the successful acknowledgment of the address byte, the bus master sends a command byte as shown
in Figure 19, which is stored in the Control Register in the TPL0401x-10-Q1. The TPL0401x-10-Q1 has only 1
register, but requires the command byte be sent during communication.
B7 B6
B5 B4 B3 B2 B1 B0
Figure 19. Register Address Byte
Table 4 shows the TPL0401x-10-Q1 register address byte.
Table 4. Register Address Byte
REGISTER ADDRESS BITS
REGISTER
ADDRESS
(HEX)
POWER-UP
DEFAULT
REGISTER
PROTOCOL
B7
B6
B5
B4
B3
B2
B1
B0
0100 0000
(0×40)
0
0
0
0
0
0
0
0
0×00
Wiper Position
Read/Write byte
See Table 1 for more information on the wiper position register values. Note that the MSB is always discarded
during a write to the wiper position register. For example, if 0×80 is written to the wiper position register, a read
returns 0×00. Another similar example is if 0×FF is written, then 0×7F is read.
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10 Application and Implementation
10.1 Application Information
There are many applications in which voltage division is needed through the use of a digital potentiometer such
as the TPL0401x-10-Q1; this is one example of the many. In conjunction with many amplifiers, the TPL0401x-10-
Q1 can effectively be used in voltage divider mode to create a buffer to adjust the reference voltage for DDR3
DIMM1 Memory.
10.2 Typical Application
1.ꢀ ë
+
1 kΩ
55w3 5Laa1
VREF
-
1 kΩ
5thÇ
ht-!at
Çt[0401!/ꢁ-10-v1
Copyright © 2016, Texas Instruments Incorporated
Figure 20. DDR3 Voltage Reference Adjustment
10.2.1 Design Requirements
Table 5 lists the design parameters for this example.
Table 5. Design Parameters
PARAMETER
Input voltage
VREF
EXAMPLE VALUE
1.5 V
0 V to 0.75 V
10.2.2 Detailed Design Procedure
The TPL0401x-10-Q1 can be used in voltage divider mode with a unity-gain op amp buffer to provide a clean
voltage reference for DDR3 DIMM1 Memory. The analog output voltage, VREF1 is determined by the wiper setting
programmed through the I2C bus.
The op amp is required to buffer the high-impedance output of the TPL0401x-10-Q1 or else loading placed on
the output of the voltage divider affects the output voltage.
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10.2.3 Application Curve
The voltage, 1.5 V, applied to terminal H of TPL0401x-10-Q1 determines the voltage that is buffered by the unity-
gain op amp and divided as the DDR3 DIMM1 voltage reference. By using the TPL0401x-10-Q1, and dividing the
1.5 V, a maximum of 0.75 V is applied to the buffer and passed to the voltage divider. The output voltage then
ranges from 0 V to 0.75 V.
0.8
0.6
0.4
0.2
0
0
8
16
24
32
40
48
56
64
72
80
88
96
104
112
120
128
TPL0401A/B Code (Digital Input)
D001
Figure 21. TPL0401-10-Q1 Digital Input vs Reference Voltage for DDR3 DIMM Memory
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11 Power Supply Recommendations
11.1 Power Sequence
Protection diodes limit the voltage compliance at SDA, SCL, terminal H, and terminal W, making it important to
power up VDD first before applying any voltage to SDA, SCL, terminal H, and terminal W. The diodes are forward-
biasing, meaning VDD can be powered unintentionally if VDD is not powered first. The ideal power-up sequence is
VDD, digital inputs, and VW and VH. The order of powering digital inputs, VH and VW does not matter as long as
they are powered after VDD
.
11.2 Power-On Reset Requirements
In the event of a glitch or data corruption, the TPL0401-10-Q1 can be reset to its default conditions by using the
power-on reset feature. Power-on reset requires that the device go through a power cycle to be completely reset.
This reset also happens when the device is powered on for the first time in an application.
V
DD
Ramp-Up
Ramp-Down
Re-Ramp-Up
t
TRR_GND
Time
Time to Re-Ramp
t
t
t
RT
FT
RT
Figure 22. VDD is Lowered to 0 V and then Ramped Up to VDD
Table 6 specifies the performance of the power-on reset feature for TCA6408A for both types of power-on reset.
Table 6. Recommended Supply Sequencing and Ramp Rates at TA = 25°C(1)
PARAMETER
MIN
0.0001
0.0001
1
MAX UNIT
tFT
Fall rate
See Figure 22
See Figure 22
See Figure 22
1000
1000
ms
ms
μs
tRT
Rise rate
tRR_GND
Time to re-ramp (when VDD drops to GND)
(1) Not tested. Specified by design.
11.3 I2C Communication After Power Up
In order to ensure a complete device reset after a power up condition, the user must wait 120 µs after power up
before initiating communication with the TPL0401x-10-Q1. See Figure 23 for an example waveform.
VDD
VDD MIN
120 µsx
SDA
START
ADDR
Figure 23. Recommended Start Up Sequence
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11.4 Wiper Position While Unpowered and After Power Up
When DPOT is powered off, the impedance of the device is undefined and not known.
Upon power-up, the device returns to 0×40h code because this device does not contain non-volatile memory.
24
Copyright © 2016, Texas Instruments Incorporated
TPL0401A-10-Q1
TPL0401B-10-Q1
www.ti.com.cn
ZHCSFW3 –NOVEMBER 2016
12 Layout
12.1 Layout Guidelines
To ensure reliability of the device, follow common printed-circuit board (PCB) layout guidelines:
•
•
•
•
•
Leads to the input must be as direct as possible with a minimum conductor length.
The ground path must have low resistance and low inductance.
Use short trace-lengths to avoid excessive loading.
It is common to have a dedicated ground plane on an inner layer of the board.
Terminals that are connected to ground must have a low-impedance path to the ground plane in the form of
wide polygon pours and multiple vias.
•
•
Use bypass capacitors on power supplies and placed them as close as possible to the VDD pin.
Apply low equivalent series resistance (0.1-μF to 10-μF tantalum or electrolytic capacitors) at the supplies to
minimize transient disturbances and to filter low-frequency ripple.
•
To reduce the total I2C bus capacitance added by PCB parasitics, data lines (SCL and SDA) must be as short
as possible and the widths of the traces must also be minimized (for example, 5 to 10 mils depending on
copper weight).
12.2 Layout Example
ëia to ë55 ꢀower ꢀlane
ëia to Db5 ꢀlane
ë55
Db5
I
í
TPL0401A/B-10-Q1
{5!
{/[
Figure 24. Layout Recommendation
版权 © 2016, Texas Instruments Incorporated
25
TPL0401A-10-Q1
TPL0401B-10-Q1
ZHCSFW3 –NOVEMBER 2016
www.ti.com.cn
13 器件和文档支持
13.1 文档支持
13.1.1 相关文档ꢀ
相关文档如下：
•
•
•
《I2C 总线上拉电阻计算》
《理解 I2C 总线》
《TPL0401 评估模块用户指南》
13.2 相关链接
下面的表格列出了快速访问链接。范围包括技术文档、支持和社区资源、工具和软件，以及样片或购买的快速访
问。
表 7. 相关链接
器件
产品文件夹
请单击此处
请单击此处
样片与购买
请单击此处
请单击此处
技术文档
请单击此处
请单击此处
工具与软件
请单击此处
请单击此处
支持与社区
请单击此处
请单击此处
TPL0401A-Q1
TPL0401B-Q1
13.3 接收文档更新通知
如需接收文档更新通知，请访问 ti.com 上的器件产品文件夹。点击右上角的提醒我 (Alert me) 注册后，即可每周定
期收到已更改的产品信息。有关更改的详细信息，请查阅已修订文档中包含的修订历史记录。
13.4 社区资源
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
13.5 商标
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
13.6 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
13.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
26
版权 © 2016, Texas Instruments Incorporated
TPL0401A-10-Q1
TPL0401B-10-Q1
www.ti.com.cn
ZHCSFW3 –NOVEMBER 2016
14 机械、封装和可订购信息
以下页中包括机械、封装和可订购信息。这些信息是针对指定器件可提供的最新数据。这些数据会在无通知且不对
本文档进行修订的情况下发生改变。欲获得该数据表的浏览器版本，请查阅左侧的导航栏。
版权 © 2016, Texas Instruments Incorporated
27
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPL0401A-10QDCKRQ1
TPL0401B-10QDCKRQ1
ACTIVE
ACTIVE
SC70
SC70
DCK
DCK
6
6
3000 RoHS & Green
3000 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 125
-40 to 125
15N
15O
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Addendum-Page 2
重要声明和免责声明
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