TPL7407LA-Q1 [TI]
30V、7 通道汽车类 NMOS 阵列低侧驱动器;
| 型号： | TPL7407LA-Q1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 30V、7 通道汽车类 NMOS 阵列低侧驱动器 驱动 驱动器 |
| 文件： | 总22页 (文件大小：838K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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TPL7407LA-Q1
ZHCSIA6 –MAY 2018
TPL7407LA-Q1 30V 7 通道低侧驱动器
1 特性
2 应用
1
•
•
符合汽车类应用的 标准
具有符合 AEC-Q100 标准的下列结果：
•
电感负载
–
–
–
继电器
–
器件温度 1 级：-40℃ 至 +125℃ 的环境运行温
度范围
单极步进电机和刷式直流电机
电磁阀
–
–
器件 HBM ESD 分类等级 2
•
•
•
LED
器件 CDM ESD 分类等级 C4B
逻辑电平位移
栅极和 IGBT 驱动
•
•
600mA 额定漏极电流（每通道）
7 通道达林顿晶体管阵列 CMOS 引脚对引脚改善
（例如：ULN2003A）
3 说明
•
能效（极低 VOL
电流为 100mA 时，VOL 低于达林顿晶体管阵列
的四分之一
）
TPL7407LA-Q1 是一款高压、高电流 NMOS 晶体管阵
列。这个器件包含 7 个具有高压输出的 NMOS 晶体
管，这些晶体管具有针对开关电感负载的共阴极钳位二
极管。单个 NMOS 通道的最大漏极电流额定值为
600mA。器件添加了新的调节和驱动电路，可在全部
GPIO 范围（1.8V 至 5V）提供最大驱动能力。这些晶
体管还可以通过采用并联方式来提供更高的电流。
–
•
•
•
•
•
•
•
输出泄露极低，每通道小于 10nA
高压输出 30V
与 1.8V 和 5V 微控制器和逻辑接口兼容
用于提供电感反冲保护的内部自振荡二极管
可借助输入下拉电阻器实现三态输入驱动器
用来消除嘈杂环境中的杂散运行的输入 RC 缓冲器
ESD 保护性能超出 JESD 22 标准
相比双极达林顿晶体管实施，TPL7407LA-Q1 的主要
优势在于其具有更高的能效和更低的泄漏。依赖于较低
的 VOL，功率耗散比传统继电器驱动器减少一半，每通
道的电流低于 250mA。
–
2kV HBM，500V CDM
器件信息(1)
器件号
封装（引脚）
TSSOP (16)
封装尺寸（标称值）
TPL7407LA-Q1
5.00mm × 4.40mm
(1) 如需了解所有可用封装，请参阅产品说明书末尾的可订购产品
附录。
简化应用原理图
VSUP
M
TPL7407LA-Q1
IN1
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
COM
1.8 V Logic
IN2
IN3
IN4
IN5
IN6
IN7
GND
24 V
1.8 V Logic
CCOM
1
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。 有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确
性和有效性。 在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLRS074
TPL7407LA-Q1
ZHCSIA6 –MAY 2018
www.ti.com.cn
目录
7.4 Device Functional Modes.......................................... 7
Application and Implementation .......................... 9
8.1 Application Information.............................................. 9
8.2 Typical Application .................................................. 11
Power Supply Recommendations...................... 14
1
2
3
4
5
6
特性.......................................................................... 1
8
9
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ..................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 4
6.5 Electrical Characteristics........................................... 5
6.6 Switching Characteristics.......................................... 5
6.7 Typical Characteristics.............................................. 6
Detailed Description .............................................. 7
7.1 Overview ................................................................... 7
7.2 Functional Block Diagram ......................................... 7
7.3 Feature Description................................................... 7
10 Layout................................................................... 14
10.1 Layout Guidelines ................................................. 14
10.2 Layout Example .................................................... 14
10.3 Thermal Considerations........................................ 14
11 器件和文档支持 ..................................................... 16
11.1 接收文档更新通知 ................................................. 16
11.2 社区资源................................................................ 16
11.3 商标....................................................................... 16
11.4 静电放电警告......................................................... 16
11.5 术语表 ................................................................... 16
12 机械、封装和可订购信息....................................... 16
7
4 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
日期
修订版本
说明
2018 年 5 月
*
最初发布版本。
2
Copyright © 2018, Texas Instruments Incorporated
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5 Pin Configuration and Functions
PW Package
16-Pin TSSOP
Top View
EMF
1
2
3
4
5
6
7
8
OUT1
16
IN1
IN2
Clamp
EMF
15 OUT2
Clamp
EMF
IN3
14
13
12
OUT3
OUT4
Clamp
EMF
IN4
Clamp
EMF
OUT5
IN5
Clamp
EMF
IN6
11
10
OUT6
OUT7
Clamp
EMF
IN7
Clamp
9
GND
LDO
COM
Pin Functions
PIN
I/O
DESCRIPTION
NAME
COM
GND
NO.
Supply pin that must be tied to 6.5 V or higher for proper operation (see
the Power Supply Recommendations section for more information)
9
—
—
8
1
Ground pin
2
3
GPIO inputs that drives the outputs "low" (or sink current) when driven
"high"
IN(X)
4
I
5
6
7
10
11
12
13
14
15
16
OUT(X)
O
Driver output that sinks currents after input is driven "high"
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6 Specifications
6.1 Absolute Maximum Ratings
at 25°C free-air temperature (unless otherwise noted)
(1)
MIN
–0.3
–0.3
–0.3
–0.3
MAX
32
UNIT
V
VOUT
VOK
VCOM
VIN
Pins OUT1-OUT7 to GND voltage
Output clamp diode reverse voltage(2)
COM pin voltage(2)
32
V
32
V
(2)
Pins IN1-IN7 to GND voltage
30
V
IDS
Continuous drain current per channel(3) (4)
600
500
–2
mA
mA
A
IOK
Output clamp current
IGND
TJ
Total continuous GND-pin current
Operating virtual junction temperature
Storage temperature
–40
–65
150
150
°C
°C
Tstg
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to the GND/substrate pin, unless otherwise noted.
(3) Maximum power dissipation is a function of TJ(max), θJA, and TA. The maximum allowable power dissipation at any allowable ambient
temperature is PD = (TJ(max) – TA)/θJA. Operating at the absolute maximum TJ of 150°C can affect reliability.
(4) The package thermal impedance is calculated in accordance with JESD 51-7.
6.2 ESD Ratings
VALUE
±2000
±500
UNIT
Human-body model (HBM), per AEC Q100-002(1)
V(ESD)
Electrostatic discharge
All pins
Corner pins (1, 8, 9, 16)
V
Charged-device model (CDM), per AEC
Q100-011
±750
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
Over operating temperature range
MIN
0
MAX
UNIT
V
VOUT
VCOM
VIL
OUT1 – OUT7 pin voltage for recommended operation
COM pin voltage range for full output drive
IN1- IN7 input low voltage ("Off" high impedance output)
IN1- IN7 input high voltage ("Full Drive" low impedance output)
Operating free-air temperature
30
30
6.5
V
0.9
V
VIH
1.5
–40
0
V
TA
125
500
°C
mA
IDS
Continuous drain current
6.4 Thermal Information
TPL7407LA-Q1
THERMAL METRIC(1)
TSSOP (PW)
UNIT
16 PINS
113.1
46.5
58.6
7
θJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
θJCtop
θJB
Junction-to-board thermal resistance
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
ψJB
58
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
4
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6.5 Electrical Characteristics
TJ= –40°C to +125°C; Typical Values at TA= 25°C
(1)
PARAMETER
TEST CONDITIONS
MIN
TYP
210
430
MAX
450
900
0.9
UNIT
V
IN ≥ 1.5 V
ID = 100 mA
ID = 200 mA
OUT1- OUT7 low-level output
voltage
VOL (VDS
)
mV
VIL
IN1- IN7 low-level input voltage
IN1- IN7 high-level input voltage
ID = 5 µA
V
V
VIH
ID = 100 mA
1.5
IOUT(OFF)
OUT1- OUT7 OFF-state leakage
current
VOUT = 30 V, VIN ≤ 0.9 V
10
17
500
nA
(IDS_OFF
)
VF
Clamp forward voltage
IF = 200 mA
1.4
500
10
V
IIN(off)
IIN(ON)
ICOM
IN1- IN7 Off-state input current
IN1- IN7 ON state input current
VINX = 0 V
VOUT = 30 V
nA
μA
VINX = 1.5 V – 5 V
VCOM = 6.5 V – 30 V
Static current flowing through
COM pin
30
μA
(1) During production testing, device is tested under short duration, therefore TA = TJ.
6.6 Switching Characteristics
Typical Values at TA= 25°C
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
V
48 Ω
INX ≥ 1.65 V, Vpull-up = 30 V, Rpull-up =
tPLH
Propagation delay time, low- to high-level output
350
ns
V
48 Ω
INX ≥ 1.65 V, Vpull-up = 30 V, Rpull-up =
tPHL
Ci
Propagation delay time, high- to low-level output
Input capacitance
350
5
ns
VI = 0,
f = 100 kHz
pF
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6.7 Typical Characteristics
2.4
500
450
400
350
300
250
200
150
100
50
-40°C
25°C
125°C
2
1.6
1.2
0.8
0.4
0
0
0
100
200
300
400
500
0
0.2
0.4
0.6
VF (V)
0.8
1
1.2
1.4
Output Drain Current IDS (mA)
D001
D002
图 1. VOL (VDS
)
图 2. Flyback Diode Forward Voltage at 25°C
0.55
0.5
0.55
N = 1
N = 1
0.5
0.45
0.4
N = 2
N = 3
N = 4
N = 5
N = 6
N = 7
N = 2
N = 3
N = 4
N = 5
N = 6
N = 7
0.45
0.4
0.35
0.3
0.35
0.3
0.25
0.2
0.25
0.2
0.15
0.1
0.15
0.1
0.05
0
0.05
0
0
20%
40%
60%
80%
100%
0
20%
40%
60%
80%
100%
Duty Cycle
Duty Cycle
D007
D008
图 3. Maximum Collector Current vs Duty Cycle at 25°C
图 4. Maximum Collector Current vs Duty Cycle at 70°C
6
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7 Detailed Description
7.1 Overview
The TPL740LA-Q1 integrates seven low side NMOS transistors that are capable of sinking up to 600 mA and
wide GPIO range capability.
The TPL7407LA-Q1 comprises seven high voltage, high current NMOS transistors tied to a common ground
driven by internal level shifting and gate drive circuitry. The TPL7407LA-Q1 offers solutions to many interface
needs, including solenoids, relays, lamps, small motors, and LEDs. Applications requiring sink currents beyond
the capability of a single output may be accommodated by paralleling the outputs.
The TPL7407LA-Q1 also enables pin to pin replacement with legacy 7 channel darlington pair implementations.
This device can operate over a wide temperature range (–40°C to +125°C).
7.2 Functional Block Diagram
COM
Regulation
Circuitry
OUT(1-7)
50 k
IN(1-7)
DRIVER
OVP
1M
7.3 Feature Description
Each channel of the TPL7407LA-Q1 consists of high power low side NMOS transistors driven by level shifting
and gate driving circuitry. The gate drivers allow for high output current drive with a very low input voltage,
meaning full operation with low GPIO voltages.
In order to enable floating inputs a 1-MΩ pull-down resistor exists on each channel. Another 50-kΩ resistor exists
between the input and gate driving circuitry. This exists to limit the input current whenever there is an over
voltage and the internal Zener clamps. It also interacts with the inherent capacitance of the gate driving circuitry
to behave as an RC snubber to help prevent spurious switching in noisy environment.
In order to power the gate driving circuitry an LDO exists. See the Power Supply Recommendations section for
further detail on this circuitry.
The diodes connected between the output and COM pin is used to suppress kick-back voltage from an inductive
load that is excited when the NMOS drivers are turned off (stop sinking) and the stored energy in the coils
causes a reverse current to flow into the coil supply.
7.4 Device Functional Modes
7.4.1 Inductive Load Drive
When the COM pin is tied to the coil supply voltage, the TPL7407LA-Q1 is able to drive inductive loads and
suppress the kick-back voltage via the internal free wheeling diodes.
7.4.2 Resistive Load Drive
When driving a resistive load, a pull-up resistor is needed in order for the TPL7407LA-Q1 to sink current and for
there to be a logic high level. The COM pin must be supplied ≥ 6.5 V for full functionality.
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Device Functional Modes (接下页)
7.4.3 ON State Input Current
The current into the INx pins is defined in the electrical characteristics table for input voltages from 1.5 V to 5 V.
At higher voltages, this leakage increases, and the input current can be estimated using the approximate clamp
voltage for the OVP diode, 6.4 V. 公式 1 shows how to approximate input current for input voltages greater than
6.4 V:
IIN(ON) = VIN / 1 MΩ + (VIN - 6.4 V) / 50 kΩ
where
•
•
•
•
VIN is the input voltage
1 MΩ is the input pull-down resistance
50 kΩ is the input series resistance
6.8 V is the approximate clamp voltage for the OVP diode
(1)
8
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8 Application and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TPL7407LA-Q1 is typically used to drive a high voltage and/or current peripheral from an MCU or logic
device that cannot tolerate these conditions. The following design is a common application of the TPL7407LA-
Q1, driving inductive loads. This includes motors, solenoids and relays. Each load type can be modeled by
what's seen in 图 7.
8.1.1 Unipolar Stepper Motor Driver
Motor
VSUP
Motor Control Pulses
(1.8 V to 5 V)
TPL7407LA-Q1
IN1
IN2
IN3
IN4
IN5
IN6
IN7
GND
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
COM
Phase_A
Phase_C
Phase_B
Phase_D
Optional
CCOM
图 5. Stepper Motor Driver Schematic
图 5 shows an implementation of the TPL7407LA-Q1 for driving a uniploar stepper motor. The unconnected input
channels can be used for other functions. When an input pin is left open the internal 1-MΩ pull down resistor
pulls the respective input pin to GND potential. For higher noise immunity use an external short across an
unconnected input and GND pins. The COM pin must be tied to the supply of whichever inductive load is being
driven for the driver to be protected by the free-wheeling diode.
For more information on this application, see the Stepper Motor Driving With Peripheral Drivers (Driver ICs)
application report.
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Application Information (接下页)
8.1.2 Multi-Purpose Sink Driver
VSUP
M
TPL7407LA-Q1
IN1
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
COM
1.8 V Logic
IN2
IN3
IN4
IN5
IN6
IN7
GND
24 V
1.8 V Logic
CCOM
图 6. Multi-Purpose Sink Driver Schematic
When configured as per 图 6, the TPL7407LA-Q1 may be used as a multi-purpose driver. The output channels
may be tied together to sink more current. The TPL7407LA-Q1 can easily drive motors, relays and LEDs with
little power dissipation. COM must be tied to highest load voltage, which may or may not be same as inductive
load supply.
10
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8.2 Typical Application
A common application for the TPL7407LA-Q1 is driving inductive loads such as relays, solenoids, and unipolar
stepper motors.
12 V
TPL7407LA-Q1
IN1
IN2
IN3
IN4
IN5
IN6
IN7
GND
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
COM
1.8 V Logic
Simultaneous operation
is limited or enabled by
relay resistance, coil
voltage and temperature
12 V
1.8 V Logic
CCOM
图 7. Inductive Load Driver Schematic
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Typical Application (接下页)
8.2.1 Design Requirements
For this design example, use the parameters listed in 表 1 as the input parameters.
表 1. Design Parameters
DESIGN PARAMETER
GPIO Voltage
EXAMPLE VALUE
1.8 V, 3.3 V or 5 V
Coil supply voltage
Number of channels
6.5 V to 30 V
7
Output current (RCOIL
)
20 mA to 300 mA per channel
CCOM
0.1 µF
100%
Duty cycle
8.2.2 Detailed Design Procedure
When using the TPL7407LA-Q1 in a coil driving application, determine the following:
•
•
•
•
Input Voltage Range
Temperature Range
Output & Drive Current
Power Dissipation
8.2.2.1 TTL and other Logic Inputs
The TPL7407LA-Q1 input interface is specified for standard 1.8 V through 5 V CMOS logic interface and can
tolerate up to 30 V. At any input voltage the output drivers is going to be driven at its maximum when VCOM is
greater than or equal to 6.5 V.
8.2.2.2 Input RC Snubber
The TPL7407LA-Q1 features an input RC snubber that helps prevent spurious switching in noisy environments.
Connect an external 1 kΩ to 5 kΩ resistor in series with the input to further enhance the TPL7407LA-Q1’s noise
tolerance.
8.2.2.3 High-Impedance Input Drivers
The TPL7407LA-Q1 features a 1-MΩ input pull-down resistor. The presence of this resistor allows the input
drivers to be tri-stated. When a high-impedance driver is connected to a channel input the TPL7407LA-Q1
detects the channel input as a low level input and remains in the OFF position. The input RC snubber helps
improve noise tolerance when input drivers are in the high-impedance state.
8.2.2.4 Drive Current
The coil current is determined by the coil voltage (VSUP), coil resistance & output low voltage (VOL) as shown in
公式 2.
ICOIL= (VSUP - VOL)/RCOIL
(2)
8.2.2.5 Output Low Voltage
The output low voltage (VOL) is drain to source (VDS) voltage of the output NMOS transistors when the input is
driven high and it is sinking current and can be determined by the Electrical Characteristics section or 图 1.
12
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8.2.3 Application Curve
图 8 was generated with TPL7407LA-Q1 driving an OMRON G5NB relay -- Vin = 5 V; Vsup = 12 V & RCOIL = 2.8
kΩ
图 8. Output Response With De-Activation of Coil (Turnoff)
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9 Power Supply Recommendations
The COM pin is the power supply pin of this device to power the gate drive circuitry. While a bypass capacitor on
this pin is recommended for sensitive power supplies, it is not required for proper operation of the device. The
COM pin supply ensures full drive potential with any GPIO above 1.5 V. The gate drive circuitry is based on low
voltage CMOS transistors that can only handle a max gate voltage of 7 V. An integrated LDO reduces the COM
voltage of 6.5 V to 30 V to a regulated voltage of 5.3 V. Though 6.5 V minimum is recommended for VCOM, the
part still functions with a reduced COM voltage that has a reduced gate drive voltage and a resulting higher
Rdson.
10 Layout
10.1 Layout Guidelines
Thin traces can be used on the input due to the low current logic that is typically used to drive the TPL7407LA-
Q1. Care must be taken to separate the input channels as much as possible, as to eliminate cross-talk. Thick
traces are recommended for the output, in order to drive whatever high currents that may be needed. Wire
thickness can be determined by the trace material's current density and desired drive current.
Since all of the channels currents return to a common ground, it is best to size that trace width to be very wide.
Some applications require up to 2 A.
Since the COM pin only draws up to 30 µA, thick traces are not necessary.
10.2 Layout Example
TPL7407LA-Q1
IN1
IN2
IN3
IN4
IN5
IN6
IN7
GND
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
COM
GND
Only needed
for fluctuating
supplies
CCOM
GND
图 9. Package Layout
10.3 Thermal Considerations
The number of coils driven is dependent on the coil current and on-chip power dissipation. The number of coils
driven can be determined by 图 3 or 图 4.
14
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Thermal Considerations (接下页)
For a more accurate determination of number of coils possible, use 公式 3 to calculate TPL7407LA-Q1 on-chip
power dissipation PD:
N
V
´ILi
P = å
D
OLi
i=1
where
•
•
N is the number of channels active together
VOLi is the OUTi pin voltage for the load current ILi. This is the same as VCE(SAT)
(3)
In order to guarantee reliability of TPL7407LA-Q1 and the system, the on-chip power dissipation must be lower
than or equal to the maximum allowable power dissipation (PD(MAX)) dictated by below equation 公式 4.
T
- TA
(
)
J MAX
(
)
PD(MAX
=
)
qJA
where
•
•
•
TJ(MAX) is the target maximum junction temperature
TA is the operating ambient temperature
θJA is the package junction to ambient thermal resistance
(4)
It is recommended to limit rhe TPL7407LA-Q1 IC’s die junction temperature to less than 125°C. The IC junction
temperature is directly proportional to the on-chip power dissipation.
10.3.1 Improving Package Thermal Performance
θJA value depends on the PC board layout. An external heat sink and/or a cooling mechanism, like a cold air fan,
can help reduce θJA and thus improve device thermal capabilities. Refer to TI’s design support web page at
www.ti.com/thermal for a general guidance on improving device thermal performance.
版权 © 2018, Texas Instruments Incorporated
15
TPL7407LA-Q1
ZHCSIA6 –MAY 2018
www.ti.com.cn
11 器件和文档支持
11.1 接收文档更新通知
要接收文档更新通知，请导航至 TI.com.cn 上的器件产品文件夹。单击右上角的通知我 进行注册，即可每周接收产
品信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
11.2 社区资源
下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，
并且不一定反映 TI 的观点；请参阅 TI 的 《使用条款》。
TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在
e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。
设计支持
TI 参考设计支持 可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。
11.3 商标
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.4 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
11.5 术语表
SLYZ022 — TI 术语表。
这份术语表列出并解释术语、缩写和定义。
12 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且
不会对此文档进行修订。如需获取此产品说明书的浏览器版本，请查看左侧的导航栏。
16
版权 © 2018, Texas Instruments Incorporated
重要声明和免责声明
TI 均以“原样”提供技术性及可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资
源，不保证其中不含任何瑕疵，且不做任何明示或暗示的担保，包括但不限于对适销性、适合某特定用途或不侵犯任何第三方知识产权的暗示
担保。
所述资源可供专业开发人员应用TI 产品进行设计使用。您将对以下行为独自承担全部责任：(1) 针对您的应用选择合适的TI 产品；(2) 设计、
验证并测试您的应用；(3) 确保您的应用满足相应标准以及任何其他安全、安保或其他要求。所述资源如有变更，恕不另行通知。TI 对您使用
所述资源的授权仅限于开发资源所涉及TI 产品的相关应用。除此之外不得复制或展示所述资源，也不提供其它TI或任何第三方的知识产权授权
许可。如因使用所述资源而产生任何索赔、赔偿、成本、损失及债务等，TI对此概不负责，并且您须赔偿由此对TI 及其代表造成的损害。
TI 所提供产品均受TI 的销售条款 (http://www.ti.com.cn/zh-cn/legal/termsofsale.html) 以及ti.com.cn上或随附TI产品提供的其他可适用条款的约
束。TI提供所述资源并不扩展或以其他方式更改TI 针对TI 产品所发布的可适用的担保范围或担保免责声明。IMPORTANT NOTICE
邮寄地址：上海市浦东新区世纪大道 1568 号中建大厦 32 楼，邮政编码：200122
Copyright © 2018 德州仪器半导体技术（上海）有限公司
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPL7407LAQPWRQ1
ACTIVE
TSSOP
PW
16
2000 RoHS & Green
NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
TPL747LAQ
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OUTLINE
PW0016A
TSSOP - 1.2 mm max height
S
C
A
L
E
2
.
5
0
0
SMALL OUTLINE PACKAGE
SEATING
PLANE
C
6.6
6.2
TYP
A
0.1 C
PIN 1 INDEX AREA
14X 0.65
16
1
2X
5.1
4.9
4.55
NOTE 3
8
9
0.30
16X
4.5
4.3
NOTE 4
1.2 MAX
0.19
B
0.1
C A B
(0.15) TYP
SEE DETAIL A
0.25
GAGE PLANE
0.15
0.05
0.75
0.50
A
20
0 -8
DETAIL A
TYPICAL
4220204/A 02/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153.
www.ti.com
EXAMPLE BOARD LAYOUT
PW0016A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
SYMM
16X (1.5)
(R0.05) TYP
16
1
16X (0.45)
SYMM
14X (0.65)
8
9
(5.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL
EXPOSED METAL
EXPOSED METAL
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
NON-SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
15.000
(PREFERRED)
SOLDER MASK DETAILS
4220204/A 02/2017
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
PW0016A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
16X (1.5)
SYMM
(R0.05) TYP
16
1
16X (0.45)
SYMM
14X (0.65)
8
9
(5.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 10X
4220204/A 02/2017
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
重要声明和免责声明
TI 均以“原样”提供技术性及可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资
源，不保证其中不含任何瑕疵，且不做任何明示或暗示的担保，包括但不限于对适销性、适合某特定用途或不侵犯任何第三方知识产权的暗示
担保。
所述资源可供专业开发人员应用TI 产品进行设计使用。您将对以下行为独自承担全部责任：(1) 针对您的应用选择合适的TI 产品；(2) 设计、
验证并测试您的应用；(3) 确保您的应用满足相应标准以及任何其他安全、安保或其他要求。所述资源如有变更，恕不另行通知。TI 对您使用
所述资源的授权仅限于开发资源所涉及TI 产品的相关应用。除此之外不得复制或展示所述资源，也不提供其它TI或任何第三方的知识产权授权
许可。如因使用所述资源而产生任何索赔、赔偿、成本、损失及债务等，TI对此概不负责，并且您须赔偿由此对TI 及其代表造成的损害。
TI 所提供产品均受TI 的销售条款 (http://www.ti.com.cn/zh-cn/legal/termsofsale.html) 以及ti.com.cn上或随附TI产品提供的其他可适用条款的约
束。TI提供所述资源并不扩展或以其他方式更改TI 针对TI 产品所发布的可适用的担保范围或担保免责声明。IMPORTANT NOTICE
邮寄地址：上海市浦东新区世纪大道 1568 号中建大厦 32 楼，邮政编码：200122
Copyright © 2020 德州仪器半导体技术（上海）有限公司
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