TPS12110AQDGXRQ1 [TI]
具有保护和诊断功能的汽车用 3.5V 至 40V 高侧驱动器 | DGX | 19 | -40 to 125;
| 型号： | TPS12110AQDGXRQ1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有保护和诊断功能的汽车用 3.5V 至 40V 高侧驱动器 | DGX | 19 | -40 to 125 驱动 驱动器 |
| 文件： | 总42页 (文件大小：3532K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPS1211-Q1
ZHCSPB6A –JULY 2022 –REVISED SEPTEMBER 2022
TPS1211-Q1 具有保护和诊断功能的45V 汽车智能高侧驱动器
1 特性
3 说明
• 具有符合AEC-Q100 标准的下列特性
TPS1211-Q1 系列是一款具有保护和诊断功能的 45V
智能高侧驱动器。该器件具有3.5V 至40V 的宽工作电
压范围，适用于12V 系统设计。
– 器件温度等级1：
–40°C 至+125°C 环境工作温度范围
– 器件HBM ESD 分类等级2
– 器件CDM ESD 分类等级C4B
• 功能安全型
它具有强大的4A 灌电流(PD) 和拉电流(PU) 栅极驱动
器，可在大电流系统设计中使用并联 FET 进行电源开
关。将INP 用作栅极驱动器控制输入。
– 有助于进行功能安全系统设计的文档
• 3.5V 至40V 输入范围（绝对最大值45V）
• 具有100µA 容量的集成12V 电荷泵
• 1.7µA 低关断电流（EN/UVLO = 低电平）
• 强大的上拉和下拉栅极驱动器：4A
• 驱动外部背对背N 沟道MOSFET
• 具有集成预充电开关驱动器(TPS12111-Q1) 以驱动
容性负载的型号
• 具有可调节响应时间(TMR) 和故障标志输出
(FLT_I) 的两级可调过流保护（IWRN、ISCP）
• 快速短路保护：1.2µs (TPS12111-Q1)、5µs
(TPS12110-Q1)
该器件具有精确的电流检测（在 30mV 下为 ±2%）输
出 (IMON) 支持系统，可用于能源管理。该器件集成了
具有 FLT_I 输出的两级过流保护，具有完全可调的阈
值和响应时间。可以配置自动重试和锁存故障行为。该
器件具有远程过热保护，具有FLT_T 输出。
TPS12111-Q1 将预充电驱动器 (G) 与控制输入
(INP_G) 集成，此功能支持必须驱动大容性负载的设
计。在关断模式下 (EN/UVLO < 0.3V)，控制器的 IQ
为1.7µA。
TPS1211-Q1 可采用19 引脚VSSOP 封装。
• 精确的模拟电流监测输出(IMON) –在30mV 下为
±2% (Vsense)
• 可调节欠压锁定(UVLO) 和过压保护(OV)
• 具有故障标志输出(FLT_T) 的远程过热检测
(DIODE)
封装信息
封装(1)
封装尺寸（标称值）
器件型号
TPS12110-Q1、
TPS12111-Q1
DGX（VSSOP、
19）
5.10mm × 3.00mm
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
• 与TPS4811-Q1 引脚对引脚兼容
2 应用
• 配电盒
• 车身控制模块
• 直流/直流转换器
Q2
R
Q2
Q1
Q3
Q1
RSNS
VBATT
(12 V)
VOUT
RSET
RISCP
RSNS
VOUT
CBLK
VBATT
(12 V)
CBST
VS ISCP CS+ CS-
EN/UVLO
PU PD DIODE
SRC
BST
RSET
RISCP
VS ISCP
R1
R2
VCC
R4
CS+ CS-
PU PD DIODE
G
SRC
BST
TPS12110-Q1
CBST
VCC
R1
OFF
ON
OV
EN/UVLO
INP
FLT_I
VCC
R5
R3
TPS12111-Q1
ON OFF
VCC
R2
FLT_T
INP
ON OFF
IMON
RIMON
IWRN
TMR
GND
OFF
ON
INP_G
FLT_I
FLT_T
IMON
RIWRN
IWRN
RIWRN
TMR
GND
CTMR
CTMR
RIMON
适用于加热器负载的智能高侧驱动器
适用于直流/直流转换器的断路器
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLUSEQ9
TPS1211-Q1
ZHCSPB6A –JULY 2022 –REVISED SEPTEMBER 2022
www.ti.com.cn
Table of Contents
9 Application and Implementation..................................20
9.1 Application Information............................................. 20
9.2 Typical Application: Driving Zonal Controller
Loads on 12-V Line in Power Distribution Unit............20
9.3 Typical Application: Reverse Polarity Protection
with TPS12110-Q1...................................................... 27
9.4 Power Supply Recommendations.............................28
9.5 Layout....................................................................... 29
10 Device and Documentation Support..........................31
10.1 接收文档更新通知................................................... 31
10.2 支持资源..................................................................31
10.3 Trademarks.............................................................31
10.4 Electrostatic Discharge Caution..............................31
10.5 术语表..................................................................... 31
11 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Device Comparison Table...............................................3
6 Pin Configuration and Functions...................................3
7 Specifications.................................................................. 5
7.1 Absolute Maximum Ratings........................................ 5
7.2 ESD Ratings............................................................... 5
7.3 Recommended Operating Conditions.........................5
7.4 Thermal Information....................................................6
7.5 Electrical Characteristics.............................................6
7.6 Switching Characteristics............................................7
8 Detailed Description........................................................9
8.1 Overview.....................................................................9
8.2 Functional Block Diagram...........................................9
8.3 Feature Description...................................................10
8.4 Device Functional Modes..........................................19
Information.................................................................... 31
11.1 Tape and Reel Information......................................32
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision * (July 2022) to Revision A (September 2022)
Page
• 进行了全面更新以包含TPS12110-Q1 可订购产品............................................................................................. 1
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5 Device Comparison Table
TPS12110-Q1
TPS12111-Q1
Overvoltage protection
Precharge driver
Yes
No
No
Yes
Short-circuit protection
response time
5 µs
1.2 µs
Overtemperature fault
Auto-retry with fixed 512-ms timer
Latch-off
response
6 Pin Configuration and Functions
1
EN/UVLO
INP_G
INP
1
EN/UVLO
VS
VS
20
20
ISCP
OV
2
3
2
3
ISCP
CS+
CS-
19
18
17
19
18
17
CS+
CS-
INP
FLT_T
4
5
4
5
FLT_T
FLT_I
FLT_I
6
6
PU
PD
GND
GND
15
PU
PD
15
7
8
IMON
IMON
7
8
14
13
14
13
IWRN
TMR
IWRN
TMR
SRC
SRC
BST
12
11
9
12
11
9
BST
G
10
N.C
10
DIODE
DIODE
图6-1. VSSOP 19-Pin DGX Top View
表6-1. Pin Functions
PIN
TPS12110-Q1
TPS12111-Q1
TYPE
DESCRIPTION
NAME
DGX-19 (VSSOP)
EN/UVLO input. A voltage on this pin above 1.21 V enables normal
operation. Forcing this pin below 0.3 V shuts down the TPS1211x-
Q1, reducing quiescent current to approximately 3 µA (typical).
Optionally connect to the input supply through a resistive divider to
set the undervoltage lockout. When EN/UVLO is left floating an
internal pulldown of 100 nA pulls EN/UVLO low and keeps the
device in OFF state.
EN/UVLO
1
1
I
Adjustable overvoltage threshold input. Connect a resistor ladder
from input supply, OV to GND. When the voltage at OVP exceeds
the over voltage cutoff threshold then the PD is pulled down to
SRC turning OFF the external FET. When the voltage at OV goes
below OV falling threshold then PU gets pulled up to BST, turning
ON the external FET.
OV
2
I
—
OV must be connected to GND when not used. When OV is left
floating an internal pulldown of 100 nA pulls OV low and keeps PU
pulled up to BST.
Input signal. CMOS compatible input reference to GND that sets
the state of G pin. INP_G has an internal pulldown to GND to keep
G pulled to SRC when INP_G is left floating.
INP_G
INP
2
3
I
I
—
Input S=signal. CMOS compatible input reference to GND that sets
the state of PD and PU pins. INP has an internal pulldown to GND
to keep PD pulled to SRC when INP is left floating.
3
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表6-1. Pin Functions (continued)
PIN
TPS12110-Q1
TPS12111-Q1
TYPE
DESCRIPTION
NAME
DGX-19 (VSSOP)
Open drain fault output. This pin asserts low when overtemperature
fault is detected.
FLT_T
4
5
4
O
Open drain fault output. This pin asserts low after the voltage on
the TMR pin has reached the fault threshold of 1.1V. this pin
indicates the pass transistor is about to turn off due to an
overcurrent condition. The FLT_I pin does not go to a high-
impedance state until the overcurrent condition and the auto-retry
time expire.
FLT_I
5
O
GND
6
7
6
7
G
O
Connect GND to system ground
Analog current monitor output. This pin sources a scaled down
ratio of current through the external current sense resistor RSNS. A
resistor from this pin to GND converts current to proportional
voltage. If unused, connect it to GND.
IMON
Overcurrent detection setting. A resistor across IWRN to GND sets
the over current comparator threshold.
Connect IWRN to GND if over current protection feature is not
desired.
IWRN
TMR
8
9
8
9
I
I
I
Fault timer input. A capacitor across TMR pin to GND sets the
times for fault warning, fault turn-off (FLT_I) and retry periods.
Leave it open for fastest setting. Connect TMR to GND to disable
overcurrent protection.
Diode connection for temperature sensing. Connect it to base and
collector of an MMBT3904 NPN BJT. Connect DIODE to GND, if
remote over temperature sensing and protection feature is not
desired.
DIODE
10
10
GATE of external Precharge FET. Connect to the GATE of the
external FET
G
11
O
—
N.C
11
No connect
—
—
High-side bootstrapped supply. An external capacitor with a
minimum value of > Qg(tot) of the external FET must be connected
between this pin and SRC.
BST
SRC
PD
12
13
14
12
13
14
O
O
O
Source connection of the external FET
High current gate driver pulldown. This pin pulls down to SRC. For
the fastest turn-off, tie this pin directly to the gate of the external
high side MOSFET.
High current gate driver pullup. This pin pulls up to BST. Connect
this pin to PD for maximum gate drive transition speed. A resistor
can be connected between this pin and the gate of the external
MOSFET to control the inrush current during turn-on.
PU
15
15
O
CS-
17
18
17
18
I
I
Current sense negative input
Current sense positive input. Connect a 100-Ωresistor across
CS+ to the external current sense resistor.
CS+
I short-circuit detection threshold setting. Connect ISCP to CS–if
short-circuit protection is not desired.
ISCP
VS
19
20
19
20
I
Power Supply pin of the controller
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–1
MAX
45
UNIT
VS, CS+, CS–, ISCP to GND
VS, CS+, CS–to SRC
SRC to GND
45
–60
–30
–0.3
–0.3
–1
45
PU, PD, G, BST to SRC
16
V
Input Pins
TMR, IWRN, DIODE to GND
5.5
20
OV, EN/UVLO, INP, INP_G, FLT_I , FLT_T to GND
0.3
10
CS+ to CS–
–0.3
I(FLT_I), I(FLT_T)
mA
V
I(CS+) to I(CS–) , 1ms
PU, PD, G, BST to GND
100
60
–100
–30
–1
Output Pins
IMON to GND
5.5
150
150
(2)
Operating junction temperature, Tj
Storage temperature, Tstg
–40
–40
°C
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If
used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully
functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
(2) High junction temperatures degrade operating lifetimes. Operating lifetime is de-rated for junction temperatures greater than 125°C.
7.2 ESD Ratings
VALUE UNIT
Human body model (HBM), per AEC Q100-002(1)
±2000
±750
±500
Corner pins (EN/UVLO, DIODE,
V(ESD) Electrostatic discharge
V
Charged device model (CDM), per
AEC Q100-011
G, VS)
Other pins
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)(1)
MIN
0
NOM
MAX
40
15
15
5
UNIT
VS, CS+, CS- to GND
EN/UVLO, OV to GND
FLT_I, FLT_T to GND
IMON to GND
Input Pins
0
V
0
Output
Pins
0
VS, SRC to GND
22
0.1
–40
nF
µF
°C
External
Capacitor
BST to SRC
Tj
Operating Junction temperature(2)
150
(1) Recommended Operating Conditions are conditions under which the device is intended to be functional. For specifications and test
conditions, see Electrical Characteristics.
(2) High junction temperatures degrade operating lifetimes. Operating lifetime is de-rated for junction temperatures greater than 125°C.
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UNIT
7.4 Thermal Information
TPS1211x-Q1
DGX
THERMAL METRIC(1)
19 PINS
87
RθJA
RθJC(top)
RθJB
ΨJT
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
26.5
43.7
Junction-to-top characterization parameter
Junction-to-board characterization parameter
0.5
43.3
ΨJB
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
7.5 Electrical Characteristics
TJ = –40 ℃to +125℃. V(S) = V(CS+) = V(CS–) = 12 V, V(BST–SRC) = 12 V, V(SRC) = 0 V
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
SUPPLY VOLTAGE
VS
Operating input voltage
3.5
40
V
V
V(S_PORR)
V(S_PORF)
Input supply POR threshold, rising
Input supply POR threshold, falling
3
2.9
500
3
V
Total System Quiescent current, I(GND) V(EN/UVLO) = 2 V
SHDN current, I(GND) V(EN/UVLO) = 0 V, V(SRC) = 0 V
µA
µA
I(SHDN)
ENABLE AND UNDERVOLTAGE LOCKOUT (EN/UVLO) INPUT
V(UVLOR)
V(UVLOF)
UVLO threshold voltage, rising
UVLO threshold voltage, falling
1.16
1.11
1.18
1.12
1.2
V
V
1.15
Enable threshold voltage for low Iq
shutdown, falling
V(ENF)
0.3
V
OVER VOLTAGE PROTECTION (OV) INPUT –TPS12110-Q1 Only
V(OVR)
V(OVF)
Overvoltage threshold input, risIng
Overvoltage threshold input, falling
1.16
1.11
1.18
1.12
1.2
V
V
TPS12110-Q1 Only
1.15
CHARGE PUMP (BST-SRC)
I(BST)
Charge Pump Supply current
V(BST-SRC) = 10 V
70
11
100
µA
V
Charge Pump Turn ON voltage
Charge Pump Turnoff voltage
V(BST-SRC)
13
8
V
V(BST-SRC) UVLO voltage threshold,
rising
V
V(BST UVLO)
V(BST-SRC) UVLO voltage threshold,
falling
6
8
V
V
V(BST-SRC)
Charge Pump Voltage at V(S) = 3.5 V
GATE DRIVER OUTPUTS (PU, PD, G)
I(PU)
I(PD)
Peak Source Current
Peak Sink Current
3.7
4
A
A
Gate charge (sourcing) current, on
state
100
135
µA
I(G)
TPS12111-Q1 Only
Gate discharge (sinking) current, off
state
mA
CURRENT SENSE AND OVER CURRENT PROTECTION (CS+, CS-, IMON, ISCP, IWRN)
RSET = 100Ω, RIMON = 5kΩ,
10kΩ (corresponds to VSNS = 6mV to
30mV) Gain of 45 and 90 respectively.
Input referred offset (VSNS to VIMON
scaling)
V(OS_SET)
350
µV
–350
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7.5 Electrical Characteristics (continued)
TJ = –40 ℃to +125℃. V(S) = V(CS+) = V(CS–) = 12 V, V(BST–SRC) = 12 V, V(SRC) = 0 V
PARAMETER
TEST CONDITIONS
RSET = 100Ω R(IWRN) = 39.7 kΩ
RSET = 100Ω R(IWRN) = 120 kΩ
MIN
TYP
30
MAX UNIT
OCP threshold threshold
OCP threshold threshold
SCP Input Bias current
28
32
mV
mV
µA
V(SNS_WRN)
ISCP
10
13
35
15
17
45
40
mV
mV
R(ISCP) = 2.1 kΩ
R(ISCP) = 750 Ω
V(SNS_SCP)
SCP threshold
20
DELAY TIMER (TMR)
I(TMR_SRC_CB)
I(TMR_SRC_FLT)
I(TMR_SNK)
TMR source current
77
2.5
2.5
µA
µA
µA
TMR source current
TMR sink current
FAULT FLAG (FLT_I, FLT_T), INPUT CONTROLS (INP, INP_G)
R(FLT_T)
I(FLT_T)
V(INP_H)
V(INP_L)
V(INP_G_H)
V(INP_G_L)
TEMPERATURE SENSING AND PROTECTION (DIODE)
FLT Pull-down resistance
70
Ω
nA
V
FLT Input leakage current
400
2
0 V ≤V(FLT) ≤20 V
0.8
0.8
V
2
V
TPS12111-Q1 Only
V
High level
Low level
160
10
µA
µA
A/A
℃
I(DIODE)
External diode current source
Diode current ratio
16
T(DIODE_TSD_rising) DIODE sense TSD rising threshold
155
7.6 Switching Characteristics
TJ = –40 ℃to +125℃. V(CS+) = V(CS–) = 12 V, V(BST–SRC) = 12 V, V(SRC) = 0 V
PARAMETER
TEST CONDITIONS
INP ↑to PU ↑, CL = 47 nF
INP ↓to PD ↓, CL = 47 nF
MIN
TYP
2
MAX UNIT
tPU(INP_H)
tPD(INP_L)
INP Turn ON propogation Delay
INP Turn OFF propogation Delay
µs
µs
1
INP_G ↑to G ↑, CL = 1
nF, TPS12111-Q1 Only
tG(INP_G_H)
INP_G Turn ON propogation Delay
25
µs
INP_G ↓to G ↓, CL = 1
nF, TPS12111-Q1 Only
tG(INP_G_L)
INP_G Turn OFF propogation Delay
UVLO Turn OFF Propogation Delay
1
4
µs
µs
µs
tPD(UVLO_OFF)
tPD(VS_OFF)
UVLO ↓to PD ↓, CL = 47 nF
PD Turn OFF delay during input
supply (Vs) interruption
Vs ↓V(SPOR_F) to PD ↓, CL = 47 nF,
INP = EN/UVLO = 2 V
40
VS ↑V(SPOR_R) to PU ↑, CL = 47 nF,
INP = EN/UVLO = 2 V, V(BST–SRC)
> V( BST UVLOR)
PU Turn ON delay during input supply
(Vs) recovery
tPU(VS_ON)
350
350
µs
µs
PU Turn ON delay during transition
from shutdown mode to active mode
with CBST pre-biased
EN/UVLO ↑to PU ↑, CL = 47 nF,
INP = 2 V, V(BST–SRC) > V( BST UVLOR)
tPU(EN_ON)
OV ↑to PD ↓, CL = 47
nF, TPS12110-Q1 Only
tPD(OV_OFF)
OV Turn Off progopation Delay
3
5
µs
µs
µs
(VCS+ –VCS–) ↑I(SC) to PD ↓, CL =
47 nF, TPS12110-Q1 Only
Short Circuit Protection propogation
Delay
t(SC)
(VCS+ –VCS–) ↑I(SC) to PD ↓, CL =
47 nF, TPS12111-Q1 Only
1.2
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7.6 Switching Characteristics (continued)
TJ = –40 ℃to +125℃. V(CS+) = V(CS–) = 12 V, V(BST–SRC) = 12 V, V(SRC) = 0 V
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
(VCS+ –VCS–) ↑I(OC) to PD ↓, CL =
47 nF, C(TMR) = 0 nF
24
µs
t(OC)
Over current protection delay
(VCS+ –VCS–) ↑I(OC) to PD ↓, CL =
312
290
260
512
µs
µs
µs
ms
47 nF, C(TMR) = 18 nF
tFLT_I(IFLT_ASSERT) FLT_I assertion delay
tFLT_I(IFLT_DE_ASSER
FLT_I de-assertion delay
T)
tFLT_T(AR)
TSD Auto-retry
TPS12110-Q1 Only
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8 Detailed Description
8.1 Overview
The TPS1211-Q1 family is a 45-V smart high-side drivers with protection and diagnostics. With wide operating
voltage range of 3.5 V –40 V, the device is suitable for 12-V system designs.
The device has a strong 4-A sink (PD) and source (PU) gate driver that enables power switching using parallel
FETs in high current system designs. Use INP as the gate driver control input. MOSFET slew rate control (ON
and OFF) is possible by placing external R-C components.
The device has accurate current sensing (±2% at 30 mV) output (IMON) enabling systems for energy
management. The device has integrated two-level, overcurrent protection with FLT_I output with complete
adjustability of thresholds and response time. Auto-retry and latch-off fault behavior can be configured.
The device features remote overtemperature protection with FLT_T output enabling robust system protection.
TPS12110-Q1 has an accurate overvoltage protection (±3%), providing robust load protection.
The TPS12111-Q1 integrates a precharge driver (G) with control input (INP_G). This feature enables system
designs that must drive large capacitive loads by precharging first and then turning ON the main power FETs.
TPS1211-Q1 has an accurate undervoltage protection (±3%) using the EN/UVLO pin. Pull EN/UVLO low (< 0.3
V) to turn OFF the device and enter into shutdown mode. In shutdown mode, the controller draws a total IQ of 3
µA (maximum) at 12-V supply input.
8.2 Functional Block Diagram
Q2
RSNS
Q1
VOUT
VBATT
RISCP
ISCP
RSET
CS+
BST
CS-
DIODE
VS
PU
PD
SRC
4 A
3.7 A
Remote
Temp
sense
+
Internal
Regulators
EN
14.5 µA
EN
3.1 V
2.9 V
EN
R_Temp
VINT
POR
PU/PD_ON/OFF
+
PU/PD_ON/
OFF
CP (12 V)
EN
1V
VS
0.3V
FLT_I
100 µA
+
+
UVLO
EN/UVLO
INP
FLT_I
FLT_T
+
1.18 V
1.11 V
FLT_I
70
70
CS-
Gate Driver
control
logic
EN
Charge
pump
enable
logic
2 V
+
VREF
BST
SRC
0.8 V
+
VINT
FLT_T
OV
1.18 V
1.11 V
79 µA
/ 2.5 µA
FLT_T
4.5 V
6.5 V
R_Temp
TPS12110-Q1
GND
IMON
RIMON
IWRN
RIWRN
TMR
CTMR
图8-1. TPS12110-Q1 Functional Block Diagram
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R
Q3
V_Precharge
Q2
RSNS
Q1
VBATT
VOUT
RISCP
ISCP
RSET
CS+
BST
CS-
DIODE
VS
PU
PD
G
SRC
4 A
3.7 A
0.14 A
Remote
Temp
sense
+
Internal
Regulators
EN
14.5 µA
EN
3.1 V
2.9 V
G_ON/
OFF
EN
VS
R_Temp
VINT
POR
100 µA
PU/PD_ON/OFF
+
PU/PD_ON/
OFF
G_ON/OFF
EN
BST
CP (12 V)
1 V
0.3 V
FLT_I
+
+
UVLO
EN/UVLO
INP
FLT_I
100 µA
FLT_T
+
1.18 V
1.11 V
FLT_I
70
70
CS-
Gate Driver
control
logic
EN
2 V
+
VREF
Charge
pump
enable
logic
0.8 V
BST
+
FLT_T
VINT
INP_G
SRC
2 V
79 µA
/2.5 µA
FLT_T
0.8 V
4.5 V
6.5 V
R_Temp
TPS12111-Q1
IMON
RIMON
GND
IWRN
RIWRN
TMR
CTMR
图8-2. TPS12111-Q1 Functional Block Diagram
8.3 Feature Description
8.3.1 Charge Pump and Gate Driver Output (VS, PU, PD, BST, SRC)
图8-3 shows a simplified diagram of the charge pump and gate driver circuit implementation. The device houses
a strong 3.7-A source and 4-A sink gate drivers. The strong gate drivers enable paralleling of FETs in high power
system designs ensuring minimum transition time in saturation region. A 12-V, 100-µA charge pump is derived
from VS terminal and charges the external boot-strap capacitor, CBST that is placed across the gate driver (BST
and SRC).
In switching applications, if the charge pump supply demand is higher than 100 µA, then supply BST externally
using a low leakage diode and 12-V supply as shown in the 图8-3.
VS is the supply pin to the controller. With VS applied and EN/UVLO pulled high, the charge pump turns ON and
charges the CBST capacitor. After the voltage across CBST crosses V(BST_UVLOR), the GATE driver section is
activated. The device has a 1-V (typical) UVLO hysteresis to ensure chattering less performance during initial
GATE turn ON. Choose CBST based on the external FET QG and allowed dip during FET turn-ON. The charge
pump remains enabled until the BST to SRC voltage reaches 12.3 V, typically, at which point the charge pump is
disabled decreasing the current draw on the VS pin. The charge pump remains disabled until the BST to SRC
voltage discharges to 11.7 V typically at which point the charge pump is enabled. The voltage between BST and
SRC continue to charge and discharge between 12.3 V and 11.7 V as shown in the 图8-4.
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VS
12 V
CS+
To
current
sensing
RSNS
CS-
Charge
pump (12 V)
12 V
D1*
100 µA
BST
CBST
Q1
PU
PD
INP
Level Shifter
Q2
SRC
TPS1211x-Q1
RLOAD
图8-3. Gate Driver
TON
TDRV_EN
TOFF
VIN
Vs
0V
VEN/UV LO
12.3 V
11.7 V
VBST-SRC
7.5 V
V(BST UVLOR)
GATE DRIVER
ENABLE
图8-4. Charge Pump Operation
Use the following equation to calculate the initial gate driver enable delay.
CBST × V(BST_UVLOR)
TDRV_EN
Where,
=
100 µA
(1)
C(BST) is the charge pump capacitance connected across BST and SRC pins.
V(BST_UVLOR) = 7.5 V (typical).
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If TDRV_EN must be reduced, then pre-bias the BST terminal externally using an external 12-V supply through a
low leakage diode D1 as shown in 图8-3. With this connection, TDRV_EN reduces to 350 µs.
8.3.2 Capacitive Load Driving
Certain end equipments like automotive power distribution unit power different loads including other ECUs.
These ECUs can have large input capacitances. If power to the ECUs is switched on in uncontrolled way, large
inrush currents can occur potentially damaging the power FETs.
To limit the inrush current during capacitive load switching, the following system design techniques can be used
with TPS1211x-Q1 devices.
8.3.2.1 FET Gate Slew Rate Control
For limiting inrush current during turn-ON of the FET with capacitive loads, use R1, R2, C1 as shown in 图 8-5.
The R1 and C1 components slow down the voltage ramp rate at the gate of the FET. The FET source follows the
gate voltage resulting in a controlled voltage ramp across the output capacitors.
BST
CBST
Q1
R1
PU
PD
INP
Level Shifter
R2
C1
SRC
TPS1211x-Q1
CLOAD
图8-5. Inrush Current Limiting with FET Gate Slew Rate Control
Use the 方程式2 to calculate the inrush current during turn-ON of the FET.
VBATT
IINRUSH
=
CLOAD
×
Tcharge
(2)
(3)
0.63 × V(BST-SRC) × CLOAD
R1 × C1
IINRUSH
=
Where,
CLOAD is the load capacitance, VBATT is the input voltage and Tcharge is the charge time, V(BST-SRC) is the charge
pump voltage (12 V),
Use a damping resistor R2 (approximately 10 Ω) in series with C1. 方程式3 can be used to compute required C1
value for a target inrush current. A 100-kΩresistor for R1 can be a good starting point for calculations.
Connecting PD pin of TPS1211x-Q1 directly to the gate of the external FET ensures fast turn-OFF without any
impact of R1 and C1 components.
C1 results in an additional loading on CBST to charge during turn-ON. Use 方程式 4 to calculate the required
CBST value.
CBST > Qg(total) + 10 × C1
(4)
Where, Qg(total) is the total gate charge of the FET.
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8.3.2.2 Using Precharge FET - (with TPS12111-Q1 Only)
In high-current applications where several FETs are connected in parallel, the gate slew rate control for the main
FETs is not recommended due to unequal distribution of inrush currents among the FETs. This action makes
FET selection complex and results in over sizing of the FETs.
The TPS12111-Q1 integrates precharge gate driver (G) with a dedicated control input (INP_G). This feature can
be used to drive a separate FET that can be used to precharge the capacitive load. 图 8-6 shows the precharge
FET implementation for capacitive load charging using TPS12111-Q1. An external capacitor Cg reduces the gate
turn-ON slew rate and controls the inrush current.
VBATT
BST
CBST
Q1
PU
PD
INP
Level Shifter
Level Shifter
Q2
SRC
G
INP_G
Q3
Rg
Cg
IG
VOUT
CLOAD
BST
TPS12111-Q1
图8-6. Capacitor Charging Using Gate Slew Rate Control of Precharge FET
During power up with EN/UVLO high and C(BST) voltage above V(BST_UVLOR) threshold, INP and INP_G controls
are active. For the precharge functionality, drive INP low to keep the main FETs OFF and drive INP_G high. G
output gets pulled up to BST with IG. Use 方程式5 to calculate the required Cg value.
IINRUSH
IG = Cg ×
COUT
(5)
Where,
IG is 100 µA (typical),
Use 方程式2 to calculate the IINRUSH
.
A series resistor Rg must be used in conjunction with Cg to limit the discharge current from Cg during turn-off .
The recommended value for Rg is between 220 Ω to 470 Ω. After the output capacitor is charged, turn OFF the
precharge FET by driving INP_G low. G gets pulled low to SRC with an internal 135-mA pulldown switch. The
main FETs can be turned ON by driving INP high.
图8-7 shows other system design approaches to charge large output capacitors in high current applications. The
designs involve an additional power resistor in series in series with precharge FET. The back-to-back FET
topology shown is typically used in bi-directional power control applications like battery management systems.
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Q2
R
Q3
R
Q4
Q3
G
Q1
Q2
Q1
RSNS
VOUT
CBLK
RSNS
VOUT
CBLK
VBATT
(12 V)
VBATT
(12 V)
RSET
RISCP
CBST
BST
RSET
RISCP
CS+ CS-
ISCP
PU PD DIODE
G
VS
VS ISCP CS+ CS-
EN/UVLO
SRC
PU PD
SRC
BST
CBST
VCC
R1
DIODE
OFF
ON
ON OFF
OFF
EN/UVLO
INP
OFF
ON
G
G
VCC
TPS12111-Q1
VCC
R2
TPS12111-Q1
ON OFF
INP
VCC
R2
R1
ON
INP_G
FLT_I
OFF
ON
INP_G
FLT_I
FLT_T
IMON
IWRN
RIWRN
TMR
GND
FLT_T
IMON
IWRN
RIWRN
TMR
GND
CTMR
RIMON
CTMR
RIMON
图8-7. TPS12111-Q1 application Circuits for Capacitive Load Driving Using Precharge FET and a Series
Power Resistor
8.3.3 Overcurrent and Short-Circuit Protection
TPS1211x-Q1 has two-level current protection.
• Adjustable overcurrent protection (IOC) threshold and response time (TOC),
• Adjustable short-circuit threshold (ISC) with internally fixed fast response (TSC).
图8-8 shows the I-T characteristics.
Time
TOC
Nominal current
Over current
No Shutdown
Shutdown with
adjustable delay
Short circuit
Immediate
shutdown
TSC
Current
IOC
ISC
图8-8. Overcurrent and Short-Circuit Protection Characteristics
The device senses the voltage across the external current sense resistor through CS+ and CS–. Set the
overcurrent protection threshold using an external resistor RIWRN across IWRN and GND. Use 方程式 6 to
calculate the required RIWRN value.
11.9 × RSET
RIWRN ( ) =
RSNS × IOC
(6)
Where, RSET is the resistor connected across CS+ and VS, RSNS is the current sense resistor, and IOC is the
overcurrent level.
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8.3.3.1 Overcurrent Protection with Auto-Retry
The C(TMR) programs the over current protection delay (TOC) and auto-retry time (TRETRY). Once the voltage
across CS+ and CS– exceeds the set point, the C(TMR)starts charging with 77-µA pullup current. After the
C(TMR)charges up to V(TMR_FLT), FLT_I asserts low providing warning on impending FET turn OFF. After C(TMR)
charges to V(TMR_OC), PD pulls low to SRC turning OFF the FET. Post this event, the auto-retry behavior starts.
The C(TMR) capacitor starts discharging with 2.5-uA pulldown current. After the voltage reaches V(TMR_Low) level,
the capacitor starts charging with 2.5-uA pullup. After 32 charging, discharging cycles of C(TMR)the FET turns ON
back and FLT_I de-asserts after de-assertion delay of 260 µs.
Use 方程式7 to calculate the TOC duration.
1.2 × CTMR
TOC
=
77.5 µ
(7)
(8)
Where, TOC is the delay to turn OFF the FET, CTMR is the capacitance across TMR to GND.
Use 方程式8 to calculate the TFLT duration.
1.1 × CTMR
TFLT
=
77.5 µ
Where, TFLT is the FLT_I assertion delay.
The auto-retry time can be computed as, TRETRY = 22.7 × 106 × CTMR
.
If the overcurrent pulse duration is below T(OC), then the FET remains ON and C(TMR) gets discharged using
internal pulldown switch.
IOC
TPULSE
0-A
TOC
VINT
VTMR_OC
77 µA
/ 5 µA
VTMR_FLT
VTMR_Low
TMR
1st
2nd
32nd
2.5 µA
Vcc
0-V
TPS1211x-Q1
TWRN
TFLT_I = 0.9 x TOC
12 V
0-V
图8-9. Overcurrent Protection with Auto-Retry
8.3.3.2 Overcurrent Protection with Latch-Off
Connect an approximately 100-kΩ resistor across C(TMR) as shown in the following figure. With this resistor,
during the charging cycle, the voltage across C(TMR) gets clamped to a level below V(TMR_OC) resulting in a latch-
off behavior.
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Toggle INP or EN/UVLO (below ENF) or power cycle Vs below VSPORF to reset the latch. At low edge, the timer
counter is reset and C(TMR) is discharged. PU pulls up to BST when INP is pulled high.
IOC
TPULSE
0-A
TOC
VTMR_OC
The resistor across TMR to GND prevents the VTMR to charge to upper threshold
and the counter does not see next counts, resulting in FET to stay latch OFF
VTMR_FLT
VTMR_Low
VINT
77 µA
/5 µA
1st
TMR
Vcc
0-V
100 kΩ
2.5 µA
TWRN
TPS1211x-Q1
TFLT_I = 0.9 x TOC
12 V
0-V
When INP is pulled low, the timer counter is reset
and TMR cap is discharged
Starts a fresh turn ON cycle
图8-10. Overcurrent Protection with Latch-Off
8.3.3.3 Short-Circuit Protection
Connect a resistor, RISCP, as shown in 图8-11.
Use 方程式9 to calculate the required RISCP value.
ISC × RSNS
600
RISCP ( ) =
14.5 µ
(9)
Where, RSNS is the current sense resistor, and ISC is the desired short-circuit protection level. After the current
exceeds the ISC threshold then, PD pulls low to SRC within 1.2 µs in TPS12111-Q1 and 5 µs in TPS12110-Q1,
protecting the FET. FLT_I asserts low at the same time. Subsequent to this event, the charge and discharge
cycles of C(TMR) starts similar to the behavior post FET OFF event in the over current protection scheme.
Latch-off can also achieved in the similar way as explained in the overcurrent protection scheme.
8.3.4 Analog Current Monitor Output (IMON)
TPS1211x-Q1 features an accurate analog load current monitor output (IMON) with adjustable gain. The current
source at IMON terminal is configured to be proportional to the current flowing through the RSNS current sense
resistor. This current can be converted to a voltage using a resistor RIMON from IMON terminal to GND terminal.
This voltage, computed using 方程式10 can be used as a means of monitoring current flow through the system.
Use 方程式10 to calculate the VIMON
.
VIMON = (VSNS + VOS_SET) × Gain
(10)
Where VSNS = ILOAD × RSNS and VOS_SET is the input referred offset (± 350 µV) of the current sense amplifier
(VSNS to VIMON scaling). Use the following equation to calculate gain.
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0.9 × RIMON
Gain =
RSET
(11)
Where 0.9 is the current mirror factor between the current sense amplifier and the IMON pass FET.
The maximum voltage range for monitoring the current (V(IMONmax)) is limited to minimum([V(VS) – 0.5V],
5.5V) to ensure linear output. This puts limitation on maximum value of RIMON resistor. The IMON pin has an
internal clamp of 6.5 V (typical).
Accuracy of the current mirror factor is < ± 1%. Use the following equation to calculate the overall accuracy of
VIMON
.
VOS_SET
× 100
% VIMON
=
VSNS
(12)
图 8-11 shows external connections and simplified block diagram of current sensing and overcurrent protection
implementation.
RSNS
VIN
RISCP
ISCP
RSET
50
100
-
CS+
CS-
14.5 µA
SC
Comparator
+
CS-
To control Logic
VREF
+
OC
Comparator
4.5 V
6.5 V
TPS1211x-Q1
IMON
RIMON
IWRN
RIWRN
图8-11. Current Sensing and Overcurrent Protection
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8.3.5 Overvoltage (OV) and Undervoltage Protection (UVLO)
VIN
R1
R1
EN/UVLO
EN/UVLO
OV
+
+
+
UVLOb
UVLOb
OVP
1.18 V
1.12 V
1.18 V
1.12 V
R2
R2
R3
1.18 V
TPS12111-Q1
1.12 V
TPS12110-Q1
图8-12. Programming Overvoltage and Undervoltage Protection Threshold
8.3.6 Remote Temperature Sensing and Protection (DIODE)
The device features an integrated remote temperature sensing, protection and dedicated fault output. With a
companion BJT, MMBT3904 as a remote temperature sense element, the controller gets the temperature
information of the sense point. Connect the DIODE pin of TPS1211-Q1 to the collector, base of a MMBT3904
BJT. After the sensed temperature reaches approximately 155ºC, the device pulls PD low to SRC, turning off the
external FET and also asserts FLT_T low. After the temperature reduces to 125ºC (minimum), an internally fixed
auto-retry cycle of 512 ms commences. FLT_T de-asserts and the external FET turns ON after the re-try
duration of 512 ms is lapsed.
In TPS12111-Q1, after the sensed temperature crosses 155°C, PD and G get pulled low to SRC. After the TSD
hysteresis, PU and G stays latched OFF. The latch gets reset by toggling EN/UVLO below V(ENF) or by power
cycling Vs below VSPORF
.
8.3.7 TPS1211x-Q1 as a Simple Gate Driver
图 8-13 shows application schematics of TPS1211x-Q1 as a simple gate driver in load disconnect switch as well
as back-to-back FETs driving topologies. The protection features like two-level overcurrent protection,
overvoltage protection, and overtemperature protection are disabled.
Q2
Q1
Q1
VOUT
VOUT
VIN
VIN
RSET
RSET
100 Ω
100 Ω
CBST
CBST
CS+ CS-
CS+ CS-
ISCP
VS
ISCP
VS
PU PD SRC
PU PD SRC
BST
BST
OFF
OFF
OFF
ON
ON
ON
ON
EN/UVLO
INP
EN/UVLO
INP
TPS12110-Q1
TPS12110-Q1
FLT_I
FLT_I
OFF
FLT_T
IMON
FLT_T
IMON
DIODE GND OV
DIODE GND OV
TMR
IWRN
IWRN
TMR
图8-13. Connection Diagram of TPS12110-Q1 for Simple Gate Driver Design
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8.4 Device Functional Modes
The TPS1211-Q1 has two modes of operation. Active mode and low IQ shutdown mode. If the EN/UVLO pin
voltage is greater than the rising threshold, then the device is in active mode. In active state the internal charge
pump is enabled, gate drivers and all the protection and diagnostic features are enabled. If the EN/UVLO voltage
is pulled < 0.3 V, the device enters into low IQ shutdown mode. In this mode, the charge pump, gate drivers and
all the protection features are disabled. The external FETs turn OFF. The TPS1211-Q1 consumes low IQ of 1.7
µA (typical) in this mode.
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9 Application and Implementation
备注
以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客 户应负责确定
器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。
9.1 Application Information
The TPS1211x-Q1 family is a 45-V smart high-side driver with protection and diagnostics. The TPS1211x-Q1
device controls external N-channel MOSFETs and its drive architecture is suitable to drive back-to-back N-
Channel MOSFETs. The strong gate 4-A source and sink capabilities enable switching parallel MOSFETs in high
current applications such as circuit breaker in powertrain (DC/DC converter), driving loads in power distribution
unit, electric power steering, driving PTC heater loads, and so forth. The TPS1211x-Q1 device provides two-
level, adjustable, overcurrent protection with adjustable circuit breaker timer, fast short-circuit protection,
accurate analog current monitor output, and remote overtemperature protection.
The variant TPS12111-Q1 features a separate precharge driver (G) with independent control input (INP_G). This
feature enables system designs that must precharge the large output capacitance before turning ON the main
power path.
The following design procedure can be used to select the supporting component values based on the application
requirement.
9.2 Typical Application: Driving Zonal Controller Loads on 12-V Line in Power Distribution Unit
Q3
DIODE
G
Q2
Rg
Q4
Cg
G1
Q1
RSNS
VOUT
CBLK
VBATT
(12 V)
G1
PU PD
RSET
RISCP
CBST
BST
R1
VS ISCP CS+ CS-
EN/UVLO
SRC
R2
DIODE
DIODE
G
G
VCC
TPS12111-Q1
ON OFF
INP
VCC
R2
R1
OFF
ON
INP_G
FLT_I
FLT_T
IMON
IWRN
RIWRN
TMR
GND
CTMR
RIMON
图9-1. Typical Application Schematic: Driving Zonal Controller Loads with Precharging the Output
Capacitance
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9.2.1 Design Requirements
表9-1 shows the design parameters for this application example.
表9-1. Design Parameters
PARAMETER
VALUE
12 V
Typical input voltage, VIN
Undervoltage lockout set point, VINUVLO
Maximum load current, IOUT
6.5 V
25 A
Overcurrent protection threshold, IOC
30 A
Short-circuit protection threshold, ISC
35 A
1 ms
Fault timer period (TOC
)
Fault response
Auto-retry
1 mF
Load capacitance, COUT
Charging time, Tstart
10 ms
9.2.2 Detailed Design Procedure
Selection of Current Sense Resistor, RSNS
The recommended range of the overcurrent protection threshold voltage, V(SNS_WRN), extends from 10 mV to 30
mV. Values near the low threshold of 10 mV can be affected by the system noise. Values near the upper
threshold of 30 mV can cause high power dissipation in the current sense resistor. To minimize both the
concerns, 25 mV is selected as the overcurrent protection threshold voltage. Use the following equation to
calculate the current sense resistor, RSNS
.
V(SNS-WRN)
25 mV
30 A
833 µΩ
=
RSNS
=
=
IOC
(13)
The next smaller available sense resistor 800 μΩ, 1% is chosen.
To improve signal to noise ratio or for better overcurrent protection accuracy, higher overcurrent protection
threshold voltage, V(SNS_WRN) can be selected. The maximum allowed V(SNS_WRN) voltage is 250 mV.
Selection of Scaling Resistor, RSET
RSET is the resistor connected between VS and CS+ pins. This resistor scales the overcurrent protection
threshold voltage and coordinates with RIWRN and RIMON to determine the overcurrent protection threshold and
current monitoring output. The recommended range of RSET is 50 Ω –100 Ω.
RSET is selected as 100 Ω, 1% for this design example.
Programming the Overcurrent Protection Threshold –RIWRN Selection
The RIWRN sets the overcurrent protection threshold, whose value can be calculated using 方程式14.
11.9 × RSET
RIWRN ( ) =
RSNS × IOC
(14)
To set 30 A as overcurrent protection threshold, RIWRN value is calculated to be 49.5 kΩ.
Choose the closest available standard value: 49.9 kΩ, 1%
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.
Programming the Short-Circuit Protection Threshold –RISCP Selection
The RISCP sets the short-circuit protection threshold. Use the following equation to calculate the value.
ISC × RSNS
600
RISCP ( ) =
14.5 µ
(15)
To set 35 A as overcurrent protection threshold, RISCP value is calculated to be 1.33 kΩ.
Choose the closest available standard value: 1.43 kΩ, 1%.
In case where large di/dt is involved, the system and layout parasitic inductances can generate large differential
signal voltages between ISCP and CS– pins. This action can trigger false short-circuit protection and nuisance
trips in the system. To overcome such scenario, TI recommends to add filter capacitor of 1 nF across ISCP and
CS– pins close to the device. Because nuisance trips are dependent on the system and layout parasitics, TI
recommends to test the design in a real system and tweaked as necessary.
Programming the Fault timer Period –CTMR Selection
For the design example under discussion, overcurrent transients are allowed for 1-ms duration. This blanking
interval, TOC can be set by selecting appropriate capacitor CTMR from TMR pin to ground. Use the following
equation to calculate the value of CTMR to set 1 ms for TOC
.
TOC × 77.5 µA
64.58 nF
CTMR
=
=
1.2
(16)
Choose closest available standard value: 68 nF, 10%.
Selection of MOSFETs, Q1 and Q2
For selecting the MOSFET Q1, important electrical parameters are the maximum continuous drain current ID, the
maximum drain-to-source voltage VDS(MAX), the maximum drain-to-source voltage VGS(MAX), and the drain-to-
source ON-resistance RDSON
.
The maximum continuous drain current, ID, rating must exceed the maximum continuous load current.
The maximum drain-to-source voltage, VDS(MAX), must be high enough to withstand the highest voltage seen in
the application. Considering 35 V as the maximum application voltage, MOSFETs with VDS voltage rating of 40 V
is suitable for this application.
The maximum VGS TPS1211-Q1 can drive is 13 V, so a MOSFET with 15-V minimum VGS rating must be
selected.
To reduce the MOSFET conduction losses, lowest possible RDS(ON) is preferred.
Based on the design requirements, BUK7S0R5-40HJ is selected and its ratings are:
• 40-V VDS(MAX) and 20-V VGS(MAX)
• RDS(ON) is 0.47-mΩtypical at 10-V VGS
• MOSFET Qg(total) is 190 nC
Selection of Bootstrap Capacitor, CBST
The internal charge pump charges the external bootstrap capacitor (connected between BST and SRC pins) with
approximately 100 μA. Use the following equation to calculate the minimum required value of the bootstrap
capacitor for driving two parallel BUK7S0R5-40HJ MOSFETs.
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Qg(total)
1 V
380 nF
CBST
=
=
(17)
Choose closest available standard value: 470 nF, 10 %.
Setting the Undervoltage Lockout
The undervoltage lockout (UVLO) can be adjusted using an external voltage divider network of R1 and R2
connected between VS, EN/UVLO and GND pins of the device. The values required for setting the undervoltage
and overvoltage are calculated by solving 方程式18.
R2
V(UVLOR)
=
× VINUVLO
(R1 + R2)
(18)
For minimizing the input current drawn from the power supply, TI recommends to use higher values of resistance
for R1 and R2. However, leakage currents due to external active components connected to the resistor string can
add error to these calculations. So, the resistor string current, I(R12) must be chosen to be 20 times greater than
the leakage current of UVLO pin.
From the device electrical specifications, V(UVLOR) = 1.18 V. From the design requirements, VINUVLO is 6.5 V. To
solve the equation, first choose the value of R1 = 470 kΩ and use 方程式18 to solve for R2 = 104.24 kΩ. Choose
the closest standard 1% resistor values: R1 = 470 kΩ, and R2 = 105 kΩ.
Selection of Precharge Path Components, Cg and Rg
For charging the large capacitors on output, the output slew rate can be controlled by using a capacitor on the
gate (G) of the precharge FET Q3. The target inrush current to charge 1 mF of output capacitance to 12-V in 10
ms can be estimated by 方程式 19. The required gate capacitance Cg to limit the inrush current to 1.2 A can be
calculated by using 方程式 16, where Ig = 100 μA (typical) is the gate charging current of pin 'G'. By solving 方
程式20, we get Cg as 83.33 nF.
Choose the closest available standard value: 82 nF, 10%.
VIN
1.2 A
IINRUSH
=
COUT
=
×
Tstart
(19)
(20)
IINRUSH
Ig = Cg ×
COUT
A series resistor Rg must be used in conjunction with Cg to limit the discharge current from Cg during turn-off and
to stabilize the gate 'G' during slew rate control. The recommended value for Rg is between 220 Ω to 470 Ω.
Choosing the Current Monitoring Resistor, RIMON
Voltage at IMON pin VIMON is proportional to the output load current. This can be connected to an ADC of the
downstream system for monitoring the operating condition and health of the system. The RIMON must be
selected based on the maximum load current and the input voltage range of the ADC used. RIMON is set using 方
程式21.
0.9 × RIMON
VIMON = (VSNS + VOS_SET) ×
RSET
(21)
Where VSNS = IOC × RSNS and VOS_SET is the input referred offset (± 350 µV) of the current sense amplifier.
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The maximum voltage range for monitoring the current (V(IMONmax)) is limited to minimum([V(VS) – 0.5V],
5.5V) to ensure linear output. This puts a limitation on the maximum value of RIMON resistor. The IMON pin has
an internal clamp of 6.5 V (typical).
For IOC = 30 A and considering the operating range of ADC to be 0 V to 3.3 V (for example, VIMON = 3.3 V),
RIMON can be calculated as
VIMON × RSET
16.52 k
RIMON
=
=
(VSNS + VOS_SET) × 0.9
(22)
Selecting RIMON value less than shown in 方程式 22 ensures that ADC limits are not exceeded for maximum
value of load current. Choose the closest available standard value: 16.5 kΩ, 1%.
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9.2.3 Application Curves
图9-2. Start-Up Profile of Bootstrap Voltage for INP 图9-3. Start-Up Profile of Bootstrap Voltage for INP
= GND = HIGH
图9-4. Turn-ON Response of TPS12111-Q1 for INP - 图9-5. Turn-OFF Response of TPS12111-Q1 for INP
> LOW to HIGH
-> HIGH to LOW
I_LOAD
IMON
图9-6. IMON Response During 12-A Load Step
图9-7. Overcurrent Response of TPS12111-Q1 for a
Load Step from 20 A to 32 A with 30-A Overcurrent
Protection Setting
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图9-8. Auto-Retry Response of TPS12111-Q1 for 图9-9. Latch-Off Response of TPS12111-Q1 for an
an Overcurrent Fault
Overcurrent Fault
图9-10. Response During Coming out of Overload
图9-11. Precharge Profile of the Output
Fault with INP Reset
Capacitance (VIN = 12 V, COUT = 1 mF, No Load)
图9-12. Output Hot-Short Response of the TPS12111-Q1 Device
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9.3 Typical Application: Reverse Polarity Protection with TPS12110-Q1
Q3
GND
Q2
Q1
RSNS
VOUT
VBATT
(12 V)
CBLK
RSET
RISCP
CBST
R1
VS ISCP CS+ CS-
EN/UVLO
SRC
BST
DIODE
PU PD
R2
R3
VCC
R1
OV
TPS12110-Q1
VCC
R2
FLT_I
GND
ON
INP
IWRN
RIWRN
OFF
FLT_T
IMON
GND
TMR
CTMR
RIMON
GND
D1
RBIAS
VBATT
(12 V)
PGND
图9-13. Typical Application Schematic: TPS12110-Q1 High-Side Driver with Input Reverse Polarity
Protection
For applications such as powering electronic power steering (EPS) system, the input must be protected from any
possible reverse polarity scenarios. The TPS12110-Q1 configured as shown in 图 9-13 meets the system
requirements. The back-to-back FET (Q1 and Q2) configuration blocks reverse current flow and provides
protection for the load against static input reverse polarity event. The N-MOSFET (Q4) in the ground path
protects the TPS12110-Q1 controller, and Zener diode D1 is added for VGS protection of Q4.
9.3.1 Design Requirements
表9-2 shows the design parameters for this application example.
表9-2. Design Parameters
PARAMETER
VALUE
12 V
Typical input voltage, VIN
Undervoltage lockout set point, VINUVLO
OV set point, VINOVP
6.5 V
36 V
Maximum load current, IOUT
20 A
Overcurrent protection threshold, IOC
Short-circuit protection threshold, ISC
24 A
30 A
Fault timer period (TOC
)
1 ms
Fault response
Auto-retry
Yes
Input reverse polarity protection
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9.3.2 External Component Selection
By following similar design procedure as outlined in Detailed Design Procedure, the external component values
are calculated as below:
• RSNS = 1 mΩ.
• RSET = 100 Ω.
• RIWRN = 49.9 kΩto set 24 A as overcurrent protection threshold.
• RISCP = 1.468 kΩto set 30 A as short-circuit protection threshold.
• CTMR = 68 nF to set 1-ms over current protection time.
• R1 , R2 and R3 are selected as 390 kΩ, 71.5 kΩand 15.8 kΩrespectively to set VIN undervoltage lockout
threshold at 6.5 V and overvoltage cutoff threshold at 36 V.
• RIMON = 15 kΩto limit maximum V(IMON) voltage to 3.3 V at full-load current of 24 A.
• To reduce conduction losses, BUK7S0R5-40HJ MOSFET is selected. Two FETs are used in back-to-back
configuration for reverse current blocking.
– 40-V VDS(MAX) and 20-V VGS(MAX)
.
– RDS(ON) is 0.47-mΩtypical at 10-V VGS
.
– Qg of each MOSFET is 190 nC.
• CBST = (2 × Qg) / 1 V = 380 nF; Choose the closest available standard value: 470 nF, 10 %.
• Q4 selection: Any signal N-MOSFET with 40-V VDS support is sufficient. DMN601WKQ-7 is selected for the
current design and a 12-V Zener diode SZMM3Z12VST1G is used for VGS protection.
9.3.3 Application Curves
图9-14. Overvoltage Cutoff Response of
图9-15. Input Reverse Polarity Protection with
TPS12110-Q1 at 36-V Level
TPS12110-Q1
9.4 Power Supply Recommendations
When the external MOSFETs turn OFF during the conditions such as INP control, overvoltage cutoff, overcurrent
protection causing an interruption of the current flow, the input parasitic line inductance generates a positive
voltage spike on the input and output parasitic inductance generates a negative voltage spike on the output. The
peak amplitude of voltage spikes (transients) depends on the value of inductance in series to the input or output
of the device. These transients can exceed the Absolute Maximum Ratings of the device if steps are not taken to
address the issue. Typical methods for addressing transients include:
• Use of a TVS diode and input capacitor filter combination across input to and GND to absorb the energy and
dampen the positive transients.
• Use of a diode or a TVS diode across the output and GND to absorb negative spikes.
The TPS1211-Q1 gets powered from the Vs pin. Voltage at this pin must be maintained above V(S_POR) level to
ensure proper operation. If the input power supply source is noisy with transients, then TI recommends to place
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a RVS-CVS filter between the input supply line and Vs pin to filter out the supply noise. TI recommends RVS value
around 100 Ω.
The following figure shows the circuit implementation with optional protection components.
Parasitic
inductance
Parasitic
inductance
Q1
RSNS
RSET
VBATT
VOUT
CBST
RISCP
RVS
ISCP CS+ CS-
VS
PU PD SRC BST
D2
D1
CVS
TPS1211x-Q1
GND
图9-16. Circuit Implementation with Optional Protection Components for TPS1211-Q1
9.5 Layout
9.5.1 Layout Guidelines
• The sense resistor (RSNS) must be placed close to the TPS1211x-Q1 and then connect RSNS using the Kelvin
techniques. Refer to Choosing the Right Sense Resistor Layout for more information on the Kelvin
techniques.
• For all the applications, TI recommends a 0.1 µF or higher value ceramic decoupling capacitor between VS
terminal and GND. Consider adding RC network at the supply pin (VS) of the controller to improve decoupling
against the power line disturbances.
• The high-current path from the board input to the load, and the return path, must be parallel and close to
each other to minimize loop inductance.
• The external MOSFETs must be placed close to the controller such that the GATE of the MOSFETs are close
to PU/PD pins to form short GATE loop. Consider adding a place holder for a resistor in series with the Gate
of each external MOSFET to damp high frequency oscillations if need arises.
• Place a TVS diode at the input to clamp the voltage transients during hot-plug and fast turn-off events.
• The external boot-strap capacitor must be placed close to BST and SRC pins to form very short loop.
• The ground connections for the various components around the TPS1211x-Q1 must be connected directly to
each other, and to the TPS1211x-Q1 GND, and then connected to the system ground at one point. Do not
connect the various component grounds to each other through the high current ground line.
• The DIODE pin sources current to measure the temperature. TI recommends BJT MMBT3904 to use as a
remote temperature sense element. Take care in the PCB layout to keep the parasitic resistance between the
DIODE pin and the MMBT3904 low so as not to degrade the measurement. In addition, TI recommends to
make a Kelvin connection from the emitter of the MMBT3904 to the GND of the part to ensure an accurate
measurement. Additionally, a small 1000=pF bypass capacitor must be placed in parallel with the MMBT3904
to reduce the effects of noise.
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9.5.2 Layout Example
Top Layer
Inner Layer GND plane
Inner Layer PGND plane
Via to GND plane
Via to PGND plane
B
RG2
C
Q3
E
G
S
S
S
S
S
S
G
D
RSNS
D
Q2
Q1
VIN
SRC
VOUT
RG1
RSET
CBST
RISCP
CSCP
* Optional
TPS12110-Q1
PGND
PGND
Inner Layer
GND plane
Inner Layer
PGND plane
GND
图9-17. Typical PCB Layout Example for TPS12110-Q1 with B2B MOSFETs
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10 Device and Documentation Support
10.1 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
10.2 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
10.3 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
10.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
10.5 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
11 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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11.1 Tape and Reel Information
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
Reel
Diameter
(mm)
Reel
Width W1
(mm)
Package
Type
Package
Drawing
A0
(mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
(mm)
Pin1
Quadrant
Device
Pins
SPQ
PTPS12110AQDGXRQ1 VSSOP
PTPS12111LQDGXRQ1 VSSOP
DGX
DGX
19
19
5000
5000
330
330
16.0
16.0
5.4
5.4
5.4
5.4
1.45
1.45
8
8
12
12
Q1
Q1
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TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
Device
Package Type
Package Drawing Pins
SPQ
5000
5000
Length (mm) Width (mm)
Height (mm)
PTPS12110AQDGXRQ1
PTPS12111LQDGXRQ1
VSSOP
VSSOP
DGX
DGX
19
19
853.0
853.0
449.0
449.0
35
35
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PACKAGE OUTLINE
DGX0019A
VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE
PIN 1 INDEX
AREA
C
SEATING
PLANE
5.1
4.7
TYP
0.1 C
A
18X 0.5
20
1
5.2
5.0
2X 4.5
NOTE 3
4X (0 -15 )
10
11
0.275
0.165
20X
3.1
2.9
B
0.1
C A B
SEE DETAIL A
4X (7 -15 )
(0.15) TYP
0.25
GAGE PLANE
1.1 MAX
0.7
0.4
0.15
0.05
0 -8
A
20
DETAIL A
TYPICAL
4226944/A 07/2021
PowerPAD is a trademark of Texas Instruments.
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. No JEDEC registration as of July 2021.
5. Features may differ or may not be present.
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EXAMPLE BOARD LAYOUT
DGX0019A
VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE
SYMM
20X (1.45)
20
1
20X (0.3)
(R0.05) TYP
18X (0.5)
SYMM
10
11
(4.4)
LAND PATTERN EXAMPLE
SCALE: 16X
METAL
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
SOLDER MASK
OPENING
EXPOSED METAL
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
EXPOSED METAL
SOLDER MASK
DEFINED
NON-SOLDER MASK
DEFINED
(PREFERRED)
15.000
SOLDER MASK DETAILS
4226944/A 07/2021
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
8. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
numbers SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004).
9. Size of metal pad may vary due to creepage requirement.
10. Vias are optional depending on application, refer to device data sheet. It is recommended that vias under paste be filled, plugged
or tented.
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TPS1211-Q1
ZHCSPB6A –JULY 2022 –REVISED SEPTEMBER 2022
www.ti.com.cn
EXAMPLE STENCIL DESIGN
DGX0019A
VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE
20X (1.45)
20X (0.3)
SYMM
1
20
(R0.05) TYP
SYMM
(18X 0.5)
11
10
(4.4)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 16X
4226944/A 07/2021
NOTES: (continued)
11. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
12. Board assembly site may have different recommendations for stencil design.
www.ti.com
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Product Folder Links: TPS1211-Q1
PACKAGE OPTION ADDENDUM
www.ti.com
14-Mar-2023
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS12110AQDGXRQ1
TPS12111LQDGXRQ1
ACTIVE
ACTIVE
VSSOP
VSSOP
DGX
DGX
19
19
5000 RoHS & Green
5000 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 125
-40 to 125
2ZAS
2Z9S
Samples
Samples
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
14-Mar-2023
Addendum-Page 2
PACKAGE OUTLINE
DGX0019A
VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE
PIN 1 INDEX
AREA
C
SEATING
PLANE
5.1
4.7
TYP
0.1 C
A
18X 0.5
20
1
5.2
5.0
2X 4.5
NOTE 3
4X (0 -15 )
10
11
0.275
0.165
20X
3.1
2.9
B
0.1
C A B
SEE DETAIL A
4X (7 -15 )
(0.15) TYP
0.25
GAGE PLANE
1.1 MAX
0.7
0.4
0.15
0.05
0 -8
A
20
DETAIL A
TYPICAL
4226944/A 07/2021
PowerPAD is a trademark of Texas Instruments.
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. No JEDEC registration as of July 2021.
5. Features may differ or may not be present.
www.ti.com
EXAMPLE BOARD LAYOUT
DGX0019A
VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE
SYMM
20X (1.45)
20
1
20X (0.3)
(R0.05) TYP
18X (0.5)
SYMM
10
11
(4.4)
LAND PATTERN EXAMPLE
SCALE: 16X
METAL
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
SOLDER MASK
OPENING
EXPOSED METAL
0.05 MAX
ALL AROUND
0.05 MIN
EXPOSED METAL
ALL AROUND
SOLDER MASK
DEFINED
NON-SOLDER MASK
DEFINED
(PREFERRED)
15.000
SOLDER MASK DETAILS
4226944/A 07/2021
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
8. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
numbers SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004).
9. Size of metal pad may vary due to creepage requirement.
10. Vias are optional depending on application, refer to device data sheet. It is recommended that vias under paste be filled, plugged
or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
DGX0019A
VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE
20X (1.45)
SYMM
20X (0.3)
1
20
(R0.05) TYP
SYMM
(18X 0.5)
11
10
(4.4)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 16X
4226944/A 07/2021
NOTES: (continued)
11. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
12. Board assembly site may have different recommendations for stencil design.
www.ti.com
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