TPS2021 [TI]
POWER-DISTRIBUTION SWITCHES; 配电开关
| 型号： | TPS2021 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | POWER-DISTRIBUTION SWITCHES |
| 文件： | 总23页 (文件大小：378K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPS2020, TPS2021, TPS2022, TPS2023, TPS2024
POWER-DISTRIBUTION SWITCHES
SLVS175A – DECEMBER 1998 – REVISED NOVEMBER 1999
33-mΩ (5-V Input) High-Side MOSFET
Switch
D OR P PACKAGE
(TOP VIEW)
Short-Circuit and Thermal Protection
Overcurrent Logic Output
GND
IN
OUT
OUT
OUT
OC
1
2
3
4
8
7
6
5
Operating Range . . . 2.7 V to 5.5 V
Logic-Level Enable Input
IN
EN
Typical Rise Time . . . 6.1 ms
Undervoltage Lockout
Maximum Standby Supply
Current . . . 10 µA
No Drain-Source Back-Gate Diode
Available in 8-pin SOIC and PDIP Packages
Ambient Temperature Range, –40°C to 85°C
2-kV Human-Body-Model, 200-V
Machine-Model ESD Protection
description
The TPS202x family of power distribution switches is intended for applications where heavy capacitive loads
and short circuits are likely to be encountered. These devices are 50-mΩ N-channel MOSFET high-side power
switches. The switch is controlled by a logic enable compatible with 5-V logic and 3-V logic. Gate drive is
provided by an internal charge pump designed to control the power-switch rise times and fall times to minimize
current surges during switching. The charge pump requires no external components and allows operation from
supplies as low as 2.7 V.
When the output load exceeds the current-limit threshold or a short is present, the TPS202x limits the output
current to a safe level by switching into a constant-current mode, pulling the overcurrent (OC) logic output low.
When continuous heavy overloads and short circuits increase the power dissipation in the switch, causing the
junction temperature to rise, a thermal protection circuit shuts off the switch to prevent damage. Recovery from
a thermal shutdown is automatic once the device has cooled sufficiently. Internal circuitry ensures the switch
remains off until valid input voltage is present.
The TPS202x devices differ only in short-circuit current threshold. The TPS2020 limits at 0.3-A load, the
TPS2021 at 0.9-A load, the TPS2022 at 1.5-A load, the TPS2023 at 2.2-A load, and the TPS2024 at 3-A load
(see Available Options). The TPS202x is available in an 8-pin small-outline integrated-circuit (SOIC) package
and in an 8-pin dual-in-line (DIP) package and operates over a junction temperature range of –40°C to 125°C.
GENERAL SWITCH CATALOG
33 mΩ, single
80 mΩ, single
80 mΩ, dual
80 mΩ, triple
80 mΩ, quad
TPS201xA 0.2 A – 2 A
TPS2042
TPS2052
TPS2046
TPS2056
500 mA
500 mA
250 mA
250 mA
TPS202x
0.2 A – 2 A
TPS203x
0.2 A – 2 A
260 mΩ
1.3 Ω
TPS2014
TPS2015
TPS2041
TPS2051
TPS2045
TPS2055
600 mA
1 A
500 mA
500 mA
250 mA
250 mA
TPS2100/1
IN1 500 mA
IN2 10 mA
TPS2043
500 mA
500 mA
250 mA
250 mA
TPS2044
500 mA
500 mA
250 mA
250 mA
IN1
IN2
TPS2053
TPS2047
TPS2057
TPS2054
TPS2048
TPS2058
OUT
TPS2102/3/4/5
IN1 500 mA
IN2 100 mA
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 1999, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS2020, TPS2021, TPS2022, TPS2023, TPS2024
POWER-DISTRIBUTION SWITCHES
SLVS175A – DECEMBER 1998 – REVISED NOVEMBER 1999
AVAILABLE OPTIONS
RECOMMENDED
MAXIMUM CONTINUOUS
LOAD CURRENT
(A)
PACKAGED DEVICES
SMALL OUTLINE PLASTIC DIP
TYPICAL SHORT-CIRCUIT
CURRENT LIMIT AT 25°C
(A)
T
A
ENABLE
†
(D)
(P)
0.2
0.6
1
0.3
0.9
1.5
2.2
3
TPS2020D
TPS2021D
TPS2022D
TPS2023D
TPS2024D
TPS2020P
TPS2021P
TPS2022P
TPS2023P
TPS2024P
–40°C to 85°C Active low
1.5
2
†
The D package is available taped and reeled. Add an R suffix to device type (e.g., TPS2020DR)
TPS2020 functional block diagram
Power Switch
†
CS
IN
OUT
Charge
Pump
Current
Limit
EN
Driver
OC
UVLO
Thermal
Sense
GND
†
Current Sense
Terminal Functions
TERMINAL
I/O
DESCRIPTION
NO.
D OR P
NAME
EN
4
1
I
I
Enable input. Logic low turns on power switch.
GND
IN
Ground
2, 3
5
I
Input voltage
OC
OUT
O
O
Overcurrent. Logic output active low
Power-switch output
6, 7, 8
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS2020, TPS2021, TPS2022, TPS2023, TPS2024
POWER-DISTRIBUTION SWITCHES
SLVS175A – DECEMBER 1998 – REVISED NOVEMBER 1999
detailed description
power switch
The power switch is an N-channel MOSFET with a maximum on-state resistance of 50 mΩ (V
= 5 V).
I(IN)
Configured as a high-side switch, the power switch prevents current flow from OUT to IN and IN to OUT when
disabled.
charge pump
An internal charge pump supplies power to the driver circuit and provides the necessary voltage to pull the gate
of the MOSFET above the source. The charge pump operates from input voltages as low as 2.7 V and requires
very little supply current.
driver
The driver controls the gate voltage of the power switch. To limit large current surges and reduce the associated
electromagnetic interference (EMI) produced, the driver incorporates circuitry that controls the rise times and
fall times of the output voltage. The rise and fall times are typically in the 2-ms to 9-ms range.
enable (EN)
The logic enable disables the power switch, the bias for the charge pump, driver, and other circuitry to reduce
the supply current to less than 10 µA when a logic high is present on EN . A logic zero input on EN restores bias
to the drive and control circuits and turns the power on. The enable input is compatible with both TTL and CMOS
logic levels.
overcurrent (OC)
The OC open drain output is asserted (active low) when an overcurrent or overtemperature condition is
encountered. The output will remain asserted until the overcurrent or overtemperature condition is removed.
current sense
A sense FET monitors the current supplied to the load. The sense FET measures current more efficiently than
conventional resistance methods. When an overload or short circuit is encountered, the current-sense circuitry
sends a control signal to the driver. The driver, in turn, reduces the gate voltage and drives the power FET into
its saturation region, which switches the output into a constant current mode and holds the current constant
while varying the voltage on the load.
thermal sense
An internal thermal-sense circuit shuts off the power switch when the junction temperature rises to
approximately 140°C. Hysteresis is built into the thermal sense circuit. After the device has cooled
approximately 20°C, the switch turns back on. The switch continues to cycle off and on until the fault is removed.
undervoltage lockout
A voltage sense circuit monitors the input voltage. When the input voltage is below approximately 2 V, a control
signal turns off the power switch.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS2020, TPS2021, TPS2022, TPS2023, TPS2024
POWER-DISTRIBUTION SWITCHES
SLVS175A – DECEMBER 1998 – REVISED NOVEMBER 1999
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Input voltage range, V
Output voltage range, V
Input voltage range, V
Continuous output current, I
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 6 V
I(IN)
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 6 V
+ 0.3 V
O(OUT)
I(EN)
I(IN)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . internally limited
O(OUT)
Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table
Operating virtual junction temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 125°C
J
Storage temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
Lead temperature soldering 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . 260°C
Electrostatic discharge (ESD) protection: Human body model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 kV
Machine model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200V
Charged device model (CDM) . . . . . . . . . . . . . . . . . . . . . . . . . 750 V
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltages are with respect to GND.
DISSIPATION RATING TABLE
DERATING FACTOR
T
≤ 25°C
T
A
= 70°C
T = 85°C
A
A
PACKAGE
POWER RATING
ABOVE T = 25°C
POWER RATING POWER RATING
A
D
P
725 mW
5.8 mW/°C
9.4 mW/°C
464 mW
752 mW
377 mW
611 mW
1175 mW
recommended operating conditions
MIN
2.7
0
MAX
5.5
5.5
0.2
0.6
1
UNIT
V
V
V
I(IN)
Input voltage
V
I(EN)
TPS2020
TPS2021
TPS2022
TPS2023
TPS2024
0
0
Continuous output current, I
0
A
O
0
1.5
2
0
Operating virtual junction temperature, T
–40
125
°C
J
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS2020, TPS2021, TPS2022, TPS2023, TPS2024
POWER-DISTRIBUTION SWITCHES
SLVS175A – DECEMBER 1998 – REVISED NOVEMBER 1999
electrical characteristics over recommended operating junction temperature range, V
= 5.5 V,
I(IN)
I = rated current, EN = 0 V (unless otherwise noted)
O
power switch
†
PARAMETER
MIN
TYP
33
38
44
37
43
51
30
35
39
33
39
44
MAX
36
46
50
41
52
61
34
41
47
37
46
56
UNIT
TEST CONDITIONS
T = 25°C,
V
V
V
V
V
V
V
V
V
V
V
V
V
= 5 V,
= 5 V,
= 5 V,
I
O
I
O
I
O
I
O
I
O
I
O
I
O
I
O
I
O
I
O
I
O
I
O
= 1.8 A
= 1.8 A
= 1.8 A
= 1.8 A
= 1.8 A
= 1.8 A
= 0.18 A
= 0.18 A
= 0.18 A
= 0.18 A
= 0.18 A
= 0.18 A
I(IN)
I(IN)
I(IN)
I(IN)
I(IN)
I(IN)
I(IN)
I(IN)
I(IN)
I(IN)
I(IN)
I(IN)
I(IN)
J
T = 85°C,
J
T = 125°C,
J
= 3.3 V, T = 25°C,
J
= 3.3 V, T = 85°C,
J
= 3.3 V, T = 125°C,
J
r
Static drain-source on-state resistance
mΩ
DS(on)
= 5 V,
= 5 V,
= 5 V,
T = 25°C,
J
T = 85°C,
J
T = 125°C,
J
= 3.3 V, T = 25°C,
J
= 3.3 V, T = 85°C,
J
= 3.3 V, T = 125°C,
J
= 5.5 V, T = 25°C,
J
6.1
8.6
3.4
3
C
= 1 µF,
R = 10 Ω
L
L
t
t
Rise time, output
Fall time, output
ms
ms
r
V
C
= 2.7 V, T = 25°C,
J
I(IN)
= 1 µF,
R = 10 Ω
L
L
V
C
= 5.5 V, T = 25°C,
J
I(IN)
= 1 µF,
R = 10 Ω
L
L
f
V
C
= 2.7 V, T = 25°C,
J
I(IN)
= 1 µF,
R = 10 Ω
L
L
†
Pulse-testing techniques maintain junction temperature close to ambient temperature; thermal effects must be taken into account separately.
enable input (EN)
PARAMETER
TEST CONDITIONS
MIN TYP
MAX
UNIT
V
V
High-level input voltage
2.7 V ≤ V
4.5 V ≤ V
2.7 V ≤ V
≤ 5.5 V
≤ 5.5 V
≤ 4.5 V
2
V
IH
IL
I
I(IN)
I(IN)
I(IN)
0.8
0.5
0.5
Low-level input voltage
Input current
V
I
EN= 0 V or EN = V
–0.5
µA
ms
I(IN)
t
t
Turnon time
Turnoff time
C
C
= 100 µF,
= 100 µF,
R
R
= 10 Ω
= 10 Ω
20
40
on
L
L
L
L
off
current limit
†
PARAMETER
TEST CONDITIONS
MIN TYP
MAX
0.4
1.1
1.8
2.7
3.8
UNIT
TPS2020
TPS2021
TPS2022
TPS2023
TPS2024
0.22
0.66
1.1
0.3
0.9
1.5
2.2
3
T = 25°C, V = 5.5 V,
OUT connected to GND,
Device enable into short circuit
J
I
I
Short-circuit output current
A
OS
1.65
2.2
†
Pulse-testing techniques maintain junction temperature close to ambient temperature; thermal effects must be taken into account separately.
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS2020, TPS2021, TPS2022, TPS2023, TPS2024
POWER-DISTRIBUTION SWITCHES
SLVS175A – DECEMBER 1998 – REVISED NOVEMBER 1999
electrical characteristics over recommended operating junction temperature range, V
= 5.5 V,
I(IN)
I = rated current, EN = 0 V (unless otherwise noted) (continued)
O
supply current
PARAMETER
TEST CONDITIONS
MIN
TYP MAX UNIT
T = 25°C
0.3
1
10
J
Supply current, low-level output
No Load on OUT
No Load on OUT
µA
EN = V
I(IN)
–40°C ≤ T ≤ 125°C
J
T = 25°C
J
58
75
10
75
Supply current, high-level output
µA
µA
EN = 0 V
–40°C ≤ T ≤ 125°C
100
J
Leakage current
OUT connected to ground EN = V
–40°C ≤ T ≤ 125°C
J
I(IN)
undervoltage lockout
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
V
Low-level input voltage
Hysteresis
2
2.5
T = 25°C
J
100
mV
overcurrent (OC)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
0.4
1
UNIT
V
Output low voltage
I
= 10 mA,
V
O
OL(OC)
= 3.3 V
O
†
Off-state current
†
V
= 5 V,
V
µA
O
Specified by design, not production tested.
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS2020, TPS2021, TPS2022, TPS2023, TPS2024
POWER-DISTRIBUTION SWITCHES
SLVS175A – DECEMBER 1998 – REVISED NOVEMBER 1999
PARAMETER MEASUREMENT INFORMATION
OUT
t
t
f
r
RL
CL
V
90%
10%
O(OUT)
90%
10%
TEST CIRCUIT
50%
90%
50%
V
I(EN)
t
t
off
on
V
O(OUT)
10%
VOLTAGE WAVEFORMS
Figure 1. Test Circuit and Voltage Waveforms
Table of Timing Diagrams
FIGURE
Turnon Delay and Rise TIme
Turnoff Delay and Fall Time
2
3
4
5
6
Turnon Delay and Rise TIme with 1-µF Load
Turnoff Delay and Rise TIme with 1-µF Load
Device Enabled into Short
7, 8, 9,
10, 11
TPS2020, TPS2021, TPS2022, TPS2023, and TPS2024, Ramped Load on Enabled Device
TPS2024, Inrush Current
12
13
14
15
16
17
18
19
20
21
22
7.9-Ω Load Connected to an Enabled TPS2020 Device
3.7-Ω Load Connected to an Enabled TPS2020 Device
3.7-Ω Load Connected to an Enabled TPS2021 Device
2.6-Ω Load Connected to an Enabled TPS2021 Device
2.6-Ω Load Connected to an Enabled TPS2022 Device
1.2-Ω Load Connected to an Enabled TPS2022 Device
1.2-Ω Load Connected to an Enabled TPS2023 Device
0.9-Ω Load Connected to an Enabled TPS2023 Device
0.9-Ω Load Connected to an Enabled TPS2024 Device
0.5-Ω Load Connected to an Enabled TPS2024 Device
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS2020, TPS2021, TPS2022, TPS2023, TPS2024
POWER-DISTRIBUTION SWITCHES
SLVS175A – DECEMBER 1998 – REVISED NOVEMBER 1999
PARAMETER MEASUREMENT INFORMATION
V
I(EN)
(5 V/div)
V
I(EN)
(5 V/div)
V
I(EN)
V
I(EN)
V
R
T
A
= 5 V
I(IN)
= 27 Ω
L
= 25°C
V
(2 V/div)
V
(2 V/div)
O(OUT)
O(OUT)
V
R
T
A
= 5 V
= 27 Ω
= 25°C
IN
L
V
V
O(OUT)
O(OUT)
0
2
4
6
8
10 12 14 16 18 20
0
2
4
6
8
10 12 14 16 18
20
t – Time – ms
t – Time – ms
Figure 2. Turnon Delay and Rise Time
Figure 3. Turnoff Delay and Fall Time
V
I(EN)
(5 V/div)
V
I(EN)
(5 V/div)
V
I(EN)
V
I(EN)
V
(2 V/div)
O(OUT)
V
(2 V/div)
O(OUT)
V
C
R
= 5 V
= 1 µF
= 27 Ω
= 25°C
I(IN)
L
L
V
C
R
= 5 V
= 1 µF
= 27 Ω
= 25°C
I(IN)
L
L
V
V
O(OUT)
O(OUT)
T
A
T
A
0
2
4
6
8
10 12 14 16 18
20
0
2
4
6
8
10 12 14 16 18
20
t – Time – ms
t – Time – ms
Figure 5. Turnoff Delay and Fall Time
Figure 4. Turnon Delay and Rise Time
With 1-µF Load
With 1-µF Load
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS2020, TPS2021, TPS2022, TPS2023, TPS2024
POWER-DISTRIBUTION SWITCHES
SLVS175A – DECEMBER 1998 – REVISED NOVEMBER 1999
PARAMETER MEASUREMENT INFORMATION
V
(5 V/div)
O(OC)
V
I(EN)
V
I(EN)
(5 V/div)
V
O(OC)
V
T
A
= 5 V
= 25°C
I(IN)
V
T
A
= 5 V
= 25°C
I(IN)
TPS2024
TPS2023
TPS2022
I
(500 mA/div)
O(OUT)
TPS2021
TPS2020
I
O(OUT)
I
O(OUT)
I
(1 A/div)
3
O(OUT)
0
20 40 60 80 100 120 140 160 180 200
t – Time – ms
0
1
2
4
5
6
7
8
9
10
t – Time – ms
Figure 7. TPS2020, Ramped Load on
Enabled Device
Figure 6. Device Enabled Into Short
V
(5 V/div)
O(OC)
V
(5 V/div)
O(OC)
V
V
O(OC)
O(OC)
V
T
A
= 5 V
I(IN)
= 25°C
V
T
A
= 5 V
I(IN)
= 25°C
I
(1 A/div)
O(OUT)
I
(1 A/div)
O(OUT)
I
I
O(OUT)
O(OUT)
0
20 40 60 80 100 120 140 160 180 200
t – Time – ms
0
20 40 60 80 100 120 140 160 180 200
t – Time – ms
Figure 8. TPS2021, Ramped Load on Enabled
Device
Figure 9. TPS2022, Ramped Load on
Enabled Device
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS2020, TPS2021, TPS2022, TPS2023, TPS2024
POWER-DISTRIBUTION SWITCHES
SLVS175A – DECEMBER 1998 – REVISED NOVEMBER 1999
PARAMETER MEASUREMENT INFORMATION
V
(5 V/div)
O(OC)
V
(5 V/div)
O(OC)
V
V
O(OC)
O(OC)
V
= 5 V
I(IN)
T = 25°C
A
V
T
A
= 5 V
I(IN)
= 25°C
I
(1 A/div)
I
(1 A/div)
O(OUT)
O(OUT)
I
I
O(OUT)
O(OUT)
0
20 40 60 80 100 120 140 160 180 200
t – Time – ms
0
20 40 60 80 100 120 140 160 180 200
t – Time – ms
Figure 10. TPS2023, Ramped Load on
Enabled Device
Figure 11. TPS2024, Ramped Load on Enabled
Device
V
I(EN)
V
(5 V/div)
O(OC)
V
I(EN)
(5 V/div)
V
O(OC)
I
(200 mA/div)
O(OUT)
470 µF
150 µF
I
(500 mA/div)
I(IN)
V
R
T
A
= 5 V
= 7.9 Ω
= 25°C
I(IN)
L
I
I
O(OUT)
I(IN)
R
= 10 Ω
T = 25°C
A
L
47 µF
0
200 400 600 800 1000 1200 1400 1600 1800 2000
0
1
2
3
4
5
6
7
8
9
10
t – Time – µs
t – Time – ms
Figure 13. 7.9-Ω Load Connected to an Enabled
Figure 12. TPS2024, Inrush Current
TPS2020 Device
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS2020, TPS2021, TPS2022, TPS2023, TPS2024
POWER-DISTRIBUTION SWITCHES
SLVS175A – DECEMBER 1998 – REVISED NOVEMBER 1999
PARAMETER MEASUREMENT INFORMATION
V
(5 V/div)
V
(5 V/div)
O(OC)
O(OC)
V
V
O(OC)
O(OC)
V
= 5 V
= 3.7 Ω
= 25°C
V
= 5 V
= 3.7 Ω
= 25°C
I(IN)
L
I(IN)
L
R
T
R
T
A
A
I
(500 mA/div)
O(OUT)
I
(1 A/div)
O(OUT)
I
I
O(OUT)
O(OUT)
0
50 100 150 200 250 300 350 400 450 500
0
200 400 600 800 1000 1200 1400 1600 1800 2000
t – Time – µs
t – Time – µs
Figure 14. 3.7-Ω Load Connected to an Enabled
Figure 15. 3.7-Ω Load Connected to an Enabled
TPS2020 Device
TPS2021 Device
V
O(OC)
V
(5 V/div)
O(OC)
V
(5 V/div)
O(OC)
V
O(OC)
V
= 5 V
= 2.6 Ω
= 25°C
V
= 5 V
= 2.6 Ω
= 25°C
I(IN)
L
I(IN)
L
R
T
R
T
A
A
I
(1 A/div)
I
(1 A/div)
O(OUT)
O(OUT)
I
I
O(OUT)
O(OUT)
0
50 100 150 200 250 300 350 400 450 500
0
200 400 600 800 1000 1200 1400 1600 1800 2000
t – Time – µs
t – Time – µs
Figure 16. 2.6-Ω Load Connected to an Enabled
Figure 17. 2.6-Ω Load Connected to an Enabled
TPS2021 Device
TPS2022 Device
11
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POWER-DISTRIBUTION SWITCHES
SLVS175A – DECEMBER 1998 – REVISED NOVEMBER 1999
PARAMETER MEASUREMENT INFORMATION
V
(5 V/div)
O(OC)
V
(5 V/div)
O(OC)
V
V
O(OC)
O(OC)
V
R
T
A
= 5 V
= 1.2 Ω
= 25°C
I(IN)
L
I
(1 A/div)
O(OUT)
I
(2 A/div)
O(OUT)
V
R
T
A
= 5 V
= 1.2 Ω
= 25°C
I(IN)
L
I
I
O(OUT)
O(OUT)
0
100 200 300 400 500 600 700 800 900 1000
0
100 200 300 400 500 600 700 800 900 1000
t – Time – µs
t – Time – µs
Figure 18. 1.2-Ω Load Connected to an Enabled
Figure 19. 1.2-Ω Load Connected to an Enabled
TPS2022 Device
TPS2023 Device
V
(5 V/div)
V
(5 V/div)
O(OC)
O(OC)
V
V
O(OC)
O(OC)
V
= 5 V
= 0.9 Ω
= 25°C
V
= 5 V
= 0.9 Ω
= 25°C
I(IN)
L
I(IN)
L
R
T
R
T
A
A
I
(2 A/div)
O(OUT)
I
(5 A/div)
O(OUT)
I
I
O(OUT)
O(OUT)
0
100 200 300 400 500 600 700 800 900 1000
0
100 200 300 400 500 600 700 800 900 1000
t – Time – µs
t – Time – µs
Figure 21. 0.9-Ω Load Connected to an Enabled
Figure 20. 0.9-Ω Load Connected to an Enabled
TPS2024 Device
TPS2023 Device
12
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POWER-DISTRIBUTION SWITCHES
SLVS175A – DECEMBER 1998 – REVISED NOVEMBER 1999
PARAMETER MEASUREMENT INFORMATION
V
(5 V/div)
O(OC)
V
O(OC)
V
R
T
A
= 5 V
= 0.5 Ω
= 25°C
I(IN)
L
I
O(OUT)
(5 A/div)
I
O(OUT)
0
50 100 150 200 250 300 350 400 450 500
t – Time – µs
Figure 22. 0.5-Ω Load Connected to an Enabled
TPS2024 Device
TYPICAL CHARACTERISTICS
Table of Graphs
FIGURE
23
t
t
t
t
Turnon delay time
Turnoff delay time
Rise time
vs Output voltage
vs Input voltage
d(on)
24
d(off)
vs Load current
25
r
f
Fall time
vs Load current
26
Supply current (enabled)
Supply current (disabled)
Supply current (enabled)
Supply current (disabled)
vs Junction temperature
vs Junction temperature
vs Input voltage
27
28
29
vs Input voltage
30
vs Input voltage
31
I
Short-circuit current limit
OS
vs Junction temperature
vs Input voltage
32
33
vs Junction temperature
vs Input voltage
34
r
Static drain-source on-state resistance
Input voltage
DS(on)
35
vs Junction temperature
Undervoltage lockout
36
V
37
I
13
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POWER-DISTRIBUTION SWITCHES
SLVS175A – DECEMBER 1998 – REVISED NOVEMBER 1999
TYPICAL CHARACTERISTICS
TURNON DELAY TIME
vs
OUTPUT VOLTAGE
TURNOFF DELAY TIME
vs
INPUT VOLTAGE
7.5
7
18
T
C
= 25°C
= 1 µF
A
L
T
C
= 25°C
= 1 µF
A
L
6.5
6
17.5
17
5.5
5
4.5
16.5
16
4
3.5
2.5
3
3.5
4
4.5
5
5.5
6
2.5
3
3.5
4
4.5
5
5.5
6
V – Input Voltage – V
I
V – Input Voltage – V
I
Figure 23
Figure 24
RISE TIME
vs
LOAD CURRENT
FALL TIME
vs
LOAD CURRENT
6.5
3.5
T
C
= 25°C
= 1 µF
A
L
T
C
= 25°C
= 1 µF
A
L
3.25
3
6
5.5
2.75
2.5
5
0
0.5
1
1.5
2
0
0.5
1
I – Load Current – A
L
1.5
2
I
L
– Load Current – A
Figure 25
Figure 26
14
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POWER-DISTRIBUTION SWITCHES
SLVS175A – DECEMBER 1998 – REVISED NOVEMBER 1999
TYPICAL CHARACTERISTICS
SUPPLY CURRENT (ENABLED)
vs
JUNCTION TEMPERATURE
SUPPLY CURRENT (DISABLED)
vs
JUNCTION TEMPERATURE
75
65
5
4
3
2
V
= 5.5 V
I(IN)
V
= 5 V
I(IN)
V
= 5.5 V
= 5 V
I(IN)
V
I(IN)
55
1
V
= 4 V
I(IN)
= 3.3 V
V
= 4 V
= 3.3 V
45
35
I(IN)
V
I(IN)
V
I(IN)
= 2.7 V
0
V
= 2.7 V
I(IN)
V
I(IN)
–1
–50 –25
0
25
50
75
100 125 150
–50 –25
0
25
50
75
100 125 150
T
J
– Junction Temperature – °C
T
J
– Junction Temperature – °C
Figure 27
Figure 28
SUPPLY CURRENT (ENABLED)
SUPPLY CURRENT (DISABLED)
vs
vs
INPUT VOLTAGE
INPUT VOLTAGE
75
65
5
4
3
2
T
= 125°C
J
T
J
= 125°C
T
J
= 85°C
T
J
= 85°C
55
1
T
= 25°C
= 0°C
J
45
35
T
= 25°C
J
0
T
= 0°C
J
T
J
T
= –40°C
J
T
= –40°C
J
–1
2.5
3
3.5
4
4.5
5
5.5
6
2.5
3
3.5
4
4.5
5
5.5
6
V – Input Voltage – V
I
V – Input Voltage – V
I
Figure 29
Figure 30
15
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POWER-DISTRIBUTION SWITCHES
SLVS175A – DECEMBER 1998 – REVISED NOVEMBER 1999
TYPICAL CHARACTERISTICS
SHORT-CIRCUIT CURRENT LIMIT
SHORT-CIRCUIT CURRENT LIMIT
vs
vs
INPUT VOLTAGE
JUNCTION TEMPERATURE
3.5
3.5
T
A
= 25°C
TPS2024
TPS2024
3
3
2.5
2.5
TPS2023
TPS2022
TPS2023
TPS2022
2
1.5
1
2
1.5
1
TPS2021
TPS2020
TPS2021
TPS2020
0.5
0
0.5
0
–50
–25
0
25
50
75
100
2
3
4
5
6
T
J
– Junction Temperature – °C
V – Input Voltage – V
I
Figure 31
Figure 32
STATIC DRAIN-SOURCE ON-STATE RESISTANCE
vs
STATIC DRAIN-SOURCE ON-STATE RESISTANCE
vs
INPUT VOLTAGE
60
JUNCTION TEMPERATURE
60
I
O
= 0.18 A
I
O
= 0.18 A
50
40
50
40
T
J
= 125°C
V = 2.7 V
I
V = 3.3 V
I
T
J
= 25°C
30
20
30
20
V = 5.5 V
I
T
= –40°C
J
2.5
3
3.5
4
4.5
5
5.5
6
–50 –25
0
25
50
75 100 125 150
V – Input Voltage – V
I
T
J
– Junction Temperature – °C
Figure 33
Figure 34
16
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POWER-DISTRIBUTION SWITCHES
SLVS175A – DECEMBER 1998 – REVISED NOVEMBER 1999
TYPICAL CHARACTERISTICS
STATIC DRAIN-SOURCE ON-STATE RESISTANCE
vs
STATIC DRAIN-SOURCE ON-STATE RESISTANCE
vs
JUNCTION TEMPERATURE
60
INPUT VOLTAGE
60
I
O
= 1.8 A
I
O
= 1.8 A
50
40
50
40
T
J
= 125°C
V = 3.3 V
I
V = 4 V
I
V = 5.5 V
I
T
J
= 25°C
T
J
= –40°C
30
20
30
20
3
3.5
4
4.5
5
5.5
6
–50 –25
0
25
50
75 100 125 150
V – Input Voltage – V
I
T
J
– Junction Temperature – °C
Figure 35
Figure 36
UNDERVOLTAGE LOCKOUT
2.5
2.4
2.3
Start Threshold
Stop Threshold
2.2
2.1
2
–50
0
50
100
150
T
J
– Temperature – °C
Figure 37
17
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POWER-DISTRIBUTION SWITCHES
SLVS175A – DECEMBER 1998 – REVISED NOVEMBER 1999
APPLICATION INFORMATION
TPS2024
2,3
0.1 µF
Power Supply
2.7 V to 5.5 V
IN
6,7,8
Load
OUT
10 kΩ
0.1 µF
22 µF
5
4
OC
EN
GND
1
Figure 38. Typical Application
power-supply considerations
A 0.01-µF to 0.1-µF ceramic bypass capacitor between IN and GND, close to the device, is recommended.
Placing a high-value electrolytic capacitor on the output and input pins is recommended when the output load
is heavy. This precaution reduces power supply transients that may cause ringing on the input. Additionally,
bypassing the output with a 0.01-µF to 0.1-µF ceramic capacitor improves the immunity of the device to
short-circuit transients.
overcurrent
A sense FET checks for overcurrent conditions. Unlike current-sense resistors, sense FETs do not increase the
series resistance of the current path. When an overcurrent condition is detected, the device maintains a
constant output current and reduces the output voltage accordingly. Complete shutdown occurs only if the fault
is present long enough to activate thermal limiting.
Three possible overload conditions can occur. In the first condition, the output has been shorted before the
device is enabled or before V
immediately switches into a constant-current output.
has been applied (see Figure 6). The TPS202x senses the short and
I(IN)
In the second condition, the excessive load occurs while the device is enabled. At the instant the excessive load
occurs, very high currents may flow for a short time before the current-limit circuit can react (see Figures 13–22).
After the current-limit circuit has tripped (reached the overcurrent trip threshhold) the device switches into
constant-current mode.
In the third condition, the load has been gradually increased beyond the recommended operating current. The
current is permitted to rise until the current-limit threshold is reached or until the thermal limit of the device is
exceeded (see Figures 7–11). The TPS202x is capable of delivering current up to the current-limit threshold
without damaging the device. Once the threshold has been reached, the device switches into its
constant-current mode.
OC response
The OC open-drain output is asserted (active low) when an overcurrent or overtemperature condition is
encountered. The output will remain asserted until the overcurrent or overtemperature condition is removed.
Connectingaheavycapacitiveloadtoanenableddevicecancausemomentaryfalseovercurrentreportingfrom
theinrushcurrentflowingthroughthedevice, chargingthedownstreamcapacitor. AnRCfiltercanbeconnected
to the OC pin to reduce false overcurrent reporting. Using low-ESR electrolytic capacitors on the output lowers
the inrush current flow through the device during hot-plug events by providing a low impedance energy source,
thereby reducing erroneous overcurrent reporting.
18
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POWER-DISTRIBUTION SWITCHES
SLVS175A – DECEMBER 1998 – REVISED NOVEMBER 1999
APPLICATION INFORMATION
TPS202x
GND
TPS202x
GND
V+
V+
OUT
OUT
OUT
OC
OUT
OUT
OUT
OC
R
pullup
IN
IN
R
pullup
IN
IN
R
filter
EN
EN
C
filter
Figure 39. Typical Circuit for OC Pin and RC Filter for Damping Inrush OC Responses
power dissipation and junction temperature
The low on-resistance on the n-channel MOSFET allows small surface-mount packages, such as SOIC, to pass
large currents. The thermal resistances of these packages are high compared to those of power packages; it
is good design practice to check power dissipation and junction temperature. The first step is to find r
the input voltage and operating temperature. As an initial estimate, use the highest operating ambient
at
DS(on)
temperature of interest and read r
from Figures 33–36. Next, calculate the power dissipation using:
DS(on)
2
P
r
I
D
DS(on)
Finally, calculate the junction temperature:
T
P
R
T
J
D
JA
A
Where:
T = Ambient Temperature °C
A
θJA
R
= Thermal resistance SOIC = 172°C/W, PDIP = 106°C/W
Compare the calculated junction temperature with the initial estimate. If they do not agree within a few degrees,
repeat the calculation, using the calculated value as the new estimate. Two or three iterations are generally
sufficient to get an acceptable answer.
thermal protection
Thermal protection prevents damage to the IC when heavy-overload or short-circuit faults are present for
extended periods of time. The faults force the TPS202x into constant current mode, which causes the voltage
across the high-side switch to increase; under short-circuit conditions, the voltage across the switch is equal
to the input voltage. The increased dissipation causes the junction temperature to rise to high levels. The
protectioncircuitsensesthejunctiontemperatureoftheswitchandshutsitoff. Hysteresisisbuiltintothethermal
sense circuit, and after the device has cooled approximately 20 degrees, the switch turns back on. The switch
continues to cycle in this manner until the load fault or input power is removed.
undervoltage lockout (UVLO)
An undervoltage lockout ensures that the power switch is in the off state at powerup. Whenever the input voltage
falls below approximately 2 V, the power switch will be quickly turned off. This facilitates the design of
hot-insertion systems where it is not possible to turn off the power switch before input power is removed. The
UVLO will also keep the switch from being turned on until the power supply has reached at least 2 V, even if
the switch is enabled. Upon reinsertion, the power switch will be turned on, with a controlled rise time to reduce
EMI and voltage overshoots.
19
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POWER-DISTRIBUTION SWITCHES
SLVS175A – DECEMBER 1998 – REVISED NOVEMBER 1999
APPLICATION INFORMATION
generic hot-plug applications (see Figure 40)
In many applications it may be necessary to remove modules or pc boards while the main unit is still operating.
These are considered hot-plug applications. Such implementations require the control of current surges seen
by the main power supply and the card being inserted. The most effective way to control these surges is to limit
and slowly ramp the current and voltage being applied to the card, similar to the way in which a power supply
normally turns on. Because of the controlled rise times and fall times of the TPS202x series, these devices can
be used to provide a softer start-up to devices being hot-plugged into a powered system. The UVLO feature
of the TPS202x also ensures the switch will be off after the card has been removed, and the switch will be off
during the next insertion. The UVLO feature guarantees a soft start with a controlled rise time for every insertion
of the card or module.
PC Board
TPS2024
Power
Supply
Block of
Circuitry
GND
OUT
OUT
OUT
OC
IN
2.7 V to 5.5 V
0.1 µF
1000 µF
Optimum
IN
EN
Overcurrent Response
Figure 40. Typical Hot-Plug Implementation
By placing the TPS202x between the V input and the rest of the circuitry, the input power will reach this device
CC
first after insertion. The typical rise time of the switch is approximately 9 ms, providing a slow voltage ramp at
the output of the device. This implementation controls system surge currents and provides a hot-plugging
mechanism for any device.
20
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POWER-DISTRIBUTION SWITCHES
SLVS175A – DECEMBER 1998 – REVISED NOVEMBER 1999
MECHANICAL DATA
D (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PIN SHOWN
0.050 (1,27)
0.020 (0,51)
0.014 (0,35)
0.010 (0,25)
M
14
8
0.008 (0,20) NOM
0.244 (6,20)
0.228 (5,80)
0.157 (4,00)
0.150 (3,81)
Gage Plane
0.010 (0,25)
1
7
0°–8°
0.044 (1,12)
A
0.016 (0,40)
Seating Plane
0.004 (0,10)
0.010 (0,25)
0.004 (0,10)
0.069 (1,75) MAX
PINS **
8
14
16
DIM
0.197
(5,00)
0.344
(8,75)
0.394
(10,00)
A MAX
0.189
(4,80)
0.337
(8,55)
0.386
(9,80)
A MIN
4040047/D 10/96
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15).
D. Falls within JEDEC MS-012
21
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POWER-DISTRIBUTION SWITCHES
SLVS175A – DECEMBER 1998 – REVISED NOVEMBER 1999
MECHANICAL DATA
P (R-PDIP-T8)
PLASTIC DUAL-IN-LINE PACKAGE
0.400 (10,60)
0.355 (9,02)
8
5
0.260 (6,60)
0.240 (6,10)
1
4
0.070 (1,78) MAX
0.310 (7,87)
0.290 (7,37)
0.020 (0,51) MIN
0.200 (5,08) MAX
Seating Plane
0.125 (3,18) MIN
0.100 (2,54)
0°–15°
0.021 (0,53)
0.015 (0,38)
0.010 (0,25)
M
0.010 (0,25) NOM
4040082/B 03/95
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-001
22
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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Copyright 1999, Texas Instruments Incorporated
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