TPS2041CDBVT [TI]

低电平有效且具有输出放电和反向阻断功能的 0.5A 负载 4.5-5.5V、97mΩ USB 电源开关 | DBV | 5 | -40 to 125;


型号：	TPS2041CDBVT
厂家：	TEXAS INSTRUMENTS
描述：	低电平有效且具有输出放电和反向阻断功能的 0.5A 负载 4.5-5.5V、97mΩ USB 电源开关 \| DBV \| 5 \| -40 to 125 开关电源开关光电二极管输出元件电源管理电路电源电路
文件：	总32页 (文件大小：1549K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TPS20xxC, TPS20xxC-2

www.ti.com

SLVSAU6G –JUNE 2011–REVISED JULY 2013

Current-Limited, Power-Distribution Switches

FEATURES

DESCRIPTION

The TPS20xxC and TPS20xxC-2 power-distribution

switch family is intended for applications such as

USB where heavy capacitive loads and short-circuits

are likely to be encountered. This family offers

multiple devices with fixed current-limit thresholds for

applications between 0.5 A and 2 A.

•

Single Power Switch Family

Pin for Pin with Existing TI Switch Portfolio

Rated currents of 0.5 A, 1 A, 1.5 A, 2 A

±20% Accurate, Fixed, Constant Current Limit

Fast Over-Current Response – 2 µs

Deglitched Fault Reporting

The TPS20xxC and TPS20xxC-2 family limits the

output current to a safe level by operating in a

constant-current mode when the output load exceeds

the current-limit threshold. This provides a predictable

fault current under all conditions. The fast overload

response time eases the burden on the main 5 V

supply to provide regulated power when the output is

shorted. The power-switch rise and fall times are

controlled to minimize current surges during turn-on

and turn-off.

Selected Parts with (TPS20xxC) and without

(TPS20xxC-2) Output Discharge

•

Reverse Current Blocking

Built-in Softstart

Ambient Temperature Range: –40°C to 85°C

UL Listed and CB-File No. E169910

APPLICATIONS

DGN, DGK

(Top View)

DBV

(Top View)

•

USB Ports/Hubs, Laptops, Desktops

High-Definition Digital TVs

Set Top Boxes

GND

OUT

FLT

OUT

GND

FLT

Short-Circuit Protection

EN or EN

DGN Only

V_IN

R_FLT

10 kW

V_OUT

150 mF

OUT

GND

Pad*

Fault Signal

FLT

EN or

Control Signal

* DGN only

Figure 1. Typical Application

Table 1. DEVICES⁽¹⁾

STATUS

SOT23-5

MAXIMUM OPERATING

CURRENT

DEVICES

MSOP-8 ( PowerPad™)

—

MSOP-8

0.5

TPS2041C and 51C

TPS2061C and 65C

TPS2065C-2

Active and Active

—

Active and Active

Active

Active and Active

—

Active

—

1.5

TPS2068C and 69C

TPS2069C-2

Active and Active

Active

— and Active

—

TPS2000C and 01C

Active and Active

(1) For more details, see the DEVICE INFORMATION table.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PowerPad is a trademark of Texas Instruments.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

TPS20xxC, TPS20xxC-2

SLVSAU6G –JUNE 2011–REVISED JULY 2013

www.ti.com

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more

susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

DEVICE INFORMATION⁽¹⁾

PACKAGED DEVICE AND MARKING⁽²⁾

MAXIMUM

OPERATING

CURRENT

OUTPUT

DISCHARGE

BASE PART

NUMBER

ENABLE

MSOP-8 (DGN)

PowerPAD™

SOT23-5

(DBV)

MSOP-8

(DGK)

0.5

Low

High

Low

High

Low

High

Low

High

TPS2041C

TPS2051C

TPS2061C

TPS2065C

TPS2065C-2

TPS2068C

TPS2069C

TPS2069C-2

TPS2000C

TPS2001C

–

PYJI

VBYQ

PXLI

VCAQ

PYQI

–

PXMI

VCAQ

PYRI

PXNI

VBUQ

PYSI

BCMS

VBWQ

–

1.5

PYKI

–

PXFI

PXGI

–

(1) For the most current packaging and ordering information, see the Package Option Addendum at the end of this document, or see the TI

website at www.ti.com.

(2) "-" indicates the device is not available in this package.

ABSOLUTE MAXIMUM RATINGS⁽¹⁾⁽²⁾

VALUE

UNIT

MIN

–0.3

–6

MAX

(3)

Voltage range on IN, OUT, EN or EN, FLT

Voltage range from IN to OUT

Maximum junction temperature, T_J

HBM

Internally Limited

Electrostatic Discharge

CDM

IEC 61000-4-2, Contact / Air

500

(4)

(1) Absolute maximum ratings apply over recommended junction temperature range.

(2) Voltages are with respect to GND unless otherwise noted.

(3) See the Input and Output Capacitance section.

(4) V_OUTwas surged on a pcb with input and output bypassing per Figure 1 (except input capacitor was 22 µF) with no device failures.

THERMAL INFORMATION

0.5 A or 1 A

Rated

1.5 A or 2 A

Rated

0.5 A or 1 A

Rated

1.5 A or 2 A

Rated

2 A

Rated

THERMAL METRIC⁽¹⁾

UNITS

(See DEVICE INFORMATION table.)

DBV

5 PINS

224.9

95.2

DBV

5 PINS

220.4

89.7

DGN

8 PINS

72.1

87.3

42.2

7.3

DGN

8 PINS

67.1

80.8

37.2

5.6

DGK

8 PINS

205.5

94.3

θ_JA

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

θ_JCtop

θ_JB

51.4

46.9

126.9

24.7

ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

6.6

5.2

°C/W

ψ_JB

50.3

46.2

42.0

39.2

36.9

32.1

125.2

N/A

θ_JCbot

N/A

See the Power DIssipation and Junction

Temperature section

θ_JACustom

139.3

134.9

66.5

61.3

110.3

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

Submit Documentation Feedback

TPS20xxC, TPS20xxC-2

www.ti.com

SLVSAU6G –JUNE 2011–REVISED JULY 2013

RECOMMENDED OPERATING CONDITIONS

MIN

4.5

NOM

MAX

5.5

UNIT

V_IN

V_EN

V_IH

V_IL

Input voltage, IN

Input voltage, EN or EN

5.5

High-level input voltage, EN or EN

Low-level input voltage, EN or EN

0.7

0.5

TPS2041C and TPS2051C

TPS2061C, TPS2065C and TPS2065C-2

TPS2068C, TPS2069C and TPS2069C-2

TPS2000C and TPS2001C

Continuous output current,

OUT⁽¹⁾

I_OUT

1.5

T_J

Operating junction temperature

Sink current into FLT

–40

125

°C

I_FLT

(1) Some package and current rating may request an ambient temperature derating of 85°C.

ELECTRICAL CHARACTERISTICS: T_J= T_A= 25°C⁽¹⁾

Unless otherwise noted:, V_IN= 5 V, V_EN= V_INor V_EN= GND, I_OUT= 0 A. See the 'Device Information' table for the rated

current of each part number. Parametrics over a wider operational range are shown in the second 'Electrical Characteristics'

table.

PARAMETER

TEST CONDITIONS⁽¹⁾

MIN

TYP

MAX

UNIT

POWER SWITCH

0.5 A rated output, 25°C

DBV

110

130

mΩ

0.5 A rated output,

–40°C ≤ (T_J, T_A) ≤ 85°C

DBV

110

100

130

120

1 A rated output, 25°C

mΩ

DGN

DBV

1 A rated output,

–40°C ≤ (T_J, T_A) ≤ 85°C

DGN

R_DS(on)

Input – output resistance

DBV

mΩ

1.5 A rated output, 25°C

DGN

DBV

106

1.5 A rated output,

–40°C ≤ (T_J, T_A) ≤ 85°C

DGN

2 A rated output, 25°C

DGN, DGK

2 A rated output, –40°C ≤ (T_J, T_A) ≤

85°C

DGN, DGK

mΩ

CURRENT LIMIT

0.5A rated output

1 A rated output

TPS20xxC

TPS20xxC-2

TPS20xxC

TPS20xxC-2

TPS20xxC

0.67

1.3

0.85

1.55

1.53

2.15

2.23

2.9

1.01

1.8

1.18

1.7

1.88

2.5

Current-limit,

See Figure 7

(2)

I_OS

1.5 A rated output

2 A rated output

1.71

2.35

2.75

3.4

SUPPLY CURRENT

I_SDSupply current, switch disabled

I_OUT= 0 A

0.01

µA

–40°C ≤ (T_J, T_A) ≤ 85°C, V_IN= 5.5 V, I_OUT= 0 A

I_OUT= 0 A

I_SE

Supply current, switch enabled

Leakage current

–40°C ≤ (T_J, T_A) ≤ 85°C, V_IN= 5.5 V, I_OUT= 0 A

V_OUT= 0 V, V_IN= 5 V, disabled,

measure I_VIN

0.05

I_lkg

TPS20xxC-2

µA

–40°C ≤ (T_J, T_A) ≤ 85°C, V_OUT= 0 V,

V_IN= 5 V, disabled, measure I_VIN

(1) Pulsed testing techniques maintain junction temperature approximately equal to ambient temperature

(2) See CURRENT LIMIT section for explanation of this parameter.

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TPS20xxC, TPS20xxC-2

SLVSAU6G –JUNE 2011–REVISED JULY 2013

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ELECTRICAL CHARACTERISTICS: T_J= T_A= 25°C⁽¹⁾(continued)

Unless otherwise noted:, V_IN= 5 V, V_EN= V_INor V_EN= GND, I_OUT= 0 A. See the 'Device Information' table for the rated

current of each part number. Parametrics over a wider operational range are shown in the second 'Electrical Characteristics'

table.

PARAMETER

TEST CONDITIONS⁽¹⁾

MIN

TYP

MAX

UNIT

V_OUT= 5 V, V_IN= 0 V, measure I_VOUT

0.1

I_REV

Reverse leakage current

µA

–40°C ≤ (T_J, T_A) ≤ 85°C, V_OUT= 5 V, V_IN= 0 V, measure

I_VOUT

OUTPUT DISCHARGE

R_PD

Output pull-down resistance⁽³⁾

V_IN= V_OUT= 5 V, disabled

TPS20xxC

400

470

600

Ω

(3) These parameters are provided for reference only, and do not constitute part of TI's published device specifications for purposes of TI's

product warranty.

ELECTRICAL CHARACTERISTICS: –40°C ≤ T_J≤ 125°C

Unless otherwise noted:4.5 V ≤ V_IN≤ 5.5 V, V_EN= V_INor V_EN= GND, I_OUT= 0 A, typical values are at 5 V and 25°C. See the

DEVICE INFORMATION table for the rated current of each part number.

PARAMETER

TEST CONDITIONS⁽¹⁾

MIN

TYP

MAX

UNIT

POWER SWITCH

0.5 A rated output

1 A rated output

DBV

154

140

121

112

mΩ

DBV

DGN

R_DS(ON)

Input – output resistance

DBV

mΩ

1.5 A rated output

2 A rated output

DGN

DGN, DGK

ENABLE INPUT (EN or EN)

Threshold

Input rising

0.07

–1

1.45

0.13

0.20

Hysteresis

Leakage current

(V_ENor V_EN) = 0 V or 5.5 V

µA

V_IN= 5 V, C_L= 1 µF, R_L= 100 Ω, EN ↑ or EN ↓.

See Figure 2, Figure 4, and Figure 5

t_ON

Turnon time

Turnoff time

0.5A / 1A Rated

1.5A / 2A Rated

1.4

1.7

1.8

2.2

1.2

V_IN= 5 V, C_L= 1 µF, R_L= 100 Ω, EN ↓ or EN ↑.

See Figure 2, Figure 4, and Figure 5

t_OFF

0.5A and 1A Rated

1.3

1.7

1.65

2.1

1.5A / 2A Rated

2.5

C_L= 1 µF, R_L= 100 Ω, V_IN= 5 V. See Figure 3

0.5A / 1A Rated

t_R

Rise time, output

Fall time, output

0.4

0.5

0.55

0.7

1.0

1.5A / 2A Rated

C_L= 1 µF, R_L= 100 Ω, V_IN= 5 V. See Figure 3

0.5A / 1A Rated

t_F

0.25

0.3

0.35

0.43

0.45

0.55

1.5A / 2A Rated

CURRENT LIMIT

0.5 A rated output

1 A rated output

TPS20xxC

0.65

1.2

1.1

1.6

2.3

0.85

1.55

1.53

2.15

2.23

2.9

1.05

1.9

TPS20xxC

TPS20xxC-2

TPS20xxC

TPS20xxC-2

TPS20xxC

1.96

2.7

Current-limit,

See Figure 10

(2)

I_OS

1.5 A rated output

2 A rated output

2.86

3.6

(1) Pulsed testing techniques maintain junction temperature approximately equal to ambient temperature

(2) See CURRENT LIMIT section for explanation of this parameter.

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SLVSAU6G –JUNE 2011–REVISED JULY 2013

ELECTRICAL CHARACTERISTICS: –40°C ≤ T_J≤ 125°C (continued)

Unless otherwise noted:4.5 V ≤ V_IN≤ 5.5 V, V_EN= V_INor V_EN= GND, I_OUT= 0 A, typical values are at 5 V and 25°C. See the

DEVICE INFORMATION table for the rated current of each part number.

PARAMETER

TEST CONDITIONS⁽¹⁾

MIN

TYP

MAX

UNIT

V_IN= 5 V (see Figure 7),

One-half full load → R_SHORT= 50 mΩ,

Measure from application to when current falls below 120% of

final value

t_IOS

Short-circuit response time⁽³⁾

µs

SUPPLY CURRENT

I_SDSupply current, switch disabled

I_SE

I_OUT= 0 A

0.01

µA

Supply current, switch enabled

Leakage current

V_OUT= 0 V, V_IN= 5 V, disabled,

TPS20XXC-2

I_lkg

0.05

0.2

µA

measure I_VIN

I_REV

Reverse leakage current

V_OUT= 5.5 V, V_IN= 0 V, measure I_VOUT

UNDERVOLTAGE LOCKOUT

V_UVLO

Rising threshold

Hysteresis⁽³⁾

V_IN

↑

↓

3.5

3.75

0.14

V_IN

FLT

Output low voltage, FLT

Off-state leakage

FLT deglitch

I_FLT= 1 mA

0.2

V_FLT= 5.5 V

µA

t_FLT

FLT assertion or deassertion deglitch

OUTPUT DISCHARGE

V_IN= 4 V, V_OUT= 5 V, disabled

V_IN= 5 V, V_OUT= 5 V, disabled

TPS20XXC

350

300

560

470

1200

800

R_PD

Output pull-down resistance

Ω

THERMAL SHUTDOWN

In current limit

135

155

Rising threshold (T_J)

Not in current limit

°C

(4)

Hysteresis

(3) These parameters are provided for reference only, and do not constitute part of TI's published device specifications for purposes of TI's

product warranty.

(4) These parameters are provided for reference only, and do not constitute part of TI's published device specifications for purposes of TI's

product warranty.

OUT

90%

t_R

t_F

V_OUT

10%

Figure 2. Output Rise / Fall Test Load

Figure 3. Power-On and Off Timing

/EN

50%

OFF

90%

OUT

10%

Figure 4. Enable Timing, Active High Enable

Figure 5. Enable Timing, Active Low Enable

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TPS20xxC, TPS20xxC-2

SLVSAU6G –JUNE 2011–REVISED JULY 2013

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120% x I

OUT

0 A

IOS

Figure 6. Output Short Circuit Parameters

V_IN

Decreasing

Load

Resistance

Slope = -R_DS(ON)

0 V

0 A

I_OUT

I_OS

Figure 7. Output Characteristic Showing Current Limit

FUNCTIONAL BLOCK DIAGRAM

Current

Sense

OUT

Charge

Pump

Current

Limit

(Disabled+

UVLO)

EN or

Driver

FLT

UVLO

9-ms

Deglitch

OTSD

Thermal

Sense

GND

Figure 8. TPS20xxC Block Diagram

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TPS20xxC, TPS20xxC-2

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SLVSAU6G –JUNE 2011–REVISED JULY 2013

Current

Sense

OUT

FLT

Charge

Pump

Current

Limit

EN or

Driver

UVLO

9-ms

Deglitch

OTSD

Thermal

Sense

GND

Figure 9. TPS20xxC-2 Block Diagram

DEVICE INFORMATION

PIN FUNCTIONS

NAME

PINS DESCRIPTION

8-PIN PACKAGE

EN or EN

GND

Enable input, logic high turns on power switch

Ground connection

2, 3

Input voltage and power-switch drain; connect a 0.1 µF or greater ceramic capacitor from IN to GND close

to the IC

FLT

Active-low open-drain output, asserted during over-current, or over-temperature conditions

OUT

6, 7, 8 Power-switch output, connect to load

PowerPAD

(DGN ONLY)

PAD

Internally connected to GND. Connect PAD to GND plane as a heatsink for the best thermal performance.

PAD may be left floating if desired. See POWER DISSIPATION AND JUNCTION TEMPERATURE section

for guidance.

5-PIN PACKAGE

EN or EN

GND

Enable input, logic high turns on power switch

Ground connection

Input voltage and power-switch drain; connect a 0.1 µF or greater ceramic capacitor from IN to GND close

to the IC

FLT

Active-low open-drain output, asserted during over-current, or over-temperature conditions

Power-switch output, connect to load.

OUT

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TPS20xxC, TPS20xxC-2

SLVSAU6G –JUNE 2011–REVISED JULY 2013

www.ti.com

TYPICAL CHARACTERISTICS

I_OUT

V_IN

V_OUT

OUT

OUT¹

IN¹

OUT¹

V_IN

R_LOAD

680mF³

Enable

Signal

3.01kW²

EN or

FLT

Fault Signal

Pad¹GND

(1) Not every package has all pins

(2) These parts are for test purposes

(3) Helps with output shorting tests when external supply is used.

Figure 10. Test Circuit for System Operation in Typical Characteristics Section

2.00

1.75

1.50

1.25

1.00

0.75

0.50

0.25

0.00

−0.25

−0.50

2.00

1.75

1.50

1.25

1.00

0.75

0.50

0.25

0.00

−0.25

−0.50

V_IN= 5 V, C_OUT= 150 µF, R_LOAD= 5 Ω, TPS2065C

V_IN= 5 V, C_OUT= 150 µF, R_LOAD= 100 Ω, TPS2065C

Output Current

Output Voltage

FLT

Output Voltage

−1

−2m

−1

−2m

2m 4m 6m 8m 10m 12m 14m 16m 18m 20m

Time (s)

G001

G002

Figure 11. TPS2065C Output Rise / Fall 5Ω

Figure 12. TPS2065C Output Rise / Fall 100Ω

2.00

1.75

1.50

1.25

1.00

0.75

0.50

0.25

0.00

−0.25

−0.50

2.00

1.80

1.50

1.20

1.00

0.75

0.50

0.25

0.00

−0.25

−0.50

V_IN= 5 V, C_OUT= 150 µF, R_LOAD= 0 Ω, TPS2065C

V_IN= 5 V,C_OUT= 150 µF,R_LOAD= 50 mΩ, TPS2065C

Output Current

FLT

Output Current

FLT

Output Voltage

−1

−2m

−1

−2.5m

2m 4m 6m 8m 10m 12m 14m 16m 18m

Time (s)

2.5m

7.5m

12.5m

Time (s)

17.5m

22.5m25m

G003

G004

Figure 13. TPS2065C Enable into Output Short

Figure 14. TPS2065C Pulsed Short Applied

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SLVSAU6G –JUNE 2011–REVISED JULY 2013

TYPICAL CHARACTERISTICS (continued)

V_IN= 5 V, C_OUT= 0 µF, TPS2065C

V_IN= 5 V, C_OUT= 0 µF, R_LOAD= 50 mΩ, TPS2065C

Input Voltage

I_OUT

V_OUT

Output Voltage

Output Current

−1

−2

−3

−1

−1u

−5

−1u

Time (s)

G005

G006

Figure 15. TPS2065C Short Applied

Figure 16. TPS2065C Pulsed 1.45-A Load

2.5

2.00

1.75

1.50

1.25

1.00

0.75

0.50

0.25

0.00

−0.25

−0.50

V_IN= 5 V, C_OUT= 0 µF,

R_LOAD= 50 mΩ, TPS2065C

V_IN= 5 V, C_OUT= 150 µF, R_LOAD= 7.5Ω, TPS2065C

2.0

Output Voltage

1.5

1.0

EN, V_IN

I_OUT

0.5

V_OUT

FLT

0.0

Output Current

−0.5

−1.0

−1

−100u

−1

100u

200u

300u

400u

500u

600u

−5m −4m −3m −2m −1m

1m 2m 3m 4m 5m

Time (s)

G007

G008

Figure 17. TPS2065C 50 mΩ Short Circuit

Figure 18. TPS2065C Power Up - Enabled

2.00

1.75

1.50

1.25

1.00

0.75

0.50

0.25

0.00

−0.25

−0.50

3.2

2.8

2.4

2.0

1.6

1.2

0.8

0.4

0.0

−0.4

−0.8

V_IN= 5 V, C_OUT= 150 µF, R_LOAD= 7.5Ω, TPS2065C

V_IN= 5 V, C_OUT= 150 µF, R_LOAD= 2.5 Ω, TPS2001C

Output Current

FLT

EN, V_IN

Output Current

Output Voltage

−1

−2m

−40m −30m −20m −10m

10m 20m 30m 40m

2m 4m 6m 8m 10m 12m 14m 16m 18m

Time (s)

G009

G010

Figure 19. TPS2065C Power Down - Enabled

Figure 20. TPS2001C Turn ON into 2.5Ω

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SLVSAU6G –JUNE 2011–REVISED JULY 2013

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TYPICAL CHARACTERISTICS (continued)

3.6

3.2

2.8

2.4

2.0

1.6

1.2

0.8

0.4

0.0

−0.4

V_IN= 5 V, C_OUT= 150 µF, R_LOAD= 50 mΩ, TPS2001C

V_IN= 5 V, C_OUT= 150 µF,R_LOAD= 50mΩ, TPS2001C

3.2

Output Current 2.8

2.4

Output Current

FLT

2.0

1.6

1.2

Output Voltage

FLT

Output Voltage

0.8

0.4

0.0

−1

−2m

−0.4

−1

−2.5m

2m 4m 6m 8m 10m 12m 14m 16m 18m

Time (s)

2.5m 5m 7.5m 10m 12.5m 15m 17.5m 20m 22.5m

Time (s)

G011

G013

G015

G012

G014

G016

Figure 21. TPS2001C Enable into Short

Figure 22. TPS2001C Pulsed Output Short

1.4

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0.0

−0.2

−0.4

V_IN= 5 V, C_OUT= 150 µF, R_LOAD= 10 Ω, TPS2051C

Output Current

V_IN= 5 V, C_OUT= 150 µF, R_LOAD= 50 mΩ, TPS2051C

1.2

1.0

Output Current

Output Voltage

0.8

FLT

0.6

0.4

0.2

0.0

Output Voltage

FLT

−0.2

−0.4

−0.6

−1

−2m

−1

−2m

2m 4m 6m 8m 10m 12m 14m 16m 18m

Time (s)

2m 4m 6m 8m 10m 12m 14m 16m 18m

Time (s)

Figure 23. TPS2051C Turn ON into 10Ω

Figure 24. TPS2051C Enable into Short

1.4

2.5

V_IN= 5 V, C_OUT= 150 µF, R_LOAD= 50mΩ, TPS2051C

V_IN= 5 V, C_OUT= 150 µF, R_LOAD= 3.3 Ω, TPS2069C

1.2

2.0

1.0

Output Current

1.5

0.8

0.6

Output Current

1.0

0.4

0.5

0.2

FLT

0.0

FLT

Output Voltage

−0.2

−0.4

−0.6

Output Voltage

−0.5

−1.0

−1

−2.5m

−2

2.5m 5m 7.5m 10m 12.5m 15m 17.5m 20m 22.5m

−4m −2m

2m 4m 6m 8m 10m 12m 14m 16m

Time (s)

Figure 25. TPS2051C Pulsed Output Short

Figure 26. TPS2069C Turn ON into 3.3Ω

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TYPICAL CHARACTERISTICS (continued)

3.0

2.5

2.0

1.5

1.0

0.5

0.0

−0.5

3.0

2.5

2.0

1.5

1.0

0.5

0.0

−0.5

V_IN= 5 V, C_OUT= 150 µF, R_LOAD= 50 mΩ, TPS2069C

Output

Current

Output Current

FLT

−2

−4

−2

−4

Output Voltage

−7.5m

FLT

Output Voltage

−2m

2m 4m 6m 8m 10m 12m 14m 16m 18m

Time (s)

−12.5m

−2.5m

2.5m

7.5m

12.5m

Time (s)

G017

G018

Figure 27. TPS2069C Enable into Short

Figure 28. TPS2069C Pulsed Output Short

9.3

V_IN= 5 V

All Versions, 5 V

85°C

9.2

9.1

9.0

8.9

8.8

25°C

−40°C

125°C

−40 −20

100 120 140

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

Output Voltage (V)

Junction Temperature (°C)

G019

G020

Figure 29. Deglitch Period (t_FLT)vs Temperature

Figure 30. Output Discharge Current vs Output Voltage

3.5

3.0

2.5

2.0

1.5

1.0

0.5

V_IN= 5 V

All Unit Types, 5 V

2-A Rated

1.5-A Rated

1-A Rated

0.5-A Rated

−1

−40 −20

100 120 140

−40 −20

100 120 140

Junction Temperature (°C)

G021

G022

Figure 31. Short Circuit Current (I_OS) vs Temperature

Figure 32. Reverse Leakage Current (I_REV) vs Temperature

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TYPICAL CHARACTERISTICS (continued)

1.0

0.8

1.0

Input Voltage = 5.5 V

All Unit Types

0.8

0.6

125°C

85°C

0.4

0.2

0.0

−40°C and 25°C

4.50 4.75

Input Voltage (V)

−0.2

−40 −20

100 120 140

4.00

4.25

5.00

5.25

5.50

Junction Temperature (°C)

G023

G024

Figure 33. Disabled Supply Current (I_SD) vs Temperature

Figure 34. Disabled Supply Current (I_SD) vs Input Voltage

6.0

All unit types, V_IN= 0 V

All Unit Types,V_IN= 5.5 V

5.5

5.0

4.5

125°C

4.0

3.5

3.0

2.5

2.0

85°C

1.5

1.0

25°C

−40°C

0.5

0.0

−0.5

4.00

4.25

4.50

4.75

5.00

5.25

5.50

−40 −20

100 120 140

Output Voltage (V)

Junction Temperature (°C)

G025

G026

Figure 35. Reverse Leakage Current (I_REV) vs Output

Voltage

Figure 36. Enabled Supply Current (I_SE) vs Temperature

0.475

C_OUT= 1 µF, R_LOAD= 100 Ω

125°C

85°C

0.450

0.425

0.400

1.5-A and 2-A Rated, V_IN= 4.5 V

1.5-A and 2-A Rated, V_IN= 5 V

0.375

1.5-A and 2-A Rated, V_IN= 5.5 V

0.350

25°C

−40°C

0.5-A and 1-A Rated, V_IN= 5 V

0.325

4.00

4.25

4.50

4.75

5.00

5.25

5.50

−40 −20

100 120 140

Input Voltage (V)

Junction Temperature (°C)

G027

G028

Figure 37. Enabled Supply Current (I_SE) vs Input Voltage

Figure 38. Output Fall Time (t_F) vs Temperature

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TYPICAL CHARACTERISTICS (continued)

0.85

0.80

0.75

0.70

0.65

0.60

0.55

0.50

140

130

120

110

100

C_OUT= 1 µF, R_LOAD= 100 Ω

V_IN= 5 V

1.5 A, 2 A, 5.5 V

0.5-A, 1-A Rated

0.5 A, 1 A, 5 V

1.5 A, 2 A, 5 V

1.5-A, 2-A Rated

1.5 A, 2 A, 4.5 V

−40 −20

100 120 140

−40 −20

100 120 140

Junction Temperature (°C)

G029

G030

Figure 39. Output Rise Time (t_R) vs Temperature

Figure 40. Input-Output Resistance (R_DS(ON)) vs

Temperature

100

V_IN= 5 V, C_IN= 730 µF, TPS2065C, I_END= 1.68 A

I_OS

I_PK(Shorted) (A)

G031

Figure 41. Recovery vs Current Peak

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DETAILED DESCRIPTION

The TPS20xxC and TPS20xxC-2 are current-limited, power-distribution switches providing between 0.5 A and 2

A of continuous load current in 5 V circuits. These parts use N-channel MOSFETs for low resistance, maintaining

voltage regulation to the load. They are designed for applications where short circuits or heavy capacitive loads

will be encountered. Device features include enable, reverse blocking when disabled, output discharge pulldown,

overcurrent protection, over-temperature protection, and deglitched fault reporting.

UVLO

The undervoltage lockout (UVLO) circuit disables the power switch until the input voltage reaches the UVLO turn-

on threshold. Built-in hysteresis prevents unwanted on/off cycling due to input voltage drop from large current

surges. FLT is high impedance when the TPS20xxC and TPS20xxC-2 are in UVLO.

ENABLE

The logic enable input (EN, or EN), controls the power switch, bias for the charge pump, driver, and other

circuits. The supply current is reduced to less than 1 µA when the TPS20xxC and TPS20xxC-2 are disabled.

Disabling the TPS20xxC and TPS20xxC-2 will immediately clear an active FLT indication. The enable input is

compatible with both TTL and CMOS logic levels.

The turnon and turnoff times (t_ON, t_OFF) are composed of a delay and a rise or fall time (t_R, t_F). The delay times

are internally controlled. The rise time is controlled by both the TPS20xxC and TPS20xxC-2 and the external

loading (especially capacitance). TPS20xxC fall time is controlled by the loading (R and C), and the output

discharge (R_PD). TPS20xxC-2 does not have the output discharge (R_PD), fall time is controlled by the loading (R

and C). An output load consisting of only a resistor will experience a fall time set by the TPS20xxC and

TPS20xxC-2. An output load with parallel R and C elements will experience a fall time determined by the (R × C)

time constant if it is longer than the TPS20xxC and TPS20xxC-2’s t_F.

The enable should not be left open, and may be tied to VIN or GND depending on the device.

INTERNAL CHARGE PUMP

The device incorporates an internal charge pump and gate drive circuitry necessary to drive the N-channel

MOSFET. The charge pump supplies power to the gate driver circuit and provides the necessary voltage to pull

the gate of the MOSFET above the source. The driver incorporates circuitry that controls the rise and fall times of

the output voltage to limit large current and voltage surges on the input supply, and provides built-in soft-start

functionality. The MOSFET power switch will block current from OUT to IN when turned off by the UVLO or

disabled.

CURRENT LIMIT

The TPS20xxC and TPS20xxC-2 responds to overloads by limiting output current to the static I_OSlevels shown in

the Electrical Characteristics table. When an overload condition is present, the device maintains a constant

output current, with the output voltage determined by (I_OS× R_LOAD). Two possible overload conditions can occur.

The first overload condition occurs when either: 1) input voltage is first applied, enable is true, and a short circuit

is present (load which draws I_OUT> I_OS), or 2) input voltage is present and the TPS20xxC and TPS20xxC-2 are

enabled into a short circuit. The output voltage is held near zero potential with respect to ground and the

TPS20xxC and TPS20xxC-2 ramps the output current to I_OS. The TPS20xxC and TPS20xxC-2 will limit the

current to I_OSuntil the overload condition is removed or the device begins to thermal cycle. This is demonstrated

in Figure 13 where the device was enabled into a short, and subsequently cycles current off and on as the

thermal protection engages.

The second condition is when an overload occurs while the device is enabled and fully turned on. The device

responds to the overload condition within t_IOS(Figure 6 and Figure 7) when the specified overload (per Electrical

Characteristics table) is applied. The response speed and shape will vary with the overload level, input circuit,

and rate of application. The current-limit response will vary between simply settling to I_OS, or turnoff and

controlled return to I_OS. Similar to the previous case, the TPS20xxC and TPS20xxC-2 will limit the current to I_OS

until the overload condition is removed or the device begins to thermal cycle. This is demonstrated by Figure 14,

Figure 15, and Figure 16.

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The TPS20xxC and TPS20xxC-2 thermal cycles if an overload condition is present long enough to activate

thermal limiting in any of the above cases. This is due to the relatively large power dissipation [(V_IN– V_OUT) x I_OS

]

driving the junction temperature up. The device turns off when the junction temperature exceeds 135°C (min)

while in current limit. The device remains off until the junction temperature cools 20°C and then restarts.

There are two kinds of current limit profiles typically available in TI switch products similar to the TPS20xxC and

TPS20xxC-2. Many older designs have an output I vs V characteristic similar to the plot labeled "Current Limit

with Peaking" in Figure 42. This type of limiting can be characterized by two parameters, the current limit corner

(I_OC), and the short circuit current (I_OS). I_OCis often specified as a maximum value. The TPS20xxC and

TPS20xxC-2 family of parts does not present noticeable peaking in the current limit, corresponding to the

characteristic labeled "Flat Current Limit" in Figure 42. This is why the I_OCparameter is not present in the

Electrical Characteristics tables.

Current Limit

with Peaking

Flat Current

Limit

V_IN

Decreasing

Load

Resistance

Decreasing

Load

Resistance

Slope = -R_DS(ON)

0 V

0 A

I_OUT

I_OSI_OC

I_OS

Figure 42. Current Limit Profiles

FLT

The FLT open-drain output is asserted (active low) during an overload or over-temperature condition. A 9 ms

deglitch on both the rising and falling edges avoids false reporting at startup and during transients. A current limit

condition shorter than the deglitch period will clear the internal timer upon termination. The deglitch timer will not

integrate multiple short overloads and declare a fault. This is also true for exiting from a faulted state. An input

voltage with excessive ripple and large output capacitance may interfere with operation of FLT around I_OSas the

ripple will drive the TPS20xxC and TPS20xxC-2 in and out of current limit.

If the TPS20xxC and TPS20xxC-2 are in current limit and the over-temperature circuit goes active, FLT will go

true immediately (see Figure 14) however exiting this condition is deglitched (see Figure 16). FLT is tripped just

as the knee of the constant-current limiting is entered. Disabling the TPS20xxC and TPS20xxC-2 will clear an

active FLT as soon as the switch turns off (see Figure 13). FLT is high impedance when the TPS20xxC and

TPS20xxC-2 are disabled or in under-voltage lockout (UVLO).

OUTPUT DISCHARGE

A 470Ω (typical) output discharge will dissipate stored charge and leakage current on OUT when the TPS20xxC

is in UVLO or disabled. The pull-down circuit will lose bias gradually as V_INdecreases, causing a rise in the

discharge resistance as V_INfalls towards 0 V. The TPS20xxC-2 does not have this function. The output is be

controlled by an external loadings when the device is in ULVO or disabled.

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APPLICATION INFORMATION

INPUT AND OUTPUT CAPACITANCE

Input and output capacitance improves the performance of the device; the actual capacitance should be

optimized for the particular application. For all applications, a 0.1 µF or greater ceramic bypass capacitor

between IN and GND is recommended as close to the device as possible for local noise decoupling.

All protection circuits such as the TPS20xxC and TPS20xxC-2 will have the potential for input voltage overshoots

and output voltage undershoots.

Input voltage overshoots can be caused by either of two effects. The first cause is an abrupt application of input

voltage in conjunction with input power bus inductance and input capacitance when the IN terminal is high

impedance (before turn on). Theoretically, the peak voltage is 2 times the applied. The second cause is due to

the abrupt reduction of output short circuit current when the TPS20xxC and TPS20xxC-2 turns off and energy

stored in the input inductance drives the input voltage high. Input voltage droops may also occur with large load

steps and as the TPS20xxC and TPS20xxC-2 output is shorted. Applications with large input inductance (e.g.

connecting the evaluation board to the bench power-supply through long cables) may require large input

capacitance reduce the voltage overshoot from exceeding the absolute maximum voltage of the device. The fast

current-limit speed of the TPS20xxC and TPS20xxC-2 to hard output short circuits isolates the input bus from

faults. However, ceramic input capacitance in the range of 1µF to 22µF adjacent to the TPS20xxC and

TPS20xxC-2 input aids in both speeding the response time and limiting the transient seen on the input power

bus. Momentary input transients to 6.5V are permitted.

Output voltage undershoot is caused by the inductance of the output power bus just after a short has occurred

and the TPS20xxC and TPS20xxC-2 has abruptly reduced OUT current. Energy stored in the inductance will

drive the OUT voltage down and potentially negative as it discharges. Applications with large output inductance

(such as from a cable) benefit from use of a high-value output capacitor to control the voltage undershoot. When

implementing USB standard applications, a 120 µF minimum output capacitance is required. Typically a 150 µF

electrolytic capacitor is used, which is sufficient to control voltage undershoots. However, if the application does

not require 120 µF of capacitance, and there is potential to drive the output negative, a minimum of 10 µF

ceramic capacitance on the output is recommended. The voltage undershoot should be controlled to less than

1.5 V for 10 µs.

POWER DISSIPATION AND JUNCTION TEMPERATURE

It is good design practice to estimate power dissipation and maximum expected junction temperature of the

TPS20xxC and TPS20xxC-2. The system designer can control choices of package, proximity to other power

dissipating devices, and printed circuit board (PCB) design based on these calculations. These have a direct

influence on maximum junction temperature. Other factors, such as airflow and maximum ambient temperature,

are often determined by system considerations. It is important to remember that these calculations do not include

the effects of adjacent heat sources, and enhanced or restricted air flow.

Addition of extra PCB copper area around these devices is recommended to reduce the thermal impedance and

maintain the junction temperature as low as practical. The lower junction temperatures achieved by soldering the

pad improve the efficiency and reliability of both TPS20xxC and TPS20xxC-2 parts and the system. The following

examples were used to determine the θ_JACustom thermal impedances noted in the THERMAL INFORMATION

table. They were based on use of the JEDEC high-k circuit board construction (2 signal and 2 plane) with 4, 1oz.

copper weight, layers.

While it is recommended that the DGN package PAD be soldered to circuit board copper fill and vias for low

thermal impedance, there may be cases where this is not desired. For example, use of routing area under the IC.

Some devices are available in packages without the Power Pad (DGK) specifically for this purpose. The θ_JAfor

the DGN package with the pad not soldered and no extra copper, is approximately 141°C/W for 0.5 - A and 1- A

rated parts, and 139°C/W for the 1.5 - A and 2- A rated parts. The θ_JAfor the DGK mounted per Figure 45 is

110.3C/W. These values may be used in Equation 1 to determine the maximum junction temperature.

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GND: 0.052in²Total

& 3 x 0.018in vias

GND: 0.056in²total area

& 3 x 0.018in vias

C_OUT

0.050in trace

C_IN

0.050in trace

C_IN

4 x 0.01in vias

V_OUT: 0.048in²total area

5 x 0.01in vias

V_IN: 0.0145in²area

& 2 x 0.018in vias

V : 0.00925in²

V_OUT: 0.041in²total

& 3 x 0.018in vias

Figure 43. DBV Package PCB Layout Example

Figure 44. DGN Package PCB Layout Example

0.100 x 0.175

& 5 18 mil vias

0.08 x 0.250

0.15 x 0.15

0.185 x 0.045

& 3 18 mil vias

50 mil trace

0.100 x 0.060

& 3 18 mil vias to

0.07 x 0.08

10 mil trace

inner plane 2

10 mil trace

Figure 45. DGK Package PCB Layout Example

The following procedure requires iteration because power loss is due to the internal MOSFET I²× R_DS(ON), and

R_DS(ON)is a function of the junction temperature. As an initial estimate, use the R_DS(ON)at 125°C from the

TYPICAL CHARACTERISTICS, and the preferred package thermal resistance for the preferred board

construction from the THERMAL INFORMATION table.

T_J= T_A+ ((I_OUT²x R_DS(ON)) x θ_JA

)

(1)

Where:

I_OUT= rated OUT pin current (A)

R_DS(ON)= Power switch on-resistance at an assumed T_J(Ω)

T_A= Maximum ambient temperature (°C)

T_J= Maximum junction temperature (°C)

θ_JA= Thermal resistance (°C/W)

If the calculated T_Jis substantially different from the original assumption, estimate a new value of R_DS(ON)using

the typical characteristic plot and recalculate.

If the resulting T_Jis not less than 125°C, try a PCB construction and/or package with lower θ_JA

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TPS20xxC, TPS20xxC-2

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REVISION HISTORY

Changes from Original (June 2011) to Revision A

Page

•

Changed the TPS2051C, TPS2065C, and TPS2069C Devices Status From: Preview To: Active ...................................... 1

Corrected pinout numbers for the 5-PIN PACKAGE ............................................................................................................ 7

Changes from Revision A (July 2011) to Revision B

Page

•

Added the DGK Package Information throughout the data sheet ........................................................................................ 1

Changed title of Figure 17 From: NEW FIG To: TPS2065C 50 Ω Short Circuit ................................................................... 9

Changes from Revision B (September 2011) to Revision C

Page

•

Changed TPS2000C (MSOP-8) status From: Preview To: Active in Table 1 ...................................................................... 1

Changed From: PXF1 To: PXFI and From: PSG1 To: PXGI in the DEVICE INFORMATION table MOSP-8 (DGK)

column .................................................................................................................................................................................. 2

•

Changed the θJACustom 2 A Rated DGK value from N/A to 110.3 .................................................................................... 2

Added Figure 45 - DGK Package PCB Layout Example .................................................................................................... 17

Changes from Revision C (October 2011) to Revision D

Page

•

Added Feature UL Listed and CB-File No. E169910 (See Table 1) .................................................................................... 1

Added table Note 2, UL listed and CB complete. ................................................................................................................. 1

Added V_IHand V_ILinformation to the ROC Table ................................................................................................................. 3

Changes from Revision D (February 2012) to Revision E

Page

•

Changed the POWER DISSIPATION AND JUNCTION TEMPERATURE section. Replaced paragraph " While it is

recommended..." ................................................................................................................................................................. 16

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Changes from Revision E (April 2012) to Revision F

Page

•

Added device TPS20xxC-2 ................................................................................................................................................... 1

Changed Feature From: Ouput Discharge When TPS20XXC is Disabled To: Selected parts with (TPS20xxC) and

without (TPS20xxC-2) Output Discharge .............................................................................................................................. 1

•

Added devices TPS2041C, TPS2061C, TPS2065C-2, TPS2068C, and TPS2069C-2 to Table 1 and removed

Product Preview .................................................................................................................................................................... 1

•

Added the TPS2069C-2 Device ............................................................................................................................................ 1

Added devices TPS2041C, TPS2061C, TPS2065C-2, TPS2068C, and TPS2069C-2 to the Device Information table ..... 2

Added PXKI in the DEVICE INFORMATION table SOT23-5 (DBV) column (TPS2069C) ................................................... 2

Added Note 1 to the RECOMMENDED OPERATING CONDITIONS table ......................................................................... 3

Added TPS2041C, TPS2061C, TPS2068C, TPS2065C-2 and TPS2069C-2 devices to I_OUTin the RECOMMENDED

OPERATING CONDITIONS table ........................................................................................................................................ 3

•

Added the DBV option to Power Switch R_DS(on)1.5 A rated output, 25°C mΩ ..................................................................... 3

Added the DBV option to Power Switch R_DS(on)1.5 A rated output ...................................................................................... 3

Changed I_SOCurrent Limit .................................................................................................................................................... 3

Added Leakage Current ........................................................................................................................................................ 3

Added the DBV option to Power Switch R_DS(on)1.5 A rated output . .................................................................................... 4

Changed I_SOCurrent Limit .................................................................................................................................................... 4

Added Leakage Current ........................................................................................................................................................ 5

Changed the second para graph of the ENABLE section .................................................................................................. 14

Added sentence to end of paragraph in the OUTPUT DISCHARGE section .................................................................... 15

Changes from Revision F (August 2012) to Revision G

Page

•

Deleted (See Table 1) from Feature: UL Listed and CB-File No. E169910 ......................................................................... 1

Deleted Note 2 from Table 1: "UL listed and CB complete" ................................................................................................. 1

Changed From: PXKI To: PYKI in the DEVICE INFORMATION table SOT23-5 (DBV) column (TPS2069C) .................... 2

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PACKAGE OPTION ADDENDUM

www.ti.com

18-Oct-2013

PACKAGING INFORMATION

Orderable Device

905X0205100

Status Package Type Package Pins Package

Eco Plan

Lead/Ball Finish

MSL Peak Temp

Op Temp (°C)

-40 to 85

Device Marking

Samples

Drawing

Qty

(1)

(2)

(6)

(3)

(4/5)

ACTIVE

SOT-23

VSSOP

DBV

3000

Green (RoHS

& no Sb/Br)

CU NIPDAU

CU NIPDAUAG

Level-2-260C-1 YEAR

VBYQ

PXFI

TPS2000CDGK

TPS2000CDGKR

TPS2000CDGN

TPS2000CDGNR

TPS2001CDGK

TPS2001CDGKR

TPS2001CDGN

TPS2001CDGNR

TPS2041CDBVR

TPS2041CDBVT

TPS2051CDBVR

TPS2051CDBVT

TPS2061CDBVR

TPS2061CDBVT

TPS2061CDGN

TPS2061CDGNR

ACTIVE

DGK

DGN

DGK

DGN

DBV

DGN

2500

Green (RoHS

& no Sb/Br)

Green (RoHS

& no Sb/Br)

MSOP-

PowerPAD

Green (RoHS

& no Sb/Br)

CU NIPDAU |

CU NIPDAUAG

BCMS

PXGI

VBWQ

PYJI

MSOP-

PowerPAD

2500

Green (RoHS

& no Sb/Br)

CU NIPDAU |

CU NIPDAUAG

VSSOP

Green (RoHS

& no Sb/Br)

CU NIPDAUAG

VSSOP

2500

Green (RoHS

& no Sb/Br)

CU NIPDAUAG

MSOP-

PowerPAD

Green (RoHS

& no Sb/Br)

CU NIPDAU |

CU NIPDAUAG

MSOP-

PowerPAD

2500

3000

250

3000

250

3000

250

Green (RoHS

& no Sb/Br)

CU NIPDAU |

CU NIPDAUAG

SOT-23

Green (RoHS

& no Sb/Br)

CU NIPDAU

CU NIPDAUAG

Green (RoHS

& no Sb/Br)

PYJI

Green (RoHS

& no Sb/Br)

VBYQ

PXLI

Green (RoHS

& no Sb/Br)

Green (RoHS

& no Sb/Br)

Green (RoHS

& no Sb/Br)

PXLI

MSOP-

PowerPAD

Green (RoHS

& no Sb/Br)

PXMI

MSOP-

2500

Green (RoHS

& no Sb/Br)

PowerPAD

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

18-Oct-2013

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead/Ball Finish

MSL Peak Temp

Op Temp (°C)

-40 to 85

Device Marking

Samples

Drawing

Qty

(1)

(2)

(6)

(3)

(4/5)

TPS2065CDBVR

TPS2065CDBVR-2

TPS2065CDBVT

TPS2065CDBVT-2

TPS2065CDGN

ACTIVE

SOT-23

DBV

3000

Green (RoHS

& no Sb/Br)

CU NIPDAU

Level-2-260C-1 YEAR

VCAQ

ACTIVE

DBV

DGN

DBV

DGN

3000

250

Green (RoHS

& no Sb/Br)

PYQI

VCAQ

PYQI

VCAQ

PYRI

VCAQ

PYRI

PXNI

PYKI

VBUQ

PYSI

VBUQ

PYSI

Green (RoHS

& no Sb/Br)

Green (RoHS

& no Sb/Br)

MSOP-

PowerPAD

Green (RoHS

& no Sb/Br)

CU NIPDAU |

CU NIPDAUAG

TPS2065CDGN-2

TPS2065CDGNR

TPS2065CDGNR-2

TPS2068CDGN

MSOP-

PowerPAD

Green (RoHS

& no Sb/Br)

CU NIPDAUAG

MSOP-

PowerPAD

2500

Green (RoHS

& no Sb/Br)

CU NIPDAU |

CU NIPDAUAG

MSOP-

PowerPAD

Green (RoHS

& no Sb/Br)

CU NIPDAUAG

CU NIPDAU

MSOP-

PowerPAD

Green (RoHS

& no Sb/Br)

TPS2068CDGNR

TPS2069CDBVR

TPS2069CDBVT

TPS2069CDGN

MSOP-

PowerPAD

2500

3000

250

Green (RoHS

& no Sb/Br)

SOT-23

Green (RoHS

& no Sb/Br)

Green (RoHS

& no Sb/Br)

CU NIPDAU

MSOP-

PowerPAD

Green (RoHS

& no Sb/Br)

CU NIPDAU |

CU NIPDAUAG

TPS2069CDGN-2

TPS2069CDGNR

TPS2069CDGNR-2

MSOP-

PowerPAD

Green (RoHS

& no Sb/Br)

CU NIPDAUAG

MSOP-

PowerPAD

2500

Green (RoHS

& no Sb/Br)

CU NIPDAU |

CU NIPDAUAG

MSOP-

Green (RoHS

& no Sb/Br)

CU NIPDAUAG

PowerPAD

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

Addendum-Page 2

PACKAGE OPTION ADDENDUM

www.ti.com

18-Oct-2013

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that

lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between

the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight

in homogeneous material)

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

⁽⁶⁾Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish

value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 3

PACKAGE MATERIALS INFORMATION

www.ti.com

8-Jul-2013

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

TPS2000CDGKR

TPS2000CDGNR

VSSOP

DGK

DGN

2500

330.0

12.4

5.3

3.4

1.4

8.0

12.0

MSOP-

Power

PAD

TPS2001CDGKR

TPS2001CDGNR

VSSOP

DGK

DGN

2500

330.0

12.4

5.3

3.4

1.4

8.0

12.0

MSOP-

Power

PAD

TPS2041CDBVR

TPS2051CDBVR

TPS2061CDBVR

TPS2061CDGNR

SOT-23

DBV

DGN

3000

2500

178.0

330.0

9.0

3.23

5.3

3.17

3.4

1.37

1.4

4.0

8.0

9.0

8.0

MSOP-

Power

PAD

12.4

12.0

TPS2065CDBVR

TPS2065CDBVR-2

TPS2065CDGNR

SOT-23

DBV

DGN

3000

2500

178.0

330.0

9.0

3.23

5.3

3.17

3.4

1.37

1.4

4.0

8.0

MSOP-

Power

PAD

12.4

12.0

TPS2065CDGNR-2

MSOP-

Power

DGN

2500

330.0

12.4

5.3

3.4

1.4

8.0

12.0

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

8-Jul-2013

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

PAD

TPS2068CDGNR

MSOP-

Power

PAD

DGN

2500

330.0

12.4

5.3

3.4

1.4

8.0

12.0

TPS2069CDBVR

TPS2069CDGNR

SOT-23

DBV

DGN

3000

2500

178.0

330.0

9.0

3.23

5.3

3.17

3.4

1.37

1.4

4.0

8.0

MSOP-

Power

PAD

12.4

12.0

TPS2069CDGNR-2

MSOP-

Power

PAD

DGN

2500

330.0

12.4

5.3

3.4

1.4

8.0

12.0

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

TPS2000CDGKR

TPS2000CDGNR

TPS2001CDGKR

TPS2001CDGNR

TPS2041CDBVR

TPS2051CDBVR

TPS2061CDBVR

TPS2061CDGNR

VSSOP

MSOP-PowerPAD

VSSOP

DGK

DGN

DGK

DGN

DBV

DGN

2500

3000

2500

366.0

360.0

366.0

360.0

180.0

366.0

364.0

162.0

364.0

162.0

180.0

364.0

50.0

98.0

50.0

98.0

18.0

50.0

MSOP-PowerPAD

SOT-23

MSOP-PowerPAD

Pack Materials-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

8-Jul-2013

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

TPS2065CDBVR

TPS2065CDBVR-2

TPS2065CDGNR

TPS2065CDGNR-2

TPS2068CDGNR

TPS2069CDBVR

TPS2069CDGNR

TPS2069CDGNR-2

SOT-23

DBV

DGN

DBV

DGN

3000

2500

3000

2500

180.0

360.0

366.0

180.0

360.0

366.0

180.0

162.0

364.0

180.0

162.0

364.0

18.0

98.0

50.0

18.0

98.0

50.0

SOT-23

MSOP-PowerPAD

SOT-23

MSOP-PowerPAD

Pack Materials-Page 3

IMPORTANT NOTICE

Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other

changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest

issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and

complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale

supplied at the time of order acknowledgment.

TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms

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to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily

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TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and

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Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

TPS2041CDBVT [TI]

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