TPS2047BDG4 [TI]
CURRENT-LIMITED, POWER-DISTRIBUTION SWITCHES; 限流配电开关型号: | TPS2047BDG4 |
厂家: | TEXAS INSTRUMENTS |
描述: | CURRENT-LIMITED, POWER-DISTRIBUTION SWITCHES |
文件: | 总29页 (文件大小:881K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
TPS2045B, TPS2055B
DBV-5
D-8
D-16
TPS2046B, TPS2047B
www.ti.com
SLVS532C–JULY 2004–REVISED OCTOBER 2007
CURRENT-LIMITED, POWER-DISTRIBUTION SWITCHES
1
FEATURES
APPLICATIONS
•
Heavy Capacitive Loads
•
70-mΩ High-Side MOSFET
•
Short-Circuit Protections
•
•
•
•
•
•
•
•
•
250-mA Continuous Current
Thermal and Short-Circuit Protection
Accurate Current Limit (0.3 A min, 0.7 A max)
Operating Range: 2.7 V to 5.5 V
0.6-ms Typical Rise Time
TPS2047B
D PACKAGE
(TOP VIEW)
TPS2045B/TPS2055B
DBV PACKAGE
(TOP VIEW)
TPS2046B
D PACKAGE
(TOP VIEW)
OUT
IN
GND
IN
GND
IN1
OC1
OC1
OUT1
OUT2
OUT1
OUT2
OC2
GND
OC
EN1
EN2
EN1
EN2
GND
EN †
OC2
Undervoltage Lockout
OC3
Deglitched Fault Report (OC)
No OC Glitch During Power Up
TPS2045B/TPS2055B
D PACKAGE
(TOP VIEW)
IN2
OUT3
NC
NC
EN3
NC
GND
IN
OUT
OUT
OUT
Maximum Standby Supply Current:
1-μA (Single and Dual) or 2-μA (Triple)
NC - No Connection
IN
EN †
OC
•
•
•
•
Bidirectional Switch
†All enable inputs are active high (EN) for the TPS2055B.
Ambient Temperature Range: –40°C to 85°C
ESD Protection
UL Pending
DESCRIPTION
The TPS204xB/TPS2055B power-distribution switches are intended for applications where heavy capacitive
loads and short circuits are likely to be encountered. These devices incorporate 70-mΩ N-channel MOSFET
power switches for power-distribution systems that require multiple power switches in a single package. Each
switch is controlled by a logic-enable input. Gate drive is provided by an internal charge pump designed to
control the power-switch rise times and fall times to minimize current surges during switching. The charge pump
requires no external components and allows operation from supplies as low as 2.7 V.
When the output load exceeds the current-limit threshold or a short is present, the device limits the output current
to a safe level by switching into a constant-current mode, pulling the overcurrent (OCx) logic output low. When
continuous heavy overloads and short-circuits increase the power dissipation in the switch, causing the junction
temperature to rise, a thermal protection circuit shuts off the switch to prevent damage. Recovery from a thermal
shutdown is automatic once the device has cooled sufficiently. Internal circuitry ensures that the switch remains
off until valid input voltage is present. This power-distribution switch is designed to set current limit at 0.5 A
typically.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
UNLESS OTHERWISE NOTED this document contains
Copyright © 2004–2007, Texas Instruments Incorporated
PRODUCTION DATA information current as of publication date.
Products conform to specifications per the terms of Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
TPS2045B, TPS2055B
TPS2046B, TPS2047B
www.ti.com
SLVS532C–JULY 2004–REVISED OCTOBER 2007
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
AVAILABLE OPTIONS
RECOMMENDED
MAXIMUM
CONTINUOUS
LOAD CURRENT
(A)
TYPICAL
SHORT-CIRCUIT
CURRENT LIMIT
AT 25°C
NUMBER
OF
SWITCHES
PACKAGED
TA
ENABLE
DEVICES
(1)
(A)
SOIC (D)
SOT-23 (DBV)
SOIC (D)
TPS4045BD
TPS4045BDBV
TPS4055BD
TPS4055BDBV
TPS2046BD
TPS2047BD
Active low
Active high
Active low
0.25
0.25
0.25
0.5
0.5
0.5
Single
Single
–40°C to 85°C
SOT-23 (DBV)
SOIC (D)
Dual
Triple
SOIC (D)
(1) The D package is available taped and reeled. Add an R suffix to device type (e.g., TPS2046BDR)
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted(1)
UNIT
VI(IN), VI(INx)
VO(OUTx)
VI(/ENx)
Input voltage range(2)
Output voltage range
Input voltage range
Voltage range
–0.3 V to 6 V
(2)
–0.3 V to 6 V
–0.3 V to 6 V
–0.3 V to 6 V
VI(/OCx)
IO(OUTx)
Continuous output current
Internally limited
See Dissipation Rating Table
–40°C to 125°C
–65°C to 150°C
2 kV
Continuous total power dissipation
Operating virtual junction temperature range
Storage temperature range
TJ
Tstg
Human body model MIL-STD-883C
Charge device model (CDM)
ESD
Electrostatic discharge protection
500 V
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages are with respect to GND.
DISSIPATING RATING TABLE
T
A ≤ 25°C
DERATING FACTOR
ABOVE TA = 25°C
TA = 70°C
POWER RATING
TA = 85°C
POWER RATING
PACKAGE
POWER RATING
D-8
D-16
585.82 mW
5.8582 mW/°C
8.9847 mW/°C
3.086419 mW/°C
322.2 mW
494.15 mW
169.753 mW
234.32 mW
359.38 mW
898.47 mW
DBV-5
308.6419 mW
123.4567 mW
2
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Copyright © 2004–2007, Texas Instruments Incorporated
Product Folder Link(s): TPS2045B TPS2055B TPS2046B TPS2047B
TPS2045B, TPS2055B
TPS2046B, TPS2047B
www.ti.com
SLVS532C–JULY 2004–REVISED OCTOBER 2007
RECOMMENDED OPERATING CONDITIONS
MIN
2.7
0
MAX UNIT
VI(IN), VI(INx)
VI(/ENx), VI(ENx)
IO(OUT), IO(OUTx)
TJ
Input voltage
5.5
5.5
V
V
Input voltage
Continuous output current
Operating virtual junction temperature
0
250
125
mA
°C
-40
ELECTRICAL CHARACTERISTICS
over recommended operating junction temperature range, VI(IN) = 5.5 V, IO = 0.25 A, VI(ENx) = 0 V (unless otherwise noted)
PARAMETER
POWER SWITCH
TEST CONDITIONS(1)
MIN TYP MAX UNIT
Static drain-source on-state resistance,
5-V operation and 3.3-V operation
VI(IN) = 5 V or 3.3 V, IO = 0.25 A
–40°C ≤ TJ≤ 125°C
70 135 mΩ
75 150 mΩ
rDS(on)
Static drain-source on-state resistance,
2.7-V operation(2)
VI(IN) = 2.7 V,
IO = 0.25 A –40°C≤ TJ≤ 125°C
VI(IN) = 5.5 V
VI(IN) = 2.7 V
VI(IN) = 5.5 V
VI(IN) = 2.7 V
0.6
0.4
1.5
1
(2)
tr
Rise time, output
Fall time, output
CL = 1 μF,
TJ = 25°C
RL = 20 Ω
ms
0.05
0.05
0.5
0.5
tf(2)
ENABLE INPUT ENx
VIH
VIL
II
High-level input voltage
2.7 V ≤ VI(IN) ≤ 5.5 V
2.7 V ≤ VI(IN) ≤ 5.5 V
VI(/ENx) = 0 V or 5.5 V
CL = 100 μF, RL = 20 Ω
CL = 100 μF, RL = 20 Ω
2
V
Low-level input voltage
Input current
0.8
0.5
3
-0.5
μA
ms
(2)
ton
toff
Turnon time
(2)
Turnoff time
10
CURRENT LIMIT
VI(IN) = 5 V, OUT connected to GND, device enabled into
short-circuit
IOS
Short-circuit output current
0.3
0.5
0.7
A
SUPPLY CURRENT (TPS2045B, TPS2055B)
TJ = 25°C
0.5
0.5
43
1
5
No load on OUT, VI(/ENx) = 5.5 V
or VI(/ENx) = 0 V
Supply current, low-level output
μA
μA
–40°C ≤ TJ ≤ 125°C
TJ = 25°C
60
70
No load on OUT, VI(/ENx) = 0 V
or VI(/ENx) = 5.5 V
Supply current, high-level output
Leakage current
–40°C ≤ TJ ≤ 125°C
43
OUT connected to ground,
VI(/ENx) = 5.5 V, or VI(ENx) = 0 V
VI(OUTx) = 5.5 V, IN = ground(2)
–40°C ≤ TJ ≤ 125°C
TJ = 25°C
1
0
μA
μA
Reverse leakage current
SUPPLY CURRENT (TPS2046B)
TJ = 25°C
0.5
0.5
50
1
5
Supply current, low-level output
Supply current, high-level output
No load on OUT, VI(/ENx) = 5.5 V
No load on OUT, VI(/ENx) = 0 V
μA
μA
–40°C ≤ TJ ≤ 125°C
TJ = 25°C
70
90
-40°C ≤ TJ ≤ 125°C
50
OUT connected to ground,
VI(ENx) = 5.5 V
VI(OUTx) = 5.5 V, IN = ground(2)
Leakage current
-40°C ≤ TJ ≤ 125°C
TJ = 25°C
1
μA
μA
Reverse leakage current
0.2
(1) Pulse-testing techniques maintain junction temperature close to ambient temperature; thermal effects must be taken into account
separately.
(2) Not tested in production, specified by design.
Copyright © 2004–2007, Texas Instruments Incorporated
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3
Product Folder Link(s): TPS2045B TPS2055B TPS2046B TPS2047B
TPS2045B, TPS2055B
TPS2046B, TPS2047B
www.ti.com
SLVS532C–JULY 2004–REVISED OCTOBER 2007
ELECTRICAL CHARACTERISTICS (continued)
over recommended operating junction temperature range, VI(IN) = 5.5 V, IO = 0.25 A, VI(ENx) = 0 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS(1)
MIN TYP MAX UNIT
SUPPLY CURRENT (TPS2047B)
TJ = 25°C
0.5
0.5
65
2
10
90
Supply current, low-level output
No load on OUT, VI(/ENx) = 5.5 V
No load on OUT, VI(/ENx) = 0 V
μA
μA
–40°C ≤ TJ ≤ 125°C
TJ = 25°C
Supply current, high-level output
Leakage current
–40°C ≤ TJ ≤ 125°C
65 110
OUT connected to ground,
VI(/ENx) = 5.5 V
VI(OUTx) = 5.5 V, INx = ground(3)
–40°C≤ TJ≤ 125°C
TJ = 25°C
1
μA
μA
Reverse leakage current
UNDERVOLTAGE LOCKOUT
Low-level input voltage, IN, INx
Hysteresis, IN, INx
0.2
2
4
2.5
75
V
TJ = 25°C
mV
OVERCURRENT OC and OCx
Output low voltage, VOL(/OCx)
Off-state current(3)
IO(/OCx) = 5 mA
0.4
1
V
VO(/OCx) = 5 V or 3.3 V
OCx assertion or deassertion
μA
ms
OC deglitch(3)
8
15
THERMAL SHUTDOWN(4)
Thermal shutdown threshold(3)
Recovery from thermal shutdown(3)
Hysteresis(3)
135
125
°C
°C
°C
10
(3) Not tested in production, specified by design.
(4) The thermal shutdown only reacts under overcurrent conditions.
4
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Copyright © 2004–2007, Texas Instruments Incorporated
Product Folder Link(s): TPS2045B TPS2055B TPS2046B TPS2047B
TPS2045B, TPS2055B
TPS2046B, TPS2047B
www.ti.com
SLVS532C–JULY 2004–REVISED OCTOBER 2007
DEVICE INFORMATION
Terminal Functions (TPS2045B and TPS2055B)
TERMINAL
D PACKAGE
I/O
DESCRIPTION
DBV PACKAGE
TPS2045B TPS2055B
NAME TPS2045B
TPS2055B
EN
4
-
4
4
-
I
I
Enable input, logic low turns on power switch
Enable input, logic high turns on power switch
Ground
EN
-
1
-
4
2
5
3
1
GND
IN
1
2
5
3
1
2, 3
5
2, 3
5
I
Input voltage
OC
OUT
O
O
Overcurrent open-drain output, active-low
Power-switch output
6, 7, 8
6, 7, 8
FUNCTIONAL BLOCK DIAGRAM (TPS2045B and TPS2055B)
(See Note A)
CS
OUT
IN
Charge
Pump
Current
EN
Driver
Limit
(See Note B)
OC
UVLO
Deglitch
Thermal
GND
Sense
A. Current sense
B. Active low (EN) for TPS2045B. Active high (EN) for TPS2055B.
Copyright © 2004–2007, Texas Instruments Incorporated
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Product Folder Link(s): TPS2045B TPS2055B TPS2046B TPS2047B
TPS2045B, TPS2055B
TPS2046B, TPS2047B
www.ti.com
SLVS532C–JULY 2004–REVISED OCTOBER 2007
Terminal Functions (TPS2046B)
TERMINAL
I/O
DESCRIPTION
NAME
EN1
NUMBER
3
4
1
2
8
5
7
6
I
I
Enable input, logic low turns on power switch IN-OUT1
Enable input, logic low turns on power switch IN-OUT2
Ground
EN2
GND
IN
I
Input voltage
OC1
OC2
OUT1
OUT2
O
O
O
O
Overcurrent, open-drain output, active low, IN-OUT1
Overcurrent, open-drain output, active low, IN-OUT2
Power-switch output, IN-OUT1
Power-switch output, IN-OUT2
FUNCTIONAL BLOCK DIAGRAM (TPS2046B)
OC1
Thermal
Deglitch
Sense
GND
EN1
Current
Driver
Limit
Charge
Pump
(See Note A)
CS
OUT1
OUT2
UVLO
(See Note A)
CS
IN
Charge
Pump
Current
Driver
Limit
OC2
EN2
Thermal
Sense
Deglitch
A. Current sense
6
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Product Folder Link(s): TPS2045B TPS2055B TPS2046B TPS2047B
TPS2045B, TPS2055B
TPS2046B, TPS2047B
www.ti.com
SLVS532C–JULY 2004–REVISED OCTOBER 2007
Terminal Functions (TPS2047B)
TERMINAL
I/O
DESCRIPTION
NAME
EN1
NUMBER
3
4
I
I
I
Enable input, logic low turns on power switch IN1-OUT1
Enable input, logic low turns on power switch IN1-OUT2
Enable input, logic low turns on power switch IN2-OUT3
Ground
EN2
EN3
GND
IN1
7
1, 5
2
I
I
Input voltage for OUT1 and OUT2
IN2
6
Input voltage for OUT3
NC
8, 9, 10
16
No connection
OC1
OC2
OC3
OUT1
OUT2
OUT3
O
O
O
O
O
O
Overcurrent, open-drain output, active low, IN1-OUT1
Overcurrent, open-drain output, active low, IN1-OUT2
Overcurrent, open-drain output, active low, IN2-OUT3
Power-switch output, IN1-OUT1
13
12
15
14
Power-switch output, IN1-OUT2
11
Power-switch output, IN2-OUT3
FUNCTIONAL BLOCK DIAGRAM (TPS2047B)
OC1
Thermal
GND
EN1
Sense
Deglitch
Current
Limit
Driver
(See Note A)
CS
CS
OUT1
OUT2
UVLO
(See Note A)
IN1
Current
Limit
Driver
OC2
EN2
Thermal
Sense
Deglitch
Charge
Pump
VCC
Selector
(See Note A)
IN2
CS
OUT3
Current
Limit
EN3
Driver
OC3
UVLO
Deglitch
Thermal
Sense
GND
A. Current sense
Copyright © 2004–2007, Texas Instruments Incorporated
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Product Folder Link(s): TPS2045B TPS2055B TPS2046B TPS2047B
TPS2045B, TPS2055B
TPS2046B, TPS2047B
www.ti.com
SLVS532C–JULY 2004–REVISED OCTOBER 2007
PARAMETER MEASUREMENT INFORMATION
OUT
t
f
t
r
R
L
C
L
V
90%
10%
O(OUT)
90%
10%
TEST CIRCUIT
50%
90%
50%
50%
50%
V
V
I(EN)
I(EN)
t
off
t
off
t
on
t
on
90%
V
V
O(OUT)
O(OUT)
10%
10%
VOLTAGE WAVEFORMS
Figure 1. Test Circuit and Voltage Waveforms
R
C
T
A
= 20 W,
= 1 mF
= 255C
L
L
V
V
V
I(EN)
I(EN)
I(EN)
5 V/div
5 V/div
R
C
T
= 20 W,
= 1 mF
= 255C
L
L
V
O(OUT)
2 V/div
V
A
O(OUT)
2 V/div
t - Time - 500 ms/div
t - Time - 500 ms/div
Figure 2. Turnon Delay and Rise Time With 1-μF Load
Figure 3. Turnoff Delay and Fall Time With 1-μF Load
8
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Product Folder Link(s): TPS2045B TPS2055B TPS2046B TPS2047B
TPS2045B, TPS2055B
TPS2046B, TPS2047B
www.ti.com
SLVS532C–JULY 2004–REVISED OCTOBER 2007
PARAMETER MEASUREMENT INFORMATION (continued)
V
I(EN)
V
I(EN)
5 V/div
5 V/div
V
O(OUT)
2 V/div
R = 20 W,
L
V
O(OUT)
C = 100 mF
L
2 V/div
T = 255C
A
t - Time - 1 ms
t - Time - 1 ms
Figure 5. Turnoff Delay and Fall Time With 100-μF Load
Figure 4. Turnon Delay and Rise Time With 100-μF Load
V = 5 V,
I
V
V
I(EN)
I(EN)
R = 20 W,
L
5 V/div
5 V/div
T = 255C
A
150 mF
300 mF
I
O(OUT)
I
O(OUT)
250 mA/div
250 mA/div
68 mF
t - Time - 2 ms
t - Time - 500 ms/div
Figure 6. Short-Circuit Current,
Device Enabled Into Short
Figure 7. Inrush Current With Different
Load Capacitance
Copyright © 2004–2007, Texas Instruments Incorporated
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Product Folder Link(s): TPS2045B TPS2055B TPS2046B TPS2047B
TPS2045B, TPS2055B
TPS2046B, TPS2047B
www.ti.com
SLVS532C–JULY 2004–REVISED OCTOBER 2007
PARAMETER MEASUREMENT INFORMATION (continued)
V
O(OC)
V
O(OC)
2 V/div
2 V/div
I
I
O(OUT)
O(OUT)
250 mA/div
250 mA/div
t - Time - 2 ms/div
Figure 8. 4-Ω Load Connected to Enabled Device
t - Time - 2 ms/div
Figure 9. 3-Ω Load Connected to Enabled Device
TYPICAL CHARACTERISTICS
TURNON TIME
vs
INPUT VOLTAGE
TURNOFF TIME
vs
INPUT VOLTAGE
1.6
1.4
1.2
1
6
5
C
R
T
A
= 100 mF,
= 20 W,
= 255C
L
L
C = 100 mF,
L
4
3
R
L
= 20 W,
= 255C
T
A
0.8
0.6
2
0.4
1
0
0.2
0
2
3
4
5
6
2
3
4
5
6
V - Input Voltage - V
I
V - Input Voltage - V
I
Figure 10.
Figure 11.
10
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Product Folder Link(s): TPS2045B TPS2055B TPS2046B TPS2047B
TPS2045B, TPS2055B
TPS2046B, TPS2047B
www.ti.com
SLVS532C–JULY 2004–REVISED OCTOBER 2007
TYPICAL CHARACTERISTICS (continued)
RISE TIME
vs
INPUT VOLTAGE
FALL TIME
vs
INPUT VOLTAGE
160
140
500
450
400
C = 1 mF,
L
C = 1 mF,
L
R = 20 W,
L
R = 20 W,
T = 255C
A
L
T = 255C
A
120
100
80
350
300
250
200
150
60
40
100
50
20
0
0
2
3
4
5
6
2
3
4
5
6
V - Input Voltage - V
I
V - Input Voltage - V
I
Figure 12.
Figure 13.
TPS2046B
TPS2047B
SUPPLY CURRENT, OUTPUT ENABLED
SUPPLY CURRENT, OUTPUT ENABLED
vs
vs
JUNCTION TEMPERATURE
JUNCTION TEMPERATURE
90
80
70
60
50
40
30
20
70
60
50
40
30
20
10
V = 5.5 V
I
V = 5.5 V
I
V = 5 V
I
V = 5 V
I
V = 3.3 V
I
V = 3.3 V
I
V = 2.7 V
I
V = 2.7 V
I
10
0
0
−50
0
50
100
150
−50
0
50
100
150
T − Junction Temperature − 5C
J
T − Junction Temperature − 5C
J
Figure 14.
Figure 15.
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Product Folder Link(s): TPS2045B TPS2055B TPS2046B TPS2047B
TPS2045B, TPS2055B
TPS2046B, TPS2047B
www.ti.com
SLVS532C–JULY 2004–REVISED OCTOBER 2007
TYPICAL CHARACTERISTICS (continued)
TPS2046B
SUPPLY CURRENT, OUTPUT DISABLED
vs
TPS2047B
SUPPLY CURRENT, OUTPUT DISABLED
vs
JUNCTION TEMPERATURE
JUNCTION TEMPERATURE
0.5
0.45
0.4
0.5
V = 5.5 V
I
V = 5.5 V
0.45
I
V = 5 V
V = 5 V
I
I
0.4
0.35
0.3
0.35
0.3
V = 3.3 V
I
V = 3.3 V
I
V = 2.7 V
I
V = 2.7 V
I
0.25
0.2
0.25
0.2
0.15
0.1
0.15
0.1
0.05
0.05
0
−50
0
−50
0
50
100
150
0
50
100
150
T − Junction Temperature − 5C
J
T − Junction Temperature − 5C
J
Figure 16.
Figure 17.
STATIC DRAIN-SOURCE ON-STATE RESISTANCE
SHORT-CIRCUIT OUTPUT CURRENT
vs
vs
JUNCTION TEMPERATURE
JUNCTION TEMPERATURE
0.54
0.53
0.52
0.51
0.5
120
100
80
I
O
= 0.25 A
V = 2.7 V
I
V = 2.7 V
I
V = 3.3 V
I
V
I
= 3.3 V
60
0.49
0.48
0.47
V
I
= 5 V
V = 5 V
I
40
V = 5.5 V
I
20
0
0.46
0.45
-50
0
50
100
150
-50
0
50
100
150
T - Junction Temperature - 5C
J
T - Junction Temperature - 5C
J
Figure 18.
Figure 19.
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SLVS532C–JULY 2004–REVISED OCTOBER 2007
TYPICAL CHARACTERISTICS (continued)
THRESHOLD TRIP CURRENT
UNDERVOLTAGE LOCKOUT
vs
JUNCTION TEMPERATURE
vs
INPUT VOLTAGE
1.5
2.3
T
A
= 255C
Load Ramp = 1A/10 ms
UVLO Rising
UVLO Falling
1.3
1.1
0.9
2.26
2.22
2.18
0.7
0.5
2.14
2.1
2.5
3
3.5
4
4.5
5
5.5
6
−50
0
50
100
150
V - Input Voltage - V
I
T − Junction Temperature − 5C
J
Figure 20.
Figure 21.
CURRENT-LIMIT RESPONSE
vs
PEAK CURRENT
200
V = 5 V,
I
T
A
= 255C
150
100
50
0
0
1
2
3
4
5
Peak Current - A
Figure 22.
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SLVS532C–JULY 2004–REVISED OCTOBER 2007
APPLICATION INFORMATION
POWER-SUPPLY CONSIDERATIONS
TPS2046B
2
Power Supply
2.7 V to 5.5 V
IN
7
6
Load
Load
OUT1
0.1 µF
0.1 µF
0.1 µF
22 µF
22 µF
8
OC1
EN1
OC2
3
5
OUT2
4
EN2
GND
1
Figure 23. Typical Application (Example, TPS2046B)
A 0.01-μF to 0.1-μF ceramic bypass capacitor between IN and GND, close to the device, is recommended.
Placing a high-value electrolytic capacitor on the output pin(s) is recommended when the output load is heavy.
This precaution reduces power-supply transients that may cause ringing on the input. Additionally, bypassing the
output with a 0.01-μF to 0.1-μF ceramic capacitor improves the immunity of the device to short-circuit transients.
OVERCURRENT
A sense FET is employed to check for overcurrent conditions. Unlike current-sense resistors, sense FETs do not
increase the series resistance of the current path. When an overcurrent condition is detected, the device
maintains a constant output current and reduces the output voltage accordingly. Complete shutdown occurs only
if the fault is present long enough to activate thermal limiting.
Three possible overload conditions can occur. In the first condition, the output has been shorted before the
device is enabled or before VI(IN) has been applied (see Figure 6). The TPS204xB/TPS2055B senses the short,
and immediately switches into a constant-current output.
In the second condition, a short or an overload occurs while the device is enabled. At the instant the overload
occurs, high currents may flow for a short period of time before the current-limit circuit can react. After the
current-limit circuit has tripped (reached the overcurrent trip threshold), the device switches into constant-current
mode.
In the third condition, the load has been gradually increased beyond the recommended operating current. The
current is permitted to rise until the current-limit threshold is reached or until the thermal limit of the device is
exceeded. The TPS204xB/TPS2055B is capable of delivering current up to the current-limit threshold without
damaging the device. Once the threshold has been reached, the device switches into its constant-current mode.
OC RESPONSE
The OCx open-drain output is asserted (active low) when an overcurrent or overtemperature shutdown condition
is encountered after a 10-ms deglitch timeout. The output remains asserted until the overcurrent or
overtemperature condition is removed. Connecting a heavy capacitive load to an enabled device can cause a
momentary overcurrent condition; however, no false reporting on OCx occurs due to the 10-ms deglitch circuit.
The TPS204xB/TPS2055B is designed to eliminate false overcurrent reporting. The internal overcurrent deglitch
eliminates the need for external components to remove unwanted pulses. OCx is not deglitched when the switch
is turned off due to an overtemperature shutdown.
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SLVS532C–JULY 2004–REVISED OCTOBER 2007
V+
R
pullup
TPS2046B
GND
OC1
OUT1
OUT2
OC2
IN
EN1
EN2
Figure 24. Typical Circuit for the OC Pin (Example, TPS2046B)
POWER DISSIPATION AND JUNCTION TEMPERATURE
The low on-resistance on the N-channel MOSFET allows the small surface-mount packages to pass large
currents. The thermal resistances of these packages are high compared to those of power packages; it is good
design practice to check power dissipation and junction temperature. Begin by determining the rDS(on) of the
N-channel MOSFET relative to the input voltage and operating temperature. As an initial estimate, use the
highest operating ambient temperature of interest and read rDS(on) from Figure 18. Using this value, the power
dissipation per switch can be calculated by:
•
PD = rDS(on) × I2
Multiply this number by the number of switches being used. This step renders the total power dissipation from
the N-channel MOSFETs.
Finally, calculate the junction temperature:
•
TJ = PD × RθJA + TA
Where:
•
•
•
TA= Ambient temperature °C
θJA = Thermal resistance
PD = Total power dissipation based on number of switches being used.
R
Compare the calculated junction temperature with the initial estimate. If they do not agree within a few degrees,
repeat the calculation, using the calculated value as the new estimate. Two or three iterations are generally
sufficient to get a reasonable answer.
THERMAL PROTECTION
Thermal protection prevents damage to the IC when heavy-overload or short-circuit faults are present for
extended periods of time. The TPS204xB/TPS2055B implements a thermal sensing to monitor the operating
junction temperature of the power distribution switch. In an overcurrent or short-circuit condition, the junction
temperature rises due to excessive power dissipation. Once the die temperature rises to approximately 140°C
due to overcurrent conditions, the internal thermal sense circuitry turns the power switch off, thus preventing the
power switch from damage. Hysteresis is built into the thermal sense circuit, and after the device has cooled
approximately 10°C, the switch turns back on. The switch continues to cycle in this manner until the load fault or
input power is removed. The OCx open-drain output is asserted (active low) when an overtemperature shutdown
or overcurrent occurs.
UNDERVOLTAGE LOCKOUT (UVLO)
An undervoltage lockout ensures that the power switch is in the off state at power up. Whenever the input
voltage falls below approximately 2 V, the power switch is quickly turned off. This facilitates the design of
hot-insertion systems where it is not possible to turn off the power switch before input power is removed. The
UVLO also keeps the switch from being turned on until the power supply has reached at least 2 V, even if the
switch is enabled. On reinsertion, the power switch is turned on, with a controlled rise time to reduce EMI and
voltage overshoots.
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SLVS532C–JULY 2004–REVISED OCTOBER 2007
UNIVERSAL SERIAL BUS (USB) APPLICATIONS
The universal serial bus (USB) interface is a 12-Mb/s, or 1.5-Mb/s, multiplexed serial bus designed for
low-to-medium bandwidth PC peripherals (e.g., keyboards, printers, scanners, and mice). The four-wire USB
interface is conceived for dynamic attach-detach (hot plug-unplug) of peripherals. Two lines are provided for
differential data, and two lines are provided for 5-V power distribution.
USB data is a 3.3-V level signal, but power is distributed at 5 V to allow for voltage drops in cases where power
is distributed through more than one hub across long cables. Each function must provide its own regulated 3.3 V
from the 5-V input or its own internal power supply.
The USB specification defines the following five classes of devices, each differentiated by power-consumption
requirements:
•
•
•
•
•
Hosts/self-powered hubs (SPH)
Bus-powered hubs (BPH)
Low-power, bus-powered functions
High-power, bus-powered functions
Self-powered functions
Self-powered and bus-powered hubs distribute data and power to downstream functions. The
TPS204xB/TPS2055B can provide-power distribution solutions to many of these classes of devices.
HOST/SELF-POWERED AND BUS-POWERED HUBS
Hosts and self-powered hubs have a local power supply that powers the embedded functions and the
downstream ports. This power supply must provide from 5.25 V to 4.75 V to the board side of the downstream
connection under full-load and no-load conditions. Hosts and SPHs are required to have current-limit protection
and must report overcurrent conditions to the USB controller. Typical SPHs are desktop PCs, monitors, printers,
and stand-alone hubs.
Bus-powered hubs obtain all power from upstream ports and often contain an embedded function. The hubs are
required to power up with less than one unit load. The BPH usually has one embedded function, and power is
always available to the controller of the hub. If the embedded function and hub require more than 100 mA on
power up, the power to the embedded function may need to be kept off until enumeration is completed. This can
be accomplished by removing power or by shutting off the clock to the embedded function. Power switching the
embedded function is not necessary if the aggregate power draw for the function and controller is less than one
unit load. The total current drawn by the bus-powered device is the sum of the current to the controller, the
embedded function, and the downstream ports, and it is limited to 500 mA from an upstream port.
LOW-POWER BUS-POWERED AND HIGH-POWER BUS-POWERED FUNCTIONS
Both low-power and high-power bus-powered functions obtain all power from upstream ports; low-power
functions always draw less than 100 mA; high-power functions must draw less than 100 mA at power up and can
draw up to 500 mA after enumeration. If the load of the function is more than the parallel combination of 44 Ω
and 10 μF at power up, the device must implement inrush current limiting (see Figure 25).
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SLVS532C–JULY 2004–REVISED OCTOBER 2007
Power Supply
3.3 V
D+
D-
TPS2046B
2
8
IN
V
BUS
7
10 µF
0.1 µF
Internal
OUT1
GND
Function
0.1 µF
10 µF
OC1
EN1
OC2
EN2
3
5
USB
Control
6
4
OUT2
GND
Internal
Function
0.1 µF
10 µF
1
Figure 25. High-Power Bus-Powered Function (Example, TPS2046B)
USB POWER-DISTRIBUTION REQUIREMENTS
USB can be implemented in several ways, and, regardless of the type of USB device being developed, several
power-distribution features must be implemented.
•
•
Hosts/self-powered hubs must:
–
–
Current-limit downstream ports
Report overcurrent conditions on USB VBUS
Bus-powered hubs must:
–
–
–
Enable/disable power to downstream ports
Power up at <100 mA
Limit inrush current (<44 Ω and 10 μF)
•
Functions must:
–
–
Limit inrush currents
Power up at <100 mA
The feature set of the TPS204xB/TPS2055B allows them to meet each of these requirements. The integrated
current-limiting and overcurrent reporting is required by hosts and self-powered hubs. The logic-level enable and
controlled rise times meet the need of both input and output ports on bus-powered hubs, as well as the input
ports for bus-powered functions (see Figure 26 through Figure 27).
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SLVS532C–JULY 2004–REVISED OCTOBER 2007
TUSB2040
Hub Controller
SN75240
BUSPWR
Tie to TPS2041B EN Input
Downstream
Ports
Upstream
Port
A
B
C
D
GANGED
DP1
DM1
D +
D -
DP0
DM0
D +
D -
Ferrite Beads
A
B
C
D
GND
5 V
†
GND
SN75240
DP2
DM2
TPS2041B
OC EN
IN OUT
1 µF
33 µF
5-V Power
Supply
DP3
DM3
5 V
D +
D -
A
B
C
D
Ferrite Beads
TPS76333
IN
SN75240
GND
DP4
DM4
0.1 µF
4.7 µF
V
CC
3.3 V
GND
5 V
†
4.7 µF
TPS2046B
PWRON1
GND
EN1
OC1
OUT1
OUT2
33 µF
OVRCUR1
PWRON2
OVRCUR2
48-MHz
Crystal
EN2
OC2
XTAL1
XTAL2
D +
D -
IN
0.1 µF
Ferrite Beads
Tuning
Circuit
GND
5 V
†
TPS2046B
EN1
PWRON3
OUT1
OCSOFF
GND
OC1 OUT2
EN2
OVRCUR3
33 µF
PWRON4
OC2
IN
OVRCUR4
D +
D -
0.1 µF
Ferrite Beads
GND
5 V
†
33 µF
†
USB rev 1.1 requires 120 µF per hub.
Figure 26. Hybrid Self/Bus-Powered Hub Implementation, TPS2046B
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www.ti.com
SLVS532C–JULY 2004–REVISED OCTOBER 2007
TUSB2040
Hub Controller
1/2 SN75240
BUSPWR
Tie to TPS2041B EN Input
Downstream
Ports
Upstream
Port
A
B
C
D
GANGED
DP1
DM1
D +
D -
DP0
DM0
D +
D -
Ferrite Beads
A
B
C
D
GND
5 V
†
GND
SN75240
DP2
DM2
TPS2041B
47 µF
5-V Power
Supply
OC
IN
EN
OUT
DP3
DM3
5 V
D +
D -
A
B
C
D
1 µF
Ferrite Beads
TPS76333
IN
1/2 SN75240
GND
0.1 µF
4.7 µF
V
3.3 V
GND
CC
5 V
†
4.7 µF
TPS2047B
PWRON1
GND
EN1
OC1
OUT1
47 µF
OUT2
IN1
OVRCUR1
PWRON2
OVRCUR2
EN2
OC2
D +
D -
48-MHz
Crystal
XTAL1
XTAL2
0.1 µF
Ferrite Beads
GND
5 V
†
PWRON3
EN3
OC3
Tuning
Circuit
OUT3
IN2
OVRCUR3
47 µF
OCSOFF
GND
0.1 µF
GND
GND
†
USB rev 1.1 requires 120 µF per hub.
Figure 27. Hybrid Self / Bus-Powered Hub Implementation, TPS2047B
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SLVS532C–JULY 2004–REVISED OCTOBER 2007
GENERIC HOT-PLUG APPLICATIONS
In many applications it may be necessary to remove modules or pc boards while the main unit is still operating.
These are considered hot-plug applications. Such implementations require the control of current surges seen by
the main power supply and the card being inserted. The most effective way to control these surges is to limit and
slowly ramp the current and voltage being applied to the card, similar to the way in which a power supply
normally turns on. Due to the controlled rise times and fall times of the TPS204xB/TPS2055B, these devices can
be used to provide a softer start-up to devices being hot-plugged into a powered system. The UVLO feature of
the TPS204xB/TPS2055B also ensures that the switch is off after the card has been removed, and that the
switch is off during the next insertion. The UVLO feature insures a soft start with a controlled rise time for every
insertion of the card or module.
PC Board
TPS2046B
Power
Supply
Block of
Circuitry
OC1
GND
2.7 V to 5.5 V
IN
OUT1
OUT2
0.1 µF
EN1
EN2
1000 µF
Optimum
OC2
Block of
Circuitry
Overcurrent Response
Figure 28. Typical Hot-Plug Implementation (Example, TPS2046B)
By placing the TPS204xB/TPS2055B between the VCC input and the rest of the circuitry, the input power reaches
these devices first after insertion. The typical rise time of the switch is approximately 1 ms, providing a slow
voltage ramp at the output of the device. This implementation controls system surge currents and provides a
hot-plugging mechanism for any device.
DETAILED DESCRIPTION
POWER SWITCH
The power switch is an N-channel MOSFET with a low on-state resistance. Configured as a high-side switch, the
power switch prevents current flow from OUT to IN and IN to OUT when disabled. The power switch supplies a
minimum current of 250 mA.
CHARGE PUMP
An internal charge pump supplies power to the driver circuit and provides the necessary voltage to pull the gate
of the MOSFET above the source. The charge pump operates from input voltages as low as 2.7 V and requires
little supply current.
DRIVER
The driver controls the gate voltage of the power switch. To limit large current surges and reduce the associated
electromagnetic interference (EMI) produced, the driver incorporates circuitry that controls the rise times and fall
times of the output voltage.
ENABLE (ENx)
The logic enable pin disables the power switch and the bias for the charge pump, driver, and other circuitry to
reduce the supply current. The supply current is reduced to less than 1 μA or 2 μA when a logic high is present
on EN. A logic zero input on EN restores bias to the drive and control circuits and turns the switch on. The
enable input is compatible with both TTL and CMOS logic levels.
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SLVS532C–JULY 2004–REVISED OCTOBER 2007
ENABLE (ENx)
The logic enable disables the power switch and the bias for the charge pump, driver, and other circuitry to reduce
the supply current. The supply current is reduced to less than 1 μA or 2 μA when a logic low is present on ENx.
A logic high input on ENx restores bias to the drive and control circuits and turns the switch on. The enable input
is compatible with both TTL and CMOS logic levels.
OVERCURRENT (OCx)
The OCx open-drain output is asserted (active low) when an overcurrent or overtemperature condition is
encountered. The output remains asserted until the overcurrent or overtemperature condition is removed. A
10-ms deglitch circuit prevents the OCx signal from oscillation or false triggering. If an overtemperature shutdown
occurs, the OCx is asserted instantaneously.
CURRENT SENSE
A sense FET monitors the current supplied to the load. The sense FET measures current more efficiently than
conventional resistance methods. When an overload or short circuit is encountered, the current-sense circuitry
sends a control signal to the driver. The driver in turn reduces the gate voltage and drives the power FET into its
saturation region, which switches the output into a constant-current mode and holds the current constant while
varying the voltage on the load.
THERMAL SENSE
The TPS204xB/TPS2055B implements a thermal sensing to monitor the operating temperature of the power
distribution switch. In an overcurrent or short-circuit condition, the junction temperature rises. When the die
temperature rises to approximately 140°C due to overcurrent conditions, the internal thermal sense circuitry turns
off the switch, thus preventing the device from damage. Hysteresis is built into the thermal sense, and after the
device has cooled approximately 10 degrees, the switch turns back on. The switch continues to cycle off and on
until the fault is removed. The open-drain false reporting output (OCx) is asserted (active low) when an
overtemperature shutdown or overcurrent occurs.
UNDERVOLTAGE LOCKOUT
A voltage sense circuit monitors the input voltage. When the input voltage is below approximately 2 V, a control
signal turns off the power switch.
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PACKAGE OPTION ADDENDUM
www.ti.com
16-Mar-2007
PACKAGING INFORMATION
Orderable Device
TPS2046BD
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SOIC
D
8
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TPS2046BDG4
TPS2046BDR
TPS2046BDRG4
TPS2047BD
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
D
D
D
D
D
D
D
8
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
8
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
8
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
16
16
16
16
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TPS2047BDG4
TPS2047BDR
TPS2047BDRG4
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Sep-2008
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0 (mm)
B0 (mm)
K0 (mm)
P1
W
Pin1
Diameter Width
(mm) W1 (mm)
(mm) (mm) Quadrant
TPS2046BDR
TPS2047BDR
SOIC
SOIC
D
D
8
2500
2500
330.0
330.0
12.4
16.4
6.4
6.5
5.2
2.1
2.1
8.0
8.0
12.0
16.0
Q1
Q1
16
10.3
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Sep-2008
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPS2046BDR
TPS2047BDR
SOIC
SOIC
D
D
8
2500
2500
340.5
333.2
338.1
345.9
20.6
28.6
16
Pack Materials-Page 2
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TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms
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相关型号:
TPS2047DG4
0.345A, 2.7-5.5V Triple (2In/3Out) Hi-Side MOSFET, Fault Report, Act-Low Enable 16-SOIC -40 to 85
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