TPS2147_技术文档

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SLVS333 − AUGUST 2001

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FEATURES

DESCRIPTION

D

Two 340-mΩ (Typical) High-Side MOSFETs

200 mA Low-Dropout Voltage Regulator In

Fixed 3.3-V or Adjustable Versions

Two power-distribution switches and an adjustable

(TPS2145) or fixed (TPS2147) LDO are incorporated in

one small package, providing a power management

solution that saves up to 60% in board space over

typical implementations.

D

Independent Thermal- and Short-Circuit

Protection for LDO and Each Switch

D

Overcurrent Indicators With Transient Filter

2.9-V to 5.5-V Operating Range

Designed to meet USB 2.0 bus-powered hub

requirements, these devices also allow core and I/O

voltage sequencing in DSP applications, or power

segmentation in portable equipment. Each current-

limited switch is a 340-mΩ N-channel MOSFET capable

of supplying 200 mA of continuous current. A logic

enable compatible with 5-V logic and 3-V logic controls

each MOSFET as well as the LDO in the TPS2145. The

internal charge pump provides the gate drive controlling

the power-switch rise times and fall times, minimizing

current surges during switching. The charge pump

requires no external components.

CMOS- and TTL-Compatible Enable Inputs

75-µA (Typical) Supply Current

Available in 10-Pin MSOP or 14-Pin TSSOP

(PowerPAD)

D

−40°C to 85°C Ambient Temperature Range

APPLICATIONS

D

USB Hubs and Peripherals

− Keyboards

− Zip Drives

The LDO has a drop-out voltage of only 0.35 V and with

the independent enable on the TPS2145 LDO, the LDO

can be used as an additional switch. The LDO output

range for the TPS2145 is 1 V to 3.3 V, while the

TPS2147 is fixed at 3.3 V.

− Speakers and Headsets

D

PDAs and Portable Electronics

DSP Power Sequencing

The TPS2145 and TPS2147 have active-low switch

enables and the TPS2155 and TPS2157 have

active-high switch enables.

LDO and dual switch family selection guide and schematics

TPS2149/59

MSOP−8

TPS2148/58

MSOP−8

TPS2145/55

TSSOP−14

TPS2147/57

MSOP−10

LDO_OUT

LDO_ADJ

VIN/SW1

VIN

LDO

LDO_OUT

VIN/SW1

LDO_EN

VIN/SW1

LDO_OUT

LDO

LDO_EN

EN2

OC1

OUT2

OUT1

OC

OUT1

EN1

OUT1

OUT2

OC2

OUT2

OC2

SW2

EN1

GND

EN2

GND

EN2

GND

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PowerPAD is a trademark of Texas Instruments.

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Copyright  2001, Texas Instruments Incorporated

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1

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SLVS333 − AUGUST 2001

AVAILABLE OPTIONS

PACKAGED DEVICES

PACKAGE

AND PIN

COUNT

T

A

DESCRIPTION

ACTIVE LOW

ACTIVE HIGH

(SWITCH)

TPS2145IPWP

TPS2147IDGQ

Adjustable LDO with LDO enable

3.3-V fixed LDO

TSSOP-14

MSOP-10

TPS2155IPWP

TPS2157IDGQ

−40°C to 85°C

3.3-V Fixed LDO with LDO enable and LDO output

switch

MSOP-8

TPS2148IDGN

TPS2149IDGN

TPS2158IDGN

TPS2159IDGN

3.3-V Fixed LDO, shared input with switches

NOTE: All options available taped and reeled. Add an R suffix (e.g. TPS2145IPWPR)

TPS2145, TPS2155

TSSOP (PWP) PACKAGE

(TOP VIEW)

TPS2147, TPS2157

MSOP (DGQ) PACKAGE

(TOP VIEW)

†

EN1

EN2

1

2

3

4

5

6

7

14

13

12

11

10

9

OUT1

VIN/SWIN1

SWIN2

LDO_OUT

OUT2

†

OUT1

VIN/SWIN1

SWIN2

EN1

EN2

1

2

3

4

5

10

9

†

OC1

OC2

LDO_EN

NC

GND

8

OC1

OC2

GND

LDO_OUT

OUT2

7

6

NC

LDO_ADJ

8

†

Pin 9 and 10 are active high for TPS2157.

NC − No internal connection

†

Pin 13 and 14 are active high for TPS2155.

†

absolute maximum ratings over operating free-air temperature (unless otherwise noted)

Input voltage range: V

Output voltage range: V

Maximum output current, I

Continuous output current, I

, V

,V

, V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 6 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 6 V

I(VIN/SWIN1) I(SWIN2) I(ENx) I(LDO_EN)

, V

O(OUTx) O(LDO_OUT) O(OCx)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 mA

O(OCx)

I

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internally limited

O(OUTx), O(LDO_OUT)

Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table

Operating virtual-junction temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 110°C

J

Storage temperature range, T

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C

stg

Lead temperature soldering 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C

Electrostatic discharge (ESD) protection: Human body model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 kV

Charged device model (CDM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 kV

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

All voltages are with respect to GND.

‡

DISSIPATION RATING TABLE

T

≤ 25°C

DERATING FACTOR

T

= 70°C

T = 85°C

A

PACKAGE

POWER RATING

ABOVE T = 25°C

POWER RATING POWER RATING

A

MSOP10

PWP14

1293.1 mW

17.2 mW/°C

26.6 mW/°C

517.2 mW

800 mW

258.6 mW

400 mW

2000 mW

2

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SLVS333 − AUGUST 2001

recommended operating conditions

MIN

2.9

0

MAX

5.5

UNIT

V

I(VIN/SWIN1)

I(SWIN2)

I(ENx)

5.5

Input voltage

V

5.5

0

5.5

I(LDO_EN)

LDO_OUT

200

150

550

400

100

Continuous output current, I

mA

O

OUT1, OUT2

LDO_OUT

275

200

−40

Output current limit, I

O(LMT)

mA

OUT1, OUT2

Operating virtual-junction temperature range, T

°C

J

electrical characteristics over recommended operating junction-temperature range,

2.9 V ≤ V

≤ 5.5 V, 2.9 V ≤ V

≤ 5.5 V, T = −40°C to 100°C (unless otherwise noted)

I(VIN/SWIN1)

I(SWIN2) J

general

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

V

= 5 V (inactive),

I(ENx)

= 0 V (inactive),

I(LDO_EN)

Off-state supply current

Forward leakage current

20

µA

= no load,

O(LDO_OUT)

= no load

O(OUTx)

V

= 5 V,

= 5 V

V

= 5 V (inactive),

I(VIN/SWIN1)

I(SWIN2)

I(ENx)

I(LDO_EN)

O(LDO_OUT)

O(OUTx)

= 0 V (inactive),

= 0 V,

= 0 V

1

µA

(measured from outputs to

ground)

V

= 5 V (active),

= 0 V (inactive),

= 5 V (active),

I(LDO_EN)

I(ENx)

150

100

µA

= on (active)

V

= 5 V,

I(VIN/SWIN1)

I(SWIN2)

V

Total input current at VIN/SWIN1

and SWIN2

I(LDO_EN)

I(ENx)

I

= on (active)

No load on OUTx,

No load on LDO_OUT

V

I(LDO_EN)

I(ENx)

= off (inactive)

3

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SLVS333 − AUGUST 2001

electrical characteristics over recommended operating junction-temperature range,

2.9 V ≤ V ≤ 5.5 V, 2.9 V ≤ V ≤ 5.5 V, V = 0 V or V = 5 V,

I(VIN/SWIN1)

I(SWIN2)

I(ENx)

V

= 5 V, T = −40°C to 100°C (unless otherwise noted)

I(LDO_EN)

J

power switches

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

T = −40°C to 100°C,

J

I

= 200 mA,

580

O(LDO_OUT)

IOUT1 and IOUT2 = 150 mA

Static drain-source on-state resistance,

VIN/SWIN1 or SWIN2 to OUTx

r

mΩ

DS(on)

T = 25°C,

J

I

= 200 mA,

340

O(LDO_OUT)

IOUT1 and IOUT2 = 150 mA

V

= 5 V,

= 0 V,

I(ENx)

10

SWIN2 floating,

V

= 5 V

I(VIN/SWIN1)

V

= 5 V,

= 0 V,

= 0,

I(ENx)

I(SWIN2)

V

= 5 V,

O(OUTx)

LDO_EN = don’t care

I

Reverse leakage current at OUTx

µA

lkg(R)

= 2.9 V

= 0 V

I(VIN/SWIN1)

V

= 5 V,

= 0 V,

I(ENx)

I(SWIN2)

I(VIN/SWIN1)

10

= 0,

OUTx connected to GND, device enabled into short

circuit

Short circuit output current

0.2

0.4

A

OS

Delay time for asserting OC flag

Delay time for deasserting OC flag

From IOUTx at 95% of current limit level to 50% OC

5.5

ms

10.5

timing parameters, power switches

PARAMETER

TEST CONDITIONS

MIN

0.5

TYP

MAX

6

UNIT

C

= 100 µF

= 1 µF

L

t

Turnon time, OUTx switch, (see Note 1)

Turnoff time, OUTx switch (see Note 1)

Rise time, OUTx switch (see Note 1)

Fall time, OUTx switch (see Note 1)

R

= 33 Ω

on

off

r

L

0.1

3

= 100 µF

= 1 µF

5.5

12

4

ms

0.05

0.5

= 100 µF

= 1 µF

5

0.1

2

= 100 µF

= 1 µF

5.5

9

f

0.05

1.2

NOTE 1. Specified by design, not tested in production.

undervoltage lockout at VIN/SWIN1

PARAMETER

UVLO Threshold

TEST CONDITIONS

MIN

TYP

MAX

UNIT

V

2.2

2.85

Hysteresis (see Note 1)

260

mV

µs

Deglitch (see Note 1)

50

NOTE 1. Specified by design, not tested in production.

4

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SLVS333 − AUGUST 2001

electrical characteristics over recommended operating junction-temperature range,

2.9 V ≤ V ≤ 5.5 V, 2.9 V ≤ V ≤ 5.5 V, V = 0 V or V = 5 V,

I(VIN/SWIN1)

I(SWIN2)

I(ENx)

V

= 5 V, T = −40°C to 100°C (unless otherwise noted) (continued)

I(LDO_EN)

J

undervoltage lockout at SWIN2

PARAMETER

UVLO Threshold

TEST CONDITIONS

MIN

TYP

MAX

UNIT

V

2.2

2.85

Hysteresis (see Note 1)

260

mV

µs

Deglitch (see Note 1)

50

NOTE 1. Specified by design, not tested in production.

electrical characteristics over recommended operating junction-temperature range,

2.9 V ≤ V ≤ 5.5 V, 2.9 V ≤ V ≤ 5.5 V, V = 0 V or V = 5 V,

I(VIN/SWIN1)

I(SWIN2)

I(ENx)

V

= 5 V, C

= 10 µF, T = −40°C to 100°C (unless otherwise noted)

I(LDO_EN)

L(LDO_OUT) J

fixed-voltage regulator, 3.3 V

†

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

V

I

= 4.25 V to 5.25 V,

= 0.5 mA to 200 mA

I(VIN/SWIN1)

O(LDO_OUT)

V

Output voltage, dc

Dropout voltage

3.20

3.3

3.40

V

O

V

I

= 3.2 V,

= 200 mA,

= 150 mA

I(VIN/SWIN1)

O(LDO_OUT)

0.35

0.1

V

I

O(OUT1)

V

= 4.25 V to 5.25 V,

= 5 mA

I(VIN/SWIN1)

O(LDO_OUT)

Line regulation voltage (see Note 1)

Load regulation voltage (see Note 1)

Short-circuit current limit

%/V

I

V

= 4.25 V,

= 5 mA to 200 mA

I(VIN/SWIN1)

O(LDO_OUT)

0.4% 1.15%

I

V

= 4.25 V,

I(VIN/SWIN1)

I

0.275

0.33

10

0.55

A

OS

LDO_OUT connected to GND

V

= 3.3 V,

= 0 V,

= 0 V

O(LDO_OUT)

I(VIN/SWIN1)

I(LDO_EN)

µA

Reverse leakage current into

LDO_OUT

lkg(R)

V

= 5.5 V,

= 2.9 V,

= 0 V

O(LDO_OUT)

I(VIN/SWIN1)

I(LDO_EN)

10

µA

Turnoff time, LDO_EN

transitioning low (see Note 1)

t

R

= 16 Ω, C

= 10 µF

0.25

0.1

1

ms

on

L

L(LDO_OUT)

Turnon time, LDO_EN

transitioning high (see Note 1)

= 16 Ω, C

off

V

= 5 V, VIN/SWIN1 ramping up from 10%

I(LDO_EN)

Ramp-up time, LDO_OUT (0% to 90%) to 90% in 0.1 ms, R = 16 Ω,

0.1

1

ms

L

C

= 10 µF

L(LDO_OUT)

f = 1 kHz, C

= 4.7 µF,

L(LDO_OUT)

Power supply rejection

ESR = 0.25 Ω, IO = 5 mA,

50

dB

V

= 100 mV

I(VIN/SWIN1)p−p

Pulse-testing techniques maintain junction temperature close to ambient temperature; thermal effects must be taken into account separately.

NOTE 1. Specified by design, not tested in production.

†

5

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SLVS333 − AUGUST 2001

electrical characteristics over recommended operating junction-temperature range,

2.9 V ≤ V ≤ 5.5 V, 2.9 V ≤ V ≤ 5.5 V, V = 0 V or V = 5 V,

I(VIN/SWIN1)

I(SWIN2)

I(ENx)

V

= 5 V, C

= 10 µF, T = −40°C to 100°C (unless otherwise noted) (continued)

I(LDO_EN)

L(LDO_OUT) J

adjustable voltage regulator (Vx = 1 V to 3.3 V)

†

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

V

=Vx + 0.6 V to 5.5 V and

> 2.9 V,

I(VIN/SWIN1)

= 0.5 mA to 200 mA

V

O

Output voltage, dc (see Note 2)

0.97Vx

Vx 1.03Vx

I

O

Dropout voltage (VIN/SWIN1 to LDO_OUT)

Line regulation voltage (see Note 1)

V

= Vx − 0.1 V, I = 200 mA

0.5

0.1

V

I(VIN/SWIN1)

O

V

I

= Vx + 0.6 V to 5.5 V and

> 2.9 V,

I(VIN/SWIN1)

%/V

= 5 mA

O

V

= Vx + 0.6 V to 5.5 V and

> 2.9 V,

= 5 mA to 200 mA

I(VIN/SWIN1)

Load regulation voltage (see Note 1)

Short-circuit current limit

0.4%

1%

I

O

V

= Vx + 0.6 V to 5.5 V and

> 2.9 V,

I(VIN/SWIN1)

I

0.275

0.33

10

0.575

A

OS

LDO_OUT connected to GND

V

= Vx,

= 0 V,

= 0 V

O(LDO_OUT)

I(VIN/SWIN1)

I(LDO_EN)

µA

Reverse leakage current into LDO_OUT

lkg(R)

V

= 5.5 V,

= 2.8 V,

= 0 V

O(LDO_OUT)

I(VIN/SWIN1)

I(LDO_EN)

10

Turnoff time, LDO_EN

transitioning low (see Note 1)

From 50% LDO_EN to 10% LDO_OUT,

R = Vx/0.2 Ω, C = 10 µF

L

t

0.1

1

ms

on

L(LDO_OUT)

From 50% LDO_EN to 90% LDO_OUT,

Turnon time, LDO_EN

transitioning high (see Note 1)

off

R

= Vx/0.2 Ω, C

= 10 µF

L

L(LDO_OUT)

V

= 5 V, VIN/SWIN1 ramping up

I(LDO_EN)

Ramp-up time, LDO_OUT (0% to 90%)

from 10% to 90% in 0.1 ms, R = Vx/0.2 Ω,

C

0.1

0

1

ms

dB

L

= 10 µF

L(LDO_OUT)

Output tracking

LDO load R = Vx/0.2 Ω,

L

OUT1 lag time from LDO_OUT given

LDO_EN and EN1 have been asserted si-

multaneously to turnon their respective out-

puts. Measured at 1 V. (see Note 1)

C

= 10 µF,

L(LDO_OUT)

OUT1 R = 33 Ω, 10 µF,

L

V

= 3.3 V

I(VIN/SWIN1)

f = 1 kHz, C

ESR = 0.25 Ω, IO = 5 mA,

V

= 4.7 µF,

L(LDO_OUT)

Power supply rejection

50

= 100 mV

I(VIN/SWIN1)p−p

Pulse-testing techniques maintain junction temperature close to ambient temperature; thermal effects must be taken into account separately.

†

NOTES: 1. Specified by design, not tested in production.

2. Does not include error introduced by external resistive divider R1, R2 tolerance.

6

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SLVS333 − AUGUST 2001

electrical characteristics over recommended operating junction-temperature range,

2.9 V ≤ V ≤ 5.5 V, 2.9 V ≤ V ≤ 5.5 V, V = 0 V or V = 5 V,

I(VIN/SWIN1)

I(SWIN2)

I(ENx)

V

= 5 V, T = −40°C to 100°C (unless otherwise noted)

I(LDO_EN)

J

enable input, ENx (active low)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

V

High-level input voltage

Low-level input voltage

Input current, pullup (source)

2

IH

0.8

5

V

IL

I

V

= 0 V

µA

I(ENx)

enable input, ENx (active high)

PARAMETER

TEST CONDITIONS

MIN

MAX

UNIT

V

High-level input voltage

Low-level input voltage

Input current, pulldown (sink)

2

IH

0.8

5

V

IL

I

= 5 V

µA

I(ENx)

enable input, LDO_EN (active high)

PARAMETER

TEST CONDITIONS

MIN

MAX

UNIT

V

High-level input voltage

Low-level input voltage

2

IH

0.8

5

V

IL

I

Input current, pulldown

= 5 V

µA

µs

I(LDO_EN)

Falling-edge deglitch (see Note 1)

50

NOTE 1. Specified by design, not tested in production.

logic output, OCx

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Current sinking at V = 0.4 V

O

1

mA

thermal shutdown characteristics

PARAMETER

TEST CONDITIONS

MIN

120

110

155

UNIT

First thermal shutdown (shuts down switch or regulator

in overcurrent)

Occurs at or above specified temperature

when overcurrent is present.

Recovery from thermal shutdown

°C

Second thermal shutdown (shuts down all switches and Occurs on rising temperature, irrespective of

regulator)

overcurrent.

Second thermal shutdown hysteresis

10

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SLVS333 − AUGUST 2001

TPS2145 functional block diagram

1 V to 3.3 V / 200 mA

LDO

LDO_OUT

VIN/SWIN1

LDO_EN

LDO_ADJ

OUT1

CS

Charge

Pump

Current

Limit

Driver

OC1

EN1

Thermal

Sense

CS

OUT2

OC2

SWIN2

Current

Limit

Driver

EN2

Thermal

Sense

GND

TPS2147 functional block diagram

3.3 V / 200 mA

LDO

LDO_OUT

OUT1

VIN/SWIN1

CS

Charge

Pump

Current

Limit

Driver

OC1

EN1

Thermal

Sense

OUT2

OC2

CS

SWIN2

Current

Limit

Driver

EN2

Thermal

Sense

GND

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Terminal Functions

TERMINAL

PWP-14

NO.

I/O

DESCRIPTION

NAME

DGQ-10

TPS2145 TPS2155 TPS2147 TPS2157

EN1

EN2

GND

14

10

I

Logic level enable to transfer power to OUT1

Logic level enable to transfer power to OUT2

14

10

13

9

13

8

9

6

8

7

6

Ground

LDO_ADJ

LDO_EN

LDO_OUT

NC

7

I

User feedback for adjustable regulator

Logic level LDO enable. Active high.

LDO output

10

4

10

4

O

6, 9

12

11

1

6, 9

12

11

1

No connection

OC1

8

7

1

5

3

8

7

1

5

3

O

Overcurrent status flag for OUT1. Open-drain output.

Overcurrent status flag for OUT2. Open-drain output.

Switch 1 output

OC2

OUT1

OUT2

5

Switch 2 output

SWIN2

3

I

Input for switch 2

VIN/SWIN1

2

Input for LDO and switch 1; device supply voltage

detailed description

VIN/SWIN1

The VIN/SWIN1 serves as the input to the internal LDO and as the input to one N-channel MOSFET. The fixed

or adjustable LDO has a dropout voltage of 0.35 V and is rated for 200 mA of continuous current. The power

switch is an N-channel MOSFET with a maximum on-state resistance of 580 mΩ. Configured as a high-side

switch, the power switch prevents current flow from OUT to IN and IN to OUT when disabled. The power switch

is rated at 200 mA, continuous current. VIN/SWIN1 must be connected to a voltage source for device operation.

SWIN2

SWIN2 is the input to the other N-channel MOSFET, which also has a maximum on-state resistance of 580 mΩ.

Configured as a high-side switch, the power switch prevents current flow from OUT to IN and IN to OUT when

disabled. The power switch is rated at 200 mA, continuous current.

OUTx

OUT1 and OUT2 are the outputs from the internal power-distribution switches.

LDO_OUT

LDO_OUT is the output of the internal 200-mA LDO. The fixed version of the LDO has an output of 3.3 V. The

adjustable version has an output voltage range of 1 V to 3.3 V.

LDO_ADJ

This input only applies to the adjustable LDO version of this device (TPS2145/55). LDO_ADJ is used to adjust

the output voltage anywhere between 1 V and 3.3 V.

LDO_EN

The active high input, LDO_EN, only applies to the adjustable LDO version of this device (TPS2145/55).

LDO_EN is used to enable the internal LDO and is compatible with TTL and CMOS logic.

9

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SLVS333 − AUGUST 2001

detailed description (continued)

enable (ENx, ENx)

The logic enable disables the power switch. Both switches have independent enables and are compatible with

both TTL and CMOS logic.

overcurrent (OCx)

The OCx open-drain output is asserted (active low) when an overcurrent condition is encountered. The output

will remain asserted until the overcurrent condition is removed.

current sense

A sense FET monitors the current supplied to the load. Current is measured more efficiently by the sense FET

than by conventional resistance methods. When an overload or short circuit is encountered, the current-sense

circuitry sends a control signal to the driver. The driver in turn reduces the gate voltage and drives the power

FET into its saturation region, which switches the output into a constant-current mode and holds the current

constant while varying the voltage on the load.

thermal sense

A dual-threshold thermal trip is implemented to allow fully independent operation of the power distribution

switches. In an overcurrent or short-circuit condition, the junction temperature rises. When the die temperature

rises to approximately 120°C, the internal thermal sense circuitry determines which power switch is in an

overcurrent condition and turns off that switch, thus isolating the fault without interrupting operation of the

adjacent power switch. Because hysteresis is built into the thermal sense, the switch turns back on after the

device has cooled approximately 10 degrees. The switch continues to cycle off and on until the fault is removed.

undervoltage lockout

A voltage sense circuit monitors the input voltage. When the input voltage is below approximately 2.5 V, a control

signal turns off the power switch.

PARAMETER MEASUREMENT INFORMATION

Current

Meter

DUT

A

IN

OUT

+

Figure 1. Current Limit Test Circuit

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SLVS333 − AUGUST 2001

PARAMETER MEASUREMENT INFORMATION

50%

V

I(ENx)

t

pd(off)

on

pd(on)

t

off

90%

10%

90%

10%

V

O(OUTx)

t

f

r

90%

10%

90%

10%

O(OUTx)

TIMING

Figure 2. Timing and Internal Voltage Regulator Transition Waveforms

TYPICAL CHARACTERISTICS

SWITCH TURNON DELAY AND RISE TIME

SWITCH TURNOFF DELAY AND FALL TIME

WITH 1-µF LOAD

V

I(EN)

(5 V/div)

V

I(EN)

(5 V/div)

V

O(OUT)

(2 V/div)

V

O(OUT)

(2 V/div)

V = 5 V

I

T

= 25°C

= 1 µF

= 25 Ω

T

= 25°C

= 1 µF

= 25 Ω

A

L

C

R

0

0.4 0.8 1.2 1.6

t − Time − ms

0

0.4 0.8 1.2 1.6

t − Time − ms

2

2.4 2.8 3.2 3.6 4.2

2

2.4 2.8 3.2 3.6 4.2

Figure 3

Figure 4

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SLVS333 − AUGUST 2001

TYPICAL CHARACTERISTICS

SWITCH TURNOFF DELAY AND FALL TIME

SWITCH TURNON DELAY AND RISE TIME

WITH 120-µF LOAD

V

I(EN)

(5 V/div)

V

I(EN)

(5 V/div)

V

O(OUT)

(2 V/div)

V

O(OUT)

(2 V/div)

V = 5 V

I

T

= 25°C

= 120 µF

= 25 Ω

T

= 25°C

= 120 µF

= 25 Ω

A

L

C

R

0

4

8

12 16 20 24 28 32 36 40

t − Time − ms

0

2

4

6

8

10 12 14 16 18 20

t − Time − ms

Figure 5

Figure 6

LDO TURNON DELAY AND RISE TIME

SHORT-CIRCUIT CURRENT, SWITCH

ENABLED INTO A SHORT

WITH 4.7-µF LOAD

V = 5 V

I

A

T

= 25°C

= 4.7 µF

= 13.2 Ω

C

R

L

V

I(EN)

(5 V/div)

V

I(LDO_EN)

(5 V/div)

V

O(LDO_OUT)

(1 V/div

I

O(OUT)

(100 mA/div)

0

1

2

3

4

5

6

7

8

9

10

0

0.4 0.8 1.2 1.6

t − Time − ms

2

2.4 2.8 3.2 3.6 4.2

t − Time − ms

Figure 7

Figure 8

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TYPICAL CHARACTERISTICS

LINE TRANSIENT RESPONSE

LOAD TRANSIENT RESPONSE

I

O(LDO_OUT)

(200 mA/div)

5.25 V

V

I(VIN)

4.25 V

∆V

O(LDO_OUT)

∆V

O(LDO_OUT)

(0.05 V/div)

(100 mV/div)

T

C

= 25°C

L(LDO_OUT)

A

T

C

= 25°C

L(LDO_OUT)

A

= 4.7 µF

ESR = 1 Ω

I

= 200 mA

O(LDO_OUT)

0

100 200 300 400

500 600 700 800 900 1000

0

100 200 300 400

500 600 700 800 900 1000

t − Time − µs

Figure 10

Figure 9

SUPPLY CURRENT

vs

SUPPLY CURRENT

vs

JUNCTION TEMPERATURE

SUPPLY VOLTAGE

140

120

100

80

140

120

100

80

60

40

20

0

40

20

0

−40

−20

0

T

20

40

60

80

100

2.5

3

3.5

− Supply Voltage − V

CC

4

4.5

5

5.5

− Temperature − °C

V

J

Figure 11

Figure 12

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SLVS333 − AUGUST 2001

TYPICAL CHARACTERISTICS

STATIC DRAIN-SOURCE ON-STATE RESISTANCE

vs

JUNCTION TEMPERATURE

SUPPLY VOLTAGE

0.6

0.38

0.55

0.5

0.37

0.36

0.35

0.34

0.33

0.32

0.45

0.4

SW1

SW2

0.35

0.3

SW2

0.25

0.2

0.31

0.3

0.15

0.1

−40 −20

0

20

40

60

80

100

2.5

3

3.5

CC

4

4.5

5

5.5

T

J

− Junction Temperature − °C

V

− Supply Voltage

Figure 13

Figure 14

SHORT CIRCUIT CURRENT

vs

SHORT CIRCUIT CURRENT

vs

JUNCTION TEMPERATURE

SUPPLY VOLTAGE

400

380

360

340

320

300

280

260

240

380

360

340

320

300

280

260

240

SW1

SW2

SW1

SW2

220

200

220

200

−40

−20

0

20

40

60

80

100

2.5

3

3.5

V − Supply Voltage

CC

4

4.5

5

5.5

T

J

− Free-Air Temperature − °C

Figure 15

Figure 16

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TYPICAL CHARACTERISTICS

UNDERVOLTAGE LOCKOUT

vs

JUNCTION TEMPERATURE

2.9

2.8

2.7

2.6

2.5

2.4

2.3

2.2

2.1

Rising

Falling

−40 −25 −10

5

20 35 50 65 80 95 110

T

J

− Junction Temperature − °C

Figure 17

APPLICATION INFORMATION

external capacitor requirements on power lines

Ceramic bypass capacitors (0.01-µ to 0.1-µ) between VIN/SWIN1 and GND and SWIN2 and GND, close to the

device, are recommended to improve load transient response and noise rejection.

Bulk capacitors ( 4.7-µF) between VIN/SWIN1 and GND and between SWIN2 and GND are also recommended,

especially if load transients in the hundreds of milliamps with fast rise times are anticipated.

A 66-µF bulk capacitor is recommended from OUTx to ground, especially when the output load is heavy. This

precaution helps reduce transients seen on the power rails. Additionally, bypassing the outputs with a 0.1-µF

ceramic capacitor improves the immunity of the device to short-circuit transients.

LDO output capacitor requirements

Stabilizing the internal control loop requires an output capacitor connected between LDO_OUT and GND. The

minimum recommended capacitance is a 4.7 µF with an ESR value between 200 mΩ and 10 Ω. Solid tantalum

electrolytic, aluminum electrolytic and multilayer ceramic capacitors are all suitable, provided they meet the

ESR requirements.

The adjustable LDO (for voltages lower than 3 V) requires a bypass capacitor across the feedback resistor as

shown in Figure 18. The value of this capacitor is determined by using the following equation:

1

C_f+

* 4 pf

3

(

)

63.7e 2 3.14 R1

(1)

where R1 is derived by programming the adjustable LDO (see programming the adjustable LDO regulator

section shown below).

15

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SLVS333 − AUGUST 2001

APPLICATION INFORMATION

programming the adjustable LDO regulator

The output voltage of the TPS2145 adjustable regulator is programmed using an external resistor divider as

shown in Figure 18. The output voltage is calculated using:

R1

R2

ǒ₁₎

Ǔ

LDO_OUT + V_ref

(2)

where V = 0.8 V typical (internal reference voltage).

ref

Resistors R1 and R2 should be chosen for approximately 4-µA (minimum) divider current. Lower value resistors

can be used but offer no inherent advantage and waste more power. Higher values should be avoided as a

minimum load is required to sink the LDO forward leakage and maintain regulation. The recommended design

procedure is to choose R2 = 200 kΩ to set the divider current at 4-µA and then solve the LDO_OUT equation

for R1.

TPS2145

VIN/SWIN1 LDO_OUT

R1

C

0.1 µF

f

0.1 µF

10 µF

4.7 µF

LDO_EN

GND

LDO_ADJ

R2

Figure 18. External Resistor Divider

OUTPUT VOLTAGE PROGRAMMING GUIDE

OUTPUT VOLTAGE

R1

R2

Cfb

†

3.3

625 kΩ

550 kΩ

425 kΩ

250 kΩ

175 kΩ

50 kΩ

200 kΩ

NR

†

3.0

NR

2.5

2 pf

6 pf

1.8

1.5

1.0

10.3 pf

46 pf

†

NR − Not required

overcurrent

A sense FET is used to measure current through the device. Unlike current-sense resistors, sense FETs do not

increase the series resistance of the current path. When an overcurrent condition is detected, the device

maintains a constant output current. Complete shutdown occurs only if the fault is present long enough to

activate thermal limiting.

Three possible overload conditions can occur. In the first condition, the output is shorted before the device is

enabled or before VIN has been applied. The TPS2145 and TPS2147 sense the short and immediately switch

to a constant-current output.

In the second condition, the short occurs while the device is enabled. At the instant the short occurs, very high

currents may flow for a very short time before the current-limit circuit can react. After the current-limit circuit has

tripped (reached the overcurrent trip threshold), the device switches into constant-current mode.

16

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APPLICATION INFORMATION

overcurrent (continued)

In the third condition, the load has been gradually increased beyond the recommended operating current. The

current is permitted to rise until the current-limit threshold is reached or until the thermal limit of the device is

exceeded. The TPS2145 and TPS2147 are capable of delivering current up to the current-limit threshold without

damaging the device. Once the threshold has been reached, the device switches into its constant-current mode.

OC response

The OCx open-drain output is asserted (active low) when an overcurrent condition is encountered. The output

will remain asserted until the overcurrent condition is removed. Connecting a heavy capacitive load to an

enabled device can cause momentary false overcurrent reporting from the inrush current flowing through the

device, charging the downstream capacitor. The TPS2145 and TPS2147 are designed to reduce false

overcurrent reporting. An internal overcurrent transient filter eliminates the need for external components to

remove unwanted pulses. Using low-ESR electrolytic capacitors on OUTx lowers the inrush current flow through

the device during hot-plug events by providing a low-impedance energy source, also reducing erroneous

overcurrent reporting.

power dissipation and junction temperature

The major source of power dissipation for the TPS2145 and TPS2147 comes from the internal voltage regulator

and the N-channel MOSFETs. Checking the power dissipation and junction temperature is always a good

design practice and it starts with determining the r

of the N-channel MOSFET according to the input

DS(on)

voltage and operating temperature. As an initial estimate, use the highest operating ambient temperature of

interest and read r from the graphs shown in the Typical Characteristics section of this data sheet. Using

DS(on)

this value, the power dissipation per switch can be calculated using:

2

P

+ r

I

D

DS(on)

(3)

(4)

Multiply this number by two to get the total power dissipation coming from the N-channel MOSFETs.

The power dissipation for the internal voltage regulator is calculated using:

₊ǒ_{V –V}

Ǔ

P

I

D

I

O(min)

O

The total power dissipation for the device becomes:

₎ǒ_{2 P}

Ǔ

P

+ P

D(total)

D(voltage regulator)

D(switch)

(5)

(6)

Finally, calculate the junction temperature:

T + P R

) T

J

D

qJA

A

Where:

T = Ambient Temperature °C

A

R

= Thermal resistance °C/W, equal to inverting the derating factor found on the power dissipation table

θJA

in this data sheet.

Compare the calculated junction temperature with the initial estimate. If they do not agree within a few degrees,

repeat the calculation, using the calculated value as the new estimate. Two or three iterations are generally

sufficient to get a reasonable answer.

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APPLICATION INFORMATION

thermal protection

Thermal protection prevents damage to the IC when heavy-overload or short-circuit faults are present for

extended periods of time. The faults force the TPS2145 and TPS2147 into constant-current mode at first, which

causes the voltage across the high-side switch to increase; under short-circuit conditions, the voltage across

the switch is equal to the input voltage. The increased dissipation causes the junction temperature to rise to high

levels.

The protection circuit senses the junction temperature of the switch and shuts it off. Hysteresis is built into the

thermal sense circuit, and after the device has cooled approximately 10 degrees, the switch turns back on. The

switch continues to cycle in this manner until the load fault or input power is removed.

The TPS2145 and TPS2147 implement a dual thermal trip to allow fully independent operation of the power

distribution switches. In an overcurrent or short-circuit condition, the junction temperature will rise. Once the die

temperature rises to approximately 120°C, the internal thermal-sense circuitry checks to determine which

power switch is in an overcurrent condition and turns that power switch off, thus isolating the fault without

interrupting operation of the adjacent power switch. Should the die temperature exceed the first thermal trip

point of 120°C and reach 155°C, the device will turn off.

undervoltage lockout (UVLO)

An undervoltage lockout ensures that the device (LDO and switches) is in the off state at power up. The UVLO

will also keep the device from being turned on until the power supply has reached the start threshold (see

undervoltage lockout table), even if the switches are enabled. The UVLO will also be activated whenever the

input voltage falls below the stop threshold as defined in the undervoltage lockout table. This function facilitates

the design of hot-insertion systems where it is not possible to turn off the power switches before input power

is removed. Upon reinsertion, the power switches will be turned on with a controlled rise time to reduce EMI and

voltage overshoots.

universal serial bus (USB) applications

The universal serial bus (USB) interface is a multiplexed serial bus operating at either 12-Mb/s, or 1.5-Mb/s for

USB 1.1, or 480 Mb/s for USB 2.0. The USB interface is designed to accommodate the bandwidth required by

PC peripherals such as keyboards, printers, scanners, and mice. The four-wire USB interface was conceived

for dynamic attach-detach (hot plug-unplug) of peripherals. Two lines are provided for differential data, and two

lines are provided for 5-V power distribution.

USB data is a 3.3-V level signal, but power is distributed at 5 V to allow for voltage drops in cases where power

is distributed through more than one hub across long cables. Each function must provide its own regulated 3.3-V

from the 5-V input or its own internal power supply.

The USB specification defines the following five classes of devices, each differentiated by power-consumption

requirements:

D

Hosts/self-powered hubs (SPH)

Bus-powered hubs (BPH)

Low-power, bus-powered functions

High-power, bus-powered functions

Self-powered functions

The TPS2145 and TPS2147 are well suited for USB hub and peripheral applications. The internal LDO can be

used to provide the 3.3-V power needed by the controller while the dual switches distribute power to the

downstream functions.

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SLVS333 − AUGUST 2001

APPLICATION INFORMATION

USB power-distribution requirements

USB can be implemented in several ways, and, regardless of the type of USB device being developed, several

power-distribution features must be implemented.

D

Hosts/self-powered hubs must:

−

Current-limit downstream ports

Report overcurrent conditions on USB V

BUS

D

Bus-powered hubs must:

−

Enable/disable power to downstream ports

Power up at <100 mA

Limit inrush current (<44 Ω and 10 µF)

D

Functions must:

−

Limit inrush currents

Power up at <100 mA

The feature set of the TPS2145 and TPS2147 allows them to meet each of these requirements. The integrated

current-limiting and overcurrent reporting is required by hosts and self-powered hubs. The logic-level enable

and controlled rise times meet the need of both input and output ports on bus-powered hubs, as well as the input

ports for bus-powered functions.

USB applications

Figure 19 shows the TPS2147 being used in a USB bus-powered/self-powered peripheral design. The internal

3.3-V LDO is used to provide power for the USB function controller as well as to the 1.5-kΩ pullup resistor.

In bus-powered mode, switch 1 provides power to the 5-V circuitry. In self-powered mode, switch 2 provides

power to the 5-V circuitry while the USB 5-V still provides power to the 3.3-V LDO (USB allows self-powered

devices to draw up to 100 mA from V

).

BUS

19

www.ti.com

ꢀ ꢁ ꢂ ꢃ ꢄꢅ ꢆ ꢇ ꢀ ꢁꢂ ꢃ ꢄ ꢅ ꢈ

ꢀ ꢁ ꢂ ꢃ ꢄꢆ ꢆ ꢇ ꢀ ꢁꢂ ꢃ ꢄ ꢆ ꢈ

SLVS333 − AUGUST 2001

APPLICATION INFORMATION

1.5 kΩ

D+

D−

USB

Function

Controller

TPS2147

GND

5 V

LDO_OUT

VIN/SW1

3.3 V

LDO

4.7 µF

0.1 µF

10 µF

0.1 µF

OC1

OUT1

EN1

External

5-V

Supply

SW2

OUT2

5-V

Circuitry

4.7 µF

0.1 µF

EN2

OC2

Figure 19. TPS2147 USB Bus-Powered/Self-Powered Peripheral Application

DSP applications

Figure 20 shows the TPS2145 in a DSP application. DSPs use a 1.8-V core voltage and a 3.3-V I/O voltage.

In this type of application, the TPS2145 adjustable LDO is configured for a 1.8-V output specifically for the DSP

core voltage.

The additional 3.3-V circuitry is powered through switch 1 of the TPS2145 only after the DSP is up and running.

Switch 2 is used to provide power to additional circuitry operating from a different voltage source. This switch

is also controlled by the DSP.

Figures 21 thru 23 show the TPS2145 in various DSP applications using a supply voltage supervisor (SVS) chip

to control the enable for the 3.3 V powering up the DSP I/O circuitry.

20

www.ti.com

ꢀ ꢁꢂꢃ ꢄ ꢅ ꢆ ꢇ ꢀꢁ ꢂ ꢃꢄ ꢅꢈ

ꢀ ꢁꢂꢃ ꢄ ꢆ ꢆ ꢇ ꢀꢁ ꢂ ꢃꢄ ꢆꢈ

SLVS333 − AUGUST 2001

APPLICATION INFORMATION

4.7 µF

0.1 µF

DSP

TPS2145

1.8 V

VIN/SW1

LDO_EN

ADJ

LDO

3.3 V

5 V

External

Supply

10 µF

0.1 µF

OC1

Additional

3.3-V

Circuitry

OUT1

EN1

SW2

5-V

OUT2

Circuitry

4.7 µF

0.1 µF

EN2

OC2

Figure 20. TPS2145 DSP Application

TPS2145

1.8 V

External

3.3-V

Supply

VIN/SW1

0.1 µF

ADJ

LDO

4.7 µF

10 µF

0.1 µF

DSP

LDO_EN

OC1

OUT1

OUT2

EN1

SVS

Additional

3.3-V

SW2

Circuitry

EN2

OC2

Figure 21. TPS2145 DSP With SVS Application

21

www.ti.com

ꢀ ꢁ ꢂ ꢃ ꢄꢅ ꢆ ꢇ ꢀ ꢁꢂ ꢃ ꢄ ꢅ ꢈ

ꢀ ꢁ ꢂ ꢃ ꢄꢆ ꢆ ꢇ ꢀ ꢁꢂ ꢃ ꢄ ꢆ ꢈ

SLVS333 − AUGUST 2001

APPLICATION INFORMATION

TPS2145

1.8 V

External

3.3-V

Supply

VIN/SW1

0.1 µF

ADJ

LDO

4.7 µF

10 µF

0.1 µF

DSP

LDO_EN

SVS

EN1

OUT1

OC1

Additional

3.3-V

SW2

OUT2

Circuitry

EN2

OC2

Figure 22. TPS2145 DSP With SVS Application

TPS2145

1.8 V

External

3.3-V

Supply

VIN/SW1

0.1 µF

ADJ

LDO

4.7 µF

10 µF

0.1 µF

DSP

LDO_EN

OC1

OUT1

OUT2

EN1

Dual

SVS

Additional

3.3-V

SW2

Circuitry

EN2

OC2

Figure 23. TPS2145 DSP With Dual SVS Application

22

www.ti.com

ꢀ ꢁꢂꢃ ꢄ ꢅ ꢆ ꢇ ꢀꢁ ꢂ ꢃꢄ ꢅꢈ

ꢀ ꢁꢂꢃ ꢄ ꢆ ꢆ ꢇ ꢀꢁ ꢂ ꢃꢄ ꢆꢈ

SLVS333 − AUGUST 2001

APPLICATION INFORMATION

power supply sequencing

DSPs typically do not require specific power sequencing between the core supply and the I/O supply. However,

systems should be designed to ensure that neither supply is powered up for extended periods of time if the other

supply is below the proper operating voltage.

system level design consideration

System level design considerations, such as bus contention, may require supply sequencing to be

implemented. In this case, the core supply should be powered up at the same time as, or prior to (and powered

down after), the I/O buffers. This is to ensure that the I/O buffers receive valid inputs from the core before the

output buffers are powered up, thus, preventing bus contention with other chips on the board.

power supply design consideration

For some DSP systems, the core supply may be required to provide a considerable amount of current until the

I/O supply is powered up. This extra current condition is a result of uninitialized logic within the DSP(s).

Decreasing the amount of time between the core supply power up and the I/O supply power up can minimize

the effects of this current draw.

23

www.ti.com

PACKAGE OPTION ADDENDUM

www.ti.com

2-Nov-2007

PACKAGING INFORMATION

Orderable Device

TPS2145IPWP

Status ⁽¹⁾

ACTIVE

Package Package

Pins Package Eco Plan ⁽²⁾Lead/Ball Finish MSL Peak Temp ⁽³⁾

Qty

Type

Drawing

HTSSOP

PWP

14

10

90 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

TPS2145IPWPG4

TPS2145IPWPR

TPS2145IPWPRG4

TPS2147IDGQ

HTSSOP

PWP

DGQ

90 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

MSOP-

Power

PAD

80 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

TPS2147IDGQG4

TPS2147IDGQR

ACTIVE

MSOP-

Power

PAD

DGQ

10

80 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

MSOP-

Power

PAD

2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

TPS2147IDGQRG4

MSOP-

Power

PAD

2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

TPS2155IPWP

ACTIVE

HTSSOP

PWP

14

90 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

TPS2155IPWPG4

HTSSOP

90 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered

at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and

package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS

compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame

retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is

provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the

accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take

reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on

incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited

information may not be available for release.

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

2-Nov-2007

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI

to Customer on an annual basis.

Addendum-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

12-Jan-2008

TAPE AND REEL BOX INFORMATION

Device

Package Pins

Site

Reel

A0 (mm)

B0 (mm)

K0 (mm)

P1

W

Pin1

Diameter Width

(mm) (mm) Quadrant

(mm)

330

(mm)

12

TPS2145IPWPR

TPS2147IDGQR

PWP

DGQ

14

10

SITE 60

SITE 35

6.67

5.3

5.4

3.4

1.6

1.4

8

12

Q1

330

12

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

12-Jan-2008

Device

Package

Pins

Site

Length (mm) Width (mm) Height (mm)

TPS2145IPWPR

TPS2147IDGQR

PWP

DGQ

14

10

SITE 60

SITE 35

342.9

358.0

345.9

335.0

28.58

35.0

Pack Materials-Page 2

IMPORTANT NOTICE

Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements,

and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should

obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are

sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.

TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard

warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where

mandated by government requirements, testing of all parameters of each product is not necessarily performed.

TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and

applications using TI components. To minimize the risks associated with customer products and applications, customers should provide

adequate design and operating safeguards.

TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right,

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Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all

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Following are URLs where you can obtain information on other Texas Instruments products and application solutions:

Products

Applications

Audio

Automotive

Broadband

Digital Control

Medical

Amplifiers

Data Converters

DSP

Clocks and Timers

Interface

amplifier.ti.com

dataconverter.ti.com

dsp.ti.com

www.ti.com/clocks

interface.ti.com

logic.ti.com

www.ti.com/audio

www.ti.com/automotive

www.ti.com/broadband

www.ti.com/digitalcontrol

www.ti.com/medical

www.ti.com/military

Logic

Military

Power Mgmt

Microcontrollers

RFID

power.ti.com

microcontroller.ti.com

www.ti-rfid.com

Optical Networking

Security

Telephony

Video & Imaging

Wireless

www.ti.com/opticalnetwork

www.ti.com/security

www.ti.com/telephony

www.ti.com/video

RF/IF and ZigBee® Solutions www.ti.com/lprf

www.ti.com/wireless

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	TPS2147
厂家：	TEXAS INSTRUMENTS
描述：	LDO AND DUAL SWITCH WITH CONTROLLED RISE TIMES FOR DSP AND PORTABLE APPLICATIONS LDO和双管可控的上升时间为DSP和便携式应用便携式
文件：	总34页 (文件大小：1140K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TPS2147 [TI]

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