TPS2202AIDBRG4 [TI]
DUAL-SLOT PC CARD POWER-INTERFACE SWITCH WITH RESET FOR SERIAL PCMCIA CONTROLLER;
| 型号： | TPS2202AIDBRG4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | DUAL-SLOT PC CARD POWER-INTERFACE SWITCH WITH RESET FOR SERIAL PCMCIA CONTROLLER PC 信息通信管理 光电二极管 |
| 文件： | 总23页 (文件大小：359K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPS2202AI
DUAL-SLOT PC CARD POWER-INTERFACE SWITCH
WITH RESET FOR SERIAL PCMCIA CONTROLLER
SLVS123A – SEPTEMBER 1995 – REVISED JUNE 1998
DB OR DF PACKAGE
Fully Integrated V
Dual-Slot PC Card Interface
and V Switching for
pp
CC
(TOP VIEW)
2
P C 3-Lead Serial Interface Compatible
1
30
5V
5V
DATA
CLOCK
LATCH
RESET
12V
AVPP
AVCC
AVCC
AVCC
5V
With CardBus Controllers
2
29
28
27
26
25
24
23
22
21
20
19
18
17
16
NC
NC
NC
NC
3
Meets PC Card Standards
4
RESET Allows System Initialization of PC
Cards
5
6
V
DD
12-V Supply Can Be Disabled Except
During 12-V Flash Programming
7
12V
8
BVPP
BVCC
BVCC
BVCC
BPWR_GOOD
OC
9
Short Circuit and Thermal Protection
10
11
12
13
14
15
Space-Saving 30-Pin SSOP (DB) Package
Compatible With 3.3-V, 5-V and 12-V PC
Cards
GND
APWR_GOOD
RESET
3.3V
Power Saving I
= 83 µA Typ, I = 1 µA
Q
3.3V
3.3V
DD
Low r
(160-mΩ V
Switch)
DS(on)
CC
Break-Before-Make Switching
NC – No internal connection
description
The TPS2202AI PC Card power-interface switch provides an integrated power-management solution for two
PC Cards. All of the discrete power MOSFETs, a logic section, current limiting, thermal protection, and
power-good reporting for PC Card control are combined on a single integrated circuit (IC), using the Texas
Instruments LinBiCMOS process. The circuit allows the distribution of 3.3-V, 5-V, and/or 12-V card power by
2
means of the P C (PCMCIA Peripheral-Control) Texas Instruments nonproprietary serial interface. The
current-limiting feature eliminates the need for fuses, which reduces component count and improves reliability.
Current-limit reporting can help the user isolate a system fault to a specific card.
The TPS2202AI incorporates a reset function, selectable by one of two inputs, to help alleviate system errors.
The reset function enables PC Card initialization concurrent with host platform initialization, allowing a system
reset. Reset is accomplished by grounding the V
which discharges residual card voltage.
and V (flash-memory programming voltage) outputs,
CC
pp
EndequipmentfortheTPS2202AIincludesnotebookcomputers, desktopcomputers, personaldigitalassistants
(PDAs), digital cameras, handiterminals, and bar-code scanners. The TPS2202AI is only available taped and
reeled (either TPS2202AIDFLE or TPS2202AIDBLE).
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
LinBiCMOS and P C are trademarks of Texas Instruments Incorporated.
PC Card and CardBus are trademarks of PCMCIA (Personal Computer Memory Card International Association).
Copyright 1998, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TPS2202AI
DUAL-SLOT PC CARD POWER-INTERFACE SWITCH
WITH RESET FOR SERIAL PCMCIA CONTROLLER
SLVS123A – SEPTEMBER 1995 – REVISED JUNE 1998
typical PC card power-distribution application
V
DD
Power Supply
TPS2202AI
12V
5V
12 V
5 V
AVPP
V
V
V
V
pp1
pp2
CC
PC
Card A
3.3V
3.3 V
AVCC
AVCC
AVCC
CC
RESET
RESET
Supervisor
3
Serial Interface
APWR_GOOD
BPWR_GOOD
OC
BVPP
V
V
V
V
pp1
pp2
CC
PCMCIA
Controller
PC
Card B
BVCC
BVCC
BVCC
CC
Terminal Functions
TERMINAL
NAME
I/O
DESCRIPTION
NO.
3.3V
5V
15, 16, 17
I
I
3.3-V V
input for card power
input for card power
CC
1, 2, 30
5-V V
CC
12-V V input for card power
12V
7, 24
I
pp
AVCC
9, 10, 11
O
O
O
O
O
O
I
Switched output that delivers 3.3 V, 5 V, low or high impedance to card
Switched output that delivers 3.3 V, 5 V, 12 V, low or high impedance to card
Logic-level power-ready output that stays low as long as AVPP is within limits
Switched output that delivers 3.3 V, 5 V, low or high impedance
Switched output that delivers 3.3 V, 5 V, 12 V, low or high impedance
Logic-level power-ready output that remains low as long as BVPP is within limits
Logic-level clock for serial data word
AVPP
8
APWR_GOOD
BVCC
13
20, 21, 22
BVPP
23
19
4
BPWR_GOOD
CLOCK
DATA
3
I
Logic-level serial data word
GND
12
5
Ground
LATCH
NC
I
Logic-level latch for serial data word
26, 27,
28, 29
No internal connection
OC
18
6
O
I
Logic-level overcurrent reporting output that goes low when an overcurrent condition exists
Logic-level RESET input active high. Do not connect if terminal 14 is used.
Logic-level RESET input active low. Do not connect if terminal 6 is used.
5-V power to chip
RESET
RESET
14
25
I
V
DD
I
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TPS2202AI
DUAL-SLOT PC CARD POWER-INTERFACE SWITCH
WITH RESET FOR SERIAL PCMCIA CONTROLLER
SLVS123A – SEPTEMBER 1995 – REVISED JUNE 1998
†
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
Supply voltage range, V
Input voltage range for card power: V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 7 V
DD
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 7 V
I(5V)
V
V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to V
I(3.3V)
I(5V)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 14 V
I(12V)
Logic input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 7 V
Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table
Output current (each card): I
I
Operating virtual junction temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 150°C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . internally limited
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . internally limited
O(xVCC)
O(xVPP)
J
Operating free-air temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 85°C
A
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to 150°C
stg
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
DISSIPATION RATING TABLE
‡
T
≤ 25°C
DERATING FACTOR
T
= 70°C
T = 85°C
A
A
A
PACKAGE
POWER RATING
ABOVE T = 25°C
POWER RATING POWER RATING
A
DF
DB
1158 mW
9.26 mW/°C
8.2 mW/°C
741 mW
655 mW
602 mW
532 mW
1024 mW
‡
These devices are mounted on an FR4 board with no special thermal considerations.
recommended operating conditions
MIN
4.75
0
MAX
5.25
5.25
UNIT
V
Supply voltage, V
DD
V
V
V
V
I(5V)
§
Input voltage range, V
0
V
V
I
I(3.3V)
I(12V)
I(5V)
13.5
0
V
I
I
at 25°C
at 25°C
1
150
2.5
A
O(xVCC)
Output current
mA
MHz
°C
O(xVPP)
Clock frequency
0
Operating virtual junction temperature, T
–40
125
J
§
V
should not be taken above V
.
I(3.3V)
I(5V)
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TPS2202AI
DUAL-SLOT PC CARD POWER-INTERFACE SWITCH
WITH RESET FOR SERIAL PCMCIA CONTROLLER
SLVS123A – SEPTEMBER 1995 – REVISED JUNE 1998
electrical characteristics, T = 25°C, V
= 5 V (unless otherwise noted)
DD
A
dc characteristics
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
160
225
6
UNIT
5 V to xVCC
mΩ
3.3 V to xVCC
†
5 V to xVPP
3.3 V to xVPP
12 V to xVPP
Switch resistances
6
Ω
1
V
V
Clamp low voltage
Clamp low voltage
I
I
at 10 mA
at 10 mA
= 25°C
0.8
0.8
10
50
10
50
V
V
O(xVPP)
pp
O(xVCC)
CC
T
1
1
I
I
High-impedance
state
A
pp
T
= 85°C
A
I
Leakage current
Input current
µA
lkg
T
= 25°C
High-impedance
state
A
CC
T
= 85°C
A
V
V
= V
= V
= 5 V,
= 12 V
O(AVCC)
O(AVPP)
O(BVCC)
O(BVPP)
I
I
Supply current
83
150
1
µA
µA
V
DD
I
I
Supply current
in shutdown
V
= V
= V
= V
O(AVPP)
= Hi-Z
DD
O(BVCC)
O(AVCC)
O(BVPP)
Power-ready threshold,
PWR_GOOD
10.72 11.05
50
11.4
Power-ready hysteresis,
PWR_GOOD
12-V mode
mV
I
I
0.75
120
1.3
1.9
A
Short-circuit output-
current limit
O(xVCC)
T = 85°C,
J
Output powered up into a short to GND
200
400
mA
O(xVPP)
†
Pulse-testing techniques are used to maintain junction temperature close to ambient temperature; thermal effects must be taken into account
separately.
logic section
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
µA
V
Logic input current
1
Logic input high level
Logic input low level
2
0.8
0.4
V
Logic output high level
Logic output low level
Logic input minimum pulse width
V
DD
–0.4
V
I
O
= 1 mA
V
1
µs
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TPS2202AI
DUAL-SLOT PC CARD POWER-INTERFACE SWITCH
WITH RESET FOR SERIAL PCMCIA CONTROLLER
SLVS123A – SEPTEMBER 1995 – REVISED JUNE 1998
†
switching characteristics
PARAMETER
TEST CONDITIONS
O(xVCC)
MIN
TYP
1.2
5
MAX
UNIT
V
V
V
V
t
t
Output rise times
Output fall times
r
O(xVPP)
O(xVCC)
O(xVPP)
ms
10
14
5.8
18
5.8
28
4
f
t
on
t
off
t
on
t
off
t
on
t
off
ms
ms
ms
ms
ms
ms
LATCH↑ to V
O(xVPP)
‡
Propagation delay (see Figure 1 )
t
pd
LATCH↑ to xVCC (3 V)
LATCH↑ to xVCC (5 V)
30
†
‡
Refer to Parameter Measurement Information
Propagation delays are with C = 100 µF.
L
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TPS2202AI
DUAL-SLOT PC CARD POWER-INTERFACE SWITCH
WITH RESET FOR SERIAL PCMCIA CONTROLLER
SLVS123A – SEPTEMBER 1995 – REVISED JUNE 1998
PARAMETER MEASUREMENT INFORMATION
V
pp
V
CC
C
C
L
L
LOAD CIRCUIT
LOAD CIRCUIT
V
DD
V
DD
50%
50%
LATCH
LATCH
GND
GND
t
t
off
off
t
t
on
on
V
V
I(12V)
I(5V)
90%
90%
V
O(xVCC)
V
O(xVPP)
10%
10%
GND
GND
VOLTAGE WAVEFORMS
VOLTAGE WAVEFORMS
Figure 1. Test Circuits and Voltage Waveforms
Table of Timing Diagrams
FIGURE
Serial-Interface Timing
2
3
xVCC Propagation Delay and Rise Time With 1-µF Load, 3.3-V Switch
xVCC Propagation Delay and Fall Time With 1-µF Load, 3.3-V Switch
xVCC Propagation Delay and Rise Time With 100-µF Load, 3.3-V Switch
xVCC Propagation Delay and Fall Time With 100-µF Load, 3.3-V Switch
xVCC Propagation Delay and Rise Time With 1-µF Load, 5-V Switch
xVCC Propagation Delay and Fall Time With 1-µF Load, 5-V Switch
xVCC Propagation Delay and Rise Time With 100-µF Load, 5-V Switch
xVCC Propagation Delay and Fall Time With 100-µF Load, 5-V Switch
xVPP Propagation Delay and Rise Time With 1-µF Load, 12-V Switch
xVPP Propagation Delay and Fall Time With 1-µF Load, 12-V Switch
xVPP Propagation Delay and Rise Time With 100-µF Load, 12-V Switch
xVPP Propagation Delay and Fall Time With 100-µF Load, 12-V Switch
4
5
6
7
8
9
10
11
12
13
14
D8
D7
D6
D5
D4
D3
D2
D1
D0
DATA
LATCH
CLOCK
NOTE A: Data is clocked in on the positive leading edge of the clock. The latch should occur before next positive leading edge of the
clock. For definition of D0 to D8, see the control logic table.
Figure 2. Serial-Interface Timing
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TPS2202AI
DUAL-SLOT PC CARD POWER-INTERFACE SWITCH
WITH RESET FOR SERIAL PCMCIA CONTROLLER
SLVS123A – SEPTEMBER 1995 – REVISED JUNE 1998
PARAMETER MEASUREMENT INFORMATION
LATCH (2 V/div)
LATCH (2 V/div)
xVCC (1 V/div)
xVCC (1 V/div)
0
1
2
3
4
5
6
7
8
9
0
5
10 15 20 25 30 35 40 45
t – Time – ms
t – Time – ms
Figure 3. xVCC Propagation Delay and
Figure 4. xVCC Propagation Delay and
Rise Time With 1-µF Load, 3.3-V Switch
Fall Time With 1-µF Load, 3.3-V Switch
LATCH (2 V/div)
LATCH (2 V/div)
xVCC (1 V/div)
xVCC (1 V/div)
0
1
2
3
4
5
6
7
8
9
0
5
10 15 20 25 30 35 40 45
t – Time – ms
t – Time – ms
Figure 5. xVCC Propagation Delay and
Rise Time With 100-µF Load, 3.3-V Switch
Figure 6. xVCC Propagation Delay and
Fall Time With 100-µF Load, 3.3-V Switch
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TPS2202AI
DUAL-SLOT PC CARD POWER-INTERFACE SWITCH
WITH RESET FOR SERIAL PCMCIA CONTROLLER
SLVS123A – SEPTEMBER 1995 – REVISED JUNE 1998
PARAMETER MEASUREMENT INFORMATION
LATCH (2 V/div)
LATCH (2 V/div)
xVCC (1 V/div)
xVCC (1 V/div)
0
1
2
3
4
0
5
10 15 20 25 30 35 40 45
t – Time – ms
t – Time – ms
Figure 7. xVCC Propagation Delay and
Figure 8. xVCC Propagation Delay and
Rise Time With 1-µF Load, 5-V Switch
Fall Time With 1-µF Load, 5-V Switch
LATCH (2 V/div)
LATCH (2 V/div)
xVCC (1 V/div)
xVCC (1 V/div)
0
1
2
3
4
5
6
7
8
9
0
5
10 15 20 25 30 35 40 45
t – Time – ms
t – Time – ms
Figure 10. xVCC Propagation Delay and
Fall Time With 100-µF Load, 5-V Switch
Figure 9. xVCC Propagation Delay and
Rise Time With 100-µF Load, 5-V Switch
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TPS2202AI
DUAL-SLOT PC CARD POWER-INTERFACE SWITCH
WITH RESET FOR SERIAL PCMCIA CONTROLLER
SLVS123A – SEPTEMBER 1995 – REVISED JUNE 1998
PARAMETER MEASUREMENT INFORMATION
LATCH (2 V/div)
LATCH (2 V/div)
xVPP (5 V/div)
xVPP (5 V/div)
0
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8
t – Time – ms
0
1
2
3
4
5
6
7
8
9
t – Time – ms
Figure 11. xVPP Propagation Delay and
Figure 12. xVPP Propagation Delay and
Rise Time With 1-µF Load, 12-V Switch
Fall Time With 1-µF Load, 12-V Switch
LATCH (2 V/div)
LATCH (2 V/div)
xVPP (5 V/div)
xVPP (5 V/div)
0
1
2
3
4
5
6
7
8
9
0
5
10 15 20 25 30 35 40 45
t – Time – ms
t – Time – ms
Figure 14. xVPP Propagation Delay and
Fall Time With 100-µF Load, 12-V Switch
Figure 13. xVPP Propagation Delay and
Rise Time With 100-µF Load, 12-V Switch
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TPS2202AI
DUAL-SLOT PC CARD POWER-INTERFACE SWITCH
WITH RESET FOR SERIAL PCMCIA CONTROLLER
SLVS123A – SEPTEMBER 1995 – REVISED JUNE 1998
†
TYPICAL CHARACTERISTICS
Table of Graphs
FIGURE
15
I
Supply current
vs Junction temperature
vs Junction temperature
vs Junction temperature
vs Junction temperature
vs Output current
DD
r
r
r
Static drain-source on-state resistance, 3-V switch
Static drain-source on-state resistance, 5-V switch
Static drain-source on-state resistance, 12-V switch
Output voltage, 5-V switch
16
DS(on)
DS(on)
DS(on)
17
18
V
V
19
O(xVCC)
O(xVCC)
Output voltage, 3.3-V switch
vs Output current
20
xV
Output voltage, V switch
pp
vs Output current
21
pp
I
I
Short-circuit current, 5-V switch
Short-circuit current, 12-V switch
vs Junction temperature
vs Junction temperature
22
SC(xVCC)
23
SC(xVPP)
SUPPLY CURRENT
vs
JUNCTION TEMPERATURE
100
V
V
= V
= V
= 5 V
= 12 V
O(AVCC)
O(AVPP)
O(BVCC)
O(BVPP)
No load
95
90
85
80
75
–50
50
100
0
150
T
J
– Junction Temperature – °C
Figure 15
†
t = pulse tested
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TPS2202AI
DUAL-SLOT PC CARD POWER-INTERFACE SWITCH
WITH RESET FOR SERIAL PCMCIA CONTROLLER
SLVS123A – SEPTEMBER 1995 – REVISED JUNE 1998
†
TYPICAL CHARACTERISTICS
3.3-V SWITCH
STATIC DRAIN-SOURCE ON-STATE RESISTANCE
vs
5-V SWITCH
STATIC DRAIN-SOURCE ON-STATE RESISTANCE
vs
JUNCTION TEMPERATURE
JUNCTION TEMPERATURE
400
240
V
DD
V
CC
= 5 V
= 5 V
V
DD
V
CC
= 5 V
= 3.3 V
350
300
250
200
150
220
200
180
160
140
120
100
80
100
50
0
–50 –25
0
25
50
75
100
125
–50 –25
0
25
50
75
100
125
T
J
– Junction Temperature – °C
T
J
– Junction Temperature – °C
Figure 16
Figure 17
12-V SWITCH
5-V SWITCH
OUTPUT VOLTAGE
vs
STATIC DRAIN-SOURCE ON-STATE RESISTANCE
vs
JUNCTION TEMPERATURE
OUTPUT CURRENT
5.05
1700
V
DD
V
CC
= 5 V
= 5 V
V
DD
V
pp
= 5 V
= 12 V
5
1500
1300
1100
900
–40°C
4.95
4.9
25°C
4.85
85°C
125°C
700
4.8
4.75
500
–50 –25
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0
25
50
75
100
125
I
– Output Current – A
T
J
– Junction Temperature – °C
O(xVCC)
Figure 18
Figure 19
†
t = pulse tested
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TPS2202AI
DUAL-SLOT PC CARD POWER-INTERFACE SWITCH
WITH RESET FOR SERIAL PCMCIA CONTROLLER
SLVS123A – SEPTEMBER 1995 – REVISED JUNE 1998
†
TYPICAL CHARACTERISTICS
3-V SWITCH
OUTPUT VOLTAGE
vs
V
SWITCH
pp
OUTPUT VOLTAGE
vs
OUTPUT CURRENT
OUTPUT CURRENT
12.05
12
3.35
V
DD
V
pp
= 5 V
= 12 V
V
DD
V
CC
= 5 V
= 3.3.3 V
3.3
3.25
3.2
–40°C
25°C
–40°C
25°C
11.95
11.90
11.85
11.80
3.15
3.1
85°C
125°C
125°C
85°C
3.05
0
0.02
0.04
0.06
0.08
0.1
0.12
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
I
– Output Current – A
I
– Output Current – A
O(xVPP)
O(xVCC)
Figure 20
Figure 21
5-V SWITCH
12-V SWITCH
SHORT-CIRCUIT CURRENT
vs
SHORT-CIRCUIT CURRENT
vs
JUNCTION TEMPERATURE
JUNCTION TEMPERATURE
400
350
300
250
200
2
V
DD
V
pp
= 5 V
= 12 V
V
DD
V
CC
= 5 V
= 5 V
1.5
1
150
100
0.5
–50
0
J
50
100
150
–50
0
50
100
150
T
– Junction Temperature – °C
T
– Junction Temperature – °C
J
Figure 22
Figure 23
†
t = pulse tested
12
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TPS2202AI
DUAL-SLOT PC CARD POWER-INTERFACE SWITCH
WITH RESET FOR SERIAL PCMCIA CONTROLLER
SLVS123A – SEPTEMBER 1995 – REVISED JUNE 1998
APPLICATION INFORMATION
overview
PC Cards were initially introduced as a means to add EEPROM (flash memory) to portable computers with
limited on-board memory. The idea of add-in cards quickly took hold; modems, wireless LANs, GPS systems,
multimedia, and hard-disk versions were soon available. As the number of PC Card applications grew, the
engineering community quickly recognized the need for a standard to ensure compatibility across platforms.
To this end, the PCMCIA (Personal Computer Memory Card International Association) was established,
comprised of members from leading computer, software, PC card, and semiconductor manufacturers. One key
goal was to realize the “plug and play” concept. Cards and hosts from different vendors should be compatible
and able to communicate with one another transparently.
PC Card power specification
Systemcompatibilityalsomeanspowercompatibility. Themostcurrentsetofspecifications(PCCardStandard)
set forth by the PCMCIA committee states that power is to be transferred between the host and the card through
eight of the PC Card connector’s 68 terminals. This power interface consists of two V , two V , and four
CC
pp
ground terminals. Multiple V and ground terminals minimize connector-terminal and line resistance. The two
CC
V
terminals were originally specified as separate signals but are commonly tied together in the host to form
pp
a single node to minimize voltage losses. Card primary power is supplied through the V
flash-memory programming and erase voltage is supplied through the V terminals. As each terminal is rated
and V can theoretically supply up to 1 A, assuming equal terminal resistance and no terminal
failure. A conservative design would limit current to 500 mA. Some applications, however, require higher V
terminals;
CC
pp
to 0.5 A, V
CC
pp
CC
currents. Disk drives, for example, may need as much as 750-mA peak current to create the initial torque
necessary to spin up the platter. V currents, on the other hand, are defined by flash-memory programming
pp
requirements, typically under 120 mA.
future power trends
The 1-A physical-terminal current alluded to in the PC Card specification has caused some host-system
engineers to believe they are required to deliver 1 A within the voltage tolerance of the card. Future applications,
suchasRFcards, couldusetheextrapowerfortheirradiotransmitters. The5 Wrequiredforthesecardsrequire
very robust power supplies and special cooling considerations. The limited number of host sockets that are able
to support cards makes the market for these high-powered PC Cards uncertain. The vast majority of the cards
requirelessthan600mAcontinuouscurrent, andthetrendistowardsevenlowerpoweredPCCardsthatassure
compatibility with a greater number of host systems. Recognizing the need for power derating, an ad hoc
committee of the PCMCIA is currently working to limit the amount of steady-state dc current to the
PC Card to something less than the currently implied 1 A. When a system is designed to support 1 A, the switch
r
, power-supply requirements, and PC Card cooling need to be carefully considered.
DS(on)
designing around 1-A delivery
Delivering 1 A means minimizing voltage and power losses across the PC Card power interface, which requires
that designers trade off switch resistance and the cost associated with large-die (low r
) MOSFET
DS(on)
transistors. The PC Card standard requires that 5 V ±5% or 3.3 V ±0.3 V be supplied to the card. The
approximate 10% tolerance for the 3.3-V supply makes the 3.3-V r less critical than the 5-V switch. A
DS(on)
conservative approach is to allow 2% for voltage-regulator tolerance and 1% for etch- and pin-resistance drops,
which leaves 2% (100 mV) for voltage drop at the 5-V switch and at least 6% (198 mV) for the 3.3-V switch.
Calculating the r
necessary to support a 100 mV or 198 mV switch loss, using R = E/I and setting I = 1 A,
DS(on)
the 5-V and 3.3-V switches would need to be 100 mΩ and 198 mΩ respectively. One solution would be to pay
for a more expensive switch with lower r . A second, less expensive approach is to increase the headroom
DS(on)
of the power supply–for example, to increase the 5 V supply 1.5% or to 5.075 ±2%. Working through the
numbers once more, the 2% for the regulator plus 1 % for etch and terminal losses leaves 97% or 4.923 V. The
allowable
13
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TPS2202AI
DUAL-SLOT PC CARD POWER-INTERFACE SWITCH
WITH RESET FOR SERIAL PCMCIA CONTROLLER
SLVS123A – SEPTEMBER 1995 – REVISED JUNE 1998
APPLICATION INFORMATION
designing around 1-A delivery (continued)
voltage loss across the power distribution switch is now 4.923 V minus 4.750 V or 173 mV. Therefore, a switch
with 173 mΩ or less could deliver 1 A or greater. Setting the power supply high is a common practice for
delivering voltages to allow for system switch connector and etch losses. This practice has a minimal effect on
overall battery life. In the example above, setting the power supply 1.5% high would only decrease a 3-hour
battery life by approximately 2.7 minutes, trivial when compared with the decrease in battery life when running
a 5-W PC Card.
heat dissipation
A greater concern in delivering 1 A or 5 W is the ability of the host to dissipate the heat generated by the PC
Card. For desktop computers the solution is simpler: locate the PC Card cage such that it receives convection
cooling from the forced air of the fan. Notebooks and other handheld equipment will not be able to rely on
convection, but on conduction of heat away from the PC Card through the rails into the card cage. This is difficult
because PC Card/card cage heat transfer is very poor. A typical design scenario would require the PC Card
to be held at 60°C maximum with the host platform operating as high as 50°C. Preliminary testing reveals that
a PC Card can have a 20°C rise, exceeding the 10°C differential in the example, when dissipating less than 2
Wofcontinuouspower. Sixtydegreescentigradewaschosenbecauseitisthemaximumoperatingtemperature
allowable by PC Card specification. Power handling requirements and temperature rises are topics of concern
and are currently being addressed by the PCMCIA committee.
overcurrent and over-temperature protection
PC Cards are inherently subject to damage that can result from mishandling. Host systems require protection
against short-circuited cards that could lead to power supply or PCB-trace damage. Even systems sufficiently
robust to withstand a short circuit would still undergo rapid battery discharge into the damaged PC Card,
resulting in the rather sudden and unacceptable loss of system power. Most hosts include fuses for protection.
The reliability of fused systems is poor though, as blown fuses require troubleshooting and repair, usually by
the manufacturer.
The TPS2202AI takes a two-pronged approach to overcurrent protection. First, instead of fuses, sense FETs
monitor each of the power outputs. Excessive current generates an error signal that linearly limits the output
current, preventing host damage or failure. Sense FETs, unlike sense resistors or polyfuses, have an added
advantage in that they do not add to the series resistance of the switch and thus produce no additional voltage
losses. Second, when an overcurrent condition is detected, the TPS2202AI asserts a signal at OC that can be
monitored by the microprocessor to initiate diagnostics and/or send the user a warning message. In the event
that an overcurrent condition persists, causing the IC to exceed its maximum junction temperature,
thermal-protection circuitry activates, shutting down all power outputs until the device cools to within a safe
operating region.
12-V supply not required
Most PC Card switches use the externally supplied 12-V V power for switch-gate drive and other chip
pp
functions, which requires that power be present at all times. The TPS2202AI offers considerable power savings
by using an internal charge pump to generate the required higher voltages from the 5-V V
supply; therefore,
DD
the external 12-V supply can be disabled except when needed for flash-memory functions, thereby extending
battery lifetime. Do not ground the 12-V inputs when 12-V supply is not in use. Additional power savings are
realized by the TPS2202AI during a software shutdown in which quiescent current drops to a maximum of
1 µA.
14
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TPS2202AI
DUAL-SLOT PC CARD POWER-INTERFACE SWITCH
WITH RESET FOR SERIAL PCMCIA CONTROLLER
SLVS123A – SEPTEMBER 1995 – REVISED JUNE 1998
APPLICATION INFORMATION
voltage transitioning requirement
PC Cards, like portables, are migrating from 5 V to 3.3 V to minimize power consumption, optimize board space,
and increase logic speeds. The TPS2202AI is designed to meet all combinations of power delivery as currently
defined in the PCMCIA standard. The latest protocol accommodates mixed 3.3-V/5-V systems by first powering
the card with 5 V, then polling it to determine its 3.3-V compatibility. The PCMCIA specification requires that the
capacitors on 3.3-V-compatible cards be discharged to below 0.8 V before applying 3.3-V power. This ensures
that sensitive 3.3-V circuitry is not subjected to any residual 5-V charge and functions as a power reset. The
TPS2202AI offers a selectable V
specifications, to fully discharge the card capacitors while switching between V
and V ground state, in accordance with PCMCIA 3.3-V/5-V switching
CC
pp
voltages.
CC
output ground switches
SeveralPCMCIApower-distributionswitchesonthemarketdonothaveanactive-groundingFETswitch. These
devices do not meet the PC Card specification requiring a discharge of V within 100 ms. PC Card resistance
CC
can not be relied on to provide a discharge path for voltages stored on PC Card capacitance because of possible
high-impedance isolation by power-management schemes. A method commonly shown to alleviate this
problem is to add to the switch output an external 100 kΩ resistor in parallel with the PC Card. Considering that
this is the only discharge path to ground, a timing analysis will reveal that the RC time constant delays the
required discharge time to more than 2 seconds. The only way to ensure timing compatibility with PC Card
standardsistouseapower-distributionswitchthathasaninternalgroundswitch, likethatoftheTPS22xxfamily,
or add an external ground FET to each of the output lines with the control logic necessary to select it.
In summary, the TPS2202AI is a complete single-chip dual-slot PC Card power interface. It meets all currently
defined PCMCIA specifications for power delivery in 5-V, 3.3-V, and mixed systems, and offers a serial controller
interface. The TPS2202AI offers functionality, power savings, overcurrent and thermal protection, and fault
reporting in one 30-pin SSOP surface-mount package for maximum value added to new portable designs.
power supply considerations
The TPS2202AI has multiple pins for each of its 3.3-V, 5-V, and 12-V power inputs and for the switched V
CC
outputs. Any individual pin can conduct the rated input or output current. Unless all pins are connected in
parallel, the series resistance is significantly higher than that specified, resulting in increased voltage drops and
lost power. Both 12-V inputs must be connected for proper V switching; it is recommended that all input and
pp
output power pins be paralleled for optimum operation. The V
leads.
input lead must be connected to the 5-V input
DD
Although the TPS2202AI is fairly immune to power input fluctuations and noise, it is generally considered good
design practice to bypass power supplies typically with a 1-µF electrolytic or tantalum capacitor paralleled by
a 0.047-µF to 0.1-µF ceramic capacitor. It is strongly recommended that the switched V
and V outputs be
CC
pp
bypassed with a 0.1-µF or larger capacitor; doing so improves the immunity of the TPS2202AI to electrostatic
discharge (ESD). Care should be taken to minimize the inductance of PCB traces between the TPS2202AI and
theload. Highswitchingcurrentscanproducelargenegative-voltagetransients, whichforwardbiasessubstrate
diodes, resulting in unpredictable performance.
The TPS2202AI, unlike other PC Card power-interface switches, does not use the 12-V power supply for
switching or other chip functions. Instead, an internal charge pump generates the necessary voltage from V
,
DD
allowing the 12-V input supply to be shut down except when the V programming or erase voltage is needed.
pp
Careful system design using this feature reduces power consumption and extends battery lifetime.
The 3.3-V power input should not be taken higher than the 5-V input. Though doing so is nondestructive, this
results in high current flow into the device and could result in abnormal operation. In any case, this occurrence
indicates a malfunction of one input voltage or both which should be investigated.
Similarly, no pin should be taken below –0.3 V; forward biasing the parasitic-substrate diode results in substrate
currents and unpredictable performance.
15
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TPS2202AI
DUAL-SLOT PC CARD POWER-INTERFACE SWITCH
WITH RESET FOR SERIAL PCMCIA CONTROLLER
SLVS123A – SEPTEMBER 1995 – REVISED JUNE 1998
APPLICATION INFORMATION
RESET or RESET inputs
To ensure that cards are in a known state after power brownouts or system initialization, the PC Cards should
be reset at the same time as the host by applying a low impedance to the V
and V terminals. A
CC
pp
low-impedance output state allows discharging of residual voltage remaining on PC Card filter capacitance,
permittingthesystem(hostandPCCards)tobepoweredupconcurrently. TheRESETorRESETinputwillclose
internal switches S1, S4, S7, and S10 with all other switches left open (see TPS2202AI control-logic table). The
TPS2202AI remains in the low-impedance output state until the signal is deasserted and further data is clocked
in and latched. RESET or RESET is provided for direct compatibility with systems that use either an active-low
or active-high reset voltage supervisor. The unused pin is internally pulled up or down and should be left
unconnected.
overcurrent and thermal protection
TheTPS2202AIusessenseFETstocheckforovercurrentconditionsineachoftheV andV outputs. Unlike
CC
pp
sense resistors or polyfuses, these FETs do not add to the series resistance of the switch; therefore, voltage
and power losses are reduced. Overcurrent sensing is applied to each output separately. When an overcurrent
condition is detected, only the power output affected is limited; all other power outputs continue to function
normally. The OC indicator, normally a logic high, is a logic low when any overcurrent condition is detected,
providing for initiation of system diagnostics and/or sending a warning message to the user.
During power up, the TPS2202AI controls the rise time of the V
and V outputs and limits the current into
pp
CC
a faulty card or connector. If a short circuit is applied after power is established (e.g., hot insertion of a bad card),
current is initially limited only by the impedance between the short and the power supply. In extreme cases, as
much as 10 A to 15 A may flow into the short before the current limiting of the TPS2202AI engages. If the V
CC
orV outputsaredrivenbelowground, theTPS2202AImaylatchnondestructivelyinanoffstate. Cyclingpower
pp
will reestablish normal operation.
Overcurrent limiting for the V
0.75 A to 1.9 A, typically at about 1.3 A. The V outputs limit from 120 mA to 400 mA, typically around 200 mA.
outputs is designed to activate, if powered up, into a short in the range of
CC
pp
The protection circuitry acts by linearly limiting the current passing through the switch rather than initiating a full
shutdown of the supply. Shutdown occurs only during thermal limiting.
Thermal limiting prevents destruction of the IC from overheating if the package power-dissipation ratings are
exceeded. Thermal limiting disables all power outputs (both A and B slots) until the device has cooled.
calculating junction temperature
Theswitchresistance,r
is dependent on both r
,isdependentonthejunctiontemperature,T ,ofthedie.Thejunctiontemperature
J
DS(on)
DS(on)
and the current through the switch. To calculate T , first find r
from Figures
J
DS(on)
16, 17, and 18 using an initial temperature estimate about 50°C above ambient. Then calculate the power
dissipation for each switch, using the formula:
2
P
r
I
D
DS(on)
Next, sum the power dissipation and calculate the junction temperature:
°
108 C W
T
P
R
T , R
J
D
JA
A
JA
Compare the calculated junction temperature with the initial temperature estimate. If the temperatures are not
within a few degrees of each other, recalculate using the calculated temperature as the initial estimate.
16
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TPS2202AI
DUAL-SLOT PC CARD POWER-INTERFACE SWITCH
WITH RESET FOR SERIAL PCMCIA CONTROLLER
SLVS123A – SEPTEMBER 1995 – REVISED JUNE 1998
APPLICATION INFORMATION
logic input and outputs
The serial interface consists of DATA, CLOCK, and LATCH leads. The data is clocked in on the positive leading
edge of the clock (see Figure 2). The 9-bit (D0 through D8) serial data word is loaded during the positive edge
of the latch signal. The latch signal should occur before the next positive leading edge of the clock.
The shutdown bit of the data word places all V
quiescent current to 1 µA to conserve battery power.
and V outputs in a high-impedance state and reduces chip
pp
CC
The TPS2202AI serial interface is designed to be compatible with serial-interface PCMCIA controllers and
current PCMCIA and Japan Electronic Industry Development Association (JEIDA) standards.
An overcurrent output (OC) is provided to indicate an overcurrent condition in any of the V
previously discussed.
or V outputs as
pp
CC
17
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TPS2202AI
DUAL-SLOT PC CARD POWER-INTERFACE SWITCH
WITH RESET FOR SERIAL PCMCIA CONTROLLER
SLVS123A – SEPTEMBER 1995 – REVISED JUNE 1998
APPLICATION INFORMATION
TPS2202AI
Card A
S7
S8
S9
18
52
8
V
V
pp1
S1
S2
S3
pp2
9
10
11
17
51
V
V
CC
15
16
3.3V
3.3V
CS
CC
CS
Card B
CC
17
S4
S5
S6
3.3V
20
21
22
17
51
CS
V
V
CC
S10
S11
S12
1
2
5V
5V
18
52
V
V
pp1
23
30
CS
pp2
5V
7
12V
12V
24
Internal
Current Monitor
6
14
RESET
Supervisor
RESET
Thermal
3
4
5
DATA
CLOCK
LATCH
Serial
Interface
25
V
DD
Controller
19
13
18
BPWR_GOOD
APWR_GOOD
OC
GND
12
Figure 24. Internal Switching Matrix
18
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TPS2202AI
DUAL-SLOT PC CARD POWER-INTERFACE SWITCH
WITH RESET FOR SERIAL PCMCIA CONTROLLER
SLVS123A – SEPTEMBER 1995 – REVISED JUNE 1998
APPLICATION INFORMATION
TPS2202AI control logic
AVPP
CONTROL SIGNALS
D0 A_VPP_PGM D1 A_VPP_VCC
INTERNAL SWITCH SETTINGS
S8
OUTPUT
VAVPP
0 V
D8 SHDN
S7
S9
1
1
1
1
0
0
0
1
1
X
0
1
0
1
X
CLOSED
OPEN
OPEN
OPEN
OPEN
OPEN
CLOSED
OPEN
OPEN
OPEN
CLOSED
OPEN
OPEN
†
VCC
VPP(12 V)
Hi-Z
OPEN
OPEN
Hi-Z
BVPP
CONTROL SIGNALS
INTERNAL SWITCH SETTINGS
S11
OUTPUT
VBVPP
0 V
D8 SHDN
D4 B_VPP_PGM D5 B_VPP_VCC
S10
S12
OPEN
OPEN
CLOSED
OPEN
OPEN
1
1
1
1
0
0
0
1
1
X
0
1
0
1
X
CLOSED
OPEN
OPEN
OPEN
OPEN
OPEN
CLOSED
OPEN
‡
VCC
VPP(12 V)
Hi-Z
OPEN
OPEN
Hi-Z
AVCC
CONTROL SIGNALS
INTERNAL SWITCH SETTINGS
S2
OUTPUT
VAVCC
0 V
D8 SHDN
D3 A_VCC3
D2 A_VCC5
S1
S3
1
1
1
1
0
0
0
1
1
X
0
1
0
1
X
CLOSED
OPEN
OPEN
CLOSED
OPEN
OPEN
OPEN
CLOSED
OPEN
OPEN
3.3 V
5 V
OPEN
CLOSED
OPEN
OPEN
0 V
OPEN
Hi-Z
BVCC
CONTROL SIGNALS
INTERNAL SWITCH SETTINGS
S5
OUTPUT
VBVCC
0 V
D8 SHDN
D6 B_VCC3
D7 B_VCC5
S4
S6
1
1
1
1
0
0
0
1
1
X
0
1
0
1
X
CLOSED
OPEN
OPEN
CLOSED
OPEN
OPEN
OPEN
CLOSED
OPEN
OPEN
3.3 V
5 V
OPEN
CLOSED
OPEN
OPEN
0 V
OPEN
Hi-Z
†
‡
Output depends on AVCC
Output depends on BVCC
ESD protection
All TPS2202AI inputs and outputs incorporate ESD-protection circuitry designed to withstand a 2-kV
human-body-model discharge as defined in MIL-STD-883C, Method 3015. The V and V outputs can be
CC
pp
exposed to potentially higher discharges from the external environment through the PC Card connector.
Bypassing the outputs with 0.1-µF capacitors protects the devices from discharges up to 10 kV.
19
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TPS2202AI
DUAL-SLOT PC CARD POWER-INTERFACE SWITCH
WITH RESET FOR SERIAL PCMCIA CONTROLLER
SLVS123A – SEPTEMBER 1995 – REVISED JUNE 1998
APPLICATION INFORMATION
5 V
V
DD
AVCC
AVCC
AVCC
V
V
CC
CC
0.1 µF
PC Card
Connector A
12V
12V
12 V
V
pp1
V
pp2
BVCC
BVCC
BVCC
V
CC
CC
TPS2202AI
0.1 µF
V
PC Card
Connector B
V
pp1
V
pp2
AVPP
AVPP
0.1 µF
0.1 µF
5V
5V
5V
5 V
BVPP
BVPP
3.3V
3.3V
3.3V
3.3 V
DATA
DATA
CLOCK
LATCH
CLOCK
LATCH
System Voltage
Supervisor
or
RESET
RESET
PCMCIA
Controller
Bus Reset
APWR_GOOD
BPWR_GOOD
OC
AVPPGOOD
BVPPGOOD
To CPU
GND
CS
Shutdown Signal
From CPU
Figure 25. Detailed Interconnections and Capacitor Recommendations
20
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TPS2202AI
DUAL-SLOT PC CARD POWER-INTERFACE SWITCH
WITH RESET FOR SERIAL PCMCIA CONTROLLER
SLVS123A – SEPTEMBER 1995 – REVISED JUNE 1998
MECHANICAL DATA
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
28 PIN SHOWN
0,38
0,22
0,65
28
M
0,15
15
0,15 NOM
5,60
5,00
8,20
7,40
Gage Plane
1
14
0,25
A
0°–8°
1,03
0,63
Seating Plane
0,10
2,00 MAX
0,05 MIN
14
PINS **
16
20
24
28
30
38
DIM
6,50
5,90
6,50
5,90
7,50
6,90
8,50
7,90
10,50
9,90
10,50 12,90
A MAX
A MIN
9,90
12,30
4040065 /D 02/98
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
21
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TPS2202AI
DUAL-SLOT PC CARD POWER-INTERFACE SWITCH
WITH RESET FOR SERIAL PCMCIA CONTROLLER
SLVS123A – SEPTEMBER 1995 – REVISED JUNE 1998
MECHANICAL DATA
DF (R-PDSO-G30)
PLASTIC SMALL-OUTLINE PACKAGE
0,45
0,25
M
0,12
0,80
30
16
7,80 10,80
7,20 10,00
0,15 NOM
1
15
Gage Plane
13,10
12,50
0,25
0°–8°
0,84
0,76
Seating Plane
0,10
2,65 MAX
0,10 MIN
4040038/B 02/95
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
22
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
IMPORTANT NOTICE
Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
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In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
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