TPS2210APWPRG4_技术文档

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SLVS449A − DECEMBER 2002 − REVISED MAY 2003

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FEATURES

APPLICATIONS

D

Notebook and Desktop Computers

Set-Top Boxes

D

Fully Integrated V

Single-Slot or Dual-Slot PC Card Interface

and V

Switching for

PP

CC

2

Personal Digital Assistants(PDAs)

Digital Cameras

P C 3-Lead Serial Interface Compatible With

CardBus Controller

Bar Code Scanners

D

Meets PC Card Standard

RESET for System Initialization of PC Cards

DESCRIPTION

12-V Supplies Can Be Disabled Except During

12-V Flash Programming

The TPS2204A and TPS2206A PC CardBus

power-interface switches provide an integrated

power-management solution for two PC Card sockets.

The TPS2210A is a single-slot option for this family of

devices. These devices allow the controlled distribution of

3.3 V, 5 V, and 12 V to each card slot. The current-limiting

and thermal-protection features eliminate the need for

fuses. Current-limit reporting helps the user isolate a

system fault. The switch r_DS(on)and current-limit values

are set for the peak and average current requirements

stated in the PC Card specification, and are optimized for

cost.

D

Short-Circuit and Thermal Protection

24-Pin HTSSOP (PWP), 30-Pin SSOP (DB),

and 32-Pin TSSOP (DAP) Packages

D

Compatible With 3.3-V, 5-V, and 12-V PC

Cards

Low r

3.3-V V

(95-mΩ, 5-V V

Switch; 85-mΩ

CC

DS(on)

Switch)

CC

Single-Slot Switch: TPS2210A

Dual-Slot Switch: TPS2204A and TPS2206A

The TPS2206A is pin and/or functionally compatible with

the TPS2206, TPS2216, TPS2216A, TPS2226,

TPS2226A, and TPS2228 with a few exceptions, as

shown in the Available Options table.

Break-Before-Make Switching

AVAILABLE OPTIONS OF THE TPS2206A PIN COMPATABLE SWITCHES

PIN VARIATION

INDEPENDENT

INPUT

VOLTAGES

PART NUMBER

V

PP

SWITCHING

RESET

Yes

RESET

Yes

No

SHDN

No

MODE

No

STBY

No

TPS2206

TPS2206A

TPS2216

TPS2216A

TPS2226

TPS2226A

TPS2228

No

3.3 V, 5 V, 12 V

1.8 V, 3.3 V, 5 V

Yes

No

(1)

Yes/No

Yes

No

Yes

No

Yes

No

Yes/No

Yes

No

Yes

No

Yes

No

(1)

Selected by MODE pin.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments

semiconductor products and disclaimers thereto appears at the end of this data sheet.

2

P C is a trademark of Texas Instruments.

PC Card and CardBus are trademarks of PCMCIA (Personal Computer Memory Card International Association).

ꢁꢊ ꢌ ꢋꢖ ꢉ ꢀꢐ ꢌꢑ ꢋ ꢆꢀꢆ ꢗꢘ ꢙꢚ ꢛ ꢜꢝ ꢞꢗꢚꢘ ꢗꢟ ꢠꢡ ꢛ ꢛ ꢢꢘꢞ ꢝꢟ ꢚꢙ ꢣꢡꢤ ꢥꢗꢠ ꢝꢞꢗ ꢚꢘ ꢦꢝ ꢞꢢꢧ ꢁꢛ ꢚꢦꢡ ꢠꢞꢟ

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ꢁꢛ ꢚ ꢦꢡꢠ ꢞ ꢗꢚ ꢘ ꢣꢛ ꢚ ꢠ ꢢ ꢟ ꢟ ꢗꢘ ꢬ ꢦꢚ ꢢ ꢟ ꢘꢚꢞ ꢘꢢ ꢠꢢ ꢟꢟ ꢝꢛ ꢗꢥ ꢫ ꢗꢘꢠ ꢥꢡꢦ ꢢ ꢞꢢ ꢟꢞꢗ ꢘꢬ ꢚꢙ ꢝꢥ ꢥ ꢣꢝ ꢛ ꢝꢜ ꢢꢞꢢ ꢛ ꢟꢧ

Copyright  2002 − 2003, Texas Instruments Incorporated

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SLVS449A − DECEMBER 2002 − REVISED MAY 2003

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during

storage or handling to prevent electrostatic damage to the MOS gates.

ORDERING INFORMATION

PACKAGED DEVICES

T

A

PLASTIC SMALL OUTLINE

(DB)

POWERPAD PLASTIC SMALL

OUTLINE (DAP−32)

OUTLINE (PWP−24)

TPS2204APWP

TPS2210APWP

−40°C to 85°C

TPS2206ADB

TPS2206ADAP

(1)

The DB, PWP, and DAP packages are available taped and reeled. Add R suffix to device type (e.g., TPS2206ADBR) for taped and reeled.

PACKAGE DISSIPATION RATINGS

T

≤ 25°C

DERATING FACTOR

T

= 70°C

T = 85°C

A

(1)

PACKAGE

POWER RATING

ABOVE T = 25°C

POWER RATING POWER RATING

A

DB (30)

821.46 mW

10.95 mW/°C

42.55 mW/°C

33.22 mW/°C

328.58 mW

1276.5 mW

996.67 mW

164.29 mW

638.29 mW

498.33 mW

DAP (32)

PWP (24)

3191.4 mW

2491.6 mW

(1)

These devices are mounted on an JEDEC low-k board (2-oz. traces on surface).

ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range unless otherwise noted

(1)

UNITS

V

)

−0.3 V to 5.5

−0.3 V to 14

−0.3 V to 6

−0.3 V to 14

V

I(3.3V

Input voltage range for card power

Logic input/output voltage

I(5V)

I(12V)

V

O(xVCC)

Output voltage

O(xVPP)

Continuous total power dissipation

See Dissipation Rating Table

Internally Limited

−40°C to 100

−55°C to 150

260

I

O(xVCC)

Output current

O(xVPP)

Operating virtual junction temperature range, T

°C

J

Storage temperature range, T

STG

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds)

OC sink current

°C

10

mA

(1)

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

PowerPAD is a trademark of Texas Instruments.

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SLVS449A − DECEMBER 2002 − REVISED MAY 2003

RECOMMENDED OPERATING CONDITIONS

MIN MAX

UNIT

V

3

7

3.6

5.5

13.5

1

I(3.3V)(1)

Input voltage, V

is required for all circuit operations. 5 V and

12 V are only required for their respective functions.

I(3.3V)

V

I(5V)

I(12V)

I

at T = 100°C

A

O(xVCC)

J

Output current, I

O

at T = 100°C

100

2.5

mA

MHz

O(xVPP)

J

Clock frequency, f

(clock)

Data

200

250

100

250

−40

Latch

Clock

Reset

Pulse duration, t

ns

w

Data-to-clock hold time, t (see Figure 2)

ns

°C

h

Data-to-clock setup time, t (see Figure 2)

su

Latch delay time, t

(see Figure 2)

d(latch)

d(clock)

Clock delay time, t

(see Figure 2)

Operating virtual junction temperature, T (maximum to be calculated at worst case P at 85°C ambient)

100

J

D

(1)

It is understood that for V < 3 V, voltages within the absolute maximum ratings applied to pin 5 V or pin 12 V will not damage the IC.

I(3.3V)

ELECTRICAL CHARACTERISTICS

T = 25°C, V

J I(5V)

= 5 V, V

I(3.3V)

= 3.3 V, V = 12 V, all outputs unloaded (unless otherwise noted)

I(12V)

POWER SWITCH

(1)

TEST CONDITIONS

PARAMETER

3.3V to xVCC

MIN

TYP

85

MAX

110

140

130

160

1

UNIT

I

= 750 mA each

O

(2)

= 750 mA each, T = 100°C

110

95

O

J

mΩ

= 500 mA each

O

(2)

5V to xVCC

Static drain-

= 500 mA each, T = 100°C

120

0.8

1

O

J

source on-state

resistance

r

DS(on)

= 50 mA each

O

(2)

3.3V or 5V to xVPP

= 50 mA each, T = 100°C

1.3

2.5

3.4

1

O

J

Ω

= 50 mA each

2

O

(2)

12V to xVPP

= 50 mA each, T = 100°C

2.5

0.7

0.4

O

J

Discharge at xVCC

Discharge at xVPP

= 1 mA

0.5

0.2

Output discharge

resistance

O(disc)

kΩ

0.5

Limit (steady-state value),

output powered into a short

circuit

I

1

120

1

1.4

200

1.4

2

300

2

A

OS(xVCC)

OS(xVPP)

OS(xVCC)

OS(xVPP)

mA

A

I

Short-circuit output current

Thermal shutdown

OS

Limit (steady-state value),

output powered into a short

120

200

300

mA

circuit, T = 100°C

J

Thermal trip point, T

Rising temperature

135

10

3

J

°C

(2)

temperature

Hysteresis, T

J

5V to xVCC = 5 V, with 100-mΩ short to GND

5V to xVPP = 5 V, with 100-mΩ short to GND

(3)(4)

Current-limit response time

µs

(1)

(2)

(3)

(4)

Pulse-testing techniques maintain junction temperature close to ambient temperature; thermal effects must be taken into account separately.

TPS2204A and TPS2206A: two switches on. TPS2210A: one switch on.

Specified by design; not tested in production.

From application of short to 110% of final current limit.

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SLVS449A − DECEMBER 2002 − REVISED MAY 2003

ELECTRICAL CHARACTERISTICS Continued

T = 25°C, V

= 5 V, V

I(3.3V)

= 3.3 V, V

I(12V)

= 12 V, all outputs unloaded (unless otherwise noted)

J

I(5V)

PARAMETER

TEST CONDITIONS

MIN

TYP

140

8

MAX

200

12

180

2

UNIT

I

I(3.3V)

Normal

operation

V (xVCC) = V (xVPP) = 3.3 V and

O O

also for RESET = 0 V

I(5V)

100

0.3

0.1

0.3

Input current,

quiescent

I(12V)

I(3.3V)

I(5V)

I

µA

Shutdown

mode

2

V (xVCC) = V (xVPP) = Hi-Z

O

2

I(12V)

10

50

10

50

V

= 5 V,

O(xVCC)

= V

= 0 V

T = 100°C

I(5V)

I(12V)

Leakage current,

output off state

J

I

Shutdown mode

µA

lkg

V

= 12 V,

O(xVPP)

I(5V)

= V

= 0 V

T = 100°C

J

I(12V)

LOGIC SECTION (CLOCK, DATA, LATCH, RESET, SHDN, OC)

PARAMETER

TEST CONDITIONS

RESET = 5.5 V

MIN

−1

TYP

MAX

1

UNIT

(1)

I

I(RESET)

RESET = 0 V

SHDN = 5.5 V

SHDN = 0 V

LATCH = 5.5 V

LATCH = 0 V

0 V to 5.5 V

−30

−1

−20

−10

1

(1)

I

I(SHDN)

I(LATCH)

−50

−3

50

1

I

Input current, logic

µA

(1)

I

−1

2

1

I(CLOCK, DATA)

V

High-level input voltage, logic

Low-level input voltage, logic

V

IH

0.8

0.4

1

IL

Output saturation voltage at OC

Leakage current at OC

I

O

= 2 mA

0.14

0

V

O(sat)

I

V

= 5.5 V

µA

lkg

(1)

O(/OC)

LATCH has low current pulldown. RESET and SHDN have low-current pullup.

UVLO AND POR (POWER-ON RESET)

PARAMETER

TEST CONDITIONS

MIN

TYP

2.7

MAX

UNIT

V

Input voltage at 3.3V pin, UVLO

UVLO hysteresis voltage at VA

Input voltage at 5V pin, UVLO

3.3-V level below which all switches are Hi-Z

5-V level below which only 5V switches are Hi-Z

Delay from voltage hit (step from 3 V to 2.3 V)

2.4

2.9

I(3.3V)

hys(3.3V)

I(5V)

(1)

100

2.5

mV

V

2.3

2.9

(1)

UVLO hysteresis voltage at 5 V

100

mV

hys(5V)

(1)

Delay time for falling response, UVLO

t

df

4

µs

to Hi-Z control (90% V to GND)

G

3.3-V voltage below which POR is asserted

causing a RESET internally with all line

switches open and all discharge switches

closed.

(1)

Input voltage, power-on reset

V

1.7

V

I(POR)

(1)

Specified by design; not tested in production.

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SLVS449A − DECEMBER 2002 − REVISED MAY 2003

SWITCHING CHARACTERISTICS

V

= 5 V, T = 25°C, V

= 3.3 V, V

I(5V)

= 5 V, V

I(12)

= 12 V (not applicable for TPS2223A) all outputs unloaded (unless otherwise noted)

CC

A

I(3.3V)

(1)

(2)

PARAMETER

LOAD CONDITION

MIN

TYP

0.9

MAX

UNIT

TEST CONDITIONS

V

= 5 V

C

I

= 0.1 µF, C

= 0.1 µF,

= 0 A

O(xVCC)

L(xVCC)

O(xVCC)

L(xVPP)

O(xVPP)

= 0 A,

I

= 12 V

= 5 V

0.26

1.1

O(xVPP)

O(xVCC)

O(xVPP)

O(xVCC)

(3)

t

r

Output rise times

ms

C

I

= 150 µF, C

= 10 µF,

= 50 mA

L(xVCC)

O(xVCC)

L(xVPP)

= 0.75 A, I

= 12 V

= 5 V,

0.6

O(xVPP)

0.5

0.2

Discharge switches ON

C

I

= 0.1 µF, C

= 0.1 µF,

= 0 A

L(xVCC)

O(xVCC)

L(xVPP)

O(xVPP)

= 0 A,

I

V

= 12 V,

O(xVPP)

Discharge switches ON

(3)

Output fall times

t

f

ms

V

= 5 V

2.35

3.9

2

C

I

= 150 µF, C

= 10 µF,

= 50 mA

O(xVCC)

L(xVCC)

O(xVCC)

L(xVPP)

= 0.75 A, I

= 12 V

O(xVPP)

t

pdon

pdoff

pdon

pdoff

pdon

pdoff

pdon

pdoff

pdon

pdoff

pdon

pdoff

pdon

pdoff

pdon

pdoff

pdon

pdoff

pdon

pdoff

Latch↑ to xVPP (12 V)

Latch↑ to xVPP (5 V)

Latch↑ to xVPP (3.3 V)

Latch↑ to xVCC (5 V)

Latch↑ to xVCC (3.3V)

Latch↑ to xVPP (12 V)

Latch↑ to xVPP (5 V)

Latch↑ to xVPP (3.3 V)

Latch↑ to xVCC (5 V)

Latch↑ to xVCC (3.3V)

0.62

0.77

0.51

0.75

0.52

0.3

2.5

0.3

2.8

2.2

0.8

0.6

0.8

0.6

2.5

0.5

2.6

C

I

= 0.1 µF, C

= 0.1 µF,

= 0 A

L(xVCC)

O(xVCC)

L(xVPP)

O(xVPP)

ms

= 0 A,

I

Propagation delay

(3)

t

pd

times

C

= 150 µF, C

= 10 µF,

= 50 mA

L(xVCC)

O(xVCC)

L(xVPP)

ms

I

= 0.75 A, I

O(xVPP)

(1)

(2)

(3)

Refer to Parameter Measurement Information in Figure 1.

No card inserted, assumes a 0.1-µF output capacitor (see Figure 1).

Specified by design; not tested in production.

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SLVS449A − DECEMBER 2002 − REVISED MAY 2003

PIN ASSIGNMENTS

TPS2206A

DB PACKAGE

(TOP VIEW)

TPS2206A

DAP PACKAGE

(TOP VIEW)

5V

DATA

CLOCK

LATCH

NC

1

2

3

4

5

6

7

8

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

5V

NC

SHDN

12V

BVPP

BVCC

NC

5V

NC

5V

NC

SHDN

12V

BVPP

BVCC

OC

NC

3.3V

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

DATA

CLOCK

LATCH

NC

12V

AVPP

AVCC

GND

NC

RESET

3.3V

9

12V

10

11

12

13

14

15

AVPP

AVCC

GND

RESET

NC

OC

3.3V

NC − No internal connection

3.3V

TPS2204A

PWP PACKAGE

(TOP VIEW)

TPS2210A

PWP PACKAGE

(TOP VIEW)

5V

DATA

CLOCK

LATCH

NC

5V

1

2

3

4

5

6

7

8

1

2

3

4

5

6

7

8

24

23

22

21

20

19

18

17

16

15

14

13

5V

NC

SHDN

12V

BVPP

BVCC

NC

OC

3.3V

24

23

22

21

20

19

18

17

16

15

14

13

NC

SHDN

12V

NC

5V

DATA

CLOCK

LATCH

NC

12V

AVPP

AVCC

GND

AVPP

AVCC

GND

9

NC

OC

NC

10

11

12

10

11

12

RESET

3.3V

6

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SLVS449A − DECEMBER 2002 − REVISED MAY 2003

TERMINAL FUNCTIONS

TERMINAL

NUMBER

TPS2206A

I/O

DESCRIPTION

TPS2204A

TPS2210A

NAME

PWP

13, 14

1, 2, 24

DB

DAP

PWP

3.3V

15, 16, 17

1, 2, 30

16, 17, 18

1, 2, 32

13

I

3.3-V input for card power and chip power

5-V V input for card power

5V

1, 2

CC

12-V V

input for card power (xVPP). The two 12-V pins must be

externally connected.

PP

12V

7, 20

9, 10

8

7, 24

9, 10, 11

8

8, 25

10, 11, 12

9

7, 20

9, 10

8

I

AVCC

AVPP

O

Switched output that delivers 0 V, 3.3 V, 5 V, or high impedance to card.

Switched output that delivers 0 V, 3.3 V, 5 V, 12 V, or high impedance

to card.

BVCC

BVPP

CLOCK

DATA

17, 18

20, 21, 22

21, 22, 23

−−

4

O

I

Switched output that delivers 0 V, 3.3 V, 5 V, or high impedance.

Switched output that delivers 0 V, 3.3 V, 5 V, 12 V, or high impedance.

Logic-level clock for serial data word

19

4

23

4

24

5

3

4

3

I

Logic-level serial data word

GND

11

5

12

5

13

6

11

5

Ground

LATCH

I

Logic-level latch for serial data word, internal pulldown

6, 14,

16 − 19,

22−24

6, 16, 22,

23

13, 19,

26−29

3, 7, 15,

19, 27−31

NC

OC

No internal connection

Open-drain overcurrent reporting output that goes low when an

overcurrent condition exists.

15

18

20

15

O

An external pullup is required.

Hi-Z (open) all switches. Identical function to serial D8. Asynchronous

active-low command, internal pullup

SHDN

21

12

25

14

26

14

21

12

I

Logic-level RESET input active low. Do not connect if terminal 6 is

used.

RESET

TYPICAL PC CARD POWER−DISTRIBUTION APPLICATION

Power Supply

TPS2206A

V

1

2

AVPP

12 V

PP

PC

Card A

5 V

PP

AVCC

VCC

3.3 V

AVCC

RESET

SHDN

Supervisor

V

1

BVPP

PP

2

PC

Card b

3

PP

Serial

Interface

BVCC

VCC

PCMCIA

Controller

OC

7

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SLVS449A − DECEMBER 2002 − REVISED MAY 2003

PARAMETER MEASUREMENT INFORMATION

xVPP

xVCC

I

O(xVPP)

O(xVCC)

LOAD CIRCUIT (xVPP)

LOAD CIRCUIT (xVCC)

V

DD

LATCH

50%

GND

t

pd(off)

t

pd(on)

V

I(12V/5V/3.3V)

I(5V/3.3V)

90%

10%

V

O(xVPP)

V

O(xVCC)

90%

10%

GND

Propagation Delay (xVPP)

Propagation Delay (xVCC)

t

f

t

f

t

r

t

r

V

I(12V/5V/3.3V)

I(5V/3.3V)

V

O(xVPP)

90%

10%

90%

10%

O(xVCC)

GND

Rise/Fall Time (xVCC)

Rise/Fall Time (xVPP)

V

DD

LATCH

50%

LATCH

GND

t

off

t

off

t

on

t

on

V

I(5V/3.3V)

I(12V/5V/3.3V)

V

O(xVPP)

V

O(xVCC)

90%

10%

90%

10%

GND

Turnon/off Time (xVPP)

Turnon/off Time (xVCC)

VOLTAGE WAVEFORMS

Figure 1. Test Circuits and Voltage Waveforms

DATA

D8

D7

D6

D5

D4

D3

D2

D1

D0

LATCH

CLOCK

:

NOTE Data is clocked in on the positive edge of the clock. The latch should occur before the next positive leading edge of the clock. For definition

of D0to D8, see the control logic table.

Figure 2. Serial-Interface Timing for TPS2206A

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SLVS449A − DECEMBER 2002 − REVISED MAY 2003

TABLE OF GRAPHS

FIGURE

Short-circuit response, short applied to powered-on 5-V xVCC-switch output

Short-circuit response, short applied to powered-on 12-V xVPP-switch output

OC response with ramped overcurrent-limit load on 5-V xVCC-switch output

OC response with ramped overcurrent-limit load on 12-V xVPP-switch output

vs Time

3

4

vs Time

5

vs Time

6

Turnon propagation delay time, xVCC (C = 150 µF)

vs Junction temperature

vs Load capacitance

vs Junction temperature

vs Load capacitance

7

L

Turnoff propagation delay time, xVCC (C = 150 µF)

8

L

Turnon propagation delay time, xVPP (C = 10 µF)

9

L

Turnoff propagation delay time, xVPP (C = 10 µF)

10

11

12

13

14

15

16

17

18

19

20

21

22

L

Turnon propagation delay time, xVCC (T = 25°C)

J

Turnoff propagation delay time, xVCC (T = 25°C)

J

Turnon propagation delay time, xVPP (T = 25°C)

J

Turnoff propagation delay time, xVPP (T = 25°C)

J

Rise time, xVCC (C = 150 µF)

L

Fall time, xVCC (C = 150 µF)

L

Rise time, xVPP (C = 10 µF)

L

Fall time, xVPP (C = 10 µF)

L

Rise time, xVCC (T = 25°C)

J

Fall time, xVCC (T = 25°C)

J

Rise time, xVPP (T = 25°C)

J

Fall time, xVPP (T = 25°C)

J

SHORT-CIRCUIT RESPONSE,

SHORT APPLIED TO POWERED-ON 5-V

SHORT APPLIED TO POWERED-ON 12-V

xVCC-SWITCH OUTPUT

xVPP-SWITCH OUTPUT

vs

TIME

V

O(/OC)

5 V/div

V

O(/OC)

2 V/div

V

IN(5V)

2 V/div

I

O(xVPP)

2 A/div

I

O(VCC)

5 A/div

0

1

2

3

4

5

100

200

300

400

500

t − Time − ms

t − Time − µs

Figure 3

Figure 4

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SLVS449A − DECEMBER 2002 − REVISED MAY 2003

OC RESPONSE WITH RAMPED

OVERCURRENT-LIMIT LOAD ON 5-V

OC RESPONSE WITH RAMPED

OVERCURRENT-LIMIT LOAD ON 12-V

xVCC-SWITCH OUTPUT

xVPP-SWITCH OUTPUT

vs

TIME

vs

TIME

V

O(/OC)

5 V/div

V

O(/OC)

5 V/div

I

O(xVCC)

1 A/div

I

O(xVPP)

100 mA/div

0

10

20

30

40

50

0

2

4

6

8

10

t − Time − ms

Figure 5

Figure 6

TURNOFF PROPAGATION DELAY TIME, xVCC

TURNON PROPAGATION DELAY TIME, xVCC

vs

JUNCTION TEMPERATURE

2.6

0.8

0.7

0.6

0.5

xVCC = 5 V

I

C

= 0.75 A

I

C

= 0.75 A

= 150 µF

2.55

2.5

O

= 150 µF

L

2.45

2.4

0.4

0.3

2.35

0.2

0.1

0

2.3

2.25

−50

−20

10

40

70

100

−50

−20

10

40

70

100

T − Junction Temperature − °C

J

T

J

− Junction Temperature − °C

Figure 7

Figure 8

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SLVS449A − DECEMBER 2002 − REVISED MAY 2003

TURNOFF PROPAGATION DELAY TIME, xVPP

TURNON PROPAGATION DELAY TIME, xVPP

vs

JUNCTION TEMPERATURE

0.9

0.8

3

xVPP = 12 V

I

C

= 0.05 A

= 10 µF

O

2.5

L

0.7

0.6

0.5

0.4

2

1.5

0.3

0.2

0.1

1

xVCC = 12 V

I

C

= 0.05 A

= 10 µF

O

0.5

L

0

−50

−20

10

40

70

100

−50

−20

10

40

70

100

T − Junction Temperature − °C

J

T

J

− Junction Temperature − °C

Figure 9

Figure 10

TURNOFF PROPAGATION DELAY TIME, xVCC

TURNON PROPAGATION DELAY TIME, xVCC

vs

LOAD CAPACITANCE

2.55

0.7

xVCC = 5 V

I = 0.75 A

O

T = 25°C

J

xVCC = 5 V

I

T

= 0.75 A

= 25°C

O

0.6

0.5

2.5

2.45

2.4

J

0.4

0.3

0.2

0.1

0

2.35

2.3

2.25

0.1

1

10

100

1000

0.1

1

C

10

100

1000

C

L

− Load Capacitance − µF

L

Figure 11

Figure 12

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SLVS449A − DECEMBER 2002 − REVISED MAY 2003

TURNOFF PROPAGATION DELAY TIME, xVPP

TURNON PROPAGATION DELAY TIME, xVPP

vs

LOAD CAPACITANCE

0.9

2.25

xVPP = 12 V

I

T

= 0.05 A

= 25°C

0.8

0.7

O

I

T

= 0.05 A

= 25°C

O

J

2.2

2.15

2.1

J

0.6

0.5

0.4

0.3

0.2

2.05

2

0.1

0

1.95

0.1

1

10

0.1

1

10

C

L

− Load Capacitance − µF

C

L

− Load Capacitance − µF

Figure 13

Figure 14

FALL TIME, xVCC

vs

RISE TIME, xVCC

vs

JUNCTION TEMPERATURE

1.22

1.2

2.41

2.4

xVCC = 5 V

I

C

= 0.75 A

= 150 µF

O

I

C

= 0.75 A

= 150 µF

O

L

1.18

2.39

1.16

1.14

1.12

1.1

2.38

2.37

2.36

1.08

1.06

1.04

2.35

2.34

−50

−20

T

10

40

70

100

−50

−20

T

10

40

70

100

− Junction Temperature − °C

J

Figure 15

Figure 16

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SLVS449A − DECEMBER 2002 − REVISED MAY 2003

FALL TIME, xVPP

vs

JUNCTION TEMPERATURE

RISE TIME, xVPP

vs

JUNCTION TEMPERATURE

4.15

0.605

xVPP = 12 V

= 0.05 A

xVPP = 12 V

I

O

4.1

4.05

4

I

C

= 0.05 A

= 10 µF

O

C

L

= 10 µF

0.6

0.595

0.59

L

3.95

0.585

3.9

0.58

3.85

−50

0.575

−20

10

40

70

100

−50

−20

10

40

70

100

T

− Junction Temperature − °C

J

T

− Junction Temperature − °C

J

Figure 17

Figure 18

FALL TIME, xVCC

vs

RISE TIME, xVCC

vs

LOAD CAPACITANCE

1.2

2.5

2

xVCC = 5 V

I

T

= 0.75 A

= 25°C

O

J

1

0.8

1.5

1

0.6

0.4

0.2

0

xVCC = 5 V

0.5

0

I

T

= 0.75 A

= 25°C

O

J

0.1

1

10

100

1000

0.1

1

10

100

1000

C

L

− Load Capacitance − µF

C

L

− Load Capacitance − µF

Figure 19

Figure 20

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SLVS449A − DECEMBER 2002 − REVISED MAY 2003

FALL TIME, xVPP

vs

LOAD CAPACITANCE

RISE TIME, xVPP

vs

LOAD CAPACITANCE

4.5

4

0.7

xVPP = 12 V

= 0.05 A

xVPP = 12 V

I

O

I

T

= 0.05 A

= 25°C

O

T

J

= 25°C

0.6

0.5

J

3.5

3

2.5

2

0.4

0.3

1.5

1

0.2

0.1

0

0.5

0

0.1

1

10

0.1

1

10

C − Load Capacitance − µF

L

C

L

− Load Capacitance − µF

Figure 21

Figure 22

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SLVS449A − DECEMBER 2002 − REVISED MAY 2003

TYPICAL CHARACTERISTICS

TABLE OF GRAPHS

FIGURE

Input current, xVCC = 3.3 V

23

Input current, xVCC = 5 V

Input current, xVPP = 12 V

24

25

26

27

28

29

30

31

32

33

34

I

vs Junction temperature

vs Load current

I

Static drain-source on-state resistance, 3.3 V to xVCC switch

Static drain-source on-state resistance, 5 V to xVCC switch

Static drain-source on-state resistance, 12 V to xVPP switch

xVCC switch voltage drop, 3.3-V input

r

DS(on)

xVCC switch voltage drop, 5-V input

V

O

xVPP switch voltage drop, 12-V input

Short-circuit current limit, 3.3 V to xVCC

Short-circuit current limit, 5 V to xVCC

I

vs Junction temperature

OS

Short-circuit current limit, 12 V to xVPP

INPUT CURRENT, xVCC = 3.3 V

vs

INPUT CURRENT, xVCC = 5 V

vs

JUNCTION TEMPERATURE

14

12

10

180

160

140

120

100

8

6

80

60

4

2

40

20

0

−50

−20

10

40

70

100

−20

10

40

70

100

T

J

− Junction Temperature − °C

T

J

− Junction Temperature − °C

Figure 23

Figure 24

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SLVS449A − DECEMBER 2002 − REVISED MAY 2003

STATIC DRAIN-SOURCE ON-STATE RESISTANCE,

3.3 V TO xVCC SWITCH

vs

JUNCTION TEMPERATURE

INPUT CURRENT, xVPP = 12 V

vs

JUNCTION TEMPERATURE

0.12

0.1

120

100

80

0.08

0.06

0.04

0.02

0

60

40

20

0

−50

−20

10

40

70

100

−50

−20

10

40

70

100

T

J

− Junction Temperature − °C

T

J

− Junction Temperature − °C

Figure 25

Figure 26

STATIC DRAIN-SOURCE ON-STATE RESISTANCE,

5 V TO xVCC SWITCH

vs

12 V TO xVPP SWITCH

vs

JUNCTION TEMPERATURE

3

2.5

2

0.14

0.12

0.1

0.08

0.06

1.5

1

0.04

0.02

0

0.5

0

−50

−20

10

40

70

100

−50

−20

10

40

70

100

T

J

− Junction Temperature − °C

T

J

− Junction Temperature − °C

Figure 27

Figure 28

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SLVS449A − DECEMBER 2002 − REVISED MAY 2003

xVCC SWITCH VOLTAGE DROP, 5-V INPUT

xVCC SWITCH VOLTAGE DROP, 3.3-V INPUT

vs

LOAD CURRENT

0.14

0.12

0.1

0.12

0.1

T

J

= 100°C

T

J

= 100°C

0.08

T

J

= 0°C

T

J

= 0°C

0.08

0.06

0.04

0.02

0

T

J

= 25°C

T

J

= 25°C

0.06

T

J

= −40°C

T

J

= −40°C

0.04

0.02

T

J

= 85°C

T

J

= 85°C

0

0.2

0.4

0.6

0.8

1

0

0.2

0.4

0.6

0.8

1

I

L

− Load Current − A

I − Load Current − A

L

Figure 29

Figure 30

xVPP SWITCH VOLTAGE DROP, 12-V INPUT

SHORT-CIRCUIT CURRENT LIMIT, 3.3 V TO xVCC

vs

LOAD CURRENT

JUNCTION TEMPERATURE

0.14

0.12

0.1

1.395

1.39

1.385

1.38

T

J

= 100°C

0.08

0.06

0.04

0.02

0

T

= 0°C

J

1.375

1.37

T

= 25°C

J

T

J

= −40°C

1.365

1.36

T

= 85°C

J

1.355

0

0.01

0.02

0.03

0.04

0.05

−50

−20

10

40

70

100

I

L

− Load Current − A

T

J

− Junction Temperature − °C

Figure 31

Figure 32

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SLVS449A − DECEMBER 2002 − REVISED MAY 2003

SHORT-CIRCUIT CURRENT LIMIT, 5 V TO xVCC

SHORT-CIRCUIT CURRENT LIMIT, 12 V TO xVPP

vs

JUNCTION TEMPERATURE

1.435

1.43

0.208

0.206

1.425

1.42

0.204

0.202

0.2

1.415

1.41

xVPP = 12 V

0.198

0.196

0.194

1.405

1.4

1.395

1.39

0.192

0.19

1.385

−50

−20

10

40

70

100

−50

−20

10

40

70

100

T

J

− Junction Temperature − °C

T

J

− Junction Temperature − °C

Figure 33

Figure 34

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SLVS449A − DECEMBER 2002 − REVISED MAY 2003

APPLICATION INFORMATION

OVERVIEW

PC Cards were initially introduced as a means to add flash memory to portable computers. The idea of add-in cards quickly

took hold, and modems, wireless LANs, global positioning satellite system (GPS), multimedia, and hard-disk versions were

soon available. As the number of PC Card applications grew, the engineering community quickly recognized the need for

a standard to ensure compatibility across platforms. To this end, the PCMCIA (Personal Computer Memory Card

International Association) was established, comprising members from leading computer, software, PC Card, and

semiconductor manufacturers. One key goal was to realize the plug-and-play concept, so that cards and hosts from

different vendors would be transparently compatible.

PC CARD POWER SPECIFICATION

System compatibility also means power compatibility. The most current set of specifications (PC Card Standard) set forth

by the PCMCIA committee states that power is to be transferred between the host and the card through eight of the 68

terminals of the PC Card connector. This power interface consists of two V_CC, two V_pp, and four ground terminals. Multiple

V

_CCand ground terminals minimize connector-terminal and line resistance. The two V_ppterminals were originally specified

as separate signals, but are normally tied together in the host to form a single node to minimize voltage losses. Card primary

power is supplied through the V_CCterminals; flash-memory programming and erase voltage are supplied through the V_pp

terminals.

DESIGNING FOR VOLTAGE REGULATION

The current PCMCIA specification for output voltage regulation, V_O(reg), of the 5-V output is 5% (250 mV). In a typical PC

power-system design, the power supply has an output-voltage regulation, V_PS(reg), of 2% (100 mV). Also, a voltage drop

from the power supply to the PC Card results from resistive losses, V_PCB, in the PCB traces and the PCMCIA connector.

A typical design would limit the total of these resistive losses to less than 1% (50 mV) of the output voltage. Therefore, the

allowable voltage drop, V_DS, for the device would be the PCMCIA voltage regulation less the power supply regulation and

less the PCB and connector resistive drops:

V

+ V

–V

DS

O(reg) PS(reg) PCB

Typically, this would leave 100 mV for the allowable voltage drop across the TPS2204A, TPS2206A, or TPS2210A. The

voltage drop is the output current multiplied by the switch resistance of the device. Therefore, the maximum output current,

I_Omax, that can be delivered to the PC Card in regulation is the allowable voltage drop across the device, divided by the

output-switch resistance.

V

DS

I max +

r

O

DS(on)

The xVCC outputs have been designed to deliver the peak and average currents defined by the PC Card specification

within regulation over the operating temperature range. The xVPP outputs have been designed to deliver 100 mA

continuously.

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SLVS449A − DECEMBER 2002 − REVISED MAY 2003

OVERCURRENT AND OVERTEMPERATURE PROTECTION

PC Cards are inherently subject to damage that can result from mishandling. Host systems require protection against

short-circuited cards that could lead to power-supply or PCB trace damage. Even extremely robust systems could undergo

rapid battery discharge into a damaged PC Card, resulting in the rather sudden and unacceptable loss of system power.

The reliability of fused systems is poor, in comparison, as blown fuses require troubleshooting and repair, usually by the

manufacturer.

The TPS2204A, TPS2206A, and TPS2210A take a two-pronged approach to overcurrent protection. Overcurrent

protection is designed to activate if an output is shorted or when an overcurrent condition is present when switches are

powered up. First, instead of fuses, sense FETs monitor each of the xVCC and xVPP power outputs. Unlike sense resistors

or polyfuses, these FETs do not add to the series resistance of the switch; therefore voltage and power losses are reduced.

Overcurrent sensing is applied to each output separately. Excessive current generates an error signal that limits the output

current of only the affected output, preventing damage to the host. Each xVCC output overcurrent limits from 1 A to 2.2

A, typically around 1.6 A; the xVPP outputs limit from 100 mA to 250 mA, typically around 200 mA.

Second, when an overcurrent condition is detected, the device asserts an active low OC signal that can be monitored by

the microprocessor or controller to initiate diagnostics and/or send the user a warning message. If an overcurrent condition

persists, causing the IC to exceed its maximum junction temperature, thermal-protection circuitry activates, shutting down

all power outputs until the device cools to within a safe operating region, which is ensured by a thermal shutdown hysteresis.

Thermal limiting prevents destruction of the IC from overheating beyond the package power-dissipation ratings.

During power up, the devices control the rise times of the xVCC and xVPP outputs and limit the inrush current into a large

load capacitance, faulty card, or connector.

12-V SUPPLY NOT REQUIRED

Some PC Card switches use the externally supplied 12 V to power gate drive and other chip functions, which requires that

power be present at all times. The TPS2204A, TPS2206A, and TPS2210A offer considerable power savings by using an

internal charge pump to generate the required higher gate drive voltages from the 3.3-V input. Therefore, the external 12-V

supply can be disabled except when needed by the PC Card in the slot, thereby extending battery lifetime. A special feature

in the 12-V circuitry actually helps to reduce the supply current demanded from the 3.3-V input. When 12 V is supplied and

requested at the V_ppoutput, a voltage selection circuit draws the charge-pump drive current for the 12-V FETs from the

12-V input. This selection is automatic and effectively reduces demand fluctuations on the normal 3.3-V V_CCrail. For proper

operation of this feature, a minimum 3.3-V input capacitance of 4.7 µF is recommended, and a minimum 12-V input ramp-up

rate of 12 V/50 ms (240 V/s) is required. Additional power savings are realized during a software shutdown in which

quiescent current drops to a maximum of 1 µA.

BACKWARD COMPATIBILITY

The TPS2206A is backward compatible with the TPS2206 product, with the following considerations. An active low /SHDN

is added to provide fast shutdown capability. Also, the TPS2206A does not have the active−high RESET input, which is left

as no connect.

3.3–V input is required for device operation of TPS2206A.

VOLTAGE-TRANSITIONING REQUIREMENT

PC Cards, like portables, are migrating from 5 V to 3.3 V to minimize power consumption, optimize board space, and

increase logic speeds. The TPS2204A, TPS2206A, and TPS2210A meet all combinations of power delivery as currently

defined in the PCMCIA standard. The latest protocol accommodates mixed 3.3-V/5-V systems by first powering the card

with 5 V, then polling it to determine its 3.3-V compatibility. The PCMCIA specification requires that the capacitors on

3.3-V-compatible cards be discharged to below 0.8 V before applying 3.3-V power. This action ensures that sensitive 3.3-V

circuitry is not subjected to any residual 5-V charge and functions as a power RESET. PC Card specification requires that

V_CCbe discharged within 100 ms. PC Card resistance cannot be relied on to provide a discharge path for voltages stored

on PC Card capacitance because of possible high-impedance isolation by power-management schemes. The devices

include discharge transistors on all xVCC and xVPP outputs to meet the specification requirement.

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SLVS449A − DECEMBER 2002 − REVISED MAY 2003

SHUTDOWN MODE

In the shutdown mode, which can be controlled by SHDN or bit D8 of the input serial DATA word, each of the xVCC and

xVPP outputs is forced to a high-impedance state. In this mode, the chip quiescent current is reduced to 1 µA or less to

conserve battery power.

POWER-SUPPLY CONSIDERATIONS

These switches have multiple pins for each 3.3-V (except for the TPS2210A) and 5-V power input and for the switched

xVCC outputs. Any individual pin can conduct the rated input or output current. Unless all pins are connected in parallel,

the series resistance is higher than that specified, resulting in increased voltage drops and power loss. It is recommended

that all input and output power pins be paralleled for optimum operation.

To increase the noise immunity of the TPS2204A, TPS2206A, and TPS2210A, the power-supply inputs should be

bypassed with at least a 4.7-µF electrolytic or tantalum capacitor paralleled by a 0.047-µF to 0.1-µF ceramic capacitor. It

is strongly recommended that the switched outputs be bypassed with a 0.1-µF (or larger) ceramic capacitor; doing so

improves the immunity of the IC to electrostatic discharge (ESD). Care should be taken to minimize the inductance of PCB

traces between the devices and the load. High switching currents can produce large negative voltage transients, which

forward biases substrate diodes, resulting in unpredictable performance. Similarly, no pin should be taken below −0.3 V.

RESET INPUT

To ensure that cards are in a known state after power brownouts or system initialization, the PC Cards should be reset at

the same time as the host by applying low-impedance paths from xVCC and xVPP terminals to ground. A low-impedance

output state allows discharging of residual voltage remaining on PC Card filter capacitance, permitting the system (host

and PC Cards) to be powered up concurrently. The active low RESET input closes internal ground switches S1, S4, S7,

and S11 with all other switches left open. The devices remain in the low-impedance output state until the signal is

deasserted and new data is clocked in and latched. The input serial data cannot be latched during reset mode. RESET

is provided for direct compatibility with systems that use an active-low reset voltage supervisor. The RESET pin has an

internal 150-kΩ pullup resistor.

CALCULATING JUNCTION TEMPERATURE

The switch resistance, r_DS(on), is dependent on the junction temperature, T_J, of the die. The junction temperature is

dependent on both r_DS(on)and the current through the switch. To calculate T_J, first find r_DS(on)from Figures 26 through 28,

using an initial temperature estimate about 30°C above ambient. Then calculate the power dissipation for each switch,

using the formula:

2

P

+ r

I

D

DS(on)

Next, sum the power dissipation of all switches and calculate the junction temperature:

_TJ₊ǒȍ_PD

Ǔ_{) T , R}

R

+ 108°CńW

qJA

A

qJA

Compare the calculated junction temperature with the initial temperature estimate. If the temperatures are not within a few

degrees of each other, recalculate using the calculated temperature as the initial estimate.

21

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SLVS449A − DECEMBER 2002 − REVISED MAY 2003

LOGIC INPUTS AND OUTPUTS

The serial interface consists of the DATA, CLOCK, and LATCH leads. The data is clocked in on the positive edge of the

clock (see Figure 2). The 9-bit (D0−D8) serial data word is loaded during the positive edge of the latch signal. The latch

signal should occur before the next positive edge of the clock.

The shutdown bit of the data word places all V_CCand V_ppoutputs in a high-impedance state and reduces chip quiescent

current to 1 µA to conserve battery power.

The serial interface is designed to be compatible with serial-interface PCMCIA controllers and current PCMCIA and Japan

Electronic Industry Development Association (JEIDA) standards.

An overcurrent output (OC) is provided to indicate an overcurrent or overtemperature condition in any of the V_CCand V_PP

outputs as previously discussed.

see Note A

S2

3.3 V

CS

AVCC

S5

S3

S6

AVCC

S1

5 V

See Note A

S4

CS

BVCC

S8

S9

See Note A

12 V

See Note B

CS

AVPP

BVPP

S7

S10

S12

S13

S14

See Note A

12 V

See Note B

Discharge

Element

S11

Control Logic

Current Limit

Thermal Limit

SHDN

RESET

DATA

CLOCK

LATCH

GND

UVLO

POR

OC

NOTES: A. Current sense

B. The two 12-V pins must be externally connected.

Figure 35. Internal Switching Matrix, TPS2204A and TPS2206A

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SLVS449A − DECEMBER 2002 − REVISED MAY 2003

See Note C

CS

S2

S3

3.3 V

5 V

AVCC

S1

S4

S5

See Note C

CS

AVPP

S7

5 V

12 V

See Note D

S6

12 V

See Note D

Control Logic

SHDN

Current Limit

Thermal Limit

RESET

DATA

CLOCK

LATCH

GND

UVLO

POR

OC

NOTES:C. Current sense

D. The two 12-V pins must be externally connected.

Figure 36. Internal Switching Matrix, TPS2210A

CONTROL LOGIC

AVPP

BVPP

CONTROL SIGNALS

OUTPUT

VAVPP

0 V

CONTROL SIGNALS

OUTPUT

VBVPP

0 V

D8 (SHDN)

D0

0

D1

0

D8 SHDN)

D4

0

D5

0

1

0

1

0

(1)

AVCC

(2)

BVCC

0

1

0

1

0

12 V

Hi–Z

1

0

12 V

Hi–Z

1

X

(1)

(2)

Output depends on BVCC

Output depends on AVCC

AVCC

BVCC

CONTROL SIGNALS

OUTPUT

VAVCC

0 V

CONTROL SIGNALS

OUTPUT

VBVCC

0 V

D8 SHDN)

D3

0

D2

0

D8 SHDN)

D6

0

D7

0

1

0

1

0

1

3.3 V

5 V

0

1

3.3 V

5 V

1

0

1

0

1

0 V

1

0 V

X

Hi–Z

X

Hi–Z

23

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SLVS449A − DECEMBER 2002 − REVISED MAY 2003

USING THE DEVICES WITH 11-BIT SERIAL DATA INTERFACE CONTROLLERS

Even though the control logic table only shows a 9-bit interface, it can be used with most 11-bit serial data interface

controllers. With the use of the latch input, the TPS2204A, TPS2206A, and TPS2210A only latch the last 9 bits from the

serial stream. This means that for an 11-bit serial stream, bits 9 and 10 are ignored. 11-bit serial interface controllers use

bits 9 and 10 for independent voltage selection of 3.3 V and 5 V between xV_CCand xV_PP

.

ESD PROTECTIONS (see FIGURE 37)

All TPS2206A inputs and outputs of these devices incorporate ESD-protection circuitry designed to withstand a 2-kV

human-body-model discharge as defined in MIL-STD-883C, Method 3015. The xVCC and xVPP outputs can be exposed

to potentially higher discharges from the external environment through the PC Card connector. Bypassing the outputs with

0.1-µF capacitors protects the devices from discharges up to 10 kV.

TPS2206A

AVCC

V

CC

0.1 µF

see Note A

CC

PC Card

Connector A

pp1

V

AVPP

0.1 µF

see Note A

pp2

12 V

BVCC

V

12 V

5 V

CC

4.7 µF

0.1 µF

BVCC

see Note A

CC

PC Card

Connector B

pp1

5 V

V

BVPP

5 V

0.1 µF

see Note A

pp2

3.3 V

From PCI or

System Shutdown

4.7 µF

0.1 µF

SHDN

Controller

DATA

CLOCK

LATCH

CLOCK

LATCH

From PCI or

System RST

RESET

OC

GPI/O

NOTE A: Maximumrecommended output capacitance for xVCC is 220 µF including card capacitance, and for xVPP is 10 µF, without OC

glitch when switches are powered on.

Figure 37. Detailed Interconnections and Capacitor Recommendations

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SLVS449A − DECEMBER 2002 − REVISED MAY 2003

12-V FLASH MEMORY SUPPLY

The TPS6734 is a fixed 12-V output boost converter capable of delivering 120 mA from inputs as low as 2.7 V. The device

is pin-for-pin compatible with the MAX734 regulator and offers the following advantages: lower supply current, wider

operating input-voltage range, and higher output currents. As shown in Figure 36, the only external components required

are: an inductor, a Schottky rectifier, an output filter capacitor, an input filter capacitor, and a small capacitor for loop

compensation. The entire converter occupies less than 0.7 in²of PCB space when implemented with surface-mount

components. An enable input is provided to shut the converter down and reduce the supply current to 3 µA when 12 V is

not needed.

The TPS6734 is a 170-kHz current-mode PWM (pulse-width modulation) controller with an n-channel MOSFET power

switch. Gate drive for the switch is derived from the 12-V output after start-up to minimize the die area needed to realize

the 0.7-Ω MOSFET and improve efficiency at input voltages below 5 V. Soft start is accomplished with the addition of one

small capacitor. A 1.22-V reference, pin 2 of TPS6734, is brought out for external use. For additional information, see the

TPS6734 data sheet (SLVS127).

TPS2206A

AVCC

3.3 V or 5 V

R1

10 kΩ

AVCC

AVPP

TPS6734

Enable

(see Note A)

1

8

L1

18 µH

EN

VCC

2

3

7

6

REF

SS

FB

C1

33 µF

20 V

+

D1

OUT

33 µF, 20 V

4

5

12 V

COMP

GND

12 V

C2

0.01 µF

+

C1

0.1 µF

BVCC

BVPP

C4

0.001 µF

5 V

1 µF

0.1 µF

5 V

3.3 V

4.7 µF

DATA

CLOCK

LATCH

RESET

OC

SHDN

NOTE A: The enable terminal can be tied to a general-purpose I/O terminal on the PCMCIA controller or tied high.

Figure 38. TPS2206A With TPS6734 12-V, 120-mA Supply

25

PACKAGE MATERIALS INFORMATION

www.ti.com

14-Jul-2012

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

A0

B0

K0

P1

W

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

TPS2206ADBR

SSOP

DB

30

24

2000

330.0

16.4

8.2

10.5

8.3

2.5

1.6

12.0

8.0

16.0

Q1

TPS2210APWPR

HTSSOP PWP

6.95

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

14-Jul-2012

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

TPS2206ADBR

SSOP

DB

30

24

2000

367.0

38.0

TPS2210APWPR

HTSSOP

PWP

Pack Materials-Page 2

MECHANICAL DATA

MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001

DB (R-PDSO-G**)

PLASTIC SMALL-OUTLINE

28 PINS SHOWN

0,38

0,22

0,65

28

M

0,15

15

0,25

0,09

5,60

5,00

8,20

7,40

Gage Plane

1

14

0,25

A

0°–ā8°

0,95

0,55

Seating Plane

0,10

2,00 MAX

0,05 MIN

PINS **

14

16

20

24

28

30

38

DIM

6,50

5,90

6,50

5,90

7,50

8,50

7,90

10,50

9,90

10,50 12,90

A MAX

A MIN

6,90

9,90

12,30

4040065 /E 12/01

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.

D. Falls within JEDEC MO-150

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型号：	TPS2210APWPRG4
厂家：	TEXAS INSTRUMENTS
描述：	PC CARDâ¢ POWER-INTERFACE SWITCH WITH RESER FOR SERIAL PCMCIA CONTROLLER ？ PC卡 - 答?? ¢电接口开关RESER用于串行PCMCIA控制器电源电路开关电源管理电路光电二极管控制器 PC
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