TPS2216ADBRG4 [TI]
1A Dual-Slot PC Card Power Switch w/ Serial Interface 30-SSOP -40 to 70;
| 型号： | TPS2216ADBRG4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 1A Dual-Slot PC Card Power Switch w/ Serial Interface 30-SSOP -40 to 70 PC 光电二极管 |
| 文件： | 总30页 (文件大小：571K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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ꢉꢊꢆ ꢋꢌꢂ ꢋꢍ ꢀ ꢁꢎ ꢎꢆꢏ ꢉ ꢁꢍ ꢐ ꢑꢏ ꢂ ꢐꢒ ꢀꢎ ꢓꢑ ꢂ
ꢔ ꢍꢏ ꢂꢑ ꢏꢒꢆ ꢋ ꢁꢎ ꢕꢎꢒ ꢆ ꢎꢍ ꢖꢀꢏ ꢍ ꢋꢋ ꢑꢏ ꢂ
SLVS267B − DECEMBER 1999 − REVISED AUGUST 2000
TPS2214A
DB PACKAGE
(TOP VIEW)
D
D
D
D
D
D
D
D
D
D
D
D
D
Fully Integrated xVCC and xVPP Switching
xVPP Programmed Independent of xVCC
3.3-V, 5-V, and/or 12-V Power Distribution
5V
NC
MODE
NC
12V
BVPP
BVCC
BVCC
STBY
OC
3.3V
3.3V
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
16
15
14
13
5V
5V
DATA
Low r
(60-mΩ 3.3-V xVCC Switch and
DS(on)
140-mΩ 5-V xVCC Switch Typical)
Short Circuit and Thermal Protection
150-µA (Maximum) Quiescent Current
Standby Mode: 50-mA Current Limit (Typ)
12-V Supply Can Be Disabled
CLOCK
LATCH
RESET
12V
AVPP
AVCC
AVCC
GND
9
10
11
12
3.3-V Low-Voltage Mode
RESET
Ambient Temperature . . . −40°C to 70°C
Meets PC Card Standards
NC − No internal connection
TTL-Logic Compatible Inputs
PINOUTS FOR TPS2216A DAP AND DB
PACKAGES ARE PROVIDED ON PAGE 2.
Available in 24-Pin and 30-Pin SSOP (DB),
and 32-Pin TSSOP (DAP) Packages
D
Break-Before-Make Switching
Internal Power-On Reset
D
description
The TPS2214A and TPS2216A PC Card power-interface switches provide an integrated power-management
solution for two PC Cards. All of the discrete power MOSFETs, a logic section, current limiting, and thermal
protection for PC Card control are combined on single integrated circuits. These low-cost devices allow the
distribution of 3.3-V, 5-V, and/or 12-V power to the card. The current-limiting feature eliminates the need for
fuses. Current-limit reporting can help the user isolate a system fault.
The TPS2214A and TPS2216A feature a 3.3-V low-voltage mode that allows for 3.3-V switching without the
need for 5-V power. This feature facilitates low-power system designs such as sleep modes where only 3.3 V
is available. These devices also have the ability to program the xVPP outputs independent of the xVCC outputs.
A standby mode that changes all output-current limits to 50 mA (typical) has been incorporated.
End-equipment applications for these products include: notebook computers, desktop computers, personal
digital assistants (PDAs), digital cameras, and bar-code scanners.
The TPS2216A is backward-compatible with the TPS2202A, TPS2206, and TPS2216. The TPS2214A is
backward-compatible with the TPS2214.
AVAILABLE OPTIONS
†
PACKAGED DEVICES
PowerPAD PLASTIC SMALL
OUTLINE
T
A
PLASTIC SMALL OUTLINE
(DB)
(DAP)
−40°C to 70°C
TPS2214ADB(R), TPS2216ADB(R)
TPS2216ADAP(R)
†
The DB and DAP packages are available in tubes and left-end taped and reeled. Add R suffix
to device type (e.g., TPS2216ADBR) for taped and reeled.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments.
PC Card is a trademark of PCMCIA (Personal Computer Memory Card International Association).
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Copyright 2000, Texas Instruments Incorporated
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁ ꢂ ꢃ ꢃꢄ ꢅ ꢆ ꢇ ꢀ ꢁꢂ ꢃ ꢃ ꢄ ꢈ ꢆ
ꢉ ꢊꢆꢋ ꢌꢂꢋ ꢍꢀ ꢁꢎ ꢎꢆ ꢏꢉ ꢁ ꢍꢐ ꢑꢏ ꢂ ꢐꢒ ꢀ ꢎꢓꢑ ꢂ
ꢔ ꢍꢏ ꢂꢑ ꢏꢒ ꢆ ꢋ ꢁꢎ ꢕꢎ ꢒ ꢆ ꢎꢍ ꢖꢀ ꢏꢍ ꢋꢋ ꢑꢏ ꢂ
SLVS267B − DECEMBER 1999 − REVISED AUGUST 2000
TPS2216A
DAP PACKAGE
(TOP VIEW)
TPS2216A
DB PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
5V
5V
NC
5V
NC
MODE
NC
NC
NC
5V
5V
DATA
CLOCK
LATCH
RESET
12V
AVPP
AVCC
AVCC
AVCC
GND
5V
MODE
NC
NC
NC
NC
12V
BVPP
BVCC
BVCC
BVCC
STBY
OC
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
1
2
3
4
5
6
7
8
DATA
CLOCK
LATCH
RESET
12V
AVPP
AVCC
AVCC
AVCC
GND
NC
12V
9
BVPP
BVCC
BVCC
BVCC
OC
STBY
3.3V
3.3V
9
10
11
12
13
14
15
10
11
12
13
14
15
16
NC
RESET
3.3V
RESET
NC
3.3V
3.3V
3.3V
NC − No internal connection
Terminal Functions
TERMINAL
NO.
I/O
DESCRIPTION
TPS2214
TPS2216
NAME
DB-24
13, 14
1, 2, 24
7, 20
9, 10
8
DB-30
DAP
16, 17, 18
1, 2, 32
8, 25
3.3V
15, 16, 17
1, 2, 30
7, 24
I
3.3-V input for card power and/or chip power if 5 V is not present
5-V input for card power and/or chip power
5V
I
12V
I
12-V V input card power
pp
AVCC
AVPP
BVCC
BVPP
GND
MODE
9, 10, 11
8
10, 11, 12
9
O
O
O
O
VCC output: 3.3-V, 5-V, GND or high impedance to card
VPP output: 3.3-V, 5-V, 12-V, GND or high impedance to card
VCC output: 3.3-V, 5-V, GND or high impedance to card
VPP output: 3.3-V, 5-V, 12-V, GND or high impedance to card
Ground
17, 18
19
20, 21, 22
23
21, 22, 23
24
11
12
13
22
29
30
I
TPS2206 operation when floating or pulled low; must be pulled high externally for
TPS2216A operation. MODE is internally pulled low with a 150-kΩ pulldown
resistor.
OC
15
6
18
6
20
7
O
I
Logic-level output that goes low when an overcurrent or overtemperature condition
exists.
RESET
RESET
STBY
Logic-level reset input active high. Do not connect if RESET pin is used. RESET
is internally pulled low with a 150-kΩ pulldown resistor.
12
16
14
19
14
19
I
Logic-level reset input active low. Do not connect if RESET pin is used. The pin is
internally pulled high with a 150-kΩ pullup resistor.
I
Logic-level active low input sets the TPS2216 to standby mode and sets all current
limits to 50 mA. The pin is internally pulled high with a 150-kΩ pullup resistor.
CLOCK
DATA
LATCH
NC
4
4
3
5
5
4
6
I
I
I
Logic-level clock for serial data word
Logic-level serial data word
3
5
Logic-level latch for serial data word
No internal connection
21, 23
13, 25, 26,
27, 28
3, 15, 26,
27, 28, 29,
31
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂꢃ ꢃ ꢄ ꢅ ꢆ ꢇ ꢀꢁ ꢂ ꢃꢃ ꢄꢈ ꢆ
ꢉꢊꢆ ꢋꢌꢂ ꢋꢍ ꢀ ꢁꢎ ꢎꢆꢏ ꢉ ꢁꢍ ꢐ ꢑꢏ ꢂ ꢐꢒ ꢀꢎ ꢓꢑ ꢂ
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SLVS267B − DECEMBER 1999 − REVISED AUGUST 2000
functional block diagram (pin numbers refer to 30-pin DB package)
9
TPS2216A
AVCC
AVCC
10
11
15
S1
3.3V
3.3V
16
17
AVCC
S2
CS
CS
3.3V
S7
S8
8
S3
AVPP
CS
CS
S9
S10
20
21
22
BVCC
BVCC
BVCC
CS
1
2
5V
5V
S4
30
5V
S5
S6
CS
S11
S12
23
BVPP
CS
CS
CS
S13
S14
7
†
12V
24
†
12V
CS
Internal
Current Monitor
29
19
Thermal
MODE
STBY
3
4
5
6
DATA
CLOCK
LATCH
RESET
12
GND
14
18
RESET
OC
†
Both 12V pins must be connected together.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁ ꢂ ꢃ ꢃꢄ ꢅ ꢆ ꢇ ꢀ ꢁꢂ ꢃ ꢃ ꢄ ꢈ ꢆ
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SLVS267B − DECEMBER 1999 − REVISED AUGUST 2000
†
absolute maximum ratings over operating virtual free-air temperature (unless otherwise noted)
Input voltage range for card power: V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 6 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 6 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 14 V
I(3.3V)
I(5V)
V
V
I(12V)
Logic input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 6 V
Output voltage range:
V
V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 6 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 14 V
O(xVCC)
O(xVPP)
Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table
Output current: I
I
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internally limited
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internally limited
O(xVCC)
O(xVPP)
Operating virtual junction temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 125°C
J
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −55°C to 150°C
stg
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
DISSIPATION RATING TABLE
‡
T
≤ 25°C
DERATING FACTOR
T
A
= 70°C
T = 85°C
A
A
PACKAGE
POWER RATING
ABOVE T = 25°C
POWER RATING POWER RATING
A
DB
1095 mW
10.99 mW/°C
42.55 mW/°C
602 mW
438 mW
DAP
4255 mW
2340 mW
1702 mW
‡
These devices are mounted on an JEDEC low-k board (2 oz. traces on surface), 1-W power applied.
recommended operating conditions
MIN
2.7
2.7
2.7
MAX
5.25
5.25
13.5
750
200
2.5
UNIT
V
V
V
V
I(3.3V)
V
Input voltage, V
I(5V)
I
V
I(12V)
I
at T = 70°C
mA
mA
MHz
O(VCC)
O(VPP)
A
Output current, I
Clock frequency
O
I
at T = 70°C
A
Data
200
250
100
100
100
100
250
−40
Latch
Clock
Pulse duration
ns
§
Data hold time
ns
ns
ns
ns
°C
§
Data setup time
Latch delay time
Clock delay time
§
§
Operating virtual junction temperature, T
100
J
§
Refer to Figures 2 and 3.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂꢃ ꢃ ꢄ ꢅ ꢆ ꢇ ꢀꢁ ꢂ ꢃꢃ ꢄꢈ ꢆ
ꢉꢊꢆ ꢋꢌꢂ ꢋꢍ ꢀ ꢁꢎ ꢎꢆꢏ ꢉ ꢁꢍ ꢐ ꢑꢏ ꢂ ꢐꢒ ꢀꢎ ꢓꢑ ꢂ
ꢔ ꢍꢏ ꢂꢑ ꢏꢒꢆ ꢋ ꢁꢎ ꢕꢎꢒ ꢆ ꢎꢍ ꢖꢀꢏ ꢍ ꢋꢋ ꢑꢏ ꢂ
SLVS267B − DECEMBER 1999 − REVISED AUGUST 2000
electrical characteristics, T = 25°C, V
= 5 V, V
= 3.3 V, V
= 12 V, STBY floating, all
J
I(5V)
I(3.3V)
I(12V)
outputs unloaded (unless otherwise noted)
power switch
PARAMETER
TEST CONDITIONS
MIN
TYP
60
MAX
105
140
185
200
1.5
2.5
2
UNIT
T = 25°C,
V
V
I
= 0 or 5,
= 0 or 5,
I
O
I
O
= 750 mA
= 750 mA
3.3 V to xVCC, with one or
two switches on
J
I(5V)
I(5V)
T = 85°C,
J
T = 25°C,
J
T = 85°C,
J
T = 25°C,
J
90
mΩ
= 750 mA
140
160
0.7
1.4
1.4
2
5 V to xVCC, with one or
two switches on
O
I
O
I
O
I
O
= 750 mA
= 50 mA
= 50 mA
†
3.3 V/5 V/12 V to xVPP
3.3 V/5 V to xVCC
Switch resistance
T = 85°C,
J
T = 25°C, STBY = low,
I
O
I
O
I
O
I
O
= 30 mA
= 30 mA
= 30 mA
= 30 mA
J
Ω
T = 85°C, STBY = low,
3
J
T = 25°C, STBY = low,
5
7
J
3.3 V/5 V/12 V to xVPP
T = 85°C, STBY = low,
10
16
J
V
V
I
I
at 10 mA, After reset
at 10 mA, After reset
0.275
0.275
1
0.8
0.8
10
O(xVCC)
O(xVPP)
O(xVCC)
O(xVPP)
Clamp low voltage
Leakage current
V
T = 25°C
I
high-impedance
J
O(xVCC)
state
T = 85°C
2
50
J
I
I
µA
lkg
T = 25°C
1
10
I
high-impedance
J
O(xVPP)
state
T = 85°C
2
50
J
I
1
2.5
500
A
T = 85°C,
Output powered into a short to GND
O(xVCC)
J
I
250
mA
O(xVPP)
Short-circuit output
current limit
OS
T = 85°C,
†
Standby mode, I
Standby mode, I
35
30
65
60
J
O(xVCC)
mA
Output powered into a short to GND,
STBY = 0 V
O(xVPP)
xVCC switch
xVPP switch
100
16
Current limit
response time
100-mΩ short circuit
µs
‡
I
I
I
I
I
I
I
I
I
0.01
100
6
2
120
10
I(3.3V)
I(5V)
V
= V
O(xVPP)
= 5 V
µA
µA
O(xVCC)
Normal operation
and in reset
mode
I(12V)
I(3.3V)
I(5V)
100
0
120
V
V
= 0,
V
= 3.3 V,
I(5V)
O(xVPP)
O(xVCC)
§
Input current
I
I
= 12 V
22
30
1
I(12V)
I(3.3V)
I(5V)
1
Shutdown mode
V
= Hi-Z,
V
= Hi-Z
µA
°C
O(xVCC)
O(xVPP)
1
I(12V)
Trip point, T
Hysteresis
155
10
J
‡
Thermal shutdown
†
Pulse-testing techniques maintain junction temperature close to ambient temperature (250-µs-wide pulse, less than 0.5% duty cycle); thermal
effects must be taken into account separately.
Specified by design, not tested in production.
‡
§
Input currents do not include logic input currents (presented in electrical characteristics for logic section); clock is inactive.
NOTE: V
I(3.3V)
or V must be biased for switches to function.
I(5V)
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁ ꢂ ꢃ ꢃꢄ ꢅ ꢆ ꢇ ꢀ ꢁꢂ ꢃ ꢃ ꢄ ꢈ ꢆ
ꢉ ꢊꢆꢋ ꢌꢂꢋ ꢍꢀ ꢁꢎ ꢎꢆ ꢏꢉ ꢁ ꢍꢐ ꢑꢏ ꢂ ꢐꢒ ꢀ ꢎꢓꢑ ꢂ
ꢔ ꢍꢏ ꢂꢑ ꢏꢒ ꢆ ꢋ ꢁꢎ ꢕꢎ ꢒ ꢆ ꢎꢍ ꢖꢀ ꢏꢍ ꢋꢋ ꢑꢏ ꢂ
SLVS267B − DECEMBER 1999 − REVISED AUGUST 2000
electrical characteristics, T = 25°C, V
= 5 V, V
= 3.3 V, V
= 12 V, STBY floating, all
J
I(5V)
I(3.3V)
I(12V)
outputs unloaded (unless otherwise noted) (continued)
logic section (CLOCK, DATA, LATCH, MODE, RESET, RESET, STBY, OC)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
50
1
UNIT
V
V
V
V
V
V
= 5 V or V
= 0 V or V
= 5 V
= 0 V
30
I(RESET)
I(RESET)
I(MODE)
I(MODE)
I(RESET)
†
I
I
or I
I(RESET)
I(RESET)
= 5 V
I(RESET)
30
30
50
1
†
I(MODE)
= 0 V
Logic input current
µA
= 5 V
= 0 V
1
I(STBY)
I(STBY)
†
I
I
I(STBY)
50
1
or I
I(DATA)
or I
I(LATCH)
I(CLOCK)
V
V
= 5 V
2
2
I(5V)
Logic input high level
Logic input low level
V
V
= 0 V
I(5V)
0.8
0.4
V
V
= 5 V,
= 0 V,
I
I
= 1 mA
= 1 mA
V
−0.4
I(5V)
O
I(5V)
Logic output high level, OC
Logic output low level, OC
V
V
V
−0.4
I(5V)
O
I(3.3V)
I
O
= 1 mA
†
RESET and MODE have internal 150-kΩ pulldown resistors; RESET and STBY have internal 150-kΩ pullup resistors.
6
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SLVS267B − DECEMBER 1999 − REVISED AUGUST 2000
switching characteristics
†
†
†
PARAMETER
LOAD CONDITION
TEST CONDITIONS
MIN
TYP
MAX
UNIT
C
C
I
I
= 0.1 µF,
= 0.1 µF,
L(xVCC)
L(xVPP)
O(xVCC)
O(xVPP)
V
V
V
V
V
V
V
V
1
O(xVCC)
O(xVPP)
O(xVCC)
O(xVPP)
O(xVCC)
O(xVPP)
O(xVCC)
O(xVPP)
§
= 0 ,
0.8
1.2
2.5
0.01
0.01
3
§
= 0
‡
Output rise times
t
r
ms
C
C
= 150 µF,
= 10 µF,
= 1 A,
L(xVCC)
L(xVPP)
O(xVCC)
O(xVPP)
I
I
= 50 mA
C
C
= 0.1 µF,
= 0.1 µF,
L(xVCC)
L(xVPP)
O(xVCC)
O(xVPP)
§
= 0 ,
I
I
§
= 0
‡
Output fall times
t
f
ms
C
C
= 150 µF,
= 10 µF,
= 1 A,
L(xVCC)
L(xVPP)
O(xVCC)
O(xVPP)
I
I
8
= 50 mA
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
3
25
0.6
8.5
0.6
9
pd(on)
pd(off)
pd(on)
pd(off)
pd(on)
pd(off)
pd(on)
pd(off)
pd(on)
pd(off)
pd(on)
pd(off)
pd(on)
pd(off)
pd(on)
pd(off)
pd(on)
pd(off)
pd(on)
pd(off)
pd(on)
pd(off)
pd(on)
pd(off)
pd(on)
pd(off)
pd(on)
pd(off)
Latch↑ to xVPP (12 V)
Latch↑ to xVPP (5 V)
Latch↑ to xVPP (3.3 V), V
Latch↑ to xVPP (3.3 V), V
Latch↑ to xVCC (5 V)
= 5 V
= 0 V
I(5V)
C
C
I
= 0.1 µF,
= 0.1 µF,
L(xVCC)
L(xVPP)
O(xVCC)
O(xVPP)
1.4
9
I(5V)
§
= 0 ,
§
= 0
I
0.3
15
0.2
15
0.4
15
4.5
13
3.3
8
Latch↑ to xVCC (3.3 V), V
Latch↑ to xVCC (3.3 V), V
Latch↑ to xVPP (12 V)
Latch↑ to xVPP (5 V)
= 5 V
= 0 V
I(5V)
I(5V)
‡
t
pd
Propagation delay
ms
3
Latch↑ to xVPP (3.3 V), V
Latch↑ to xVPP (3.3 V), V
Latch↑ to xVCC (5 V)
= 5 V
= 0 V
I(5V)
9
C
C
I
= 150 µF,
= 10 µF,
= 1 A,
L(xVCC)
L(xVPP)
3
I(5V)
9
O(xVCC)
O(xVPP)
I
= 50 mA
1
12
0.6
12
1
Latch↑ to xVCC (3.3 V), V
Latch↑ to xVCC (3.3 V), V
= 5 V
= 0 V
I(5V)
I(5V)
12
†
‡
§
Refer to Parameter Measurement Information
Specified by design: not tested in production.
No card inserted, assumes 0.1-µF recommended output capacitor (see Figure 32).
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ꢔ ꢍꢏ ꢂꢑ ꢏꢒ ꢆ ꢋ ꢁꢎ ꢕꢎ ꢒ ꢆ ꢎꢍ ꢖꢀ ꢏꢍ ꢋꢋ ꢑꢏ ꢂ
SLVS267B − DECEMBER 1999 − REVISED AUGUST 2000
PARAMETER MEASUREMENT INFORMATION
xVPP
xVCC
I
I
O(xVPP)
O(xVCC)
LOAD CIRCUITS
V
V
DD
DD
LATCH
LATCH
50%
50%
GND
GND
t
t
pd(off)
pd(off)
t
t
pd(on)
pd(on)
90%
10%
V
O(xVPP)
V
O(xVCC)
90%
10%
GND
GND
Propagation Delay (xVPP)
Propagation Delay (xVCC)
t
f
t
f
t
t
r
r
V
V
O(xVPP)
90%
10%
90%
10%
O(xVCC)
GND
GND
Rise/Fall Time (xVCC)
Rise/Fall Time (xVPP)
V
V
DD
DD
LATCH
50%
50%
GND
GND
t
t
off
off
t
t
on
on
V
O(xVPP)
V
90%
10%
90%
10%
O(xVCC)
GND
GND
Turn On/Off Time (xVPP)
Turn On/Off Time (xVCC)
VOLTAGE WAVEFORMS
Figure 1. Test Circuits and Voltage Waveforms
8
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ꢔ ꢍꢏ ꢂꢑ ꢏꢒꢆ ꢋ ꢁꢎ ꢕꢎꢒ ꢆ ꢎꢍ ꢖꢀꢏ ꢍ ꢋꢋ ꢑꢏ ꢂ
SLVS267B − DECEMBER 1999 − REVISED AUGUST 2000
PARAMETER MEASUREMENT INFORMATION
DATA
D6
D10
D8
D7
D4
D3
D1
D9
D5
D2
D0
Data Setup Time
Data Hold Time
Latch Delay Time
LATCH
CLOCK
Clock Delay Time
NOTE: Data is clocked in on the positive edge of the clock. The positive edge of the latch signal should occur before the next positive edge of
the clock. For definition of D0 to D10, see the control logic table.
Figure 2. Serial-Interface Timing for Independent xVPP Switching When MODE = 5 V or 3.3 V
DATA
D4
D8
D6
D5
D2
D1
D7
D3
D0
Data Setup Time
LATCH
Latch Delay Time
Data Hold Time
Clock Delay Time
CLOCK
NOTE: Data is clocked in on the positive edge of the clock. The positive edge of the latch signal should occur before the next positive edge of
the clock. For definition of D0 to D8, see the control logic table.
Figure 3. Serial-Interface Timing When MODE = 0 V or Floating
†
Table of Timing Diagrams
FIGURE
Short-circuit current response, short applied to powered-on 5-V xVCC switch output
Short-circuit current response, short applied to powered-on 12-V xVPP switch output
OC response with ramped load on 5-V xVCC switch output
4
5
6
7
OC response with ramped load on 12-V xVPP switch output
†
Timing tests are conducted at free-air temperature, V
I(5V)
= 5 V, V
I(3.3V)
= 3.3 V, V = 12 V, C = 0.1 µF on each output, STBY floating.
I(12V) L
9
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ꢔ ꢍꢏ ꢂꢑ ꢏꢒ ꢆ ꢋ ꢁꢎ ꢕꢎ ꢒ ꢆ ꢎꢍ ꢖꢀ ꢏꢍ ꢋꢋ ꢑꢏ ꢂ
SLVS267B − DECEMBER 1999 − REVISED AUGUST 2000
PARAMETER MEASUREMENT INFORMATION
V
O(OC)
V
O(OC)
5 V/div
5 V/div
I
I
O(VPP)
5 A/div
O(VCC)
5 A/div
0
0
200
400
600
800
1000
200
400
600
800
1000
t − Time − µs
t − Time − µs
Figure 4. Short-Circuit Response, Short Applied
to Powered-on 5-V xVCC-Switch Output
Figure 5. Short-Circuit Response, Short Applied
to Powered-on 12-V xVPP-Switch Output
V
V
O(OC)
5 V/div
O(OC)
5 V/div
I
I
O(VPP)
O(VCC)
1 A/div
0.2 A/div
0
0
4
8
12
16
20
10
20
30
40
50
t − Time − ms
t − Time − ms
Figure 6. OC Response With Ramped Load
on 5-V xVCC-Switch Output
Figure 7. OC Response With Ramped Load on
12-V xVPP-Switch Output
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ꢔ ꢍꢏ ꢂꢑ ꢏꢒꢆ ꢋ ꢁꢎ ꢕꢎꢒ ꢆ ꢎꢍ ꢖꢀꢏ ꢍ ꢋꢋ ꢑꢏ ꢂ
SLVS267B − DECEMBER 1999 − REVISED AUGUST 2000
TYPICAL CHARACTERISTICS
Table of Graphs
FIGURE
8
t
t
t
t
t
t
t
t
t
t
t
t
Turnon propagation delay time, 3.3-V xVCC switch
vs Load capacitance
vs Load capacitance
vs Load capacitance
vs Load capacitance
vs Load capacitance
vs Load capacitance
vs Load capacitance
vs Load capacitance
vs Load capacitance
vs Load capacitance
vs Load capacitance
vs Load capacitance
vs Junction temperature
vs Junction temperature
vs Junction temperature
vs Junction temperature
vs Junction temperature
vs Junction temperature
vs Load current
pd(on)
Turnoff propagation delay time, 3.3-V xVCC switch
Turnon propagation delay time, 5-V xVCC switch
Turnoff propagation delay time, 5-V xVCC switch
Turnon propagation delay time, 12-V xVPP switch
Turnoff propagation delay time dc, 12-V xVPP switch
Rise time, 3.3-V xVCC switch
9
pd(off)
10
11
pd(on)
pd(off)
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
pd(on)
pd(off)
r
f
r
f
r
f
Fall time, 3.3-V xVCC switch
Rise time, 5-V xVCC switch
Fall time, 5-V xVCC switch
Rise time, 12-V xVPP switch
Fall time, 12-V xVPP switch
Input current at V
Input current at V
Input current at V
= V
= V
=3.3 V
=5 V
I(xVCC)
I(xVCC)
I(xVCC)
I(xVPP)
I
I
I(xVPP)
= 5 V, V
I(xVPP)
=12 V
Static drain-source on-state resistance, 3.3-V xVCC switch
Static drain-source on-state resistance, 5-V xVCC switch
Static drain-source on-state resistance, 12-V xVPP switch
DC input-to-output voltage (drop), 3.3-V xVCC switch
DC input-to-output voltage (drop), 5-V xVCC switch
DC input-to-output voltage (drop), 12-V xVPP switch
Short-circuit current limit, 3.3-V xVCC switch
r
DS(on)
V
V
IO(xVCC)
vs Load current
vs Load current
IO(xVPP)
vs Junction temperature
vs Junction temperature
vs Junction temperature
I
Short-circuit current limit, 5-V xVCC switch
OS
Short-circuit current limit, 12-V xVPP switch
NOTE: Electrical characteristics tests are conducted at V
(unless otherwise noted on Figures).
= 5 V, V
I(3.3V)
= 3.3 V, V
I(12V)
= 12 V, C = 0.1 µF on each output, STBY floating
I(5V)
L
11
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ꢔ ꢍꢏ ꢂꢑ ꢏꢒ ꢆ ꢋ ꢁꢎ ꢕꢎ ꢒ ꢆ ꢎꢍ ꢖꢀ ꢏꢍ ꢋꢋ ꢑꢏ ꢂ
SLVS267B − DECEMBER 1999 − REVISED AUGUST 2000
TYPICAL CHARACTERISTICS
TURNON PROPAGATION DELAY TIME,
TURNOFF PROPAGATION DELAY TIME,
3.3-V xVCC SWITCH
vs
3.3-V xVCC SWITCH
vs
LOAD CAPACITANCE
LOAD CAPACITANCE
1.4
1.2
1
14
12
T
J
= 85°C
T
J
= 25°C
T
J
= 85°C
0.8
10
8
T
J
= 25°C
T
J
= −40°C
0.6
T
J
= −40°C
0.4
0.2
dc Load = 1 A
100 1000
dc Load = 1 A
100 1000
6
0.1
1
10
0.1
1
10
C
− Load Capacitance − µF
L
C
− Load Capacitance − µF
L
Figure 8
Figure 9
TURNON PROPAGATION DELAY TIME,
5-V xVCC SWITCH
TURNOFF PROPAGATION DELAY TIME,
5-V xVCC SWITCH
vs
vs
LOAD CAPACITANCE
LOAD CAPACITANCE
1.6
1.4
1.2
1
14
12
T
J
= 25°C
T
J
= −40°C
T
J
= 85°C
T
J
= −40°C
T
J
= 85°C
10
T
J
= 25°C
0.8
0.6
8
6
0.4
0.2
dc Load = 1 A
100 1000
dc Load = 1 A
100 1000
0.1
1
10
0.1
1
10
C
− Load Capacitance − µF
C
− Load Capacitance − µF
L
L
Figure 11
Figure 10
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ꢔ ꢍꢏ ꢂꢑ ꢏꢒꢆ ꢋ ꢁꢎ ꢕꢎꢒ ꢆ ꢎꢍ ꢖꢀꢏ ꢍ ꢋꢋ ꢑꢏ ꢂ
SLVS267B − DECEMBER 1999 − REVISED AUGUST 2000
TYPICAL CHARACTERISTICS
TURNON PROPAGATION DELAY TIME,
TURNOFF PROPAGATION DELAY TIME dc
12-V xVPP SWITCH
vs
LOAD CAPACITANCE
12-V xVPP SWITCH
vs
LOAD CAPACITANCE
6
5
4
16
14
12
10
T
= 85°C
J
T
J
= −40°C
3
2
T
J
= 25°C
T
J
= 25°C
T
J
= −40°C
T
J
= 85°C
8
6
1
0
dc Load = 50 mA
100 1000
dc Load = 50 mA
100 1000
0.1
1
10
0.1
1
10
C
− Load Capacitance − µF
L
C
− Load Capacitance − µF
L
Figure 12
Figure 13
FALL TIME, 3.3-V xVCC SWITCH
RISE TIME, 3.3-V xVCC SWITCH
vs
vs
LOAD CAPACITANCE
LOAD CAPACITANCE
2
3.5
3
1.8
1.6
1.4
1.2
T
J
= 85°C
T
J
= 25°C
2.5
2
T
J
= 85°C
1
T
= −40°C
J
T
= 25°C
J
1.5
T
J
= −40°C
0.8
0.6
0.4
1
0.5
0
0.2
0
dc Load = 1 A
100 1000
dc Load = 1 A
100 1000
0.1
1
10
0.1
1
10
C
− Load Capacitance − µF
C
− Load Capacitance − µF
L
L
Figure 14
Figure 15
13
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ꢔ ꢍꢏ ꢂꢑ ꢏꢒ ꢆ ꢋ ꢁꢎ ꢕꢎ ꢒ ꢆ ꢎꢍ ꢖꢀ ꢏꢍ ꢋꢋ ꢑꢏ ꢂ
SLVS267B − DECEMBER 1999 − REVISED AUGUST 2000
TYPICAL CHARACTERISTICS
FALL TIME, 5-V xVCC SWITCH
vs
RISE TIME, 5-V xVCC SWITCH
vs
LOAD CAPACITANCE
LOAD CAPACITANCE
1.8
1.6
4
3.5
3
T
= 85°C
J
1.4
1.2
2.5
2
T
J
= 85°C
1
T
J
= −40°C
0.8
0.6
T
J
= 25°C
T
J
= 25°C
T
J
= −40°C
1.5
1
0.4
0.5
0
0.2
0
dc Load = 1 A
100 1000
dc Load = 1 A
100 1000
0.1
1
10
0.1
1
10
C
− Load Capacitance − µF
C
− Load Capacitance − µF
L
L
Figure 16
Figure 17
FALL TIME, 12-V xVPP SWITCH
RISE TIME, 12-V xVPP SWITCH
vs
vs
LOAD CAPACITANCE
LOAD CAPACITANCE
5
4.5
4
20
18
T
J
= 85°C
16
14
12
T
J
= 25°C
3.5
3
10
8
2.5
2
T
J
= −40°C
T
J
= −40°C
1.5
6
4
T
J
= 85°C
1
T
J
= 25°C
.5
0
2
0
dc Load = 50 mA
100 1000
dc Load = 50 mA
100 1000
0.1
1
10
0.1
1
10
C
− Load Capacitance − µF
C
− Load Capacitance − µF
L
L
Figure 18
Figure 19
14
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SLVS267B − DECEMBER 1999 − REVISED AUGUST 2000
TYPICAL CHARACTERISTICS
INPUT CURRENT AT V
= V
= 5 V
INPUT CURRENT AT V
= V
= 3.3 V
I(xVCC)
I(xVPP)
I(xVCC)
vs
I(xVPP)
vs
JUNCTION TEMPERATURE
JUNCTION TEMPERATURE
120
110
100
90
100
90
I
I
I(5V)
I(5V)
80
70
80
70
60
50
40
30
20
60
50
40
30
20
I
I(3.3V)
I
I(12V)
10
10
0
0
I
I
I(12V)
I(3.3V)
−10
−50
0
50
100
−50
0
50
100
T
J
− Junction Temperature − °C
T
J
− Junction Temperature − °C
Figure 20
Figure 21
STATIC DRAIN-SOURCE ON-STATE RESISTANCE,
INPUT CURRENT AT V
= 5 V, V
= 12 V
I(xVCC)
vs
I(xVPP)
3.3-V xVCC SWITCH
vs
JUNCTION TEMPERATURE
JUNCTION TEMPERATURE
120
110
100
0.08
dc Load = 0.75 A
0.07
0.06
0.05
0.04
0.03
0.02
I
I(5V)
90
80
70
60
50
40
I
30
20
I(12V)
10
0
I
0.01
0
I(3.3V)
−10
−50
0
50
100
−50
0
50
100
T
J
− Junction Temperature − °C
T
J
− Junction Temperature − °C
Figure 22
Figure 23
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SLVS267B − DECEMBER 1999 − REVISED AUGUST 2000
TYPICAL CHARACTERISTICS
STATIC DRAIN-SOURCE ON-STATE RESISTANCE,
STATIC DRAIN-SOURCE ON-STATE RESISTANCE,
12-V xVPP SWITCH
vs
5-V xVCC SWITCH
vs
JUNCTION TEMPERATURE
JUNCTION TEMPERATURE
0.2
1
0.9
0.8
dc Load = 0.75 A
0.16
0.7
0.6
0.5
0.12
0.08
0.4
0.3
0.2
0.04
0
0.1
0
dc Load = 50 mA
50
−50
0
100
−50
0
50
100
T
J
− Junction Temperature − °C
T
J
− Junction Temperature − °C
Figure 24
Figure 25
DC INPUT-TO-OUTPUT VOLTAGE (DROP),
DC INPUT-TO-OUTPUT VOLTAGE (DROP),
3.3-V xVCC SWITCH
vs
5-V xVCC SWITCH
vs
LOAD CURRENT
LOAD CURRENT
0.16
0.06
0.05
0.04
0.03
0.02
0.14
0.12
0.1
85°C
85°C
25°C
25°C
0.08
0.06
0.04
−40°C
−40°C
0.01
0
0.02
0
0
0.2
0.4
0.6
0.8
0
0.2
0.4
0.6
0.8
I
− Load Current − A
I
L
− Load Current − A
L
Figure 26
Figure 27
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SLVS267B − DECEMBER 1999 − REVISED AUGUST 2000
TYPICAL CHARACTERISTICS
DC INPUT-TO-OUTPUT VOLTAGE (DROP),
SHORT-CIRCUIT CURRENT LIMIT,
3.3-V xVCC SWITCH
vs
12-V xVPP SWITCH
vs
LOAD CURRENT
JUNCTION TEMPERATURE
1.9
0.06
0.05
1.85
85°C
25°C
0.04
1.8
1.75
1.7
−40°C
0.03
0.02
1.65
1.6
0.01
0
−50
0
50
100
0
0.01
0.02
0.03
0.04
0.05
T
J
− Junction Temperature − °C
I
L
− Load Current − A
Figure 28
Figure 29
SHORT-CIRCUIT CURRENT LIMIT, 5-V xVCC
SHORT-CIRCUIT CURRENT LIMIT, 12-V xVPP
SWITCH
SWITCH
vs
vs
JUNCTION TEMPERATURE
JUNCTION TEMPERATURE
2.36
0.4
2.32
2.28
0.38
0.36
2.24
2.2
0.34
0.32
0.3
2.16
2.12
−50
−20
10
40
70
100
−50
0
50
100
T
J
− Junction Temperature − °C
T
J
− Junction Temperature − °C
Figure 30
Figure 31
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SLVS267B − DECEMBER 1999 − REVISED AUGUST 2000
APPLICATION INFORMATION
overview
PC Cards were initially introduced as a means to add EEPROM (flash memory) to portable computers with
limited onboard memory. The idea of add-in cards quickly took hold; modems, wireless LANs, Global Positioning
Satellite System (GPS), multimedia, and hard-disk versions were soon available. As the number of PC Card
applications grew, the engineering community quickly recognized the need for a standard to ensure
compatibility across platforms. To this end, the PCMCIA (Personal Computer Memory Card International
Association), comprising members from leading computer, software, PC Card, and semiconductor
manufacturers, was established. One key goal was to realize the plug-and-play concept. Cards and hosts from
different vendors should be compatible or able to communicate with one another transparently.
PC Card power specification
System compatibility also means power compatibility. The most current set of specifications (PC Card Standard)
set forth by the PCMCIA committee states that power is to be transferred between the host and the card through
eight of the 68 terminals of the PC Card connector. This power interface consists of two V , two V , and four
CC
pp
ground terminals. Multiple V
and ground terminals minimize connector terminal and line resistance. The two
CC
V
terminals were originally specified as separate signals, but are commonly tied together in the host to form
a single node to minimize voltage losses. Card primary power is supplied through the V
pp
terminals;
CC
flash-memory programming and erase voltage is supplied through the V terminals.
pp
designing for voltage regulation
The current PCMCIA specification for output voltage regulation, V
a typical PC power-system design, the power supply has an output-voltage regulation, V
Also, a voltage drop from the power supply to the PC Card will result from resistive losses, V
traces and the PCMCIA connector. A typical design would limit the total of these resistive losses to less than
, of the 5-V output is 5% (250 mV). In
O(reg)
, of 2% (100 mV).
PS(reg)
, in the PCB
PCB
1% (50 mV) of the output voltage. Therefore, the allowable voltage drop, V , for the TPS2214A or TPS2216A
DS
would be the PCMCIA voltage regulation less the power supply regulation and less the PCB and connector
resistive drops:
V
+ V
–V
–V
DS
O(reg) PS(reg) PCB
Typically, this would leave 100 mV for the allowable voltage drop across the 5-V switch. The specification for
output voltage regulation of the 3.3-V output is 300 mV; so, using the same equation by deducting the voltage
drop percentages (2%) for power-supply regulation and PCB resistive loss (1%), the allowable voltage drop for
the 3.3-V switch is 200 mV. The voltage drop is the output current multiplied by the switch resistance of the
TPS2214A or TPS2216A. Therefore, the maximum output current, I max, that can be delivered to the PC Card
O
in regulation is the allowable voltage drop across the IC, divided by the output-switch resistance.
V
DS
I max +
r
O
DS(on)
The xVCC outputs can deliver 1 A continuously at 5 V and 3.3 V within regulation over the operating temperature
range. The xVPP outputs of the IC can deliver 200 mA continuously.
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SLVS267B − DECEMBER 1999 − REVISED AUGUST 2000
APPLICATION INFORMATION
designing for voltage regulation (continued)
overcurrent and overtemperature protection
PC Cards are inherently subject to damage that can result from mishandling. Host systems require protection
against short-circuited cards that could lead to power-supply or PCB trace damage. Even systems robust
enough to withstand a short circuit would still undergo rapid battery discharge into the damaged PC Card,
resulting in the rather sudden and unacceptable loss of system power. Most hosts include fuses for protection.
However, the reliability of fused systems is poor, as blown fuses require troubleshooting and repair, usually by
the manufacturer.
The TPS2214A and TPS2216A take a two-pronged approach to overcurrent protection, which is designed to
activate if an output is shorted or when an overcurrent condition is present when switches are powered up. First,
instead of fuses, sense FETs monitor each of the xVCC and xVPP power outputs. Unlike sense resistors or
polyfuses, these FETs do not add to the series resistance of the switch; therefore voltage and power losses are
reduced. Overcurrent sensing is applied to each output separately. Excessive current generates an error signal
that limits the output current of only the affected output, preventing damage to the host. Each xVCC output
overcurrent limits from 1 A to 2.2 A, typically around 1.6 A; the xVPP outputs limit from 250 mA to 500 mA,
typically around 375 mA.
Second, when an overcurrent condition is detected, these devices assert an active low OC signal that can be
monitored by the microprocessor or controller to initiate diagnostics and/or send the user a warning message.
In the event that an overcurrent condition persists, causing the IC to exceed its maximum junction temperature,
thermal-protection circuitry activates. This shuts down all power outputs until the device cools to within a safe
operating region, which is ensured by a thermal shutdown hysteresis.
12-V supply not required
Many PC Card switches use the externally supplied 12 V to power gate drive and other chip functions; this
requires that power be present at all times. The TPS2214A and TPS2216A offer considerable power savings
by using an internal charge pump to generate the required higher gate drive voltages from the 5-V or 3.3-V
power supplies. Therefore, the external 12-V supply can be disabled except when needed for flash-memory
functions, thereby extending battery lifetime. Additional power savings are realized by the IC during shutdown
mode, in which quiescent current drops to a maximum of 1 µA.
3.3-V low-voltage mode
The TPS2214A and TPS2216A will operate in 3.3-V low-voltage mode when 3.3 V is the only available input
voltage (V
= 0, V
= 0). This feature allows host and PC Cards to be operated in low-power 3.3-V-only
I(5V)
I(12V)
modes such as sleep modes. Note that in this operation mode, the IC will derive its bias current from the 3.3-V
input pin and can only provide 3.3 V to the outputs.
voltage transitioning requirement
PC Cards are migrating from 5 V to 3.3 V to minimize power consumption, optimize board space, and increase
logic speeds. The TPS2214A and TPS2216A meet all combinations of power delivery as currently defined in
the PCMCIA standard. The latest protocol accommodates mixed 3.3-V/5-V systems by first powering the card
with 5 V, then polling it to determine its 3.3-V compatibility. The PCMCIA specification requires that the
capacitors on 3.3-V-compatible cards be discharged to below 0.8 V before applying 3.3-V power. This action
ensures that sensitive 3.3-V circuitry is not subjected to any residual 5-V charge and functions as a power reset.
PC Card specification requires that V
be discharged within 100 ms. PC Card resistance can not be relied on
CC
to provide a discharge path for voltages stored on PC Card capacitance because of possible high-impedance
isolation by power-management schemes. The TPS2214A and TPS2216A include discharge transistors on all
xVCC and xVPP outputs to meet the specification requirement.
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SLVS267B − DECEMBER 1999 − REVISED AUGUST 2000
APPLICATION INFORMATION
designing for voltage regulation (continued)
shutdown mode
In the shutdown mode, which can be controlled by bit D8 of the input serial DATA word, each of the xVCC and
xVPP outputs is forced to a high-impedance state. In this mode, the chip quiescent current is limited to 1 µA
or less to conserve battery power.
standby mode
The TPS2214A and TPS2216A can be put in standby mode by pulling STBY low to conserve power during
low-power operation. In this mode, all of the power outputs (xVCC and xVPP) will have a nominal current limit
of 50 mA. STBY has an internal 150-kΩ pullup resistor. The output-switch status of the device must be set,
allowing the output capacitors to charge, prior to enabling the standby mode. Changing the setting of the output
switches with the device in standby mode may cause an overcurrent response to be generated.
mode
The mode pin programs the switches in either TPS2214A/TPS2216A or TPS2206 mode. An internal 150-kΩ
pulldown resistor is connected to the pin. Floating or pulling the mode pin low sets the switches in TPS2206
mode; pulling the mode pin high sets the switches in TPS2214A/TPS2216A mode. In TPS2206 mode, xVPP
outputs are dependent on xVCC outputs. In TPS2214A/TPS2216A mode, xVPP is programmed independent
of xVCC. Refer to TPS2214A/TPS2216A control-logic tables for more information.
power-supply considerations
The TPS2214A and TPS2216A have multiple pins for each of its 3.3-V and 5-V power inputs and for the switched
xVCC outputs. Any individual pin can conduct the rated input or output current. Unless all pins are connected
in parallel, the series resistance is higher than that specified, resulting in increased voltage drops and less
power. It is recommended that all input and output power pins be paralleled for optimum operation. Because
the two 12-V pins are not internally connected, they must be tied together externally.
To increase the noise immunity of the TPS2214A and TPS2216A, the power-supply inputs should be bypassed
with a 1-µF electrolytic or tantalum capacitor paralleled by a 0.047-µF to 0.1-µF ceramic capacitor. It is strongly
recommended that the switched outputs be bypassed with a 0.1-µF (or larger) ceramic capacitor; doing so
improves the immunity of the IC to electrostatic discharge (ESD). Care should be taken to minimize the
inductance of PCB traces between the IC and the load. High switching currents can produce large negative
voltage transients, which forward biases substrate diodes, resulting in unpredictable performance. Similarly, no
pin should be taken, or allowed to fall, below −0.3 V.
RESET and RESET inputs
To ensure that cards are in a known state after power brownouts or system initialization, the PC Cards should
be reset at the same time as the host by applying low impedance paths from xVCC and xVPP terminals to
ground. A low-impedance output state allows discharging of residual voltage remaining on PC Card filter
capacitance, permitting the system (host and PC Cards) to be powered up concurrently. The active-high RESET
or active low RESET input will close internal switches S1, S4, S7, and S11 with all other switches left open. The
TPS2214A and TPS2216A remain in the low-impedance output state until the signal is deasserted and further
data is clocked in and latched. The input serial data can not be latched during reset mode. RESET and RESET
are provided for direct compatibility with systems that use either an active-low or active-high reset voltage
supervisor. The RESET pin has an internal 150-kΩ pulldown resistor and the RESET pin has an internal 150-kΩ
pullup resistor. The device will be reset automatically when powered up.
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ꢔ ꢍꢏ ꢂꢑ ꢏꢒꢆ ꢋ ꢁꢎ ꢕꢎꢒ ꢆ ꢎꢍ ꢖꢀꢏ ꢍ ꢋꢋ ꢑꢏ ꢂ
SLVS267B − DECEMBER 1999 − REVISED AUGUST 2000
APPLICATION INFORMATION
calculating junction temperature
The switch resistance, r
, is dependent on the junction temperature, T , of the die. The junction temperature
J
DS(on)
is dependent on both r
and the current through the switch. To calculate T , first find r
from Figures 23
DS(on)
J
DS(on)
through 25, using an initial temperature estimate about 50°C above ambient. Then calculate the power
dissipation for each switch, using the formula:
2
P
+ r
I
D
DS(on)
Next, sum the power dissipation of all switches and calculate the junction temperature:
ǒ
Ǔ) T
ȍPD
T +
R
J
qJA
A
Where:
R
is the inverse of the derating factor given in the dissipation rating table.
θJA
Compare the calculated junction temperature with the initial temperature estimate. If the temperatures are not
within a few degrees of each other, recalculate using the calculated temperature as the initial estimate.
logic inputs and outputs
The serial interface consists of DATA, CLOCK, and LATCH leads. The data is clocked in on the positive edge
of the clock (see Figures 2 and 3). The 11-bit (D0−D10) serial data word is loaded during the positive edge of
the latch signal. The positive edge of the latch signal should occur before the next positive edge of the clock
occurs.
The TPS2216 serial interfaces are compatible with serial-interface PCMCIA controllers and current PCMCIA
and Japan Electronic Industry Development Association (JEIDA) standards.
An overcurrent output (OC) is provided to indicate an overcurrent or overtemperature condition in any of the
xVCC and xVPP outputs as previously discussed.
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SLVS267B − DECEMBER 1999 − REVISED AUGUST 2000
APPLICATION INFORMATION
TPS2214A/TPS2216A control logic
TPS2214A/TPS2216A mode (MODE pulled high)
xVPP
AVPP CONTROL SIGNALS
BVPP CONTROL SIGNALS
OUTPUT
OUTPUT
V_BVPP
V_AVPP
D8 (SHDN)
D0
0
D1
0
D9
X
0
D8 (SHDN)
D4
0
D5
0
D10
X
1
1
1
1
1
0
0 V
3.3 V
5 V
1
1
1
1
1
0
0 V
3.3 V
5 V
0
1
0
1
0
0
1
1
0
1
1
1
0
X
X
X
12 V
Hi-Z
Hi-Z
1
0
X
12 V
Hi-Z
Hi-Z
1
1
1
1
X
X
X
X
X
X
xVCC
AVCC CONTROL SIGNALS
BVCC CONTROL SIGNALS
OUTPUT
V_AVCC
OUTPUT
V_BVCC
D8 (SHDN)
D3
0
D2
0
D8 (SHDN)
D6
0
D7
0
1
1
1
1
0
0 V
3.3 V
5 V
1
1
1
1
0
0 V
3.3 V
5 V
0
1
0
1
1
0
1
0
1
1
0 V
1
1
0 V
X
X
Hi-Z
X
X
Hi-Z
TPS2206 mode (MODE floating or pulled low)
xVPP
AVPP CONTROL SIGNALS
BVPP CONTROL SIGNALS
OUTPUT
OUTPUT
V_BVPP
V_AVPP
D8 (SHDN)
D0
0
D1
0
D8 (SHDN)
D4
0
D5
0
1
1
1
1
0
0 V
V_AVCC
12 V
1
1
1
1
0
0 V
V_BVCC
12 V
0
1
0
1
1
0
1
0
1
1
Hi-Z
1
1
Hi-Z
X
X
Hi-Z
X
X
Hi-Z
xVCC
AVCC CONTROL SIGNALS
BVCC CONTROL SIGNALS
OUTPUT
V_AVCC
OUTPUT
V_BVCC
D8 (SHDN)
D3
0
D2
0
D8 (SHDN)
D6
0
D7
0
1
1
1
1
0
0 V
3.3 V
5 V
1
1
1
1
0
0 V
3.3 V
5 V
0
1
0
1
1
0
1
0
1
1
0 V
1
1
0 V
X
X
Hi-Z
X
X
Hi-Z
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ꢔ ꢍꢏ ꢂꢑ ꢏꢒꢆ ꢋ ꢁꢎ ꢕꢎꢒ ꢆ ꢎꢍ ꢖꢀꢏ ꢍ ꢋꢋ ꢑꢏ ꢂ
SLVS267B − DECEMBER 1999 − REVISED AUGUST 2000
APPLICATION INFORMATION
ESD protections (see Figure 32)
All TPS2214A and TPS2216A inputs and outputs incorporate ESD-protection circuitry designed to withstand
a 2-kV human-body-model discharge as defined in MIL-STD-883C, Method 3015. The xVCC and xVPP outputs
can be exposed to potentially higher discharges from the external environment through the PC Card connector.
Bypassing the outputs with 0.1-µF capacitors protects the devices from discharges up to 10 kV.
TPS2216A
AVCC
V
V
CC
†
0.1 µF
AVCC
AVCC
AVPP
CC
PC Card
Connector A
pp1
V
V
†
0.1 µF
pp2
12V
12V
BVCC
V
V
12V
5V
CC
†
10 µF
33 µF
0.1 µF
0.1 µF
0.1 µF
BVCC
BVCC
BVPP
CC
PC Card
Connector B
pp1
5V
5V
V
V
†
0.1 µF
pp2
5V
3.3V
3.3V
3.3V
3.3V
33 µF
0.1 µF
Controller
DATA
DATA
CLOCK
LATCH
RESET
RESET
OC
CLOCK
LATCH
MODE
STBY
From PCI or
System RST
GPI/O
†
Maximum recommended output capacitance for xVCC is 220 µF and for xVPP is 10 µF without OC glitch when switches are powered on.
Figure 32. Detailed Interconnections and Capacitor Recommendations
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ꢀ ꢁ ꢂ ꢃ ꢃꢄ ꢅ ꢆ ꢇ ꢀ ꢁꢂ ꢃ ꢃ ꢄ ꢈ ꢆ
ꢉ ꢊꢆꢋ ꢌꢂꢋ ꢍꢀ ꢁꢎ ꢎꢆ ꢏꢉ ꢁ ꢍꢐ ꢑꢏ ꢂ ꢐꢒ ꢀ ꢎꢓꢑ ꢂ
ꢔ ꢍꢏ ꢂꢑ ꢏꢒ ꢆ ꢋ ꢁꢎ ꢕꢎ ꢒ ꢆ ꢎꢍ ꢖꢀ ꢏꢍ ꢋꢋ ꢑꢏ ꢂ
SLVS267B − DECEMBER 1999 − REVISED AUGUST 2000
APPLICATION INFORMATION
12-V flash memory supply
The TPS6734 is a fixed 12-V output boost converter capable of delivering 120 mA from inputs as low as 2.7 V.
The device is pin-for-pin compatible with the MAX734 regulator and offers the following advantages: lower
supply current, wider operating input-voltage range, and higher output currents. As shown in Figure 33, the only
external components required are: an inductor, a Schottky rectifier, an output filter capacitor, an input filter
2
capacitor, and a small capacitor for loop compensation. The entire converter occupies less than 0.7 in of PCB
space when implemented with surface-mount components. An enable input is provided to shut the converter
down and reduce the supply current to 3 µA when 12 V is not needed.
The TPS6734 is a 170-kHz current-mode PWM (pulse-width modulation) controller with an n-channel MOSFET
power switch. Gate drive for the switch is derived from the 12-V output after start-up to minimize the die area
needed to realize the 0.7-Ω MOSFET and improve efficiency at input voltages below 5 V. Soft start is
accomplished with the addition of one small capacitor. A 1.22-V reference (pin 2) is brought out for external use.
For additional information, see the TPS6734 data sheet (SLVS127).
TPS2216A
AVCC
3.3V or 5V
R1
10 kΩ
AVCC
AVCC
AVPP
TPS6734
ENABLE
(see Note A)
1
8
L1
18 µH
EN
VCC
2
3
7
6
REF
SS
FB
C1
33 µF
20V
+
D1
OUT
33 µF, 20 V
4
5
12 V
COMP
GND
12V
12V
C2
0.01 µF
+
C1
0.1 µF
BVCC
BVCC
BVCC
BVPP
5 V
C4
0.001 µF
5V
5V
33 µF
33 µF
0.1 µF
0.1 µF
5V
3.3 V
3.3V
3.3V
3.3V
DATA
CLOCK
LATCH
RESET
RESET
OC
MODE
STBY
NOTE A: The enable terminal can be tied to a general-purpose I/O terminal on the PCMCIA controller or tied high.
Figure 33. TPS2216A with TPS6734 12-V, 120-mA Supply
24
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
24-Feb-2006
PACKAGING INFORMATION
Orderable Device
TPS2214ADB
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SSOP
DB
24
24
24
24
32
32
32
32
30
30
30
30
Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TPS2214ADBG4
TPS2214ADBR
TPS2214ADBRG4
TPS2216ADAP
TPS2216ADAPG4
TPS2216ADAPR
TPS2216ADAPRG4
TPS2216ADB
SSOP
SSOP
DB
DB
Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SSOP
DB
Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
HTSSOP
HTSSOP
HTSSOP
HTSSOP
SSOP
DAP
DAP
DAP
DAP
DB
Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TPS2216ADBG4
TPS2216ADBR
TPS2216ADBRG4
SSOP
DB
Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SSOP
DB
Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SSOP
DB
Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
24-Feb-2006
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
M
0,15
15
0,25
0,09
5,60
5,00
8,20
7,40
Gage Plane
1
14
0,25
A
0°–ā8°
0,95
0,55
Seating Plane
0,10
2,00 MAX
0,05 MIN
PINS **
14
16
20
24
28
30
38
DIM
6,50
5,90
6,50
5,90
7,50
8,50
7,90
10,50
9,90
10,50 12,90
A MAX
A MIN
6,90
9,90
12,30
4040065 /E 12/01
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
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