TPS2231PW [TI]
ExpressCard?? POWER INTERFACE SWITCH; 的ExpressCard ？电源接口开关
| 型号： | TPS2231PW |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | ExpressCard?? POWER INTERFACE SWITCH |
| 文件： | 总26页 (文件大小：935K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPS2231
TPS2236
RGP
PW
PWP
DAP
www.ti.com
SLVS536B–JULY 2004–REVISED JANUARY 2005
ExpressCard™ POWER INTERFACE SWITCH
FEATURES
•
Available in a 20-pin TSSOP, a 20-pin QFN, or
24-pin PowerPAD™ HTSSOP (Single)
•
•
•
Meets the ExpressCard™ Standard
(ExpressCard|34 or ExpressCard|54)
•
Available in a 32-pin PowerPAD™ HTSSOP
(Dual)
Compliant with the ExpressCard™
Compliance Checklists
APPLICATIONS
Fully Satisfies the ExpressCard™
Implementation Guidelines
•
•
•
•
•
Notebook Computers
Desktop Computers
Personal Digital Assistants (PDAs)
Digital Cameras
TV and Set Top Boxes
•
•
•
•
Supports Systems with WAKE Function
TTL-Logic Compatible Inputs
Short Circuit and Thermal Protection
–40°C to 85°C Ambient Operating
Temperature Range
DESCRIPTION
The TPS2231 and TPS2236 ExpressCard power interface switches provide the total power management solution
required by the ExpressCard specification. The TPS2231 and TPS2236 ExpressCard power interface switches
distribute 3.3 V, AUX, and 1.5 V to the ExpressCard socket. Each voltage rail is protected with integrated
current-limiting circuitry.
The TPS2231 supports systems with single-slot ExpressCard|34 or ExpressCard|54 sockets. The TPS2236
supports systems with dual-slot ExpressCard sockets.
End equipment for the TPS2231 and TPS2236 include notebook computers, desktop computers, personal digital
assistants (PDAs), and digital cameras.
AUXIN
3.3VIN
AUXOUT
3.3VOUT
Host
Power
Source
1.5VIN
1.5VOUT
TPS2231
PERST
CPPE
Express Card
SHDN
STBY
CPUSB
SYSRST
Host
Chip
Set/Lock
Circuits
OC
GND
RCLKEN
REFCLK+
REFCLK−
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
ExpressCard is a trademark of Personal Computer Memory Card International Association.
PowerPAD is a trademark of Texas Instruments.
UNLESS OTHERWISE NOTED this document contains PRO-
Copyright © 2004–2005, Texas Instruments Incorporated
DUCTION DATA information current as of publication date. Prod-
ucts conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily
include testing of all parameters.
TPS2231
TPS2236
www.ti.com
SLVS536B–JULY 2004–REVISED JANUARY 2005
These devices have limited built-in ESD protection. The leads should be shorted together or the device
placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
AVAILABLE OPTIONS
PACKAGED DEVICES(1)
TA
NUMBER OF CHANNELS
TSSOP
PowerPAD HTSSOP
TPS2231PWP
QFN
TPS2231RGP(2)
Single
Dual
TPS2231PW
–40°C to 85°C
TPS2236DAP
(1) The package is available taped and reeled. Add an R suffix to device types (e.g., TPS2231PWPR).
(2) Product preview stage of development
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)(1)
TPS223x
UNIT
VI(3.3VIN)
–0.3 to 6
–0.3 to 6
–0.3 to 6
–0.3 to 6
–0.3 to 6
–0.3 to 6
–0.3 to 6
V
V
V
V
V
V
V
Input voltage range for card
power
VI
VI(1.5VIN)
VI(AUXIN)
Logic input/output voltage
VO(3.3VOUT)
VO(1.5VOUT)
VO(AUXOUT)
VO
Output voltage range
Continuous total power dissipation
Output current
See Dissipation Rating Table
Internally limited
IO(3.3VOUT)
IO(AUXOUT)
IO(1.5VOUT)
IO
Internally limited
Internally limited
OC sink current
10
10
mA
PERST sink/source current
mA
°C
°C
°C
TJ
Operating virtual junction temperature range
Storage temperature range
–40 to 120
–55 to 150
260
Tstg
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
TPS2231
2
kV
Human body model
TPS2236, all pins except
PERSTx and OCx
Electrostatic discharge
(HBM) MIL-STD-883C
ESD
protection
TPS2236, PERSTx and OCx
Charge device model (CDM)
1.5
kV
V
500
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
DISSIPATION RATINGS (Thermal Resistance = °C/W)
T
A ≤ 25°C
DERATING FACTOR
ABOVE TA = 25°C
TA = 70°C
POWER RATING
TA = 85°C
POWER RATING
PACKAGE
POWER RATING
PW (20)(1)
PWP (24)(1)
704.2 mW
7.41 mW/°C
33.19 mW/°C
34.5 mW/°C
370.6 mW
1659.5 mW
1725 mW
259.5 mW
1161.6 mW
1207.3 mW
3153 mW
(2)
RGP (20)
3277.5 mW
(1) These devices are mounted on an JEDEC low-k board (2-oz. traces on surface), (The table is assuming that the maximum junction
temperature is 120°C). The power pad on the device must be soldered down to the power pad on the board if best thermal performance
is needed.
(2) Tis device is mounted on a JEDEC JESO51.5 high-k board (2 signal, 2 plane). The values assume a maxium junction temperature of
120°C.
2
TPS2231
TPS2236
www.ti.com
SLVS536B–JULY 2004–REVISED JANUARY 2005
DISSIPATION RATINGS (Thermal Resistance = °C/W) (continued)
T
A ≤ 25°C
DERATING FACTOR
ABOVE TA = 25°C
TA = 70°C
POWER RATING
TA = 85°C
POWER RATING
PACKAGE
POWER RATING
(1)
DAP (32)
993.4 mW
10.46 mW/°C
42.55 mW/°C
522.8 mW
366 mW
PowerPAD not soldered down
DAP (32)(1)
4040.8 mW
2126.8 mW
1488.7 mW
RECOMMENDED OPERATING CONDITIONS
MIN
MAX
3.6
UNIT
VI(3.3VIN)
VI(1.5VIN)
VI(AUXIN)
IO(3.3VOUT)
IO(1.5VOUT)
IO(AUXOUT)
TJ
3.3VIN is only required for its respective functions
1.5VIN is only required for its respective functions
AUXIN is required for all circuit operations
3
1.35
3
Input voltage
1.65
3.6
V
0
1.3
A
Continuous output current
TJ = 120°C
0
650
275
120
mA
mA
°C
0
Operating virtual junction temperature
–40
ELECTRICAL CHARACTERISTICS
TJ = 25°C, VI(3.3VIN) = VI(AUXIN) = 3.3 V, VI(1.5VIN) = 1.5 V, VI(/SHDNx), VI(/STBYx) = 3.3 V, VI(/CPPEx) = VI(/CPUSBx) = 0 V,
VI(/SYSRST) = 3.3 V, OCx and RCLKENx and PERSTx are open, all voltage outputs unloaded (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
POWER SWITCH
TJ = 25°C, I = 1300 mA each
TJ = 100°C, I = 1300 mA each
TJ = 25°C, I = 650 mA each
TJ = 100°C, I = 650 mA each
TJ = 25°C, I = 275 mA each
TJ = 100°C, I = 275 mA each
VI(/SHDNx) = 0 V, I(discharge) = 1 mA
45
3.3VIN to 3.3VOUT with two
switches on for dual
mΩ
68
46
Power switch
resistance
1.5VIN to 1.5VOUT With two
switches on for dual
mΩ
70
120
AUXIN to AUXOUT with two
switches on for dual
mΩ
200
R(DIS_FET) Discharge resistance on 3.3V/1.5V/AUX outputs
100
1.35
0.67
275
500
2.5
1.3
600
Ω
A
IOS(3.3VOUT) (steady-state value)
Short-circuit out-
2
1
TJ (–40, 120°C]. Output powered into
a short
IOS
IOS(1.5VOUT) (steady-state value)
IOS(AUXOUT)(steady-state value)
A
put current(1)
450
mA
Rising temperature, not in
overcurrent condition
155
120
165
Trip point, TJ
Hysteresis
°C
Thermal
shutdown
Overcurrent condition
130
10
VO(3.3VOUT) with 100-mΩ short
43
100
140
VO(1.5VOUT) with 100-mΩ short,
TPS2231
From short to the 1st threshold
within 1.1 times of final current
limit, TJ = 25°C
100
110
Current-limit
response time
µs
VO(1.5VOUT) with 100-mΩ short,
TPS2236
150
VO(AUXOUT) with 100-mΩ short
38
125
17.5
5.5
85
100
200
25
II(AUXIN)
Normal operation
of TPS2236
II(3.3VIN)
µA
µA
Outputs are unloaded,
TJ [–40, 120°C] (does not include
CPPEx and CPUSBx logic pullup
currents)
II(1.5VIN)
II(AUXIN)
15
Operation input
quiescent current
II
150
15
Normal operation
of TPS2231
II(3.3VIN)
10
II(1.5VIN)
2.5
10
(1) Pulse-testing techniques maintain junction temperature close to ambient temperature; thermal effects must be taken into account
separately.
3
TPS2231
TPS2236
www.ti.com
SLVS536B–JULY 2004–REVISED JANUARY 2005
ELECTRICAL CHARACTERISTICS (continued)
TJ = 25°C, VI(3.3VIN) = VI(AUXIN) = 3.3 V, VI(1.5VIN) = 1.5 V, VI(/SHDNx), VI(/STBYx) = 3.3 V, VI(/CPPEx) = VI(/CPUSBx) = 0 V,
VI(/SYSRST) = 3.3 V, OCx and RCLKENx and PERSTx are open, all voltage outputs unloaded (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
200
17.5
5.5
120
10
MAX UNIT
II(AUXIN)
320
Normal operation
of TPS2236
II(3.3VIN)
25
15
µA
µA
µA
µA
µA
µA
Outputs are unloaded, TJ[–40,
120°C] (include CPPEx and CPUSBx
logic pullup currents)
II(1.5VIN)
II(AUXIN)
210
15
Normal operation
of TPS2231
II(3.3VIN)
II(1.5VIN)
2.5
250
3.5
0.1
144
3.5
0.5
40
10
Total input
II
quiescent current
II(AUXIN)
440
20
Shutdown mode of
TPS2236
II(3.3VIN)
CPUSB = CPPE = 0 V SHDN = 0 V
(discharge FETs are on) (include
CPPEx and CPUSBx logic pullup
currents and SHDN pullup current) TJ
[–40, 120°C]
II(1.5VIN)
20
II(AUXIN)
270
10
Shutdown mode of
TPS2231
II(3.3VIN)
II(1.5VIN)
10
II(AUXIN)
100
100
100
50
SHDN = 3.3 V,
TPS2236
II(3.3VIN)
0.1
0.1
20
CPUSB = CPPE = 3.3 V (no card
present, discharge FETs are on);
current measured at input pins
TJ = 120°C, includes RCLKEN
pullup current
II(1.5VIN)
Forward leakage
current
Ilkg(FWD)
II(AUXIN)
TPS2231
II(AUXOUT)
II(3.3VIN)
0.1
0.1
0.1
50
II(1.5VIN)
50
TJ = 25°C
TJ = 120°C
TJ = 25°C
TJ = 120°C
TJ = 25°C
TJ = 120°C
10
µA
µA
µA
50
VO(AUXOUT) = VO(3.3VOUT)= 3.3 V;
VO(1.5VOUT) = 1.5 V; All voltage inputs
are grounded (current measured
from output pins going in)
Reverse leakage
current (TPS2236 II(3.3VOUT)
and TPS2231)
0.1
0.1
10
Ilkg(RVS)
50
10
II(1.5VOUT)
50
LOGIC SECTION (SYSRST, SHDNx, STBYx, PERSTx, RCLKENx, OCx, CPUSBx, CPPEx)
SYSRST = 3.6 V, sinking
0
0
0
1
30
1
I(/SYSRST)
Input
Input
µA
µA
SYSRST = 0 V, sourcing
SHDNx = 3.6 V, sinking
10
10
I(/SHDNx)
SHDNx = 0 V, sourcing
30
1
Logic input
supply current
STBYx = 3.6 V, sinking
I(/STBYx)
Input
Input
Inputs
µA
µA
µA
STBYx = 0 V, sourcing
10
10
30
30
1
I(RCLKENx)
RCLKENx = 0 V, sourcing
CPUSB or CPPE = 0 V, sinking
CPUSB or CPPE = 3.6 V, sourcing
0
I(/CPUSBx) or
I(/CPPEx)
10
2
30
High level
Low level
Logic input
voltage
V
V
0.8
0.4
3
RCLEN output low voltage
Output
IO(RCLKEN) = 60 µA
3.3VOUT falling
AUXOUT falling
1.5VOUT falling
2.7
2.7
1.2
PERST assertion threshold of output voltage (PERST
asserted when any output voltage falls below the
threshold)
3
V
1.35
3.3VOUT, AUXOUT, or 1.5VOUT
falling
PERST assertion delay from output voltage
PERST de-assertion delay from output voltage
PERST assertion delay from SYSRST
500
20
ns
ms
ns
3.3VOUT, AUXOUT, and 1.5VOUT
rising within tolerance
4
10
Max time from SYSRST asserted or
de-asserted
500
4
TPS2231
TPS2236
www.ti.com
SLVS536B–JULY 2004–REVISED JANUARY 2005
ELECTRICAL CHARACTERISTICS (continued)
TJ = 25°C, VI(3.3VIN) = VI(AUXIN) = 3.3 V, VI(1.5VIN) = 1.5 V, VI(/SHDNx), VI(/STBYx) = 3.3 V, VI(/CPPEx) = VI(/CPUSBx) = 0 V,
VI(/SYSRST) = 3.3 V, OCx and RCLKENx and PERSTx are open, all voltage outputs unloaded (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
3.3VOUT, AUXOUT, or 1.5VOUT
falling out of tolerance or triggered by
SYSRST
tW(PERST)
PERST minimum pulse width
100
250
µs
PERST output low voltage
PERST output high voltage
OC output low voltage
OC leakage current
0.4
V
V
IO(PERST) = 500 µA
2.4
6
IO(/OC) = 2 mA
VO(/OC) = 3.6 V
0.4
1
V
µA
Falling into or out of an overcurrent
condition
OC deglitch
20
mS
UNDERVOLTAGE LOCKOUT (UVLO)
3.3VIN level, below which 3.3VIN
and 1.5VIN switches are off
3.3VIN UVLO
2.6
1
2.9
1.25
2.9
1.5VIN level, below which 3.3VIN
and 1.5VIN switches are off
1.5VIN UVLO
V
AUXIN level, below which all
switches are off
AUXIN UVLO
2.6
UVLO hysteresis
100
mV
SWITCHING CHARACTERISTICS
TJ = 25°C, VI(3.3VIN) = VI(AUXIN) = 3.3 V, VI(1.5VIN) = 1.5 V, VI(/SHDNx), VI(/STBYx) = 3.3 V, VI(/CPPEx) = VI(/CPUSBx) = 0 V,
VI(/SYSRST) = 3.3 V, OCx and RCLKENx and PERSTx are open, all voltage outputs unloaded (unless otherwise noted)
PARAMETER
3.3VIN to 3.3VOUT
TEST CONDITIONS
MIN
0.1
0.1
0.1
0.1
0.1
0.1
10
TYP
MAX UNIT
CL(3.3VOUT) = 0.1 µF, IO(3.3VOUT) = 0 A
CL(AUXOUT) = 0.1 µF, IO(AUXOUT) = 0 A
CL(1.5VOUT) = 0.1 µF, IO(1.5VOUT) = 0 A
CL(3.3VOUT) = 100 µF, RL = VI(3.3VIN)/1 A
CL(AUXOUT) = 100 µF, RL = VI(AUXIN)/0.250 A
CL(1.5VOUT) = 100 µF, RL = VI(1.5VIN)/0.500 A
CL(3.3VOUT) = 0.1 µF, IO(3.3VOUT) = 0 A
CL(AUXOUT) = 0.1 µF, IO(AUXOUT) = 0 A
CL(1.5VOUT) = 0.1 µF, IO(1.5VOUT) = 0 A
CL(3.3VOUT) = 20 µF, IO(3.3VOUT) = 0 A
CL(AUXOUT) = 20 µF, IO(AUXOUT) = 0 A
CL(1.5VOUT) = 20 µF, IO(1.5VOUT) = 0 A
CL(3.3VOUT) = 0.1 µF, IO(3.3VOUT) = 0 A
CL(AUXOUT) = 0.1 µF, IO(AUXOUT) = 0 A
CL(1.5VOUT) = 0.1 µF, IO(1.5VOUT) = 0 A
CL(3.3VOUT) = 100 µF, RL = VI(3.3VIN)/1 A
CL(AUXOUT) = 100 µF RL = VI(AUXIN)/0.250 A
CL(1.5VOUT) = 100 µF, RL = VI(1.5VIN)/0.500 A
CL(3.3VOUT) = 0.1 µF, IO(3.3VOUT) = 0 A
CL(AUXOUT) = 0.1 µF, IO(AUXOUT) = 0A
CL(1.5VOUT) = 0.1 µF, IO(1.5VOUT) = 0 A
CL(3.3VOUT) = 100 µF, RL = VI(3.3VIN)/1 A
CL(AUXOUT) = 100 µF, RL = VI(AUXIN)/0.250 A
CL(1.5VOUT) = 100 µF, RL = VI(1.5VIN)/0.500 A
3
3
AUXIN to AUXOUT
1.5VIN to 1.5VOUT
3.3VIN to 3.3VOUT
AUXIN to AUXOUT
1.5VIN to 1.5VOUT
3.3VIN to 3.3VOUT
AUXIN to VAUXOUT
1.5VIN to 1.5VOUT
3.3VIN to 3.3VOUT
AUXIN to VAUXOUT
1.5VIN to 1.5VOUT
3.3VIN to 3.3VOUT
AUXIN to VAUXOUT
1.5VIN to 1.5VOUT
3.3VIN to 3.3VOUT
AUXIN to VAUXOUT
1.5VIN to 1.5VOUT
3.3VIN to 3.3VOUT
AUXIN to VAUXOUT
1.5VIN to 1.5VOUT
3.3VIN to 3.3VOUT
AUXIN to VAUXOUT
1.5VIN to 1.5VOUT
3
tr
Output rise times
ms
6
6
6
150
10
150
150
30
30
30
150
150
150
5
µs
ms
µs
Output fall times
10
when card removed
(both CPUSB and
CPPE de-asserted)
tf
2
2
2
10
10
Output fall times
when SHDN
asserted (card is
present)
10
tf
0.1
0.1
0.1
0.1
0.05
0.1
0.1
0.05
0.1
5
ms
5
1
0.5
1
Turn-on propagation
delay
tpd(on)
ms
1.5
1
1.5
5
TPS2231
TPS2236
www.ti.com
SLVS536B–JULY 2004–REVISED JANUARY 2005
SWITCHING CHARACTERISTICS (continued)
TJ = 25°C, VI(3.3VIN) = VI(AUXIN) = 3.3 V, VI(1.5VIN) = 1.5 V, VI(/SHDNx), VI(/STBYx) = 3.3 V, VI(/CPPEx) = VI(/CPUSBx) = 0 V,
VI(/SYSRST) = 3.3 V, OCx and RCLKENx and PERSTx are open, all voltage outputs unloaded (unless otherwise noted)
PARAMETER
3.3VIN to 3.3VOUT
TEST CONDITIONS
MIN
0.1
TYP
MAX UNIT
CL(3.3VOUT) = 0.1 µF, IO(3.3VOUT) = 0 A
CL(AUXOUT) = 0.1 µF, IO(AUXOUT) = 0 A
CL(1.5VOUT) = 0.1 µF, IO(1.5VOUT) = 0 A
CL(3.3VOUT) = 100 µF, RL = VI(3.3VIN)/1 A
CL(AUXOUT) = 100 µF, RL = VI(AUXIN)/0.250 A
CL(1.5VOUT) = 100 µF, RL = VI(1.5VIN)/0.500 A
1.5
0.5
AUXIN to VAUXOUT
1.5VIN to 1.5VOUT
3.3VIN to 3.3VOUT
AUXIN to VAUXOUT
1.5VIN to 1.5VOUT
0.05
0.1
1.5
ms
1.5
Turn-off propagation
delay
tpd(off)
0.1
0.05
0.1
0.5
1
PIN ASSIGNMENTS
TPS2231
TPS2231
PWP PACKAGE
(TOP VIEW)
PW PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
1
24
SYSRST
SHDN
STBY
OC
NC
SYSRST
SHDN
STBY
NC
OC
2
23
22
21
20
19
18
17
16
15
14
13
RCLKEN
AUXIN
AUXOUT
1.5VIN
3
RCLKEN
AUXIN
AUXOUT
1.5VIN
1.5VIN
1.5VOUT
1.5VOUT
CPPE
4
3.3VIN
3.3VIN
3.3VOUT
3.3VOUT
PERST
NC
5
3.3VIN
3.3VIN
3.3VOUT
3.3VOUT
PERST
NC
6
1.5VIN
7
1.5VOUT
1.5VOUT
CPPE
8
9
10
11
12
GND
CPUSB
GND
CPUSB
NC
NC
TPS2231
RGP PACKAGE
(TOP VIEW)
TPS2236
DAP PACKAGE
(TOP VIEW)
1
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
CPPE1
CPPE2
CPUSB1
NC
RCLKEN1
RCLKEN2
SYSRST
NC
2
3
4
20 19 18 17 16
15
5
AUXOUT
NC
1
2
3
4
NC
STBY1
STBY2
1.5VOUT1
1.5VIN
1.5VIN
1.5VOUT2
NC
STBY
6
CPUSB2
3.3VOUT1
3.3VIN
14
3.3VIN
3.3VOUT
NC
7
13
NC
8
9
3.3VIN
12
1.5VIN
1.5VOUT
10
11
12
13
14
15
16
3.3VOUT2
PERST2
NC
11
5
NC
6
7
8
9
10
GND
PERST1
AUXOUT1
AUXIN
OC2
OC1
SHDN2
SHDN1
AUXOUT2
NC - No internal connection
6
TPS2231
TPS2236
www.ti.com
SLVS536B–JULY 2004–REVISED JANUARY 2005
TERMINAL FUNCTIONS
TERMINAL
TPS2231
NO.
TPS2236
I/O
DESCRIPTION
NAME
NAME
NO.
DAP
8, 9
24, 25
15
PW
4, 5
15, 16
18
PWP
5, 6
18, 19
21
RGP
2
3.3VIN
1.5VIN
AUXIN
GND
3.3VIN
1.5VIN
AUXIN
GND
I
I
I
3.3-V input for 3.3VOUT
12
17
7
1.5-V input for 1.5VOUT
AUX input for AUXOUT and chip power
Ground
10
11
21
Switched output that delivers 0 V, 3.3 V or high impedance to
card
3.3VOUT
1.5VOUT
AUXOUT
6, 7
13, 14
17
7, 8
16, 17
20
3
3.3VOUT1
1.5VOUT1
AUXOUT1
3.3VOUT2
1.5VOUT2
AUXOUT2
SYSRST
7
O
O
O
O
O
O
I
Switched output that delivers 0 V, 1.5 V or high impedance to
card
11
15
26
14
10
23
16
30
Switched output that delivers 0 V, AUX or high impedance to
card
Switched output that delivers 0 V, 3.3 V or high impedance to
card
Switched output that delivers 0 V, 1.5 V or high impedance to
card
Switched output that delivers 0 V, AUX or high impedance to
card
System Reset input – active low, logic level signal. Internally
pulled up to AUXIN.
SYSRST
1
2
6
Card Present input for PCI Express cards. Internally pulled up to
AUXIN
CPPE
12
11
15
14
10
9
CPPE1
CPUSB1
CPPE2
1
3
2
I
I
I
CPUSB
Card Present input for USB cards. Internally pulled up to AUXIN.
Card Present input for PCI Express cards. Internally pulled up to
AUXIN.
CPUSB2
PERST1
PERST2
6
I
Card Present input for USB cards. Internally pulled up to AUXIN.
A logic level power good to slot 0 (with delay)
PERST
SHDN
8
2
9
3
8
13
11
O
O
A logic level power good to slot 1 (with delay)
Shutdown input – active low, logic level signal. Internally pulled
up to AUXIN.
20
SHDN1
SHDN2
STBY1
STBY2
17
18
28
27
I
I
I
I
Shutdown input – active low, logic level signal. Internally pulled
up to AUXIN.
Standby input – active low, logic level signal. Internally pulled up
to AUXIN.
STBY
3
4
1
Standby input – active low, logic level signal. Internally pulled up
to AUXIN.
Reference Clock Enable signal. As an output, a logic level power
good to host for slot 0 (no delay – open drain). As an input, if
kept inactive (low) by the host, prevents PERST from being
de-asserted. Internally pulled up to AUXIN.
RCLKEN
19
22
18
RCLKEN1
RCLKEN2
32
31
I/O
I/O
Reference Clock Enable signal. As an output, a logic level power
good to host for slot 1 (no delay – open drain). As an input, if
kept inactive (low) by the host, prevents PERST from being
de-asserted. Internally pulled up to AUXIN.
OC
NC
20
9
23
19
OC1
OC2
19
20
O
O
Overcurrent status output for slot 0 (open drain)
Overcurrent status output for slot 1 (open drain)
1, 10,
12, 13, 13, 14,
24 16
4, 5,
4, 5,
12, 22,
29
NC
No connection
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SLVS536B–JULY 2004–REVISED JANUARY 2005
FUNCTIONAL BLOCK DIAGRAM
Single ExpressCard Power Switch
3.3VIN
3.3VOUT
PG
(Note A)
CS
CS
CS
S1
S2
S3
(Note B)
S4
S5
S6
AUXIN
1.5VIN
PG
PG
AUXOUT
1.5VOUT
Current Limit
Thermal Limit
CPUSB
CPPE
OC
FAULT
Control
Logic
AUXIN
STBY
Delay
RCLKEN
UVLO
POR
SHDN
GND
AUXIN
PERST
SYSRST
Note A: PG = power good
Note B: CS = current sense
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SLVS536B–JULY 2004–REVISED JANUARY 2005
FUNCTIONAL BLOCK DIAGRAM (continued)
Dual ExpressCard Power Switch
3.3VIN
PG1
PG1
CS
CS
3.3VOUT1
AUXOUT1
1.5 VOUT1
S1
S4
AUXIN
S2
S5
S6
1.5VIN
PG1
PG2
CS
CS
S3
3.3VOUT2
S7
S10
S11
S12
PG2
PG2
CS
CS
AUXOUT2
1.5VOUT2
S8
S9
Current Limit
Thermal Limit
CPUSB1
CPPE1
STBY1
OC1
CHANNEL-1
FAULT
AUXIN
Delay
RCLKEN1
SHDN1
Control
Logic
CPUSB2
PERST1
SYSRST
Delay
CPPE2
RCLKEN2
STBY2
PERST2
OC2
UVLO
SHDN2
POR
CHANNEL-2
FAULT
GND
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SLVS536B–JULY 2004–REVISED JANUARY 2005
DETAILED PIN DESCRIPTIONS
CPPE
A logic low level on this input indicates that the card present supports PCI Express functions. CPPE connects to
the AUXIN input through an internal pullup. When a card is inserted, CPPE is physically connected to ground if
the card supports PCI Express functions.
CPUSB
A logic low level on this input indicates that the card present supports USB functions. CPUSB connects to the
AUXIN input through an internal pullup. When a card is inserted, CPUSB is physically connected to ground if the
card supports USB functions.
SHDN
When asserted (logic low), this input instructs the power switch to turn off all voltage outputs and the discharge
FETs are activated. SHDN has an internal pullup connected to AUXIN.
STBY
When asserted (logic low) after the card is inserted, this input places the power switch in standby mode by
turning off the 3.3-V and 1.5-V power switches and keeping the AUX switch on. If asserted prior to the card being
present, STBY places the power switch in OFF Mode by turning off the AUX, 3.3-V, and 1.5-V power switches.
STBY has an internal pullup connected to AUXIN.
RCLKEN
This pin serves as both an input and an output. On power up, a discharge FET keeps this signal at a low state as
long as any of the output power rails are out of their tolerance range. Once all output power rails are within
tolerance, the switch releases RCLKEN allowing it to transition to a high state (internally pulled up to AUXIN).
The transition of RCLKEN from a low to a high state starts an internal timer for the purpose of deasserting
PERST. As an input, RCLKEN can be kept low to delay the start of the PERST internal timer.
Because RCLKEN is internally connected to a discharge FET, this pin can only be driven low and should never
be driven high as a logic input. When an external circuit drives this pin low, RCLKEN becomes an input;
otherwise, this pin is an output.
RCLKEN can be used by the host system to enable a clock driver.
PERST
On power up, this output remains asserted (logic level low) until all power rails are within tolerance. Once all
power rails are within tolerance and RCLKEN has been released (logic high), PERST is deasserted (logic high)
after a time delay as shown in the parametric table. On power down, this output is asserted whenever any of the
power rails drop below their voltage tolerance.
The PERST signal is an output from the host system and an input to the ExpressCard module. This signal is only
used by PCI Express-based modules and its function is to place the ExpressCard module in a reset state.
During power up, power down, or whenever power to the ExpressCard module is not stable or not within voltage
tolerance limits, the ExpressCard standard requires that PERST be asserted. As a result, this signal also serves
as a power-good indicator to the ExpressCard module, and the relationship between the power rails and PERST
are explicitly defined in the ExpressCard standard.
The host can also place the ExpressCard module in a reset state by asserting a system reset SYSRST. This
system reset generates a PERST to the ExpressCard module without disrupting the voltage rails. This is what is
normally called a warm reset. However, in a cold start situation, the system reset can also be used to extend the
length of time that PERST is asserted.
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SLVS536B–JULY 2004–REVISED JANUARY 2005
Detailed Pin Descriptions (continued)
SYSRST
This input is driven by the host system and directly affects PERST. Asserting SYSRST (logic low) forces PERST
to assert. RCLKEN is not affected by the assertion of SYSRST. SYSRST has an internal pullup connected to
AUXIN.
OC
This pin is an open-drain output. When any of the three power switches (AUX, 3.3V, and 1.5V) is in an
overcurrent condition, OC is asserted (logic low) by an internal discharge FET with a deglitch delay. Otherwise,
the discharge FET is open, and the pin can be pulled up to a power supply through an external resistor.
FUNCTIONAL TRUTH TABLES
Truth Table for Voltage Outputs
VOLTAGE INPUTS(1)
LOGIC INPUTS
VOLTAGE OUTPUTS(2)
MODE(3)
(4)
AUXIN
3.3VIN
1.5VIN
SHDN
STBY
CP
AUXOUT
3.3VOUT
Off
1.5VOUT
Off
On
On
On
On
x
x
x
x
x
0
1
1
1
x
x
x
0
1
x
Off
GND
GND
On
Off
GND
GND
Off
OFF
Shutdown
No Card
x
1
0
0
GND
GND
Off
x
x
On
On
On
On
Standby
On
On
On
Card Inserted
(1) For input voltages, On means the respective input voltage is higher than its turnon threshold voltage; otherwise, the voltage is Off (for
AUX input,Off means the voltage is close to zero volt).
(2) For output voltages, On means the respective power switch is turned on so the input voltage is connected to the output; Off means the
power switch and its output discharge FET are both off; GND means the power switch is off but the output discharge FET is on so the
voltage on the output is pulled down to 0 V.
(3) Mode assigns each set of input conditions and respective output voltage results to a different name. These modes are referred to as
input conditions in the following Truth Table for Logic Outputs.
(4) CP = CPUSB and CPPE– equal to 1 when both CPUSB and CPPE signals are logic high, or equal to 0 when either CPUSB or CPPE is
low.
Truth Table for Logic Outputs
INPUT CONDITIONS
SYSRST
LOGIC OUTPUTS
MODE
OFF
RCLKEN(1)
PERST
RCLKEN(2)
Shutdown
No Card
Standby
X
X
0
0
0
0
1
1
Hi-Z
0
0
0
1
0
1
0
1
0
Card Inserted
Hi-Z
0
(1) RCLKEN as a logic input in this column. RCLKEN is an I/O pin and it can be driven low externally, left open, or connected to
high-impedance terminals, such as the gate of a MOSFET. It must not be driven high externally.
(2) RCLKEN as a logic output in this column.
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POWER STATES
If AUXIN is not present, then all input-to-output power switches are kept off (OFF mode).
If AUXIN is present and SHDN is asserted (logic low), then all input-to-output power switches are kept off and the
output discharge FETs are turned on (Shutdown mode). If SHDN is asserted and then de-asserted, the state on
the outputs is restored to the state prior to SHDN assertion.
If 3.3VIN, AUXIN and 1.5VIN are present at the input of the power switch and no card is inserted, then all
input-to-output power switches are kept off and the output discharge FETs are turned on (No Card mode).
If 3.3VIN, AUXIN and 1.5VIN are present at the input of the power switch prior to a card being inserted, then all
input-to-output power switches are turned on once a card-present signal (CPUSB and/or CPPE) is detected
(Card Inserted mode).
If a card is present and all output voltages are being applied, then the STBY is asserted (logic low); the AUXOUT
voltage is provided to the card, and the 3.3VOUT and 1.5VOUT switches are turned off (Standby mode).
If a card is present and all output voltages are being applied, then the 1.5VIN, or 3.3VIN is removed from the
input of the power switch; the AUXOUT voltage is provided to the card and the 3.3VOUT and 1.5VOUT switches
are turned off (Standby mode).
If prior to the insertion of a card, the AUXIN is available at the input of the power switch and 3.3VIN and/or
1.5VIN are not, or if STBY is asserted (logic low), then no power is made available to the card (OFF mode). If
1.5VIN and 3.3VIN are made available at the input of the power switch after the card is inserted and STBY is not
asserted, all the output voltages are made available to the card (Card Inserted mode).
DISCHARGE FETs
The discharge FETs on the outputs are activated whenever the device detects that a card is not present (No
Card mode). Activation occurs after the input-to-output power switches are turned off (break before make). The
discharge FETs de-activate if either of the card-present lines go active low, unless the SHDN pin is asserted.
The discharge FETs are also activated whenever the SHDN input is asserted and stay asserted until SHDN is
de-asserted.
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SLVS536B–JULY 2004–REVISED JANUARY 2005
PARAMETER MEASUREMENT INFORMATION
VIN
VIN
I
I
O(1.5VOUT)
O(3.3VOUT/AUXOUT)
C
L
R
L
C
L
R
L
LOAD CIRCUIT
LOAD CIRCUIT
VOLTAGE WAVEFORMS
V
V
I(1.5V)
I(3.3V/AUXIN)
VIN
VIN
50%
50%
GND
GND
t
t
pd(off)
pd(off)
t
t
pd(on)
pd(on)
V
V
I(3.3V)
I(1.5V)
90%
90%
V
V
V
O(1.5VOUT)
O(3.3VOUT/AUXOUT)
10%
10%
GND
GND
Propagation Delay (3.3VOUT/AUXOUT)
Propagation Delay (1.5VOUT)
t
f
t
f
t
r
t
r
V
I(3.3V)
V
I(1.5V)
90%
10%
90%
10%
V
O(3.3VOUT/AUXOUT)
O(1.5VOUT)
GND
GND
Rise/Fall Time (3.3VOUT/AUXOUT)
Rise/Fall Time (1.5VOUT)
50%
V
V
I(1.5V)
I(3.3V)
GND
VIN
VIN
50%
GND
t
off
t
off
t
on
t
on
V
V
I(3.3V)
I(1.5V)
90%
90%
V
V
O(1.5VOUT)
O(3.3VOUT/AUXOUT)
10%
10%
GND
GND
Turn On/Off Time (3.3VOUT/AUXOUT)
Turn On/Off Time (1.5VOUT)
Figure 1. Test Circuits and Voltage Waveforms
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SLVS536B–JULY 2004–REVISED JANUARY 2005
TYPICAL CHARACTERISTICS
Table of Graphs
FIGURE
Output voltage when card is inserted
vs Time
2
3
RCLKEN and PERST voltage during power up
RCLKEN and PERST voltage during power down
PERST asserted by SYSRST when power is on
PERST de-asserted by SYSRST when power is on
Output voltage when 3.3VIN is removed
Output voltage when 1.5VIN is removed
OC response when powered into a short (3.3VOUT)
Supply current of AUXIN
vs Time
vs Time
4
vs Time
5
vs Time
6
vs Time
7
vs Time
8
vs Time
9
vs Junction temperature
vs Junction temperature
vs Junction temperature
vs Junction temperature
vs Junction temperature
vs Junction temperature
vs Junction temperature
vs Junction temperature
10
11
12
13
14
15
16
17
Static drain-source on-state resistance
3.3-V power switch current limit
1.5-V power switch current limit
AUX power switch current limit
3.3-V power switch current limit trip
1.5-V power switch current limit trip
AUX power switch current limit trip
OUTPUT VOLTAGE WHEN CARD IS INSERTED
RCLKEN AND PERST VOLTAGE DURING POWER UP
vs
vs
TIME
TIME
V
I(CPxx)
2 V/div
V
O(3.3VOUT)
2 V/div
V
V
O(3.3VOUT)
2 V/div
V
O(RCLKEN)
2 V/div
O(1.5VOUT)
2 V/div
V
O(PERST)
2 V/div
V
O(AUXOUT)
2 V/div
t − Time − 5 ms/div
t − Time − 1 ms/div
Figure 2.
Figure 3.
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RCLKEN AND PERST VOLTAGE DURING POWER DOWN
PERST ASSERTED BY SYSRST WHEN POWER IS ON
vs
vs
TIME
TIME
V
V
O(AUXOUT)
2 V/div
V
I(SYSRST)
2 V/div
O(RCLKEN)
2 V/div
V
O(PERST)
2 V/div
V
O(PERST)
2 V/div
t − Time − 1 ms/div
t − Time − 500 ns/div
Figure 4.
Figure 5.
PERST DE-ASSERTED BY SYSRST WHEN POWER IS ON
OUTPUT VOLTAGE WHEN 3.3VIN IS REMOVED
vs
vs
TIME
TIME
V
I(3.3VIN)
2 V/div
V
I(SYSRST)
2 V/div
V
O(3.3VOUT)
2 V/div
V
V
O(1.5VOUT)
2 V/div
V
O(PERST)
2 V/div
O(AUXOUT)
2 V/div
R
R
R
C
= 3.6 W
= 2.7 W
= 12 W
L(3.3VOUT)
L(1.5VOUT)
L(AUXOUT)
= 68 mF
L(3.3V/1.5V/AUXOUT)
t − Time − 100 ms/div
t − Time − 500 ms/div
Figure 6.
Figure 7.
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SLVS536B–JULY 2004–REVISED JANUARY 2005
OC RESPONSE WHEN POWERED INTO A SHORT
OUTPUT VOLTAGE WHEN 1.5VIN IS REMOVED
(3.3VOUT)
vs
vs
TIME
TIME
V
I(1.5VIN)
V
O(OC)
2 V/div
2 V/div
V
O(3.3VOUT)
2 V/div
V
O(1.5VOUT)
2 V/div
R
R
R
C
= 3.6 W
= 2.7 W
= 12 W
L(3.3VOUT)
L(1.5VOUT)
L(AUXOUT)
I
V
O(3.3VOUT)
0.5 A/div
O(AUXVOUT)
2 V/div
= 68 mF
L(3.3V/1.5V/AUXOUT)
t − Time − 500 ms/div
t − Time − 5 ms/div
Figure 8.
Figure 9.
SUPPLY CURRENT OF AUXIN
vs
JUNCTION TEMPERATURE
STATIC DRAIN-SOURCE ON-STATE RESISTANCE
vs
JUNCTION TEMPERATURE
180
250
200
150
100
50
3.3V_AUX
160
140
120
100
80
AUXIN + CPxx + SHDN+ RCLKEN
AUXIN + CPxx
1.5VIN
AUXIN
60
40
20
3.3VIN
0
−40 −20
0
20
40
60
80
100 120
0
T − Junction Temperature − 5C
J
−40 −20
0
20
40
60
80
100 120
T − Junction Temperature − 5C
J
Figure 10.
Figure 11.
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SLVS536B–JULY 2004–REVISED JANUARY 2005
3.3-V POWER SWITCH CURRENT LIMIT
1.5-V POWER SWITCH CURRENT LIMIT
vs
vs
JUNCTION TEMPERATURE
JUNCTION TEMPERATURE
2.10
1000
990
980
970
960
950
940
930
920
910
900
2.05
2
1.95
1.90
−40 −20
0
20
40
60
80
100 120
−40 −20
0
20
40
60
80
100 120
T − Junction Temperature − 5C
J
T − Junction Temperature − 5C
J
Figure 12.
Figure 13.
AUX POWER SWITCH CURRENT LIMIT
3.3-V POWER SWITCH CURRENT LIMIT TRIP
vs
vs
JUNCTION TEMPERATURE
JUNCTION TEMPERATURE
500
490
480
470
460
450
440
430
420
410
400
390
3.20
3.10
3
2.90
2.80
2.70
2.60
2.50
−40 −20
0
20
40
60
80
100 120
−40 −20
0
20
40
60
80
100 120
T − Junction Temperature − 5C
J
T − Junction Temperature − 5C
J
Figure 14.
Figure 15.
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SLVS536B–JULY 2004–REVISED JANUARY 2005
1.5-V POWER SWITCH CURRENT LIMIT TRIP
AUX POWER SWITCH CURRENT LIMIT TRIP
vs
vs
JUNCTION TEMPERATURE
JUNCTION TEMPERATURE
800
760
720
680
640
600
2000
1900
1800
1700
1600
1500
1400
1300
1200
1100
1000
−40 −20
0
20
40
60
80
100 120
−40 −20
0
20
40
60
80
100 120
T − Junction Temperature − 5C
J
T − Junction Temperature − 5C
J
Figure 16.
Figure 17.
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APPLICATION INFORMATION
INTRODUCTION TO ExpressCard
An ExpressCard module is an add-in card with a serial interface based on PCI Express and/or Universal Serial
Bus (USB) technologies. An ExpressCard comes in two form factors defined as ExpressCard|34 or
ExpressCard|54. The difference, as defined by the name, is the width of the module, 34 mm or 54 mm,
respectively. Host systems supporting the ExpressCard module can support either the ExpressCard|34 or
ExpressCard|54 or both.
ExpressCard POWER REQUIREMENTS
Regardless of which ExpressCard module is used, the power requirements as defined in the ExpressCard
Standard apply to both on an individual slot basis. The host system is required to supply 3.3 V, 1.5 V, and AUX
to each of the ExpressCard slots. However, the voltage is only applied after an ExpressCard is inserted into the
slot.
The ExpressCard connector has two pins, CPPE and CPUSB, that are used to signal the host when a card is
inserted. If the ExpressCard module itself connects the CPPE to ground, the logic low level on that signal
indicates to the host that a card supporting PCI Express has been inserted. If CPUSB is connected to ground,
then the ExpressCard module supports the USB interface. If both PCI Express and USB are supported by the
ExpressCard module, then both signals, CPPE and CPUSB, must be connected to ground.
In addition to the Card Present signals (CPPE and CPUSB), the host system determines when to apply power to
the ExpressCard module based on the state of the system. The state of the system is defined by the state of the
3.3 V, 1.5 V, and AUX input voltage rails. For the sake of simplicity, the 3.3-V and 1.5-V rails are defined as the
primary voltage rails as oppose to the auxiliary voltage rail, AUX.
ExpressCard POWER SWITCH OPERATION
The ExpressCard power switch resides on the host, and its main function is to control when to send power to the
ExpressCard slot. The ExpressCard power switch makes decisions based on the Card Present inputs and on the
state of the host system as defined by the primary and auxiliary voltage rails.
The following conditions define the operation of the host power controller:
1. When both primary power and auxiliary power at the input of the ExpressCard power switch are off, then all
power to the ExpressCard connector is off regardless of whether a card is present.
2. When both primary power and auxiliary power at the input of the ExpressCard power switch are on, then
power is only applied to the ExpressCard after the ExpressCard power switch detects that a card is present.
3. When primary power (either +3.3 V or +1.5 V) at the input of the ExpressCard power switch is off and
auxiliary power at the input of the ExpressCard power switch is on, then the ExpressCard power switch
behaves in the following manner:
a. If neither of the Card Present inputs is detected (no card inserted), then no power is applied to the
ExpressCard slot.
b. If the card is inserted after the system has entered this power state, then no power is applied to the
ExpressCard slot.
c. If the card is inserted prior to the removal of the primary power (either +3.3 V or +1.5 V or both) at the
input of the ExpressCard power switch, then only the primary power (both +3.3 V and +1.5 V) is removed
and the auxiliary power is sent to the ExpressCard slot.
Figure 18 through Figure 23 illustrate the timing relationships between power/logic inputs and outputs of
ExpressCard.
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APPLICATION INFORMATION (continued)
EXPRESS CARD TIMING DIAGRAMS
Host Power
(AUXIN, 3.3VIN,
and 1.5VIN)
SYSRST
CPxx
a
Card Power
(AUXIN, 3.3VOUT,
and 1.5VOUT)
RCLKEN
b
PERST
Tpd
a
Units
Min
Max
System Dependent
100
System Dependent
ms
b
REFCLK
c
System Dependent
d
ms
ms
ms
e
f
100
4
g
c
d
20
10
g
e
f
Figure 18. Timing Signals - Card Present Before Host Power Is On
Host Power
(AUXIN, 3.3VIN,
and 1.5VIN)
SYSRST
CPxx
Card Power
(AUXIN, 3.3VOUT,
and 1.5VOUT)
RCLKEN
a
PERST
Tpd
a
Units
ms
Min
Max
100
10
b
ms
REFCLK
System Dependent
c
System Dependent
d
e
b
c
d
20
4
ms
e
Figure 19. Timing Signals - Host Power Is On Prior to Card Insertion
20
TPS2231
TPS2236
www.ti.com
SLVS536B–JULY 2004–REVISED JANUARY 2005
APPLICATION INFORMATION (continued)
Host Power
(AUXIN)
Host Power
(3.3VIN and 1.5VIN)
SYSRST
CPxx
Card Power
(AUXIN, 3.3VOUT,
and 1.5VOUT)
RCLKEN
PERST
REFCLK
(Either Tri-Stated or Off)
Note: Once 3.3 V and 1.5 V are applied, the power switch follows the power-up sequence of Figure 18 or Figure 19.
Figure 20. Timing Signals - Host System In Standby Prior to Card Insertion
Host Power
(AUXIN, 3.3VIN, and 1.5VIN)
c
SYSRST
CPxx
Card Power
(AUXOUT, 3.3VOUT, and 1.5VOUT)
d
RCLKEN
PERST
a
e
Tpd
a
Units
ns
Min
Max
500
b
System Dependent
System Dependent
Load Dependent
500
REFCLK
c
d
e
a
ns
Figure 21. Timing Signals - Host-Controlled Power Down
21
TPS2231
TPS2236
www.ti.com
SLVS536B–JULY 2004–REVISED JANUARY 2005
APPLICATION INFORMATION (continued)
Host Power
e
(AUXIN, 3.3VIN, and 1.5VIN)
SHDN
CPxx
f
Card Power
(AUXOUT, 3.3VOUT, and 1.5VOUT)
RCLKEN
a
d
Tpd
Units
Min
Max
PERST
a
b
c
d
e
f
Load Dependent
System Dependent
500
f
c
ns
ns
REFCLK
500
System Dependent
System Dependent
Figure 22. Timing Signals - Controlled Power Down When SHDN Asserted
Host Power
(AUXIN, 3.3VIN, and 1.5VIN)
SYSRST
CPxx
Card Power
a
(AUXOUT, 3.3VOUT, and 1.5VOUT)
RCLKEN
d
Tpd
a
Min
Max
Units
ns
PERST
Load Dependent
b
b
c
d
500
System Dependent
500
REFCLK
ns
c
Figure 23. Timing Signals - Suprise Card Removal
22
PACKAGE OPTION ADDENDUM
www.ti.com
30-Mar-2005
PACKAGING INFORMATION
Orderable Device
TPS2231PW
Status (1)
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
TSSOP
PW
20
60 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TPS2231PWG4
TSSOP
PW
20
60 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TPS2231PWP
TPS2231PWPR
TPS2231PWPRG4
ACTIVE
ACTIVE
ACTIVE
HTSSOP
HTSSOP
HTSSOP
PWP
PWP
PWP
24
24
24
60
TBD
TBD
CU NIPDAU Level-1-220C-UNLIM
CU NIPDAU Level-1-220C-UNLIM
2000
2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
TPS2231PWR
TPS2236DAP
PREVIEW
ACTIVE
ACTIVE
ACTIVE
ACTIVE
TSSOP
HTSSOP
HTSSOP
HTSSOP
HTSSOP
PW
DAP
DAP
DAP
DAP
20
32
32
32
32
Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
46 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
TPS2236DAPG4
TPS2236DAPR
TPS2236DAPRG4
46 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan
-
The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS
&
no Sb/Br)
-
please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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Addendum-Page 1
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