TPS2310IPWG4 [TI]
DUAL HOT-SWAP POWER CONTROLLERS WITH INTERDEPENDENT CIRCUIT BREAKER AND POWER-GOOD REPORTING;
| 型号： | TPS2310IPWG4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | DUAL HOT-SWAP POWER CONTROLLERS WITH INTERDEPENDENT CIRCUIT BREAKER AND POWER-GOOD REPORTING 功率控制 光电二极管 |
| 文件： | 总22页 (文件大小：423K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPS2310, TPS2311
DUAL HOT SWAP POWER CONTROLLER WITH INTERDEPENDENT
CIRCUIT BREAKER AND POWER-GOOD REPORTING
SLVS275B – FEBRUARY 2000 – REVISED APRIL 2000
PW PACKAGE
(TOP VIEW)
features
Dual-Channel High-Side MOSFET Drivers
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
GATE1
GATE2
DGND
TIMER
VREG
DISCH1
DISCH2
ENABLE
PWRGD1
FAULT
ISET1
ISET2
PWRGD2
IN2
IN1: 3 V to 13 V; IN2: 3 V to 5.5 V
Inrush Current Limiting With dv/dt Control
Circuit-Breaker Control With Programmable
Current Limit and Transient Timer
VSENSE2
VSENSE1
AGND
ISENSE2
ISENSE1
Power-Good Reporting With Transient
Filter
CMOS- and TTL-Compatible Enable Input
Low, 5-µA Standby Supply Current . . . Max
Available in 20-Pin TSSOP Package
IN1
NOTE: Terminal 18 is active high on TPS2311.
–40°C to 85°C Ambient Temperature Range
Electrostatic Discharge Protection
typical application
V
O1
applications
+
V1
3 V – 13 V
Hot-Swap/Plug/Dock Power Management
Hot-Plug PCI, Device Bay
DISCH1
IN1
ISET1
GATE1
ISENSE1
VSENSE1
VREG
Electronic Circuit Breaker
AGND
DGND
TPS2310
PWRGD1
description
FAULT
TIMER
The TPS2310 and TPS2311 are dual-channel
hot-swap controllers that use external N-channel
MOSFETs as high-side switches in power
applications. Features of these devices, such as
overcurrent protection (OCP), inrush current
control, output-power status reporting, and
separation of load transients from actual load
increases, are critical requirements for hot-swap
applications.
ENABLE
PWRGD2
VSENSE2
GATE2
IN2
ISET2
ISENSE2
DISCH2
V
O2
+
V2
3 V – 5.5 V
The TPS2310/11 devices incorporate undervoltage lockout (UVLO) and power-good (PG) reporting to ensure
the device is off at start-up and confirm the status of the output voltage rails during operation. Each internal
charge pump, capable of driving multiple MOSFETs, provides enough gate-drive voltage to fully enhance the
N-channel MOSFETs. The charge pumps control both the rise times and fall times (dv/dt) of the MOSFETs,
reducing power transients during power up/down. The circuit-breaker functionality combines the ability to sense
overcurrentconditionswithatimerfunction;thisallowsdesignssuchasDSPs, thatmayhavehighpeakcurrents
during power-state transitions, to disregard transients for a programmable period.
AVAILABLE OPTIONS
TSSOP PACKAGES (PW, PWR)
PIN
COUNT
T
A
HOT-SWAP CONTROLLER DESCRIPTION
ENABLE
ENABLE
Dual-channel with independent OCP and adjustable PG
Dual-channel with interdependent OCP and adjustable PG
Dual-channel with independent OCP
20
20
16
14
TPS2300IPW
TPS2310IPW
TPS2320IPW
TPS2330IPW
TPS2301IPW
TPS2311IPW
TPS2321IPW
TPS2331IPW
–40°C to 85°C
Single-channel with OCP and adjustable PG
†
The packages are available left-end taped and reeled (indicated by the R suffix on the device type; e.g., TPS2311IPWR).
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2000, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS2310, TPS2311
DUAL HOT SWAP POWER CONTROLLER WITH INTERDEPENDENT
CIRCUIT BREAKER AND POWER-GOOD REPORTING
SLVS275B – FEBRUARY 2000 – REVISED APRIL 2000
functional block diagram
IN1
PREREG
ISET1
ISENSE1 GATE1
Clamp
DISCH1
VREG
dv/dt Rate
Protection
Charge
Pump
Circuit
Breaker
50 µA
Pulldown FET
Circuit Breaker
UVLO and
Power-Up
VSENSE1
PWRGD1
AGND
DGND
75 µA
20-µs Deglitch
FAULT
Logic
ENABLE
50-µs Deglitch
TIMER
Second Channel
DISCH2
PWRGD2
VSENSE2
IN2
ISET2
ISENSE2 GATE2
Terminal Functions
TERMINAL
NAME
I/O
DESCRIPTION
NO.
8
AGND
DGND
I
I
Analog ground, connects to DGND as close as possible
Digital ground
3
DISCH1
DISCH2
20
19
18
16
1
O
O
I
Discharge transistor 1
Discharge transistor 2
ENABLE/ ENABLE
FAULT
Active low (TPS2310) or active high enable (TPS2311)
Overcurrent fault, open-drain output
Connects to gate of channel 1 high-side MOSFET
Connects to gate of channel 2 high-side MOSFET
Input voltage for channel 1
O
O
O
I
GATE1
GATE2
2
IN1
11
12
10
9
IN2
I
Input voltage for channel 2
ISENSE1
ISENSE2
ISET1
I
Current-sense input channel 1
I
Current-sense input channel 2
15
14
17
13
4
I
Adjusts circuit-breaker threshold with resistor connected to IN1
Adjusts circuit-breaker threshold with resistor connected to IN2
ISET2
I
PWRGD1
PWRGD2
TIMER
O
O
O
O
I
Open-drain output, asserted low when VSENSE1 voltage is less than reference.
Open-drain output, asserted low when VSENSE2 voltage is less than reference.
Adjusts circuit-breaker deglitch time
VREG
5
Connects to bypass capacitor, for stable operation
Power-good sense input channel 1
VSENSE1
VSENSE2
7
6
I
Power-good sense input channel 2
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS2310, TPS2311
DUAL HOT SWAP POWER CONTROLLER WITH INTERDEPENDENT
CIRCUIT BREAKER AND POWER-GOOD REPORTING
SLVS275B – FEBRUARY 2000 – REVISED APRIL 2000
detailed description
DISCH1, DISCH2 – DISCH1 and DISCH2 should be connected to the sources of the external N-channel
MOSFET transistors connected to GATE1 and GATE2, respectively. These pins discharge the loads when the
MOSFET transistors are disabled. They also serve as reference-voltage connections for internal gate
voltage-clamp circuitry.
ENABLE or ENABLE – ENABLE for TPS2310 is active low. ENABLE for TPS2311 is active high. When the
controller is enabled, both GATE1 and GATE2 voltages will power up to turn on the external MOSFETs. When
the ENABLE pin is pulled high for TPS2310 or the ENABLE pin is pulled low for TPS2311 for more than 50 µs,
the gate of the MOSFET is discharged at a controlled rate by a current source, and a transistor is enabled to
discharge the output bulk capacitance. In addition, the device turns on the internal regulator PREREG (see
VREG) when enabled and shuts down PREREG when disabled so that total supply current is less than 5 µA.
FAULT – FAULT is an open-drain overcurrent flag output. When an overcurrent condition in either channel is
sustained long enough to charge TIMER to 0.5 V, both channels channel latch off and pull this pin low.
GATE1, GATE2 – GATE1 and GATE2 connect to the gates of external N-channel MOSFET transistors. When
the device is enabled, internal charge-pump circuitry pulls these pins up by sourcing approximately 15 µA to
each. The turnon slew rates depend upon the capacitance present at the GATE1 and GATE2 terminals. If
desired, the turnon slew rates can be further reduced by connecting capacitors between these pins and ground.
These capacitors also reduce inrush current and protect the device from false overcurrent triggering during
powerup.The charge-pump circuitry will generate gate-to-source voltages of 9 V–12 V across the external
MOSFET transistors.
IN1, IN2 – IN1 and IN2 should be connected to the power sources driving the external N-channel MOSFET
transistors connected to GATE1 and GATE2, respectively. The TPS2310/TPS2311 draws its operating current
from IN1, and both channels will remain disabled until the IN1 power supply has been established. The IN1
channel has been constructed to support 3-V, 5-V, or 12-V operation, while the IN2 channel has been
constructed to support 3-V or 5-V operation
ISENSE1, ISENSE2, ISET1, ISET2 – ISENSE1 and ISENSE2, in combination with ISET1 and ISET2,
implement overcurrent sensing for GATE1 and GATE2. ISET1 and ISET2 set the magnitude of the current that
generates an overcurrent fault, through external resistors connected to ISET1 and ISET2. An internal current
source draws 50 µA from ISET1 and ISET2. With a sense resistor from IN1 to ISENSE1 or from IN2 to ISENSE2,
which is also connected to the drains of external MOSFETs, the voltage on the sense resistor reflects the load
current. An overcurrent condition is assumed to exist if ISENSE1 is pulled below ISET1 or if ISENSE2 is pulled
below ISET2.
PWRGD1, PWRGD2 – PWRGD1 and PWRGD2 signal the presence of undervoltage conditions on VSENSE1
and VSENSE2, respectively. These pins are open-drain outputs and are pulled low during an undervoltage
condition. To minimize erronous PWRGDx responses from transients on the voltage rail, the voltage sense
circuit incorporates a 20-µs deglitch filter. When VSENSEx is lower than the reference voltage (about 1.23 V),
PWRGDx will be active low to indicate an undervoltage condition on the power-rail voltage.
TIMER – A capacitor on TIMER sets the time during which the power switch can be in overcurrent before turning
off. When the overcurrent protection circuits sense an excessive current, a current source is enabled which
charges the capacitor on TIMER. Once the voltage on TIMER reaches approximately 0.5 V, the circuit-breaker
latch is set and the power switch is latched off. Power must be recycled or the ENABLE pin must be toggled
to restart the controller. In high-power or high-temperature applications, a minimum 50-pF capacitor is strongly
recommended from TIMER to ground, to prevent any false triggering.
VREG – The VREG pin is the output of an internal low-dropout voltage regulator. This regulator draws current
from IN1. A 0.1-µF ceramic capacitor should be connected between VREG and ground. VREG can be
connected to IN1, IN2, or to a separated power supply through a low-resistance resistor. However, the voltage
on VREG must be less than 5.5 V.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS2310, TPS2311
DUAL HOT SWAP POWER CONTROLLER WITH INTERDEPENDENT
CIRCUIT BREAKER AND POWER-GOOD REPORTING
SLVS275B – FEBRUARY 2000 – REVISED APRIL 2000
detailed description (continued)
VSENSE1, VSENSE2 – VSENSE1 and VSENSE2 can be used to detect undervoltage conditions on external
circuitry. If VSENSE1 senses a voltage below approximately 1.23 V, PWRGD1 is pulled low. Similarly, a voltage
less than 1.23 V on VSENSE2 causes PWRGD2 to be pulled low.
†
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
Input voltage range: V
, V
, V
, V
, V
,
I(IN1) I(ISENSE1) I(VSENSE1) I(VSENSE2) I(ISET1)
V
V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 15 V
I(ENABLE)
, V
, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 7 V
I(IN2) I(ISENSE2) I(ISET2)
Output voltage range:
V
V
V
V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 30 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 22V
O(GATE1)
O(GATE2)
, V
, V
, V
, V
,
O(DISCH1) O(PWRGD1) O(PWRGD2) O(FAULT) O(VREG)
, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 15V
O(DISCH2) O(TIMER)
Sink current range:
I
I
, I
, I
, I
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 mA to 100 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 mA to 10 mA
GATE1 GATE2 DISCH1 DISCH2
PWRGD1 PWRGD2 TIMER FAULT
, I
, I
, I
Operating virtual junction temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 100°C
Storage temperature range, T
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
J
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltages are respect to DGND.
DISSIPATION RATING TABLE
DERATING FACTOR
T
≤ 25°C
T
A
= 70°C
T = 85°C
A
A
PACKAGE
POWER RATING
ABOVE T = 25°C
POWER RATING POWER RATING
A
PW-20
1015 mW
13.55 mW/°C
406 mW
203 mW
recommended operating conditions
MIN NOM
MAX
13
UNIT
V
, V
, V
I(IN2) I(ISENSE2) I(ISET2)
, V
, V
3
3
I(IN1) I(ISENSE1) I(VSENSE1) I(VSENSE2) I(ISET1)
Input voltage, V
V
I
V
, V , V
5.5
VREG voltage, V
, when VREG is directly connected to IN1
O(VREG)
2.95
–40
5.5
V
Operating virtual junction temperature, T
100
°C
J
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS2310, TPS2311
DUAL HOT SWAP POWER CONTROLLER WITH INTERDEPENDENT
CIRCUIT BREAKER AND POWER-GOOD REPORTING
SLVS275B – FEBRUARY 2000 – REVISED APRIL 2000
electrical characteristics over recommended operating temperature range (–40°C < T < 85°C),
A
3 V ≤ V
≤13 V, 3 V ≤ V
≤ 5.5 V (unless otherwise noted)
I(IN1)
I(IN2)
general
PARAMETER
TEST CONDITIONS
MIN
TYP
0.5
75
MAX
1
UNIT
mA
I
I
Input current, IN1
Input current, IN2
V
V
V
V
= 5 V (TPS2311),
= 0 V (TPS2310)
= 0 V (TPS2311)
= 5 V (TPS2310)
I(IN1)
I(ENABLE)
I(ENABLE)
I(ENABLE)
I(ENABLE)
200
µA
I(IN2)
Standby current (sum of currents into IN1, IN2,
ISENSE1, ISENSE2, ISET1, and ISET2)
I
5
µA
I(stby)
GATE1
PARAMETER
TEST CONDITIONS
MIN
9
TYP
11.5
14.5
21
MAX
UNIT
V
V
V
V
I(IN1)
V
I(IN1)
V
I(IN1)
= 3 V
G(GATE1_3V)
I
= 500 nA,
I(GATE1)
DISCH1 open
Gate voltage
= 4.5 V
= 10.8 V
10.5
16.8
V
G(GATE1_4.5V)
G(GATE1_10.8V)
Clamping voltage, GATE1
to DISCH1
V
9
10
50
10
14
75
12
20
V
C(GATE1)
S(GATE1)
3 V ≤ V
≤ 13.2 V, 3 V ≤ V
≤ 5.5 V,
≤ 5.5 V,
I(IN1)
I(IN1)
O(VREG)
O(VREG)
I
Source current, GATE1
Sink current, GATE1
µA
µA
V
= V
+ 6 V
I(GATE1)
I(IN1)
3 V ≤ V
≤ 13.2 V, 3 V ≤ V
100
V
= V
I(GATE1)
I(IN1)
V
I(IN1)
V
I(IN1)
V
I(IN1)
V
I(IN1)
V
I(IN1)
V
I(IN1)
= 3 V
0.5
0.6
1
t
t
Rise time, GATE1
Fall time, GATE1
C
to GND = 1 nF (see Note 2)
to GND = 1 nF (see Note 2)
= 4.5 V
= 10.8 V
= 3 V
ms
ms
r(GATE1)
g
g
0.1
0.12
0.2
C
= 4.5 V
= 10.8 V
f(GATE)
GATE2
PARAMETER
TEST CONDITIONS
MIN
9
TYP
11.7
14.7
MAX
UNIT
V
V
V
V
= 3 V
G(GATE2_3V)
I(IN2)
Gate voltage
I
= 500 nA, DISCH2 open
V
I(GATE2)
= 4.5 V
10.5
G(GATE2_4.5V)
C(GATE2)
I(IN2)
Clamping voltage,
GATE2 to DISCH2
V
9
10
50
10
14
75
12
20
V
Source current,
GATE2
3 V ≤ V
V
≤ 5.5 V, 3 V ≤ V
≤ 5.5 V,
≤ 5.5 V,
I(IN2)
I(IN2)
O(VREG)
O(VREG)
I
µA
µA
S(GATE2)
= V
+ 6 V
I(GATE2)
I(IN2)
3 V ≤ V
V
≤ 5.5 V, 3 V ≤ V
Sink current, GATE2
Rise time, GATE2
Fall time, GATE2
100
= V
I(GATE2)
I(IN2)
V
I(IN2)
V
I(IN2)
V
I(IN2)
V
I(IN2)
= 3 V
0.5
0.6
C
to GND = 1 nF
g
t
t
ms
ms
r(GATE2)
(see Note 2)
= 4.5 V
= 3 V
V
= 3 V
O(VREG)
0.1
C
to GND = 1 nF
g
f(GATE2)
(see Note 2)
= 4.5 V
0.12
NOTE 2: Specified, but not production tested.
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS2310, TPS2311
DUAL HOT SWAP POWER CONTROLLER WITH INTERDEPENDENT
CIRCUIT BREAKER AND POWER-GOOD REPORTING
SLVS275B – FEBRUARY 2000 – REVISED APRIL 2000
electrical characteristics over recommended operating temperature range (–40°C < T < 85°C),
A
3 V ≤ V
≤13 V, 3 V ≤ V
≤ 5.5 V ( unless otherwise noted) (continued)
I(IN1)
I(IN2)
TIMER
PARAMETER
TEST CONDITIONS
MIN
TYP
0.5
50
MAX
0.6
UNIT
V
V
Threshold voltage, TIMER
Charge current, TIMER
Discharge current, TIMER
0.4
35
1
OT(TIMER)
V
V
= 0 V
= 1 V
65
µA
I(TIMER)
2.5
mA
I(TIMER)
circuit breaker
PARAMETER
Undervoltage voltage, circuit breaker
Input bias current, I
TEST CONDITIONS
MIN
TYP
50
MAX
60
UNIT
mV
V
R
= 1 kΩ
40
IT(CB)
ISETx
I
0.1
5
µA
IB(ISENSEx)
SENSEx
V
V
= 4 V
= 1 V
400
25
800
150
O(GATEx)
Discharge current, GATEx
mA
O(GATEx)
Propagation (delay) time, comparator inputs to
gate output
C
= 50 pF,
10 mV overdrive,
C = 50 pF
O(timer)
g
t
1.3
µs
pd(CB)
(50% to 10%)
ENABLE, active low (TPS2310)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
V
V
V
High-level input voltage, ENABLE
Low-level input voltage, ENABLE
2
IH(ENABLE)
0.8
V
IL(ENABLE)
Input pullup resistance,
ENABLE
R
t
See Note 3
100
200
60
300
kΩ
µs
µs
I(ENABLE)
V
increasingabovestopthreshold;100
I(ENABLE)
ns rise time, 20 mV overdrive (see Note 2)
Turnoff delay time, ENABLE
Turnon delay time, ENABLE
d_off(ENABLE)
V
decreasing below start threshold;
I(ENABLE)
t
125
d_on(ENABLE)
100 ns fall time, 20 mV overdrive (see Note 2)
NOTES: 2. Specified, but not production tested.
3. Test I of ENABLE at V
1 V
= 1 V and 0 V, then R =
I(ENABLE)
O
I(ENABLE)
I
I
0V
1V
O_
O_
ENABLE, active high (TPS2311)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
V
V
V
High-level input voltage, ENABLE
2
IH(ENABLE)
Low-level input voltage, ENABLE
0.7
V
IL(ENABLE)
Input pulldown resistance,
ENABLE
R
100
150
85
300
kΩ
µs
µs
I(ENABLE)
V
increasing above start threshold;
I(ENABLE)
100 ns rise time, 20 mV overdrive (see Note 2)
t
t
Turnon delay time, ENABLE
Turnoff delay time, ENABLE
d_on(ENABLE)
V
decreasing below stop threshold;
I(ENABLE)
100
d_off(ENABLE)
100 ns fall time, 20 mV overdrive (see Note 2)
NOTE 2: Specified, but not production tested.
PREREG
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
5.5
UNIT
V
VREG
PREREG output voltage
PREREG dropout voltage
4.5 ≤ V
≤ 13 V
3.5
4.1
I(IN1)
= 3 V
Vdrop_PREREG
V
I(IN1)
0.1
V
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS2310, TPS2311
DUAL HOT SWAP POWER CONTROLLER WITH INTERDEPENDENT
CIRCUIT BREAKER AND POWER-GOOD REPORTING
SLVS275B – FEBRUARY 2000 – REVISED APRIL 2000
electrical characteristics over recommended operating temperature range (–40°C < T < 85°C),
A
3 V ≤ V
≤13 V, 3 V ≤ V
≤ 5.5 V (unless otherwise noted) (continued)
I(IN1)
I(IN2)
VREG UVLO
PARAMETER
TEST CONDITIONS
MIN
TYP
2.85
2.78
75
MAX
UNIT
V
V
V
V
Output threshold voltage, start
Output threshold voltage, stop
Hysteresis
2.75
2.65
50
2.95
OT(UVLOstart)
OT(UVLOstop)
hys(UVLO)
V
mV
mA
UVLO sink current, GATEx
V
V
= 2 V
10
I(GATEx)
PWRGD1 and PWRGD2
PARAMETER
TEST CONDITIONS
decreasing
I(VSENSEx)
MIN
TYP
MAX
UNIT
V
V
Trip threshold, VSENSEx
1.2 1.225
1.25
V
IT(ISENSEx)
Hysteresis voltage, power-good
comparator
20
30
40
mV
hys
V
V
Output saturation voltage PWRGDx
I
I
= 2 mA
0.2
0.4
1
V
V
O(sat)(PWRGDx)
O
Minimum V
O(VREG)
for valid power-good
= 100 µA, V
= 1 V
O(PWRGDx)
O(VREGmin)
O
I
I
Input bias current, power-good comparator
Leakage current, PWRGDx
V
V
V
= 5.5 V
1
µA
µA
IB
I(VSENSEx)
O(PWRGDx)
I(VSENSEx)
= 13 V
1
lkg(PWRGDx)
increasing,
t
dr
Delay time, rising edge, PWRGDx
Delay time, falling edge, PWRGDx
Overdrive = 20 mV, t = 100 ns,
25
2
µs
µs
r
See Note 2
V
decreasing,
I(VSENSEx)
t
df
Overdrive = 20 mV, t = 100 ns,
r
See Note 2
NOTE 2: Specified, but not production tested.
FAULT output
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
0.4
1
UNIT
V
V
Output saturation voltage, FAULT
Leakage current, FAULT
I
= 2 mA
O(sat)(FAULT)
O
I
V
= 13 V
µA
lkg(FAULT)
O(FAULT)
DISCH1 and DISCH2
PARAMETER
TEST CONDITIONS
= 1.5 V, V = 5 V
I(VIN1)
MIN
5
TYP
MAX
UNIT
mA
V
I
Discharge current, DISCHx
V
10
DISCH
I(DISCHx)
V
Discharge on high-level input voltage
Discharge on low-level input voltage
2
IH(DISCH)
IL(DISCH)
V
1
V
7
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DUAL HOT SWAP POWER CONTROLLER WITH INTERDEPENDENT
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SLVS275B – FEBRUARY 2000 – REVISED APRIL 2000
PARAMETER MEASUREMENT INFORMATION
Load 12 Ω
Load 12 Ω
V
I(ENABLE)
5 V/div
V
I(ENABLE)
5 V/div
V
O(GATE1)
10 V/div
V
O(DISCH1)
5 V/div
V
O(GATE1)
10 V/div
V
O(DISCH1)
5 V/div
t – Time – 10 ms/div
t – Time – 10 ms/div
Figure 1. Turnon Voltage Transition of
Channel 1
Figure 2. Turnoff Voltage Transition of
Channel 1
Load 5 Ω
Load 5 Ω
V
I(ENABLE)
5 V/div
V
I(ENABLE)
5 V/div
V
O(GATE2)
10 V/div
V
O(GATE2)
10 V/div
V
O(DISCH2)
5 V/div
V
O(DISCH2)
5 V/div
t – Time – 10 ms/div
t – Time – 10 ms/div
Figure 3. Turnon Voltage Transition of
Channel 2
Figure 4. Turnoff Voltage Transition of
Channel 2
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PARAMETER MEASUREMENT INFORMATION
No Capacitor
on Timer
V
V
I(ENABLE)
5 V/div
I(ENABLE)
5 V/div
No Capacitor
on Timer
V
O(GATE1)
10 V/div
V
O(GATE1)
10 V/div
V
O(FAULT)
10 V/div
V
O(FAULT)
10 V/div
I
I
O(OUT1)
2 A/div
O(OUT1)
2 A/div
t – Time – 1 ms/div
t – Time – 5 ms/div
Figure 6. Channel 1 Overcurrent Response: an
Overcurrent Load Plugged Into the Enabled Board
Figure 5. Channel 1 Overcurrent Response:
Enabled Into Overcurrent Load
No Capacitor
on Timer
No Capacitor
on Timer
V
I(ENABLE)
5 V/div
V
I(ENABLE)
5 V/div
V
O(GATE2)
10 V/div
V
O(GATE2)
10 V/div
V
V
O(FAULT)
10 V/div
O(FAULT)
10 V/div
I
O(OUT2)
2 A/div
I
O(OUT2)
2 A/div
t – Time – 2 ms/div
t – Time – 0.5 ms/div
Figure 7. Channel 2 Overcurrent Response:
Enabled Into Overcurrent Load
Figure 8. Channel 2 Overcurrent Response: an
Overcurrent Load Plugged Into the Enabled Board
9
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PARAMETER MEASUREMENT INFORMATION
No Capacitor
on Timer
No Capacitor
on Timer
V
V
I(ENABLE)
5 V/div
I(ENABLE)
5 V/div
V
V
O(GATE1)
10 V/div
O(GATE2)
5 V/div
V
V
O(FAULT)
10 V/div
O(FAULT)
10 V/div
I
I
O(IN1)
O(IN2)
2 A/div
2 A/div
t – Time – 1 ms/div
t – Time – 1 ms/div
Figure 10. Channel 2 – Enabled Into Short Circuit
Figure 9. Channel 1 – Enabled Into Short
Circuit
No Capacitor
on Timer
V
No Capacitor
on Timer
I(IN1)
10 V/div
V
V
O(GATE1)
10 V/div
I(IN1)
10 V/div
V
O(GATE1)
10 V/div
V
I
O(OUT1)
10 V/div
V
I
O(OUT1)
10 V/div
O(OUT1)
1 A/div
O(OUT1)
1 A/div
t – Time – 5 ms/div
t – Time – 1 ms/div
Figure 11. Channel 1 – Hot Plug
Figure 12. Channel 1 – Hot Removal
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PARAMETER MEASUREMENT INFORMATION
No Capacitor
on Timer
V
I(IN2)
5 V/div
V
O(GATE2)
10 V/div
V
I
O(OUT2)
5 V/div
O(OUT2)
1 A/div
t – Time – 5 ms/div
Figure 13. Channel 2 – Hot Plug
No Capacitor
on Timer
V
I(IN2)
5 V/div
V
O(GATE2)
10 V/div
V
I
O(OUT2)
5 V/div
O(OUT2)
1 A/div
t – Time – 1 ms/div
Figure 14. Channel 2 – Hot Removal
11
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TYPICAL CHARACTERISTICS
SUPPLY CURRENT (ENABLED)
SUPPLY CURRENT (ENABLED)
vs
vs
VOLTAGE
VOLTAGE
52
51
50
49
71.5
71
IN1 = 13 v
IN2 = 5.5 V
T
= 85°C
A
T
= 0°C
A
T
= –40°C
A
T
A
= 25°C
70.5
70
T
A
= 25°C
48
47
46
45
T
= 85°C
A
T
A
= 0°C
69.5
69
T
A
= –40°C
68.5
68
44
43
4
5
6
7
8
9
10 11 12 13 14
2.5
3
3.5
V
4
4.5
5
5.5
6
V
– Input Voltage 1 – V
– Input Voltage 2 – V
I1
I2
Figure 15
Figure 16
SUPPLY CURRENT (DISABLED)
SUPPLY CURRENT (DISABLED)
vs
vs
VOLTAGE
VOLTAGE
15
23
21
19
17
15
T
= 85°C
A
IN2 = 5.5 V
IN1 = 13 V
14
13
12
11
10
9
T
A
= 25°C
T
A
= 85°C
T
= –40°C
A
T
A
= –40°C
T
A
= 0°C
13
11
9
T
A
= 0°C
8
7
T
= 25°C
A
7
5
4
5
6
7
8
9
10 11 12 13 14
2.5
3
3.5
4
4.5
5
5.5
6
V
I1
– Input Voltage 1 – V
V
I2
– Input Voltage 2 – V
Figure 17
Figure 18
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TYPICAL CHARACTERISTICS
GATE1 VOLTAGE
GATE1 VOLTAGE RISE TIME
vs
GATE1 LOAD CAPACITANCE
vs
INPUT VOLTAGE
22
20
18
18
15
12
C
= 1000 pF
L(GATE1)
IN1 = 12 V
T
= 85°C
A
T
= 25°C
A
T
= 25°C
A
T
A
= 0°C
T
A
= –40°C
16
14
9
6
12
10
3
0
2
3
4
5
6
7
8
9
10 11 12
0
3
6
9
12
V
I1
– Input Voltage1 – V
C
– GATE1 Load Capacitance – nF
L(GATE1)
Figure 19
Figure 20
GATE1 VOLTAGE FALL TIME
vs
GATE1 LOAD CAPACITANCE
GATE1 OUTPUT CURRENT
vs
GATE1 VOLTAGE
4
3
2
15
14.5
14
IN1 = 12 V
= 25°C
T
A
T
A
= –40°C
T
= 85°C
A
13.5
13
T
A
= 25°C
T
= 0°C
A
12.5
12
1
0
IN1 = 13 V
11.5
11
0
3
6
9
12
14 15 16 17 18 19 20 21 22 23 24
V – GATE1 Voltage
C
– GATE1 Load Capacitance – nF
L(GATE1)
Figure 21
Figure 22
13
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SLVS275B – FEBRUARY 2000 – REVISED APRIL 2000
TYPICAL CHARACTERISTICS
CIRCUIT BREAKER RESPONSE
LOAD VOLTAGE 1 DISCHARGE TIME
vs
vs
TIMER CAPACITANCE
LOAD CAPACITANCE
12
9
320
280
240
200
160
120
80
IN1 = 12 V
IN1 = 12 V
T
A
= 25°C
I
T
= 0 A
= 25°C
O1
A
6
3
0
40
0
0
0.2
0.4
0.6
0.8
1
0
100
200
300
400
500
C
– TIMER Capacitance – nF
(timer)
C
– Load Capacitance – µF
L
Figure 23
Figure 24
UVLO START AND STOP THRESHOLDS
PWRGDx THRESHOLD
vs
vs
TEMPERATURE
TEMPERATURE
2.9
2.88
2.86
2.84
2.82
2.8
1.27
1.26
Up
Start
Stop
1.25
1.24
1.23
1.22
Down
2.78
2.76
2.74
1.21
1.20
2.72
2.7
–45–35–25–15 –5
5
15 25 35 45 55 65 75 85 95
–45–35–25 –15 –5 5 15 25 35 45 55 65 75 85 95
T
A
– Temperature – °C
T
A
– Temperature – °C
Figure 26
Figure 25
14
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SLVS275B – FEBRUARY 2000 – REVISED APRIL 2000
APPLICATION INFORMATION
typical application diagram
This diagram shows a typical dual hot-swap application. The pullup resistors at PG1, PG2 and Fault should be
relatively large (e.g. 100 kΩ) to reduce power loss unless they are required to drive a large load.
System
3 V 12 V IN1
Board
R
SENSE1
V
O1
1 µF 10 µF
+
R
R
VSENSE1_TOP
R
ISET1
VSENSE1_BOTTOM
0.1 µF
V
IN1 ISET1 ISENSE1 GATE1 DISCH1 VSENSE1
reg
ENABLE
ENABLE
DGND
FAULT
PWRGD1
PWRGD2
FAULT
TPS2311
PWRGD1
PWRGD2
AGND
TIMER
IN2 ISET2 ISENSE2 GATE2 DISCH2 VSENSE2
V
V
or
R
O1
ISET2
O2
V
O2
3 V 5 V IN2
1 µF 10 µF
+
R
SENSE2
R
R
VSENSE2_TOP
VSENSE2_BOTTOM
Figure 27. Typical Dual Hot-Swap Application
input capacitor
A 0.1-µF ceramic capacitor in parallel with a 1-µF ceramic capacitor should be placed on the input power
terminals near the connector on the hot-plug board to help stabilize the voltage rails on the cards. The
TPS2310/11 does not need to be mounted near the connector or these input capacitors. For applications with
more severe power environments, a 2.2-µF or higher ceramic capacitor is recommended near the input
terminals of the hot-plug board. A bypass capacitor for IN1 and for IN2 should be placed close to the device.
output capacitor
A 0.1-µF ceramic capacitor is recommended per load on the TPS2311; these capacitors should be placed close
to the external FETs and to TPS2310/11. A larger bulk capacitor is also recommended on the load. The value
of the bulk capacitor should be selected based on the power requirements and the transients generated by the
application.
external FET
To deliver power from the input sources to the loads, each channel needs an external N-channel MOSFET. A
few widely used MOSFETs are shown in Table 1. But many other MOSFETs in the market can also be used with
TPS23xx in hot-swap systems.
15
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APPLICATION INFORMATION
Table 1. Some Available N-Channel MOSFETs
CURRENT RANGE
PART NUMBER
DESCRIPTION
MANUFACTURER
(A)
IRF7601
N-channel, r
N-channel, r
= 0.035 Ω, 4.6 A, Micro-8
= 0.040 Ω, 4.6 A, Micro-8
International Rectifier
ON Semiconductor
International Rectifier
ON Semiconductor
International Rectifier
ON Semiconductor
International Rectifier
Vishay Dale
DS(on)
MTSF3N03HDR2
IRF7101
DS(on)
0 to 2
Dual N-channel, r
= 0.1 Ω, 2.3 A, SO-8
= 0.04 Ω, 5 A, SO-8
DS(on)
DS(on)
MMSF5N02HDR2
IRF7401
Dual N-channel, r
N-channel, r
N-channel, r
= 0.022 Ω, 7 A, SO-8
= 0.025 Ω, 5 A, SO-8
DS(on)
MMSF5N02HDR2
IRF7313
DS(on)
2 to 5
Dual N-channel, r
DS(on)
= 0.029 Ω, 5.2 A, SO-8
SI4410
N-channel, r
N-channel, r
N-channel, r
= 0.020 Ω, 8 A, SO-8
= 0.019 Ω, 29 A, d-Pak
= 0.045 Ω, 14 A, d-Pak
DS(on)
DS(on)
DS(on)
IRLR3103
International Rectifier
International Rectifier
5 to 10
IRLR2703
timer
For most applications, a minimum capacitance of 50 pF is recommended to prevent false triggering. This
capacitor should be connected between TIMER and ground. The presence of an overcurrent condition on either
channel of the TPS2310/11 causes a 50-µA current source to begin charging this capacitor. If the over-
current condition persists until the capacitor has been charged to approximately 0.5 V, the TPS2310/11 will latch
off all channels and will pull the FAULT pin low. The timer capacitor can be made as large as desired to provide
additional time delay before registering a fault condition.
output-voltage slew-rate control
When enabled, the TPS2310/11 controllers supply the gates of each external MOSFET transistor with a current
of approximately 15 µA. The slew rate of the MOSFET source voltage is thus limited by the gate-to-drain
capacitance C of the external MOSFET capacitor to a value approximating:
gd
15
C
A
dvs
dt
gd
If a slower slew rate is desired, an additional capacitance can be connected between the gate of the external
MOSFET and ground.
VREG capacitor
The internal voltage regulator connected to VREG requires an external capacitor to ensure stability. A 0.1-µF
or 0.22-µF ceramic capacitor is recommended.
16
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APPLICATION INFORMATION
gate drive circuitry
The TPS2310/11 includes four separate features associated with each gate-drive terminal:
A charging current of approximately 15 µA is applied to enable the external MOSFET transistor. This current
is generated by an internal charge pump that can develop a gate-to-source potential (referenced to DISCH1
or DISCH2) of 9 V–12 V. DISCH1 and DISCH2 must be connected to the respective external MOSFET
source terminals to ensure proper operation of this circuitry.
A discharge current of approximately 75 µA is applied to disable the external MOSFET transistor. Once the
transistor gate voltage has dropped below approximately 1.5 V, this current is disabled and the UVLO
discharge driver is enabled instead. This feature allows the part to enter a low-current shutdown mode while
ensuring that the gates of the external MOSFET transistors remain at a low voltage.
During a UVLO condition, the gates of both MOSFET transistors are pulled down by internal PMOS
transistors. ThesetransistorscontinuetooperateevenifIN1andIN2arebothat0V. Thiscircuitryalsohelps
hold the external MOSFET transistors off when power is suddenly applied to the system.
During an overcurrent fault condition, the external MOSFET transistor that exhibited an over-current
condition will be rapidly turned off by an internal pulldown circuit capable of pulling in excess of 400 mA (at
4 V) from the pin. Once the gate has been pulled below approximately 1.5 V, this driver is disengaged and
the UVLO driver is enabled instead. If any channel experiences an overcurrent condition, then both
channels will be turned off rapidly.
setting the current-limit circuit-breaker threshold
Using channel one as an example, the current sensing resistor R
and the current limit setting resistor
ISENSE1
R
determine the current limit of the channel, and can be calculated by the following equation:
ISET1
–6
R
50 10
ISET1
R
I
LMT1
ISENSE1
Typically R
the junction of R
is usually very small (0.001 Ω to 0.1 Ω). If the trace and solder-junction resistances between
ISENSE1
and ISENSE1 and the junction of R
and R
are greater than 10% of the
value used in the calculation
ISENSE1
ISENSE1
ISET1
R
value, then these resistance values should be added to the R
ISENSE1
ISENSE1
above.
The above information and calculation also apply to channel 2. Table 2 shows some of the current sense
resistors available in the market.
Table 2. Some Current Sense Resistors
CURRENT RANGE
PART NUMBER
DESCRIPTION
MANUFACTURER
(A)
0 to 1
1 to 2
2 to 4
4 to 6
6 to 8
8 to 10
WSL-1206, 0.05 1%
WSL-1206, 0.025 1%
WSL-1206, 0.015 1%
WSL-2010, 0.010 1%
WSL-2010, 0.007 1%
WSR-2, 0.005 1%
0.05 Ω, 0.25 W, 1% resistor
0.025 Ω, 0.25 W, 1% resistor
0.015 Ω, 0.25 W, 1% resistor
0.010 Ω, 0.5 W, 1% resistor
0.007 Ω, 0.5 W, 1% resistor
0.005 Ω, 0.5 W, 1% resistor
Vishay Dale
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APPLICATION INFORMATION
setting the power good threshold voltage
The two feedback resistors R
resistor divider setting the voltage at the VSENSEx pins. VSENSE1 voltage equals to
and R
connected between V and ground form a
VSENSEx_TOP
VSENSEx_BOT Ox
V
= V × R /(R + R
)
VSENSE1_BOT
I(SENSE1)
O
VSENSE1_BOT VSENSE1_TOP
Thisvoltageiscomparedtoaninternalvoltagereference(1.225V±2%)todeterminewhethertheoutputvoltage
level is within a specified tolerance. For example, given a nominal output voltage at V , and defining V
as the minimum required output voltage, then the feedback resistors are defined by:
O1
O1_min
V
1.225
O1_min
R
R
VSENSE1_TOP
VSENSE1_BOT
1.225
Start the process by selecting a large standard resistor value for R
to reduce power loss. Then
VSENSE1_BOT
R
than V
canbecalculatedbyinsertingalloftheknownvaluesintotheequationabove.WhenV islower
, PWRGD1 will be low as long as the controller is enabled.
VSENSE1_TOP
O1
O1_min
undervoltage lockout (UVLO)
The TPS2310/11 includes an undervoltage lockout (UVLO) feature that monitors the voltage present on the
VREG pin. This feature will disable both external MOSFETs if the voltage on VREG drops below 2.78 V
(nominal) and will re-enable normal operation when it rises above 2.85 V (nominal). Since VREG is fed from
IN1 through a low-dropout voltage regulator, the voltage on VREG will track the voltage on IN1 within 50 mV.
While the undervoltage lockout is engaged, both GATE1 and GATE2 are held low by internal PMOS pulldown
transistors, ensuringthattheexternalMOSFETtransistorsremainoffatalltimes, evenifallpowersupplieshave
fallen to 0 V.
single-channel operation
Some applications may require only a single external MOS transistor. Such applications should use GATE1 and
the associated circuitry (IN1, ISENSE1, ISET1, DISCH1). The IN2 pin should be grounded to disable the
circuitry associated with the GATE2 pin. The VSENSE2 and PWRGD2 circuitry is unaffected by disabling
GATE2, and may still be used if so desired.
power-up control
The TPS2310/11 includes a 500 µs (nominal) startup delay that ensures that internal circuitry has sufficient time
to start before the device begins turning on the external MOSFETs. This delay is triggered only upon the rapid
application of power to the circuit. If the power supply ramps up slowly, the undervoltage lockout circuitry will
provide adequate protection against undervoltage operation.
3-channel hot-swap application
Some applications require hot-swap control of up to three voltage rails, but may not explicitly require the sensing
of the status of the output power on all three of the voltage rails. One such application is device bay, where dv/dt
control of 3.3 V, 5 V, and 12 V is required. By using channel 2 to drive both the 3.3-V and 5-V power rails and
channel 1 to drive the 12-V power rail, as is shown below, TPS2310/11 can deliver three different voltages to
three loads while monitoring the status of two of the loads.
18
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APPLICATION INFORMATION
System
12 V IN1
Board
R
SENSE1
V
O1
1 µF 10 µF
+
R
R
VSENSE1_TOP
R
ISET1
VSENSE1_BOTTOM
0.1 µF
V
IN1 ISET1 ISENSE1 GATE1 DISCH1 VSENSE1
reg
ENABLE
ENABLE
DGND
FAULT
PWRGD1
PWRGD2
FAULT
TPS2311
PWRGD1
PWRGD2
AGND
TIMER
IN2 ISET2 ISENSE2 GATE2 DISCH2 VSENSE2
R
V
V
or
R
ISET2
O1
g1
O2
V
O2
3.3 V IN2
1 µF 10 µF
+
R
SENSE2
R
R
VSENSE2_TOP
R
g2
VSENSE2_BOTTOM
V
O3
5 V IN3
1 µF 10 µF
+
Figure 28. Three-Channel Application
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APPLICATION INFORMATION
Figure 29 shows ramp-up waveforms of the three output voltages.
V
O1
V
V
O3
O2
t – Time – 2.5 ms/div
Figure 29
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CIRCUIT BREAKER AND POWER-GOOD REPORTING
SLVS275B – FEBRUARY 2000 – REVISED APRIL 2000
MECHANICAL DATA
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
M
0,10
0,65
0,19
14
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
8
14
16
20
24
28
DIM
3,10
2,90
5,10
4,90
5,10
4,90
6,60
6,40
7,90
7,70
9,80
9,60
A MAX
A MIN
4040064/F 01/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
21
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