TPS2330ID [TI]

SINGLE HOT-SWAP POWER CONTROLLERS WITH CIRCUIT BREAKER AND POWER-GOOD REPORTING; 带断路器和电源良好报告单一热插拔电源控制器


型号：	TPS2330ID
厂家：	TEXAS INSTRUMENTS
描述：	SINGLE HOT-SWAP POWER CONTROLLERS WITH CIRCUIT BREAKER AND POWER-GOOD REPORTING 带断路器和电源良好报告单一热插拔电源控制器断路器电源电路电源管理电路功率控制光电二极管控制器
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TPS2330

TPS2331

www.ti.com

SLVS277G –MARCH 2000–REVISED JULY 2013

SINGLE HOT-SWAP POWER CONTROLLERS WITH

CIRCUIT BREAKER AND POWER-GOOD REPORTING

Check for Samples: TPS2330, TPS2331

FEATURES

D OR PW PACKAGE

•

Single-Channel High-Side MOSFET Driver

(TOP VIEW)

Input Voltage: 3 V to 13 V

GATE

DGND

TIMER

VREG

VSENSE

AGND

ISENSE

DISCH

ENABLE

PWRGD

FAULT

ISET

Output dV/dt Control Limits Inrush Current

Circuit-Breaker With Programmable

Overcurrent Threshold and Transient Timer

AGND

•

Power-Good Reporting With Transient Filter

CMOS- and TTL-Compatible Enable Input

Low 5-μA Standby Supply Current (Max)

Available in 14-Pin SOIC and TSSOP Package

–40°C to 85°C Ambient Temperature Range

Electrostatic Discharge Protection

NOTE: Terminal 13 is active-high on TPS2331.

typical application

VIN

3 V–13 V

DISCH

ISET

GATE

ISENSE

VSENSE

VREG

APPLICATIONS

•

Hot-Swap/Plug/Dock Power Management

Hot-Plug PCI, Device Bay

AGND

DGND

PWRGD

TPS2330

FAULT

TIMER

ENABLE

Electronic Circuit Breaker

DESCRIPTION

The TPS2330 and TPS2331 are single-channel hot-swap controllers that use external N-channel MOSFETs as

high-side switches in power applications. Features of these devices, such as overcurrent protection (OCP),

inrush-current control, output-power status reporting, and the ability to discriminate between load transients and

faults, are critical requirements for hot-swap applications.

The TPS2330/31 devices incorporate undervoltage lockout (UVLO) and power-good (PG) reporting to ensure the

device is off at start-up and confirm the status of the output voltage rails during operation. An internal charge

pump, capable of driving multiple MOSFETs, provides enough gate-drive voltage to fully enhance the N-channel

MOSFETs. The charge pump controls both the rise times and fall times (dV/dt) of the MOSFETs, reducing power

transients during power up/down. The circuit-breaker functionality combines the ability to sense overcurrent

conditions with a timer function; this allows designs such as DSPs, that may have high peak currents during

power-state transitions, to disregard transients for a programmable period.

Table 1. AVAILABLE OPTIONS

PACKAGES⁽¹⁾

T_A

HOT-SWAP CONTROLLER DESCRIPTION

PIN COUNT

ENABLE

Dual-channel with independent OCP and adjustable PG

Dual-channel with interdependent OCP and adjustable PG

TPS2300IPW

TPS2310IPW

TPS2301IPW

TPS2311IPW

TPS2320ID

TPS2320IPW

TPS2321ID

TPS2321IPW

–40°C to 85°C

Dual-channel with independent OCP

TPS2330ID

TPS2330IPW

TPS2331ID

TPS2331IPW

Single-channel with OCP and adjustable PG

(1) The packages are available left-end taped and reeled (indicated by the R suffix on the device type; e.g., TPS2331IPWR).

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

TPS2330

TPS2331

SLVS277G –MARCH 2000–REVISED JULY 2013

www.ti.com

FUNCTIONAL BLOCK DIAGRAM

PREREG

ISET

ISENSE

GATE

Clamp

DISCH

VREG

dv/dt Rate

Protection

Charge

Pump

Circuit

Breaker

50 µA

Pulldown FET

Circuit Breaker

UVLO and

Power Up

VSENSE

PWRGD

AGND

DGND

75 µA

Deglitcher

FAULT

TIMER

Logic

Deglitcher

ENABLE

Table 2. Terminal Functions

TERMINAL

NAME

I/O

DESCRIPTION

NO.

6, 9

AGND

DGND

DISCH

Analog ground, connects to DGND as close as possible

Digital ground

Discharge transistor

ENABLE/ENABLE

FAULT

GATE

Active-low (TPS2330) or active-high enable (TPS2331)

Overcurrent fault, open-drain output

Connects to gate of high-side MOSFET

Input voltage

ISENSE

ISET

Current-sense input

Adjusts circuit-breaker threshold with resistor connected to IN

PWRGD

TIMER

Open-drain output, asserted low when VSENSE voltage is less than reference.

Adjusts circuit-breaker deglitch time

VREG

Connects to bypass capacitor, for stable operation

Power-good sense input

VSENSE

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TPS2331

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SLVS277G –MARCH 2000–REVISED JULY 2013

DETAILED DESCRIPTION

DISCH – DISCH should be connected to the source of the external N-channel MOSFET transistor connected to

GATE. This pin discharges the load when the MOSFET transistor is disabled. They also serve as reference-

voltage connection for internal gate-voltage-clamp circuitry.

ENABLE or ENABLE – ENABLE for TPS2330 is active-low. ENABLE for TPS2331 is active-high. When the

controller is enabled, GATE voltage powers up to turn on the external MOSFETs. When the ENABLE pin is

pulled high for TPS2330 or the ENABLE pin is pulled low for TPS2331 for more than 50 μs, the gate of the

MOSFET is discharged at a controlled rate by a current source, and a transistor is enabled to discharge the

output bulk capacitance. In addition, the device turns on the internal regulator PREREG (see VREG) when

enabled and shuts down PREREG when disabled so that total supply current is much less than 5 μA.

FAULT – FAULT is an open-drain overcurrent flag output. When an overcurrent condition is sustained long

enough to charge TIMER to 0.5 V, the device latches off and pulls FAULT low. In order to turn the device back

on, either the enable pin must be toggled or the input power must be cycled.

GATE – GATE connects to the gate of the external N-channel MOSFET transistor. When the device is enabled,

internal charge-pump circuitry pulls this pin up by sourcing approximately 15 μA. The turnon slew rates depend

on the capacitance present at the GATE terminal. If desired, the turnon slew rates can be further reduced by

connecting capacitors between this pin and ground. These capacitors also reduce inrush current and protect the

device from false overcurrent triggering during power up. The charge-pump circuitry generates gate-to-source

voltages of 9 V–12 V across the external MOSFET transistor.

IN – IN should be connected to the power source driving the external N-channel MOSFET transistor connected

to GATE. The TPS2330/31 draws its operating current from IN, and remains disabled until the IN power supply

has been established. The device has been constructed to support 3-V, 5-V, or 12-V operation.

ISENSE, ISET – ISENSE in combination with ISET implements overcurrent sensing for GATE. ISET sets the

magnitude of the current that generates an overcurrent fault, through an external resistor connected to ISET. An

internal current source draws 50 μA from ISET. With a sense resistor from IN to ISENSE, which is also

connected to the drain of the external MOSFET, the voltage on the sense resistor reflects the load current. An

overcurrent condition is assumed to exist if ISENSE is pulled below ISET. To ensure proper circuit breaker

operation, V_I(ISENSE)and V_I(ISET)should never exceed V_I(IN)

PWRGD – PWRGD signals the presence of undervoltage conditions on VSENSE. The pin is an open-drain

output and is pulled low during an undervoltage condition. To minimize erroneous PWRGD responses from

transients on the voltage rail, the voltage sense circuit incorporates a 20-μs deglitch filter. When VSENSE is

lower than the reference voltage (about 1.23 V), PWRGD is active-low to indicate an undervoltage condition on

the power-rail voltage. PWRGD may not correctly report power conditions when the device is disabled because

there is no gate drive power for the PWRGD output transistor in the disable mode, or, in other words, PWRGD is

floating. Therefore, PWRGD is pulled up to its pullup power supply rail in disable mode.

TIMER – A capacitor on TIMER sets the time during which the power switch can be in overcurrent before turning

off. When the overcurrent protection circuits sense an excessive current, a current source is enabled which

charges the capacitor on TIMER. Once the voltage on TIMER reaches approximately 0.5 V, the circuit-breaker

latch is set and the power switch is latched off. Power must be recycled or the ENABLE pin must be toggled to

restart the controller. In high-power or high-temperature applications, a minimum 50-pF capacitor is strongly

recommended from TIMER to ground, to prevent any false triggering.

VREG – VREG is the output of an internal low-dropout voltage regulator, where IN1 is the input. The regulator is

used to generate a regulated voltage source, less than 5.5 V, for the device. A 0.1-μF ceramic capacitor should

be connected between VREG and ground to aid in noise rejection. In this configuration, on disabling the device,

the internal low-dropout regulator also is disabled, which removes power from the internal circuitry and allows the

device to be placed in low-quiescent-current mode. In applications where IN1 is less than 5.5 V, VREG and IN1

may be connected together. However, under these conditions, disabling the device may not place the device in

low-quiescent-current mode, because the internal low-dropout voltage regulator is being bypassed, thereby

keeping internal circuitry operational. If VREG and IN1 are connected together, a 0.1-μF ceramic capacitor

between VREG and ground is not needed if IN1 already has a bypass capacitor of 1 μF to 10 μF.

VSENSE – VSENSE can be used to detect undervoltage conditions on external circuitry. If VSENSE senses a

voltage below approximately 1.23 V, PWRGD is pulled low.

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TPS2330

TPS2331

SLVS277G –MARCH 2000–REVISED JULY 2013

www.ti.com

ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range (unless otherwise noted)

(1) (2)

VALUE

–0.3 to 15

–0.3 to 7

–0.3 to 30

–0.3 to 15

0 to 100

0 to 10

UNIT

V_I(IN1), V_I(ISENSE), V_I(VSENSE), V_I(ISET), V_I(ENABLE)

Input voltage range

V_I(VREG)

V_O(GATE)

Output voltage range

V_O(DISCH), V_O(PWRGD), V_{O( FAULT )}, V_O(TIMER)

I_(GATE), I_(DISCH)

Sink current range

°C

I_(PWRGD), I_(TIMER), I_{( FAULT )}

Operating virtual junction temperature range, T_J

Storage temperature range, T_stg

–40 to 100

–55 to 150

260

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating

conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltages are with respect to DGND.

DISSIPATION RATING TABLE

_A≤ 25°C

DERATING FACTOR

ABOVE T_A= 25°C

T_A= 70°C

POWER RATING

T_A= 85°C

POWER RATING

PACKAGE

POWER RATING

PW-14

D-14

755 mW

10.07 mW/°C

8.18 mW/°C

302 mW

245 mW

151 mW

123 mW

613 mW

RECOMMENDED OPERATING CONDITIONS

MIN

NOM

MAX UNIT

V_I(IN), V_I(ISENSE), V_I(VSENSE), V_I(ISET)

V_I

Input voltage

V_I(VREG)

5.5

V_I(IN)

100

V_I(ISENSE), V_I(ISET), V_I(VSENSE)

T_J

Operating virtual junction temperature

–40

°C

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TPS2331

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SLVS277G –MARCH 2000–REVISED JULY 2013

ELECTRICAL CHARACTERISTICS

over recommended operating temperature range (–40°C < T_A< 85°C), 3V ≤ V_I(IN1)≤13 V, 3 V ≤ V_I(IN2)≤ 5.5 V (unless

otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

GENERAL

V_I(ENABLE)= 5 V (TPS2331),

V_{I( ENABLE )}= 0 V (TPS2330)

I_I(IN)

Input current, IN

0.5

Standby current (sum of currents into

IN, ISENSE, and ISET)

V_I(ENABLE)= 0 V (TPS2331),

V_{I( ENABLE )}= 5 V (TPS2330)

I_I(stby)

μA

GATE

V_{G(GATE_3V)}

V_{G(GATE_4.5V)}

V_{G(GATE_10.8V)}

V_C(GATE)

V_I(IN)= 3 V

10.5

16.8

11.5

14.5

Gate voltage

I_I(GATE)= 500 nA, DISCH open

V_I(IN)= 4.5 V

V_I(IN)= 10.8 V

Clamping voltage, GATE to DISCH

Source current, GATE

3 V ≤ V_I(IN)≤ 13.2 V, 3 V ≤ V_O(VREG)≤ 5.5 V,

I_S(GATE)

μA

V_I(GATE)= V_I(IN)+ 6 V

3 V ≤ V_I(IN)≤ 13.2 V, 3 V ≤ V_O(VREG)≤ 5.5 V,

Sink current, GATE

Rise time, GATE

100

μA

V_I(GATE)= V_I(IN)

V_I(IN)= 3 V

0.5

0.6

t_r(GATE)

C_gto GND = 1 nF⁽¹⁾

V_I(IN)= 4.5 V

V_I(IN)= 10.8 V

V_I(IN)= 3 V

0.1

0.12

0.2

t_f(GATE)

Fall time, GATE

V_I(IN)= 4.5 V

V_I(IN)= 10.8 V

TIMER

V_{(TO_TIMER)}

Threshold voltage, TIMER

Charge current, TIMER

Discharge current, TIMER

0.4

0.5

0.6

V_I(TIMER)= 0 V

V_I(TIMER)= 1 V

μA

2.5

CIRCUIT BREAKER

R_ISET= 1 kΩ

R_ISET= 400 Ω, T_A= 25°C

R_ISET= 1 kΩ, T_A= 25°C

R_ISET= 1.5 kΩ, T_A= 25°C

V_IT(CB)

Threshold voltage, circuit breaker

I_{(IB_ISENSE)}

Input bias current, I_SENSE

Discharge current, GATE

0.1

800

150

μA

V_O(GATE)= 4 V

V_O(GATE)= 1 V

400

Propagation (delay) time, comparator

inputs to gate output

C_g= 50 pF,

(50% to 10%),

10-mV overdrive,

C_TIMER= 50 pF

t_pd(CB)

1.3

μs

ENABLE, ACTIVE LOW (TPS2330)

V_{IH( ENABLE )}

V_{IL( ENABLE )}

R_{I( ENABLE )}

High-level input voltage, ENABLE

Low-level input voltage, ENABLE

Input pullup resistance, ENABLE

0.8

(2)

See

100

200

300

kΩ

V_{I( ENABLE )}increasing above stop threshold;

100 ns rise time, 20 mV overdrive⁽¹⁾

t_{d(off_ ENABLE )}

t_{d(on_ ENABLE )}

Turnoff delay time, ENABLE

Turnon delay time, ENABLE

μs

V_{I( ENABLE )}decreasing below start threshold;

100 ns fall time, 20 mV overdrive⁽¹⁾

125

(1) Specified, but not production tested.

(2) Test I_Oof ENABLE at V_{I( ENABLE )}= 1 V and 0 V, then R_{I( ENABLE )}

1 V

* I

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SLVS277G –MARCH 2000–REVISED JULY 2013

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ELECTRICAL CHARACTERISTICS (Continued)

over recommended operating temperature range (–40°C < T_A< 85°C), 3 V ≤V_I(IN1)≤13 V, 3 V ≤ V_I(IN2)≤ 5.5 V (unless

otherwise noted)

PARAMETER

TEST CONDITIONS

MIN TYP MAX

UNIT

ENABLE, ACTIVE HIGH (TPS2331)

V_IH(ENABLE)

V_IL(ENABLE)

R_I(ENABLE)

High-level input voltage, ENABLE

Low-level input voltage, ENABLE

Input pulldown resistance, ENABLE

0.7

100

150

300

kΩ

V_I(ENABLE)increasing above start threshold;

100-ns rise time, 20-mV overdrive⁽¹⁾

t_{d(on_ENABLE)}

t_{d(off_ENABLE)}

Turnon delay time, ENABLE

Turnoff delay time, ENABLE

μs

V_I(ENABLE)decreasing below stop threshold;

100

4.1

(1)

100-ns fall time, 20-mV overdrive

PREREG

V_(VREG)

PREREG output voltage

4.5 ≤ V_I(IN)≤ 13 V

3.5

5.5

0.1

V_{(drop_PREREG)}PREREG dropout voltage

V_I(IN)= 3 V

VREG UVLO

V_{(TO_UVLOstart)}

V_{(TO_UVLOstop)}

V_hys(UVLO)

Output threshold voltage, start

Output threshold voltage, stop

Hysteresis

2.75 2.85 2.95

2.65 2.78

UVLO sink current, GATE

V_I(GATE)= 2 V

PWRGD1 and PWRGD2

V_I(VSENSE)decreasing

1.22

V_IT(ISENSE)

Trip threshold, VSENSE

1.2

1.25

Hysteresis voltage, power-good

comparator

V_hys

0.4

V_{O(sat_PWRGD)}

V_{O(VREG_min)}

Output saturation voltage, PWRGD

I_O= 2 mA

0.2

Minimum V_O(VREG)for valid power-

good

I_O= 100 μA, V_O(PWRGD)= 1 V

Input bias current, power-good

comparator

V_I(VSENSE)= 5.5 V

μA

μs

I_lkg(PWRGD)

t_dr

Leakage current, PWRGD

V_O(PWRGD)= 13 V

V_I(VSENSE)increasing, overdrive = 20 mV,

t_r= 100 ns⁽¹⁾

Delay time, rising edge, PWRGD

V_I(VSENSEx)decreasing, overdrive = 20 mV,

t_r= 100 ns⁽¹⁾

t_df

Delay time, falling edge, PWRGDx

μs

FAULT OUTPUT

V_{O(sat_ FAULT )}Output saturation voltage, FAULT

I_O= 2 mA

0.4

I_{lkg( FAULT )}

DISCH

Leakage current, FAULT

V_{O( FAULT )}= 13 V

μA

I_(DISCH)

Discharge current, DISCH

V_I(DISCH)= 1.5 V, V_I(VIN)= 5 V

V_IH(DISCH)

V_IL(DISCH)

Discharge on high-level input voltage

Discharge on low-level input voltage

(1) Specified, but not production tested.

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SLVS277G –MARCH 2000–REVISED JULY 2013

PARAMETER MEASUREMENT INFORMATION

Load 12 W

V_I(ENABLE)

5 V/div

V_I(ENABLE)

5 V/div

V_O(GATE)

10 V/div

V_O(DISCH)

5 V/div

V_O(GATE)

10 V/div

V_O(DISCH)

5 V/div

t – Time – 10 ms/div

Figure 1. Turnon Voltage Transition

Figure 2. Turnoff Voltage Transition

No Capacitor on Timer

V_I(ENABLE)

5 V/div

V_O(GATE)

10 V/div

5 V/div

V_O(GATE)

10 V/div

V_O(FAULT)

10 V/div

V_O(FAULT)

10 V/div

I_O(OUT)

2 A/div

t – Time – 5 ms/div

t – Time – 1 ms/div

Figure 3. Overcurrent Response:

Enabled Into Overcurrent Load

Figure 4. Overcurrent Response: an Overcurrent

Load Plugged Into the Enabled Board

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SLVS277G –MARCH 2000–REVISED JULY 2013

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PARAMETER MEASUREMENT INFORMATION (continued)

No Capacitor on Timer

V_I(ENABLE)

5 V/div

V_I(IN)

10 V/div

V_O(GATE)

10 V/div

V_O(GATE)

10 V/div

V_O(FAULT)

10 V/div

V_O(OUT)

10 V/div

I_O(OUT)

I_I(IN)

1 A/div

2 A/div

t – Time – 1 ms/div

t – Time – 5 ms/div

Figure 5. Enabled Into Short Circuit

Figure 6. Hot Plug

No Capacitor on Timer

V_I(IN)

10 V/div

V_O(GATE)

10 V/div

V_O(OUT)

10 V/div

I_O(OUT)

1 A/div

t – Time – 1 ms/div

Figure 7. Hot Removal

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SLVS277G –MARCH 2000–REVISED JULY 2013

TYPICAL CHARACTERISTICS

INPUT CURRENT (ENABLED)

INPUT CURRENT (DISABLED)

INPUT VOLTAGE

= 85°C

IN = 5 V to 13 V

= 85°C

= 25°C

= –40°C

= 0°C

= –40°C

10 11 12 13 14

V_I– Input Voltage – V

Figure 8.

Figure 9.

GATE OUTPUT VOLTAGE

GATE VOLTAGE RISE TIME

GATE LOAD CAPACITANCE

INPUT VOLTAGE

= 1000 pF

L(GATE)

IN = 12 V

= 25°C

= 85°C

= 25°C

= 0°C

= –40°C

10 11 12

V – Input Voltage – V

– GATE Load Capacitance – nF

L(GATE)

Figure 10.

Figure 11.

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SLVS277G –MARCH 2000–REVISED JULY 2013

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TYPICAL CHARACTERISTICS (continued)

GATE VOLTAGE FALL TIME

GATE OUTPUT CURRENT

GATE LOAD CAPACITANCE

GATE VOLTAGE

14.5

IN = 12 V

= 25°C

= –40°C

= 85°C

13.5

= 25°C

= 0°C

12.5

11.5

IN = 13 V

14 15 16 17 18 19 20 21 22 23 24

V – GATE Voltage – V

– GATE Load Capacitance – nF

L(GATE)

Figure 12.

Figure 13.

CIRCUIT-BREAKER RESPONSE TIME

LOAD VOLTAGE DISCHARGE TIME

TIMER CAPACITANCE

LOAD CAPACITANCE

320

280

240

200

160

120

IN = 12 V

= 0 A

= 25°C

0.2

0.4

0.6

0.8

100

200

300

400

500

C_TIMER– TIMER Capacitance – nF

– Load Capacitance – mF

Figure 14.

Figure 15.

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SLVS277G –MARCH 2000–REVISED JULY 2013

TYPICAL CHARACTERISTICS (continued)

UVLO START AND STOP THRESHOLDS

PWRGD INPUT THRESHOLD

TEMPERATURE

2.9

1.27

1.26

1.25

1.24

1.23

1.22

1.21

1.20

2.88

2.86

2.84

2.82

2.8

Start

Down

2.78

2.76

2.74

2.72

2.7

Stop

–45–35–25–15 –5

15 25 35 45 55 65 75 85 95

–45–35–25–15 –5

15 25 35 45 55 65 75 85 95

– Temperature – °C

Figure 16.

Figure 17.

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APPLICATION INFORMATION

This diagram shows a typical dual hot-swap application. The pullup resistors at PWRGD and FAULT should be

relatively large (e.g. 100 kΩ) to reduce power loss unless they are required to drive a large load.

System

3 V 13 V IN

Board

SENSE

1 µF 10 µF

VSENSE_TOP

ISET

VSENSE_BOTTOM

0.1 µF

VREG IN ISET ISENSE GATE DISCH VSENSE

ENABLE

DGND

FAULT

TPS2331

PWRGD

AGND

TIMER

Figure 18. Typical Hot-Swap Application

INPUT CAPACITOR

A 0.1-μF ceramic capacitor in parallel with a 1-μF ceramic capacitor should be placed on the input power

terminals near the connector on the hot-plug board to help stabilize the voltage rails on the cards. There is no

need to mount the TPS2330/31 near the connector or these input capacitors. For applications with more severe

power environments, a 2.2-μF or higher ceramic capacitor is recommended near the input terminals of the hot-

plug board. A bypass capacitor for IN should be placed close to the device.

OUTPUT CAPACITOR

A 0.1-μF ceramic capacitor is recommended per load on the TPS2330/31; these capacitors should be placed

close to the external FETs and to TPS2330/31. A larger bulk capacitor on the load is also recommended. The

value of the bulk capacitor should be selected based on the power requirements and the transients generated by

the application.

EXTERNAL FET

To deliver power from the input sources to the loads, the controller needs an external N-channel MOSFET. A few

widely used MOSFETs are shown in Table 3. But many other MOSFETs on the market can also be used with

the TPS23xx in hot-swap systems.

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SLVS277G –MARCH 2000–REVISED JULY 2013

Table 3. Some Available N-Channel MOSFETs

CURRENT RANGE

(A)

PART NUMBER

DESCRIPTION

MANUFACTURER

IRF7601

N-channel, r_DS(on)= 0.035 Ω, 4.6 A, Micro-8

N-channel, r_DS(on)= 0.040 Ω, 4.6 A, Micro-8

Dual N-channel, r_DS(on)= 0.1 Ω, 2.3 A, SO-8

Dual N-channel, r_DS(on)= 0.04 Ω, 5 A, SO-8

N-channel, r_DS(on)= 0.022 Ω, 7 A, SO-8

N-channel, r_DS(on)= 0.025 Ω, 5 A, SO-8

Dual N-channel, r_DS(on)= 0.029 Ω, 5.2 A, SO-8

N-channel, r_DS(on)= 0.020 Ω, 8 A, SO-8

N-channel, r_DS(on)= 0.019 Ω, 29 A, d-Pak

N-channel, r_DS(on)= 0.045 Ω, 14 A, d-Pak

International Rectifier

ON Semiconductor

International Rectifier

ON Semiconductor

International Rectifier

ON Semiconductor

International Rectifier

Vishay Dale

MTSF3N03HDR2

IRF7101

0 to 2

2 to 5

MMSF5N02HDR2

IRF7401

MMSF5N02HDR2

IRF7313

SI4410

IRLR3103

International Rectifier

5 to 10

IRLR2703

TIMER

For most applications, a minimum capacitance of 50 pF is recommended to prevent false triggering. This

capacitor should be connected between TIMER and ground. The presence of an overcurrent condition on of the

TPS2330/31 causes a 50-μA current source to begin charging this capacitor. If the overcurrent condition persists

until the capacitor has been charged to approximately 0.5 V, the TPS2330/31 latches off the transistor and pulls

the FAULT pin low. The timer capacitor can be made as large as desired to provide additional time delay before

registering a fault condition. The time delay is approximately:

dt(sec) = C_(TIMER)(F) × 10,000(Ω)

OUTPUT-VOLTAGE SLEW-RATE CONTROL

When enabled, the TPS2330/TPS2331 controllers supply the gate of an external MOSFET transistor with a

current of approximately 15 μA. The slew rate of the MOSFET source voltage is thus limited by the gate-to-drain

capacitance C_gdof the external MOSFET capacitor to a value approximating:

15 mA

(1)

If a slower slew rate is desired, an additional capacitance can be connected between the gate of the external

MOSFET and ground.

VREG CAPACITOR

The internal voltage regulator connected to VREG requires an external capacitor to ensure stability. A 0.1-μF or

0.22-μF ceramic capacitor is recommended.

GATE DRIVE CIRCUITRY

The TPS2330/TPS2331 includes four separate features associated with each gate-drive terminal:

•

A charging current of approximately 15 μA is applied to enable the external MOSFET transistor. This current

is generated by an internal charge pump that can develop a gate-to-source potential (referenced to DISCH) of

9 V–12 V. DISCH must be connected to the external MOSFET source terminal to ensure proper operation of

this circuitry.

•

A discharge current of approximately 75 μA is applied to disable the external MOSFET transistor. Once the

transistor gate voltage has dropped below approximately 1.5 V, this current is disabled and the UVLO

discharge driver is enabled instead. This feature allows the part to enter a low-current shutdown mode while

ensuring that the gate of the external MOSFET transistor remains at a low voltage.

•

During a UVLO condition, the gate of the MOSFET transistor is pulled down by an internal PMOS transistor.

This transistor continues to operate even if the voltage at IN is 0 V. This circuitry also helps hold the external

MOSFET transistor off when power is suddenly applied to the system.

During an overcurrent fault condition, the external MOSFET transistor that exhibited an overcurrent condition

is rapidly turned off by an internal pulldown circuit capable of pulling in excess of 400 mA (at 4 V) from the

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pin. Once the gate has been pulled below approximately 1.5 V, this driver is disengaged and the UVLO driver

is enabled instead.

SETTING THE CURRENT-LIMIT CIRCUIT-BREAKER THRESHOLD

The current sensing resistor R_ISENSEand the current limit setting resistor R_ISETdetermine the current limit of the

channel, and can be calculated by the following equation:

–6

50 10

ISET

LMT

ISENSE

(2)

Typically R_ISENSEis usually very small (0.001 Ω to 0.1 Ω). If the trace and solder-junction resistances between the

junction of R_ISENSEand ISENSE and the junction of R_ISENSEand R_ISETare greater than 10% of the R_ISENSEvalue,

then these resistance values should be added to the R_ISENSEvalue used in the foregoing calculation.

Table 4 shows some of the current-sense resistors available in the market.

Table 4. Some Current-Sense Resistors

CURRENT RANGE

PART NUMBER

DESCRIPTION

MANUFACTURER

(A)

0 to 1

1 to 2

2 to 4

4 to 6

6 to 8

8 to 10

WSL-1206, 0.05 1%

0.05 Ω, 0.25 W, 1% resistor

0.025 Ω, 0.25 W, 1% resistor

0.015 Ω, 0.25 W, 1% resistor

0.010 Ω, 0.5 W, 1% resistor

0.007 Ω, 0.5 W, 1% resistor

0.005 Ω, 0.5 W, 1% resistor

WSL-1206, 0.025 1%

WSL-1206, 0.015 1%

WSL-2010, 0.010 1%

WSL-2010, 0.007 1%

WSR-2, 0.005 1%

Vishay Dale

SETTING THE POWER-GOOD THRESHOLD VOLTAGE

The two feedback resistors R_{VSENSE_TOP}and R_{VSENSE_BOT}connected between V_Oand ground form a resistor

divider, setting the voltage at the VSENSE pins. VSENSE voltage equals:

V_I(SENSE)= V_O× R_{VSENSE_BOT}/(R_{VSENSE_TOP}+ R_{VSENSE_BOT}

)

This voltage is compared to an internal voltage reference (1.225 V ±2%) to determine whether the output voltage

level is within a specified tolerance. For example, given a nominal output voltage at V_O, and defining V_{O_min}as

the minimum required output voltage, then the feedback resistors are defined by:

* 1.225

O_min

VSENSE_TOP

VSENSE_BOT

1.225

(3)

Start the process by selecting a large standard resistor value for R_{VSENSE_BOT}to reduce power loss. Then

R_{VSENSE_TOP}can be calculated by inserting all of the known values into the preceding equation. When V_Ois lower

than V_{O_min}, PWRGD is low as long as the controller is enabled.

UNDERVOLTAGE LOCKOUT (UVLO)

The TPS2330/TPS2331 includes an undervoltage lockout (UVLO) feature that monitors the voltage present on

the VREG pin. This feature disables the external MOSFET if the voltage on VREG drops below 2.78 V (nominal)

and re-enables normal operation when it rises above 2.85 V (nominal). Because VREG is fed from IN through a

low-dropout voltage regulator, the voltage on VREG tracks the voltage on IN within 50 mV. While the

undervoltage lockout is engaged, GATE is held low by an internal PMOS pulldown transistor, ensuring that the

external MOSFET transistor remain off at the times, even if the power supply has fallen to 0 V.

POWER-UP CONTROL

The TPS2330/TPS2331 includes a 500-μs (nominal) start-up delay that ensures that internal circuitry has

sufficient time to start before the device begins turning on the external MOSFETs. This delay is triggered only on

the rapid application of power to the circuit. If the power supply ramps up slowly, the undervoltage lockout

circuitry provides adequate protection against undervoltage operation.

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SLVS277G –MARCH 2000–REVISED JULY 2013

THREE-CHANNEL HOT-SWAP APPLICATION

Some applications require hot-swap control of up to three voltage rails, but may not explicitly require the sensing

of the status of the output power on all three of the voltage rails. One such application is a device bay, where

dV/dt control of 3.3 V, 5 V, and 12 V is required. By using TPS2330/TPS2331 to drive all three power rails, as is

shown in Figure 19, TPS2330/31 can deliver three different voltages to three loads while monitoring the status of

one of the loads.

System

Board

3.3 V IN2

1 µF 10 µF

5 V IN3

1 µF 10 µF

SENSE

12 V IN1

VSENSE_TOP

ISET

VSENSE_BOTTOM

0.1 µF

VREG IN ISET ISENSE GATE DISCH VSENSE

ENABLE

DGND

FAULT

PWRGD

TPS2331

AGND

TIMER

Figure 19. Three-Channel Application

Figure 20 shows ramp-up waveforms of the three output voltages.

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t – Time – 2.5 ms/div

Figure 20.

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SLVS277G –MARCH 2000–REVISED JULY 2013

REVISION HISTORY

Note: Revision history for previous versions is not available. Page numbers of previous versions may differ.

Changes from Revision F (November 2006) to Revision G

Page

•

Added text to ISENSE, ISET pin description paragraph for clarification. ............................................................................. 3

Added additional V_Ispecs to ROC table for clarification ...................................................................................................... 4

Added minus sign to 40°C MIN T_Jtemperature ................................................................................................................... 4

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PACKAGE OPTION ADDENDUM

www.ti.com

11-Apr-2013

PACKAGING INFORMATION

Orderable Device

TPS2330ID

Status Package Type Package Pins Package

Eco Plan Lead/Ball Finish

MSL Peak Temp

Op Temp (°C)

-40 to 85

Top-Side Markings

Samples

Drawing

Qty

(1)

(2)

(3)

(4)

ACTIVE

SOIC

Green (RoHS

& no Sb/Br)

CU NIPDAU

Level-1-260C-UNLIM

TPS2330I

TPS2330IDG4

TPS2330IDR

ACTIVE

2500

Green (RoHS

& no Sb/Br)

TPS2330I

PD2330I

TPS2331I

PD2331I

SOIC

Green (RoHS

& no Sb/Br)

TPS2330IDRG4

TPS2330IPW

SOIC

Green (RoHS

& no Sb/Br)

TSSOP

SOIC

Green (RoHS

& no Sb/Br)

TPS2330IPWG4

TPS2330IPWR

TPS2330IPWRG4

TPS2331ID

Green (RoHS

& no Sb/Br)

2000

Green (RoHS

& no Sb/Br)

Green (RoHS

& no Sb/Br)

Green (RoHS

& no Sb/Br)

TPS2331IDG4

TPS2331IDR

SOIC

Green (RoHS

& no Sb/Br)

SOIC

2500

Green (RoHS

& no Sb/Br)

TPS2331IDRG4

TPS2331IPW

SOIC

Green (RoHS

& no Sb/Br)

TSSOP

Green (RoHS

& no Sb/Br)

TPS2331IPWG4

TPS2331IPWR

TPS2331IPWRG4

Green (RoHS

& no Sb/Br)

2000

Green (RoHS

& no Sb/Br)

Green (RoHS

& no Sb/Br)

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

11-Apr-2013

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that

lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between

the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight

in homogeneous material)

⁽³⁾MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)

Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a

continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

9-Jul-2013

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

TPS2330IDR

TPS2330IPWR

TPS2331IDR

TPS2331IPWR

SOIC

TSSOP

SOIC

2500

2000

2500

2000

330.0

16.4

12.4

16.4

12.4

6.5

6.9

6.5

6.9

9.0

5.6

9.0

5.6

2.1

1.6

2.1

1.6

8.0

16.0

12.0

16.0

12.0

TSSOP

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

9-Jul-2013

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

TPS2330IDR

TPS2330IPWR

TPS2331IDR

TPS2331IPWR

SOIC

TSSOP

SOIC

2500

2000

2500

2000

367.0

38.0

35.0

38.0

35.0

TSSOP

Pack Materials-Page 2

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TPS2330ID [TI]

相关型号：

TPS2330IDG4

TPS2330IDR

TPS2330IDRG4

TPS2330IPW

TPS2330IPWG4

TPS2330IPWR

TPS2330IPWRG4

TPS2330PW

TPS2331

TPS2331D

TPS2331ID

TPS2331IDG4