TPS2358RGZTG4 [TI]
TPS2358 Dual-Slot ATCA AdvancedMC⑩ Controller; TPS2358双插槽ATCA的AdvancedMC ™控制器
| 型号： | TPS2358RGZTG4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | TPS2358 Dual-Slot ATCA AdvancedMC⑩ Controller |
| 文件： | 总34页 (文件大小：933K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPS2358
www.ti.com ................................................................................................................................................... SLUS820D–FEBRUARY 2008–REVISED JUNE 2008
TPS2358 Dual-Slot ATCA AdvancedMC™ Controller
1
FEATURES
DESCRIPTION
2
•
ATCA AdvancedMC™ Compliant
•
Full Power Control for Two
AdvancedMC™Modules
The TPS2358 dual-slot hot-plug controller provides all
required power interface functions for two
AdvancedMC™
modules.
(Advanced
Mezzanine
Card)
•
•
•
•
•
Independent 12-V Current Limit and Fast Trip
12-V FET ORing for MicroTCA™
Internal 3.3-V Current Limit
Two fully integrated 3.3-V channels provide inrush
control, current limiting, and overload protection. The
two 12-V channels use an external FET to provide
the same functions, along with ORing control circuits
that allow an external FET to prevent reverse current
flow. The 3.3-V current limits are factory set to
AdvancedMC™ compliant levels and the 12-V current
limits are programmed using external sense resistors.
The accurate current sense comparators of the
TPS2358 satisfy the narrow ATCA AdvancedMC™
current limit requirements.
Power Good and Fault Outputs
48-Pin PQFN Package
APPLICATIONS
•
•
•
•
•
ATCA Carrier Boards
MicroTCA™ Power Modules
AdvancedMC™ Slots
Systems Using 12 V and 3.3 V
Base Stations
TYPICAL APPLICATION DIAGRAM
12 V in
3v3 in
3v3 in
12 V in
COMMON
CIRCUITRY
IN12B
IN12A
SENPB
SENPA
R
SET
R
SET
SETB
SETA
R
R
SENSE
SENSE
TPS2358
SENMB
SENMA
48 PIN QFN
PASSB
BLKB
PASSA
BLKA
OUT12B
OUT12A
OUT3B
OUT3A
R
R
SUM3B
SUM12B
R
R
SUM12A
SUM3A
3.3 V
12 V
3.3 V
12 V
COMMON
CIRCUITRY
AdvancedMC™
AdvancedMC™
Optional ORing FETs for
Redundant Systems Only
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
AdvancedMC, MicroTCA are trademarks of PICMG.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2008, Texas Instruments Incorporated
TPS2358
SLUS820D–FEBRUARY 2008–REVISED JUNE 2008 ................................................................................................................................................... www.ti.com
ORDERING INFORMATION(1)
DEVICE
TEMPERATURE
PACKAGE(2)
ORDERING CODE
TPS2358
-40°C to 85°C
QFN48
TPS2358RGZ
(1) Add an R suffix to the device type for tape and reel.
(2) For the most current package and ordering information see the Package Option Addendum at the end of this document or see the TI
Web site at www.ti.com.
ABSOLUTE MAXIMUM RATINGS(1)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
VALUE
0 to 30
0 to 17
0 to 5
Unit
PASSx, BLKx
IN12x, OUT12x, SENPx, SENMx, SETx, EN12x, FLTx, PGx, ORENx
V
IN3x, OUT3x, EN3x, VDDx, CTx, SUMx
AGND, GNDx
FLTx, PGx
SUMx
–0.3 to 0.3
5
5
mA
VINT
–1 to 1
Internally limited
OUT3x
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only. Functional operation of the device under any conditions beyond those indicated under recommended operating conditions is
neither implied nor guaranteed. Exposure to absolute maximum rated conditions for extended periods of time may affect device
reliability.
ELECTROSTATIC DISCHARGE (ESD) PROTECTION
TEST METHOD
MIN
2
UNITS
Human Body Model (HBM)
Charged Device Model (CDM)
kV
0.5
DISSIPATION RATINGS
PACKAGE
θJA - High-k (°C/W)
QFN48 - RGZ
29.1
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
PARAMETER
MIN
TYP
MAX
UNITS
VIN12x
VIN3x
12-V input supply
8.5
3
12
3.3
3.3
15
4
3.3-V input supply
V
VVDD3x
IOUT3x
ISUMx
3.3-V input supply
3
4
3.3-V output current
165
1000
1
mA
Summing pin current
100
10
µA
PASSx pin board leakage current
VINT bypass capacitance
Operating junction temperature range
-1
1
250
125
nF
°C
TJ
–40
2
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ELECTRICAL CHARACTERISTICS
IN3A = IN3B = VDD3A = VDD3B = 3.3 V. IN12A = IN12B = SENPA = SENPB = SENMA = SENMB = SETPA =
SETPB = 12 V. EN12A = EN12B = EN3A = EN3B = ORENA = ORENB = CT12A = CT12B = CT3A = CT3B = AGND =
GNDA = GNDB = 0 V. SUM12A = SUM12B = 6.8 kΩ to ground. SUM3A = SUM3B = 3.3 kΩ to ground. All other pins open.
Over free air temperature operating range and all voltages referenced to AGND, unless otherwise noted.
PARAMETER
ENABLE Inputs
CONDITIONS
MIN
TYP
MAX
UNITS
Threshold voltage, falling
edge
1.2
1.3
1.4
V
Hysteresis(1)
20
5
50
8
80
15
15
5
mV
Pullup current
ENx = ORENx = 0 V
Input bias current
Input bias current
3.3-V turn off time
EN12x = ORENx = 17 V
6
µA
µs
EN3x = 5 V
1
EN3x deasserts to VOUT3x < 1.0 V, COUT = 0 µF
10
EN12x deasserts to VOUT12x < 1.0 V, COUT = 0 µF,
QGATE = 35 nF
12-V turn off time
20
POWER GOOD Outputs
Low voltage
Sinking 2 mA
0.14
0.25
1
V
Leakage current
Threshold voltage
PGx = 17 V
µA
PG12x, falling VOUT12x
PG3x, falling VOUT3x
PG12x, measured at OUT12x
PG3x, measured at OUT3x
PGx falling
10.2
2.7
10.5
2.8
10.8
2.9
V
Hysteresis(1)
130
50
mV
Deglitch time(1)
FAULT Outputs
Low voltage
50
100
150
µs
Sinking 2 mA
PGx = 17 V
0.14
2.3
0.25
1
V
Leakage current
VINT
µA
Output voltage
0 < IVINT < 50 µA
2
2.8
V
Fault Timer
Sourcing current
Sinking current
Upper threshold voltage
Lower threshold voltage
12-V Summing Node
VCTx = 0 V, during fault
VCTx = 2 V
–7
7
–10
10
–13
13
µA
1.3
0.33
1.35
0.35
1.4
V
0.37
VSENMx = 10.8 – 13.2 V, VSENPx = VSENMx + 50 mV,
measure VSETx – VSENMx
Input referred offset
–2
2
mV
Summing threshold
Leakage current
VPASSx = 15 V
0.66
0.675
50
0.69
1
V
VSETx = VSENMx – 10 mV
µA
12-V Current Limit
RSUMx = 6.8 kΩ, RSETx = 422 Ω, increase ILOADx and
measure VSENPx – VSENMx when VPASSx = 15 V
Current limit threshold
47.5
52.5
40
mV
Sink current in current
limit
VSUMx = 1 V, VPASSx = 12 V, measure IPASSx
20
80
µA
Fast trip threshold
Fast turn-off delay(1)
Measure VSENPx – VSENMx
100
200
120
300
mV
ns
20 mV overdrive, CPASSx = 0 pF, tp50-50
VPASSx - VINx when timer starts, while VPASSx falling
due to over current
Timer start threshold
5
6
7
V
(1) Not production tested.
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ELECTRICAL CHARACTERISTICS (continued)
IN3A = IN3B = VDD3A = VDD3B = 3.3 V. IN12A = IN12B = SENPA = SENPB = SENMA = SENMB = SETPA =
SETPB = 12 V. EN12A = EN12B = EN3A = EN3B = ORENA = ORENB = CT12A = CT12B = CT3A = CT3B = AGND =
GNDA = GNDB = 0 V. SUM12A = SUM12B = 6.8 kΩ to ground. SUM3A = SUM3B = 3.3 kΩ to ground. All other pins open.
Over free air temperature operating range and all voltages referenced to AGND, unless otherwise noted.
PARAMETER
12-V UVLO
CONDITIONS
MIN
TYP
MAX
UNITS
UVLO rising
IN12x rising
IN12x falling
8.1
8.5
0.5
8.9
V
UVLO hysteresis(2)
12-V BLOCKING
Turn-on threshold
Turn-off threshold
Turn-off delay(2)
0.44
0.59
Measure VSENPx – VOUTx
5
10
–3
15
0
mV
ns
Measure VSENPx – VOUTx
–5
20 mV overdrive, CBLKx = 0 pF, tp50-50
200
300
12-V Gate Drivers ( PASSx, BLKx )
Output voltage
VINx = VOUTx = 10 V
21.5
20
0.5
6
23
30
1
24.5
40
V
µA
A
Sourcing current
VIN12x = VOUT12x = 10 V, VPASSx = VBLKx = 17 V
Fast turnoff, VPASSx = VBLKx = 14 V
Sustained, VPASSx = VBLKx = 4 – 25 V
In OTSD ( at 150 °C )
Sinking current
14
20
10
25
26
mA
kΩ
µs
µs
ms
Pulldown resistance
Fast turn-off duration(2)
Disable delay(2)
14
5
15
EN12x pin to PASSx and BLKx, tp50-90
IN12x rising to PASSx and BLKx sourcing
1
Startup time(2)
0.25
3.3-V Summing Node
Summing threshold
3.3-V Current Limit
On resistance
655
675
695
mV
IOUT3x = 150 mA
290
195
300
750
500
225
mΩ
mA
ns
Current limit
RSUM3x = 3.3 kΩ , VOUT3x = 0 V
170
250
Fast trip threshold
Fast turn-off delay(2)
3.3-V UVLO
400
IOUT3x = 400 mA, tp50-50
1300
UVLO rising
UVLO hysteresis(2)
IN3x rising
IN3x falling
2.65
200
2.75
240
2.85
300
V
mV
Supply Currents (IINx + ISENPx + ISENMx + ISETx + IVDDx
)
All channels enabled
All channels disabled
Thermal Shutdown
IOUT3A = IOUT3B = 0
3.1
2
4
mA
°C
2.8
Whole-chip shutdown
temperature(2)
TJ rising, IOUT3A = IOUT3B = 0
140
130
150
3.3 V channel shutdown
temperature(2)
Hysteresis(2)
TJ rising, IOUT3A or IOUT3B in current limit
Whole chip or 3.3-V channel
140
10
(2) Not production tested.
4
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TPS2358
www.ti.com ................................................................................................................................................... SLUS820D–FEBRUARY 2008–REVISED JUNE 2008
DEVICE INFORMATION
SIGNAL AND PIN NAMING BLOCK
The PICMG™ AdvancedMC™ specification refers to 3.3-V power as management power and refers to 12-V
power as payload power. This datasheet uses a naming convention that reflects the associated voltage (12 V to
3 V) and AdvancedMC™ slot (A or B).
•
•
•
•
Signals and pins associated with slot A 12-V payload power end with 12A.
Signals and pins associated with slot A 3.3-V management power end with 3A.
Signals and pins associated with slot B 12-V payload power end with 12B.
Signals and pins associated with slot B 3.3-V management power end with 3B.
Pins and signals unique to 12-V channels have only an A or B suffix.
TPS2358 Block Diagrams
R
SENSE
R
SET
IN12x
SENPx
SETx
SENMx
PASSx
BLKx
OUT12x
pgat\
100 mv
12dis
Q
Pump
+
30 uA
30 uA
ogat
Vcp
~25 v
10 us
10 us
Fault
Timer
C
FLT12x\
T
Vcp
CT12x
EN12x\
+
R
vthoc - 675 mv nominal
SUM
PG12x\
10 mv
-3 mv
SUM12x
vpg
6810
100
us
+
+
R
S
Q
Q
+
ogat
OUT
OUT12x
pgat\
oren
Figure 1. 12-V Channel Circuitry
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0.1 W
IN3x
OUT3x
PG3x\
2.8 V
245 W
gat
VDD3x
en\
30mv
30 us
Q
Pump
+
30 uA
vcpx
~25 v
12dis
Fault
Timer
vcpx
FLT3x \
CT3x
30 us
SUM3x
RSUM
3300
+
vthoc - [ 675 mvnominal ]
en\
EN3x\
10mv
-3mv
+
+
gat
R
S
Q
Q
OUT3x
Figure 2. 3-V Channel Circuitry
IN12A
IN12B
VINT
en
por
Selector
IN3A
IN3B
OUT12A
OUT12B
OUT3A
OUT3B
PREREG
POR
Trim
NVM
2.2V
AGND
GNDA
GNDB
Figure 3. Circuitry Common to all Channels
6
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Control
48
47
46
45
44
43
42
41
40
39
38
37
OUT3A
CT3A
IN12A
SENPA
SETA
1
2
36
35
34
33
32
31
30
29
28
27
26
25
3
4
5
6
FLT3A
PG3A
SENMA
VINT
3A, 3B
SUM3A
AGND
PG12A
48 Pin QFN
SUM12A
7
8
VDD3B
SUM3B
ORENA
9
GND
GND
PG3B
10
11
12
FLT3B
CT3B
PG12B
SUM12B
OUT3B
13
14
15
16
17
18
19
20
21
22
23
24
12A, 12B
TERMINAL FUNCTIONS
PIN#
1
NAME
IN12A
TYPE
DESCRIPTION
VDD
12A input
2
SENPA
SETA
I
I
12A input sense
12A current limit set
12A current limit sense
3
4
SENMA
VINT
I
5
I/O
O
Bypass capacitor connection point for internal supply
6
PG12A
SUM12A
ORENA
GND
12A power good output, active low, asserts when OUT12A > VPG12A
12A summing node
7
I/O
I
8
12A blocking transistor enable, active low
Connect pin to ground
9
GND
GND
O
10
11
12
GND
Connect pin to ground
PG12B
SUM12B
12B power good output, active low, asserts when OUT12B > VPG12B
12B summing node
I/O
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TERMINAL FUNCTIONS (continued)
PIN#
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
NAME
CT12B
FLT12B
BLKB
TYPE
I/O
O
DESCRIPTION
12B fault timing capacitor
12B fault output, active low, asserted when 12B fault timer runs out
12B blocking transistor gate drive
12B output
O
OUT12B
GNDB
ORENB
PASSB
SENMB
SETB
I/O
GND
I
12B power ground
12B blocking transistor enable, active low
12B pass transistor gate drive
12B current limit sense
O
I
I
12B current limit set
SENPB
IN12B
I
12B input sense
VDD
VDD
I/O
I/O
O
12B input
IN3B
3B input
OUT3B
CT3B
3B output
3B fault timing capacitor
FLT3B
PG3B
3B fault output, active low, asserted when 3B fault timer runs out
3B power good output, active low, asserts when OUT3B > 2.8 V
3B summing node
O
SUM3B
VDD3B
AGND
SUM3A
PG3A
I/O
VDD
GND
I/O
O
3B charge pump input
Analog ground
3A summing node
3A power good output, active low, asserts when OUT3A > 2.8 V
3A fault output, active low, asserted when 3A fault timer runs out
3A fault timing capacitor
FLT3A
CT3A
O
I/O
I/O
VDD
VDD
I
OUT3A
IN3A
3A output
3A input
VDD3A
EN3B
3A charge pump input
3B enable, (default active low)
3A enable, (default active low)
12B enable, (default active low)
12A pass transistor gate drive
12A enable, (default active low)
12A power ground
EN3A
I
EN12B
PASSA
EN12A
GNDA
OUT12A
BLKA
I
O
I
GND
I/O
O
12A output
12A blocking transistor gate drive
12A fault output, active low, asserted when 12A fault timer runs out
12A fault timing capacitor
FLT12A
CT12A
I/O
I/O
8
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DEVICE INFORMATION
DETAILED PIN DESCRIPTION
AGND Ground pin for the analog circuitry inside the TPS2358.
BLKx Gate drive pin for the 12x channel BLK FET. This pin sources 30 µA to turn the FET on. An internal clamp
prevents this pin from rising more than 14.5 V above OUT12x. Setting the ORENx pin high holds the BLKx pin
low.
CTx A capacitor from CTx to GND sets the time the channel can remain in current limit before it shuts down and
declares a fault. Current limit causes this pin to source 10 µA into the external capacitor (CT). When VCTx
reaches 1.35 V, the TPS2358 shuts the channel off by pulling the PASSx pin low and declares an over-current
fault by pulling the FLTx pin low.
EN12x Active low enable input. Pulling this pin high (or allowing it to float high) turns off channel 12x by pulling
both BLKx and PASSx low. An internal 200-kΩ resistor pulls this pin up to VINT when disconnected.
EN3x Active low enable input. Pulling this pin high (or allowing it to float high) turns off channel 3x by pulling the
gate of the internal pass FET to GND. An internal 200-kΩ resistor pulls this pin up to VINT when disconnected.
FLTx Active low open-drain output indicating that channel x has remained in current limit long enough to time out
the fault timer and shut the channel down.
IN12x Supply pin for channel 12x internal circuitry.
IN3x Supply pin for channel 3x internal pass FET.
ORENx Active low input. Pulling this pin low allows the 12x channel ORing function to operate normally. Pulling
this pin high (or allowing it to float high) disables the ORing function by pulling the BLKx pin low. An internal
200-kΩ resistor pulls this pin up to VINT when disconnected.
OUT12x Senses the output voltage of the channel 12x path.
OUT3x Output of the channel 3x internal pass FET.
PASSx Gate drive pin for the 12x channel pass FET. This pin sources 30 µA to turn the FET on. An internal
clamp prevents this pin from rising more than 14.5 V above IN12x.
PGx Active low open-drain output indicating that channel x output voltage has dropped below the PG threshold,
which nominally equals 2.85 V for the 3x channels and 10.5 V for the 12x channels.
SENMx Senses the voltage on the low side of the channel 12x current sense resistor.
SENPx Senses the voltage on the high side of the channel 12x current sense resistor.
SETx A resistor connected from this pin to SENPx sets the current limit level in conjunction with the current
sense resistor and the resistor connected to the SUM12x pin, as described in 12-V thresholds – setting current
limit and fast over current trip section.
SUMx A resistor connected from this pin to ground forms part of the channel x current limit. As the current
delivered to the load increases, so does the voltage on this pin. When the voltage on this pin reaches a threshold
of 675 mV, the current limit amplifier acts to prevent the current from further increasing.
VDD3x Supply pin for channel3x internal circuitry.
VINT This pin connects to the internal 2.35-V rail. A 0.1-µF capacitor must be connected from this pin to ground.
Do not connect other external circuitry to this pin.
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TYPICAL CHARACTERISTICS
IDD at 25°C
vs
12-V VDD
3-V CHANNEL ORING TURN-ON THRESHOLD
12
2.45
2.40
11
2.35
2.30
10
2.25
9
2.20
2.15
8
2.10
-50
0
50
100
150
-50
0
50
100
150
TJ - Temperature - °C
VDD - 25°C
Figure 4.
Figure 5.
3-V CHANNEL ORING TURN-OFF THRESHOLD
12-V CURRENT LIMIT THRESHOLD
51.0
50.8
0.0
-1.0
50.6
50.4
-2.0
-3.0
-4.0
-5.0
50.2
50.0
-50
0
50
100
150
-50
0
50
100
150
TJ - Temperature - °C
TJ - Temperature - °C
Figure 6.
Figure 7.
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TYPICAL CHARACTERISTICS (continued)
3-V IDD
vs
TEMPERATURE
12-V CHANNEL ORING TURN-OFF THRESHOLD
0.0
0.26
-1.0
0.25
0.24
-2.0
0.23
-3.0
0.22
-4.0
0.21
-5.0
0.20
-50
0
50
100
150
-50
0
50
100
150
TJ - Temperature - °C
TJ - Temperature - °C
Figure 8.
Figure 9.
12-V CURRENT (mA)
vs
TEMPERATURE
12-V CHANNEL ORING TURN-ON THRESHOLD
12.0
11.5
2.4
2.3
11.0
10.5
10.0
9.5
2.2
2.1
2.0
6
9.0
8.5
8.0
-50
0
50
100
150
-50
0
50
100
150
TJ - Temperature - °C
TJ - Temperature - °C
Figure 10.
Figure 11.
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TYPICAL CHARACTERISTICS (continued)
Figure 12. OUT3A Startup Into 22-Ω ( 150 mA ) 150-µF Load
Figure 13. OUT3A Load Stepped from 165 mA to 240 mA
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TYPICAL CHARACTERISTICS (continued)
Figure 14. OUT3A Short Circuit under Full Load (165 mA) Zoom View
Figure 15. OUT3A Short Circuit Under Full Load (165 mA) Wide View
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TYPICAL CHARACTERISTICS (continued)
Figure 16. OUT3A Startup Into Short Circuit
Figure 17. OUT12A Startup Into 500-Ω, 830-µF Load
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TYPICAL CHARACTERISTICS (continued)
Figure 18. OUT12A Startup Into 80-Watt, 830-µF Load
Figure 19. OUT12A Short Circuit Under Full Load (6.7 A) Wide View
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TYPICAL CHARACTERISTICS (continued)
Figure 20. OUT12A Short Circuit Under Full Load (6.7 A) Zoom View
Figure 21. OUT12A Startup Into Short Circuit
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TYPICAL CHARACTERISTICS (continued)
Figure 22. OUT12A Overloaded While Supplying 6.7 A
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REFERENCE INFORMATION
The TPS2358 has been designed to simplify compliance with the PICMG-AMC.R2.0 and PICMG-MTCA.0
specifications. These specifications were developed by the PCI Industrial Computer Manufacturers Group
(PICMG). These two specifications are derivations of the PICMG-ATCA (Advanced Telecommunication
Computing Architecture) specification originally released in December, 2002.
PICMG-AMC Highlights
•
•
•
•
•
•
•
•
•
AMC – Advanced Mezzanine Cards
Designed to Plug Into ATCA Carrier Boards
AdvancedMC™ Focuses on Low Cost
1 to 8 AdvancedMC™ per ATCA Carrier Board
3.3-V Management Power (maximum current draw of 150 mA)
12-V Payload Power – (converted to required voltages on AMC)
Maximum 80-W Dissipation per AdvancedMC™
Hotswap and Current Limiting Must be Present on Carrier Board
For Details,See www.picmg.org/v2internal/AdvancedMC.htm
PICMG-MTCA Highlights
•
•
•
•
•
•
•
MTCA - MicroTelecommunications Computing Architecture
Architecture for Using AMCs Without an ATCA Carrier Board
Up to 12 AMCs Per System, Plus Two MCHs and Two CUs
Focuses on Low Cost
All Functions of ATCA Carrier Board Must be Provided
MicroTCA is Also Known as MTCA, mTCA, or uTCA
For Details, See www.picmg.org/v2internal/microTCA.htm
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SYSTEM OPERATION
Introduction
The TPS2358 controls two 12-V power paths and two 3.3-V power paths. Each power path can draw from a
single common supply, or from two independent supplies. The TPS2358 is in a 48-pin QFN package. The
following sections describe the main functions of the TPS2358 and provide guidance for designing systems
around this device.
Control Logic and Power-On Reset
The TPS2358's circuitry draws power from an internal bus fed by a preregulator. A capacitor attached to the
VINT pin provides decoupling and output filtering for this preregulator. It can draw power from any of four inputs
(IN12A, IN12B, IN3A, or IN3B) or from any of four outputs (OUT12A, OUT12B, OUT3A, or OUT3B). This feature
allows the internal circuitry to function regardless of which channels receive power, or from what source. The four
external FET drive pins (PASSA, PASSB, BLKA, and BLKB) are held low during startup to ensure that the two
12-V channels remain off. The internal 3.3-V channels are also held off. When the voltage on the internal VINT
rail exceeds approximately 1 V, the power-on reset circuit initializes the TPS2358.
Enable Functions
The TPS2358 provides three external enable pins for each of its two AdvancedMC™ slots. Pulling the EN3x low
turns on the 3x channel. Pulling the EN12x pin turns on the 12x channel. If the EN12x pin goes high, the
TPS2358 pulls both the PASSx and BLKx pins to ground. Pulling the ORENx pin low turns on the reverse
blocking circuitry in the 12x channel. If the ORENx pin goes high, then the BLKx pin remains low. Each of the six
enable pins has an internal 200-kΩ pullup resistor to VINT.
Power Good (PG) Outputs
The TPS2358 provides four active-low open-drain outputs that monitor the status of the four output voltage rails.
The power good output for each channel pulls low whenever the voltage on its OUTx pin exceeds the PG
threshold. The 3.3-V channels have nominal thresholds of 2.85 V and the 12-V channels have nominal
thresholds of 10.5 V.
Fault (FLT) Outputs
The TPS2358 provides four active-low, open-drain fault outputs, one for each channel. A fault output pulls low
when the channel has remained in current limit long enough to run out the fault timer. A channel experiencing a
fault condition automatically shuts down. To clear the fault and re-enable the channel, turn the channel off and
back on using the appropriate ENx pin.
Current Limit and Fast Trip Thresholds
All four channels monitor current by sensing the voltage across a resistor. The 3.3-V channels use internal sense
resistors with a nominal value of 290 mΩ. The 12-V channels use external sense resistors that typically lie in the
range of 4 - 10 mΩ. Each channel features two distinct thresholds: a current limit threshold and a fast trip
threshold.
The current limit threshold sets the regulation point of a feedback loop. If the current flowing through the channel
exceeds the current limit threshold, then this feedback loop reduces the gate-to-source voltage imposed on the
pass FET. This causes the current flowing through the channel to settle to the value determined by the current
limit threshold. For example, when a module first powers up, it draws an inrush current to charge its load
capacitance. The current limit feedback loop ensures that this inrush current does not exceed the current limit
threshold.
The current limit feedback loop has a finite response time. Serious faults such as shorted loads require a faster
response in order to prevent damage to the pass FETs or voltage sags on the supply rails. A comparator
monitors the current flowing through the sense resistor, and if it ever exceeds the fast trip threshold, then it
immediately shuts off the channel. The channel turns back on slowly, allowing the current limit feedback loop
time to respond. One normally sets the fast trip threshold some 2 to 5 times higher than the current limit.
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3.3-V Current Limiting
The 3.3-V management power channels include internal pass FETs and current sense resistors. The
on-resistance of a management channel - including pass FET, sense resistor, metallization resistance, and bond
wires - typically equals 290 mΩ and never exceeds 500 mΩ. The AdvancedMC™ specification allows a total of 1
Ω between the power source and the load. The TPS2358 never consumes more than half of this budget.
3.3-V Fast Trip Function
The 3.3-V fast trip function protects the channel against short-circuit events. If the current through the channel
exceeds a nominal value of 300 mA, then the TPS2358 immediately disables the internal pass transistor and
then allows it to slowly turn back on into current limiting.
3.3-V Current Limit Function
The 3.3-V current limit function internally limits the current to comply with the AdvancedMC™ and MicroTCA™
specifications. External resistor RSUM3x allows the user to adjust the current limit threshold. The nominal current
limit threshold ILIMIT equals:
650V
ILIMIT
=
RSUM 3x
(1)
A 3320-Ω resistor gives a nominal current limit of ILIMIT = 195 mA which complies with AdvancedMC™ and
MicroTCA™ specifications. This resistance corresponds to an EIA 1% value. Alternatively, a 3.3-kΩ resistor will
also suffice. Whenever a 3.3-V channel enters current limit, its fault timer begins to operate (see Fault Timer
Programming section).
3.3-V Over-Temperature Shutdown
The 3.3-V over-temperature shutdown trips if a 3.3-V channel remains in current limit so long that the die
temperature exceeds approximately 140°C. When this occurs, any 3.3-V channel operating in current limit turns
off until the chip cools by approximately 10°C. This feature prevents a prolonged fault on one 3.3-V channel from
disabling the other 3.3-V channel, or disabling either of the 12-V channels.
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12-V Fast Trip and Current Limiting
Figure 23 shows a simplified block diagram of the circuitry associated with the fast trip and current limit circuitry
within a 12-V channel. Each 12-V channel requires an external N-channel pass FET and three external resistors.
These resistors allow the user to independently set the fast trip threshold and the current limit threshold, as
described below.
12-V Fast Trip Function
The 12-V fast trip function is designed to protect the channel against short-circuit events. If the voltage across
RSENSE exceeds a nominal threshold of 100 mV, the device immediately disables the pass transistor and
declares a fault condition. The nominal fast current limit equals:
100mV
IFT
=
RS
(2)
12-V Current Limit Function
The 12-V current limit function regulates the PASSx pin voltage to prevent the current through the channel from
exceeding ILIMIT. The current limit circuitry includes two amplifiers, A1 and A2, as shown in Figure 23. Amplifier A1
forces the voltage across external resistor RSET to equal the voltage across external resistor RSENSE. The current
that flows through RSET also flows through external resistor RSUM, generating a voltage on the 12SUMx pin equal
to:
æ
ç
è
ö
÷
ø
RSENSE RSUM
V
=
I
SENSE
12SUMx
RSET
(3)
Amplifier A2 senses the voltage on the 12SUMx pin. As long as this voltage is less than the reference voltage on
its positive input (nominally 0.675 V), the amplifier sources current to PASSx. When the voltage on the 12SUMx
pin exceeds the reference voltage, amplifier A2 begins to sink current from PASSx. The gate-to-source voltage of
pass FET MPASS drops until the the voltages on the two inputs of amplifier A2 balance. The current flowing
through the channel then nominally equals:
æ
ç
è
ö
÷
ø
RSET
ILIMIT
=
×0.675V
RSUM RSENSE
(4)
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The recommended value of RSUM is 6810 Ω. This resistor should never equal less than 675 Ω to prevent
excessive currents from flowing through the internal circuitry. Using the recommended values of RSENSE = 5 mΩ
and RSUM = 6810 Ω gives:
ILIMIT = ( 0.0198A / W )× RSET
(5)
A system capable of powering an 80-Watt AdvancedMC™ module consumes a maximum of 8.25 A according to
MicroTCA™ specifications. The above equation suggests RSET = 417 Ω. The nearest 1% EIA value equals 422
Ω. The selection of RSET for MicroTCA™ power modules is described in the Redundant vs. Non-Redundant
Inrush Current Limiting section.
RSENSE
MPASS
IN12x
RSET
Fast Trip
Comparator
SENPx
SENMx
PASSx
+
100 mV
30 mA
A1
675 mV
+
A2
Current Limit
Amp
SUM12x
RSUM
Figure 23. 12-V Channel Threshold Circuitry
Fault Timer Programming
The fault timers of the four channels in a TPS2358 use identical internal circuitry. Each channel requires an
external capacitor CT connected between the CTx pin and ground. When a channel goes into current limit, the
TPS2358 injects 10 µA into the external capacitor. If the channel remains in current limit long enough for the
voltage on the CTx pin to reach 1.35 V, then the TPS2358 shuts the channel down and pulls the FLTx pin low to
declare a fault. If the channel does not remain in current limit long enough to trip the timer, then the CTx
capacitor is discharged through an internal 200-Ω pulldown resistor. The nominal fault time tf equals:
1.35V
tf =
CT
10mA
(6)
The user should select capacitors that provide the shortest fault times sufficient to allow down-stream loads and
bulk capacitors to charge. Shorter fault times reduce the stresses imposed on the pass FETs under fault
conditions. This consideration may allow the use of smaller and less expensive FETs for the 12-V channels.
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Multiswap Operation in Redundant Systems
TheTPS2358 features an additional mode of operation called Multiswap redundancy. This technique does not
require a microcontroller, making it simpler and faster than the redundancy schemes described in the
MicroTCA™ standard. Multiswap is especially attractive for AdvancedMC™ applications that require redundancy
but need not comply with the MicroTCA™ power module standard.
In order to implement Multiswap redundancy, connect the SUM pins of the redundant supplies together and tie a
single RSUM resistor from this node to ground. The current limit thresholds now apply to the sum of the currents
delivered by the redundant supplies. When implementing multiswap redundancy on 12-V channels, all of the
channels must use the same values of resistors for RSENSE and RSET
.
Figure 24 compares the redundancy technique advocated by the MicroTCA™ specification to multiswap
redundancy. MicroTCA™ redundancy independently limits the current delivered by each power source. The
current drawn by the load cannot exceed the sum of the current limits of the individual power sources. Multiswap
redundancy limits the current drawn by the load to a fixed value regardless of the number of operational power
sources. Removing or inserting power sources within a multiswap system does not affect the current limit seen
by the load.
TM
MicroTCA Redundancy
Multiswap Redundancy
Power Source 1
Power Source 2
Power Source 1
Power Source 2
TPS2358
TPS2358
TPS2358
TPS2358
SUM12x
SUM3x
SUM12x
SUM3x
SUM12x
SUM3x
SUM12x
SUM3x
mC
mC
Backplane
Backplane
Figure 24. MicroTCA™ Redundancy vs. Multiswap Redundancy
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12-V Inrush Slew Rate Control
As normally configured, the turn-on slew rate of the 12-V channel output voltage VOUT equals:
dVout Isrc
@
dt
Cg
(7)
where ISRC equals the current sourced by the PASSx pin (nominally 30 µA) and Cg equals the effective gate
capacitance. For purposes of this computation, one can assume that the effective gate capacitance
approximately equals the reverse transfer capacitance, CRSS. To reduce the slew rate, increase Cg by connecting
additional capacitance from PASSx to ground. Place a resistor of at least 1000 Ω in series with the additional
capacitance to prevent it from interfering with the fast turn off of the FET.
RSENSE
IN12x
C
R > 1k
PASSx
Figure 25. RC Slew Rate Control
12-V ORing Operation for Redundant Systems
The 12-V channels use external pass FETs to provide reverse blocking. The TPS2358 pulls the BLKx pin high
when the input-to-output differential voltage VIN12x-OUT12x exceeds a nominal value of 10 mV, and it pulls the
pin low when this differential falls below a nominal value of -3 mV. These thresholds provide a nominal 13 mV of
hysteresis to help prevent false triggering (Figure 26).
The source of the blocking FET connects to the source of the pass FET, and the drain of the blocking FET
connects to the load. This orients the body diode of the blocking FET such that it conducts forward current and
blocks reverse current. The body diode of the blocking FET does not normally conduct current because the FET
turns on when the voltage differential across it exceeds 10 mV.
25 V
Gnd
V
OR
Figure 26. ORing Thresholds
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Using the TPS2358 to Control Two AdvancedMC™ Slots
The TPS2358 has been designed for use on ATCA Carrier boards with a minimum number of external
components. Carrier boards do not usually have redundant 3.3-V or 12-V supplies, so it is not necessary to
provide ORing functions in the power supply feeds. Consequently, the external 12-V ORing FETs have been
omitted and the BLKx pins are left unconnected.
12 V
R
SENSE
NC
AdvancedMC™
SENPA
IN12A
SETA
SENMA
PASSA
BLKA
OUT12A
OUT3A
3.3 V
EN12A
EN3A
ORENA
From
IPMC
3.3 V
CT12A
CT3A
IN3A
PG12A
FLT12A
PG3A
To IPMC
and/or
LED’s
VDD3A
FLT3A
SUM12A
SUM3A
VINT
3.3 V
TPS2358
GND
GND
GND
AGND
GND
12 V in
48 PIN QFN
3.3 V
EN12B
EN3B
ORENB
From
IPMC
PG12B\
FLT12B\
PG3B\
To IPMC
and/or
LED’s
CT12B
CT3B
FLT3B\
IN3B
SUM12B
SUM3B
VDD3B
OUT3B
3.3 V
IN12B
OUT12B
SENPB SETB
SENMB
PASSB
BLKB
AdvancedMC™
R
R
SENSE
NC
SET
12 V
Figure 27. Block Diagram of TPS2358 In a Non-Redundant System
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Layout Considerations
TPS2358 applications require layout attention to ensure proper performance and minimize susceptibility to
transients and noise. In general, all runs should be as short as possible but the list below deserves first
consideration.
1. Decoupling capacitors on IN12A, IN12B, IN3A, and IN3B should have minimal length to the pin and to GND.
2. SENMx and SENPx runs must be short and run side by side to maximize common mode rejection. Kelvin
connections should be used at the points of contact with RSENSE (Figure 28).
3. SETx runs need to be short on both sides of RSET
4. These runs should be as short as possible and sized to carry at least 20 Amps, more if possible.
a. Runs on both side of RSENSE
.
.
b. Runs from the drains and sources of the external FETs.
5. Runs from the BLK FETs to OUT12x should be as short as possible.
6. Runs connecting to IN3x and OUT3x should be sized for 1 Amp or more.
7. Connections to GND and SUMx pins should be minimized after the runs above have been placed.
8. The device dissipates low to average power so soldering the powerpad to the board is not a requirement.
However, doing so will improve thermal performance and reduce susceptibility to noise.
LOAD CURRENT
PATH
LOAD CURRENT
PATH
SENSE
RESISTOR
R
R
SET
SET
432
432
TPS2359
TPS2359
(a)
(b)
Figure 28. Recommended RSENSE Layout
NOTE:
Additional details omitted for clarity.
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Transient Protection
TPS2358 devices in deployed systems are not likely to have long, inductive feeds or long load wires. However, it
is always advised that an analysis be performed to determine the need for transient protection. When the
TPS2358 interrupts current flow, any inductance on the input will tend to cause a positive voltage spike on the
input, and any inductance on the output will tend to cause a negative voltage spike on the output. The following
equations allow the designer to make a reasonably accurate prediction of the voltage spike due to interruptions in
current.
L
VSPIKE =VNOM + ILOAD
C
(8)
where:
•
•
•
•
VNOM = nominal voltage at terminal being analyzed
L = combined inductance of feed and RTN lines
C = capacitance at point of disconnect
ILOAD = current through terminal at TDISCONNECT
é
4 ´ length
ù
æ
ç
è
ö
÷
ø
LSTRAIGHTWIRE ~ 0.2 ´length´ ln
- 0.75 nH
ê
ë
ú
û
diameter
•
This equation can be used to calculate the capacitance required to limit the voltage spike to a desired level
above the nominal voltage:
LI2
C =
2
(VSPIKE -VNOM
)
(9)
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PACKAGE OPTION ADDENDUM
www.ti.com
11-Jul-2008
PACKAGING INFORMATION
Orderable Device
TPS2358RGZR
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
QFN
RGZ
48
48
48
48
2500 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
TPS2358RGZRG4
TPS2358RGZT
QFN
QFN
QFN
RGZ
RGZ
RGZ
2500 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
TPS2358RGZTG4
250 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Jun-2008
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0 (mm)
B0 (mm)
K0 (mm)
P1
W
Pin1
Diameter Width
(mm) W1 (mm)
(mm) (mm) Quadrant
TPS2358RGZR
TPS2358RGZT
QFN
QFN
RGZ
RGZ
48
48
2500
250
330.0
180.0
16.4
16.4
7.3
7.3
7.3
7.3
1.5
1.5
12.0
12.0
16.0
16.0
Q2
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Jun-2008
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPS2358RGZR
TPS2358RGZT
QFN
QFN
RGZ
RGZ
48
48
2500
250
346.0
190.5
346.0
212.7
33.0
31.8
Pack Materials-Page 2
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amplifier.ti.com
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logic.ti.com
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