TPS23731RMTR_技术文档

TPS23731

_{SLVSER7 – OC}T_TOP_BS_E2_R3₂7₀3₂1₀

SLVSER7 – OCTOBER 2020

www.ti.com

TPS23731 IEEE 802.3bt Type 3 Class 1-4 PoE PD with No-Opto Flyback DC-DC

Controller

1 Features

3 Description

•

Complete IEEE 802.3bt Type 3 (Class 1-4) and

802.3at PoE PD Solution

The TPS23731 device combines a Power over

Ethernet (PoE) powered device (PD) interface, and a

current-mode DC-DC controller optimized for flyback

switching regulator designs where the use of primary-

side regulation (PSR) is supported. The PoE interface

supports the IEEE 802.3bt and IEEE 802.3at

standards for applications needing up to 25.5 W or

less at PD input.

– EA Gen 2 logo-ready (PoE 2 PD Controller)

– Robust 100-V, 0.3-Ω (typ) Hotswap MOSFET

– Supports power levels for up to 30-W operation

Integrated PWM controller for flyback configuration

– Flyback control with primary-side regulation

•

Supports CCM operation

Programmable spread spectrum frequency dithering

(SSFD) is provided to minimize the size and cost of

EMI filter. Advanced Startup with adjustable soft-start

helps to use minimal bias capacitor while simplifying

converter startup and hiccup design, also ensuring

that IEEE 802.3bt/at startup requirements are met.

±1.5% (typ, 5-V output) load regulation

(0-100% load range) — with Sync FET

±3% (typ, 12-V output) load regulation

(5-100% load range) — diode rectified

•

– Also supports secondary-side regulation

– Soft-start control with advanced startup and

hiccup mode overload protection

The soft-stop feature minimizes stress on switching

sync FET(s), allowing FET BOM cost reduction.

– Soft-stop shutdown

– Adjustable frequency with synchronization

– Programmable frequency dithering for EMI

Automatic Maintain Power Signature (MPS)

– Auto-adjust to PSE type and load current with

auto-stretch

The PSR feature of the DC-DC controller uses

feedback from an auxiliary winding for control of the

output voltage, eliminating the need for external shunt

regulator and optocoupler. It is optimized for

continuous conduction mode (CCM), and can work

with secondary side synchronous rectification,

resulting in optimum efficiency, regulation accuracy

and step load response over multiple outputs.

•

Primary adapter priority input

–40°C to 125°C junction temperature range

2 Applications

The DC-DC controller features slope compensation

and blanking. Typical switching frequency is 250 kHz.

•

Video and VoIP Telephones

Access Points

Security Cameras

The automatic MPS enables applications with low

power modes or multiple power feeds. It automatically

adjusts its pulsed current amplitude and duration

according to PSE Type and system conditions, to

maintain power while minimizing consumption.

Redundant Power Feeds or Power Sharing

Device Information ⁽¹⁾

PART NUMBER

PACKAGE

BODY SIZE (NOM)

TPS23731

VSON (45)

7.00 mm × 5.00 mm

(1) For all available packages, see the orderable addendum at

the end of the data sheet.

T1

TPS23731

V_CC

+

R_CLC_CL

VDD

DEN

C_BULK

D_CL

V_OUT2

C_OUT2

R_DEN

APDO

T2P

GATE

CS

0.1 ꢀF

58V

CLS

R_CS

V_OUT1

VCC

C_OUT

COMP

D_CC

VSS

APD

C_COMP

R_COMP

I_in

R₁

C_VCC

FB

C_CC2

LINEUV

FRS

R_UV2

D_A

CP

R₂

SST

C_SST

R_DTR

EA_DIS

VB

DTHR

RTN GND I_STP PSRS

C_VB

R_APD2

C_DTR

R_FRS

48V

Adapter

R_{I_STP}

Simplified Application

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

Submit Document Feedback

1

Product Folder Links: TPS23731

TPS23731

SLVSER7 – OCTOBER 2020

www.ti.com

Table of Contents

1 Features............................................................................1

2 Applications.....................................................................1

3 Description.......................................................................1

4 Revision History.............................................................. 2

5 Device Comparison Table...............................................3

6 Pin Configuration and Functions...................................3

7 Specifications.................................................................. 6

7.1 Absolute Maximum Ratings ....................................... 6

7.2 ESD Ratings .............................................................. 6

7.3 Recommended Operating Conditions ........................7

7.4 Thermal Information ...................................................7

7.5 Electrical Characteristics: DC-DC Controller

Section ......................................................................... 7

7.6 Electrical Characteristics PoE ..................................10

7.7 Typical Characteristics..............................................13

8 Detailed Description......................................................17

8.1 Overview...................................................................17

8.2 Functional Block Diagram.........................................18

8.3 Feature Description...................................................19

8.4 Device Functional Modes..........................................27

9 Application and Implementation..................................41

9.1 Application Information............................................. 41

9.2 Typical Application.................................................... 41

10 Power Supply Recommendations..............................44

11 Layout...........................................................................45

11.1 Layout Guidelines................................................... 45

11.2 Layout Example...................................................... 45

11.3 EMI Containment.................................................... 45

11.4 Thermal Considerations and OTSD........................45

11.5 ESD.........................................................................45

12 Device and Documentation Support..........................46

12.1 Documentation Support.......................................... 46

12.2 Support Resources................................................. 46

12.3 Trademarks.............................................................46

12.4 Electrostatic Discharge Caution..............................46

12.5 Glossary..................................................................46

13 Mechanical, Packaging, and Orderable

Information.................................................................... 46

4 Revision History

DATE

REVISION

NOTES

October 2020

*

Initial release.

2

Submit Document Feedback

Product Folder Links: TPS23731

TPS23731

SLVSER7 – OCTOBER 2020

www.ti.com

5 Device Comparison Table

KEY FEATURES

Class Range

ACF Support

SSFD

TPS23730

1-6

TPS23731

1-4

TPS23734

1-4

Yes

No

Yes

Soft-stop

Yes

Advanced Startup

PSR (Flyback)

Auto MPS

Yes

PPD

Yes

No

APD

Yes

PoE allocated power and AUX power

indicator(s)

TPH/TPL (parallel) or TPL

(serial)

T2P, APDO

6 Pin Configuration and Functions

CS

1

COMP

35

34

33

32

31

30

AGND

DTHR

2

3

4

5

6

FB

SST

FRS

APD

NC

I_STP

NC

PAD_G

TEST

7

8

9

RTN

NC

29

28

27

26

25

24

23

VSS

NC

10

11

12

13

NC

PAD_S

NC

EMPS

DEN

VDD

NC

APDO

Figure 6-1. Package Pinout

Table 6-1. Pin Functions

I/O

DESCRIPTION

NO.

NAME

DC-DC controller current sense input. Connect directly to the external power current sense

resistor.

1

CS

I/O

Submit Document Feedback

3

Product Folder Links: TPS23731

TPS23731

SLVSER7 – OCTOBER 2020

www.ti.com

Table 6-1. Pin Functions (continued)

I/O

DESCRIPTION

NO.

NAME

2

AGND

-

AGND is the DC-DC converter analog return. Tie to RTN and GND on the circuit board.

Used for spread spectrum frequency dithering. Connect a capacitor (determines the modulating

frequency) from DTHR to RTN and a resistor (determines the amount of dithering) from DTHR to

FRS. If dithering is not used, short DTHR to VB pin.

3

4

DTHR

FRS

O

I

This pin controls the switching frequency of the DC-DC converter. Tie a resistor from this pin to

RTN to set the frequency.

Primary auxiliary power detect input. Raise 1.5 V above RTN to disable pass MOSFET, also

turning class off. If not used, connect APD to RTN.

5

APD

RTN

I

-

I

7, 8, 9

11

RTN is the output of the PoE hotswap and the reference ground for the DC-DC controller.

Automatic MPS enable input, referenced to RTN, internally pulled-up to 5-V internal rail. Tie to

RTN to disable automatic MPS.

EMPS

Active low output referenced to RTN, indicates that an auxiliary power adapter is detected via the

APD input.

13

14

APDO

T2P

O

Active low output that indicates a PSE has performed the IEEE 802.3at Type 2 hardware

classification, or APD is active.

17

21

REF

CLS

O

Internal 1.25-V voltage reference. Connect a 49.9-kΩ_1% resistor from REF to VSS.

Connect a resistor from CLS to VSS to program the classification current.

Positive input power rail for PoE interface circuit and source of DC-DC converter start-up current.

Bypass with a 0.1 µF to VSS and protect with a TVS.

23

24

VDD

DEN

—

Connect a 25.5-kΩ resistor from DEN to VDD to provide the PoE detection signature. Pulling this

pin to VSS during powered operation causes the internal hotswap MOSFET to turn off.

I/O

27, 28

30

VSS

-

Negative power rail derived from the PoE source.

Used internally for test purposes only. Leave open.

TEST

O

This pin sets the SST discharge current during a soft-stop event independently from the setting

used during a regular soft-start event. Connect a resistor from this pin to AGND to set the DC/DC

soft-stop rate.

32

33

I_STP

SST

I

A capacitor from SST to RTN pin sets the soft-start (I_SSCcharge current) and the hiccup timer (I_SSD

discharge current) for the DC-DC converter. Connect a capacitor from this pin to RTN to set the

DC/DC startup rate.

I/O

Converter error amplifier inverting (feedback) input. If flyback configuration with primary-side

regulation, it is typically driven by a voltage divider and capacitor from the auxiliary winding,

working with CP pin, FB also being connected to the COMP compensation network. If optocoupler

feedback is enabled, tie FB to VB.

34

FB

I

Compensation output of the DC-DC convertor error amplifier or control loop input to the PWM. If

the internal error amplifier is used, connect the compensation networks from this pin to the FB pin

to compensate the converter. If optocoupler feedback is enabled, the optocoupler and its network

pulled up to VB directly drives the COMP pin.

35

36

COMP

I/O

I

Error Amplifier disable input, referenced to AGND, internally pulled-up to 5V internal rail. Leave

EA_DIS open to disable the Error amplifier, to enable optocoupler feedback for example. Connect

to AGND otherwise.

EA_DIS

5-V bias rail for DC/DC control circuits and the feedback optocoupler (when in use). Connect a 0.1-

uF capacitor from this pin to AGND to provide bypassing.

37

38

VB

O

I

LINEUV is used to monitor the bulk capacitor voltage to trigger a soft-stop event when an

undervoltage condition is detected if APD is low. If not used, connect LINEUV to VB pin.

LINEUV

PSR Sync enable input, referenced to AGND, internally pulled-up to 5V internal rail. PSRS works

with CP pin to support flyback architecture using primary-side regulation. Leave PSRS open if the

flyback output stage is configured with synchronous rectification and uses PSR. If diode

rectification is used, or for applications not using PSR, connect PSRS to AGND.

39

40

PSRS

VBG

I

5-V bias rail for the switching FET gate driver circuit. For internal use only. Bypass with a 0.1-μF

ceramic capacitor to GND pin.

O

DC/DC converter bias voltage. The internal startup current source and converter bias winding

output power this pin. Connect a 1µF minimum ceramic capacitor to RTN.

42

43

VCC

I/O

O

GATE

Gate drive output for the main DC-DC converter switching MOSFET

4

Submit Document Feedback

Product Folder Links: TPS23731

TPS23731

SLVSER7 – OCTOBER 2020

www.ti.com

Table 6-1. Pin Functions (continued)

I/O

DESCRIPTION

NO.

44

NAME

CP

CP provides the clamp for the primary-side regulation loop. Connect this pin to the lower end of the

bias winding of the flyback transformer.

O

-

45

GND

.Power ground used by the flyback power FET gate driver and CP. Connect to RTN.

6, 10, 12,

15, 16,

18-20, 22,

25, 26, 29,

31, 41

NC

-

No connect pin. Leave open.

The exposed thermal pad must be connected to VSS. A large fill area is required to assist in heat

dissipation.

47

46

PAD_S

PAD_G

-

The exposed thermal pad must be connected to RTN. A large fill area is required to assist in heat

dissipation.

Submit Document Feedback

5

Product Folder Links: TPS23731

TPS23731

SLVSER7 – OCTOBER 2020

www.ti.com

7 Specifications

7.1 Absolute Maximum Ratings

Voltage are with respect to V_SS(unless otherwise noted)⁽¹⁾

MIN

–0.3

-0.3

MAX

100

UNIT

VDD, DEN, GND, AGND, RTN⁽²⁾

Input voltage

VDD to RTN

100

V

APD, FB, CS, EA_DIS, LINEUV, PSRS, EMPS, all to RTN

6.5

FRS⁽³⁾, COMP, VB⁽³⁾, VBG⁽³⁾, I_STP⁽³⁾, DTHR⁽³⁾, SST⁽³⁾, all to RTN

6.5

VCC to RTN

GATE⁽³⁾to RTN

CP to GND

GND, AGND, all to RTN

REF⁽³⁾, CLS⁽³⁾

T2P, APDO , all to RTN

VB, VBG, VCC

COMP

19

VCC+0.3

60

Voltage

V

0.3

6.5

19

Internally limited

Sourcing current

Sinking current

mA

REF

CLS

65

1

RTN

Internally limited

DEN

COMP

T2P, APDO

10

2

mA

A

Peak sourcing

current

CP

Peak sinking current CP

T_J(max)Maximum junction temperature

T_stgStorage temperature

0.7

A

Internally Limited

–65

°C

150

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under

Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device

reliability.

(2) I_RTN= 0 for V_RTN> 80 V.

(3) Do not apply voltage to these pins.

7.2 ESD Ratings

VALUE

±2000

±500

UNIT

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾

Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾

IEC 61000-4-2 contact discharge⁽³⁾

V_(ESD)

Electrostatic discharge

V

±8000

±15000

IEC 61000-4-2 air-gap discharge⁽³⁾

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

(3) Surges per EN61000-4-2, 1999 applied between RJ-45 and output ground and between adapter input and output ground of

the TPS23730, TPS23730EVM-093 evaluation module (documentation available on the web). These were the test levels, not the

failure threshold.

6

Submit Document Feedback

Product Folder Links: TPS23731

TPS23731

SLVSER7 – OCTOBER 2020

www.ti.com

7.3 Recommended Operating Conditions

Voltage with respect to V_SS(unless otherwise noted)

MIN

0

NOM

MAX

60

UNIT

VDD, RTN, GND, AGND

VCC to RTN

0

16

Input voltage range APD, EA_DIS, LINEUV, PSRS, FB, all to RTN

0

VB

2

V

CS to RTN

CP to GND

0

45

Voltage range

Sinking current

COMP to RTN

VB

VCC

0.65

3

V

T2P, APDO, all to RTN

0

RTN

A

T2P, APDO

mA

VCC

20

Sourcing current

mA

μF

VB

5

VB, VBG⁽¹⁾

0.08

0.7

0.1

1

Capacitance

Resistance

VCC

100

499

I_STOP

16.5

30

KΩ

Ω

CLS⁽¹⁾

REF⁽¹⁾

48.9

35

49.9

50.9

125

kΩ

ns

°C

Synchronization pulse width input (when used)

Operating junction temperature

T_J

–40

(1) Voltage should not be externally applied to this pin.

7.4 Thermal Information

RMT (VSON)

45 PINS

38.5

THERMAL METRIC

UNIT

(1)

R_θJA

Junction-to-ambient thermal resistance

R_θJC(top)

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

23.6

(1)

R_θJB

19.3

(1)

ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom PAD_S pad) thermal resistance

6.8

°C/W

(1)

ψ_JB

19.3

R_{θJC(bot_POE)}

3.9

R_{θJC(bot_DCDC)}Junction-to-case (bottom PAD_G pad) thermal resistance

9.1

(1) Thermal metrics are not JEDEC standard values and are based on the TPS23731EVM-095 evaluation board.

7.5 Electrical Characteristics: DC-DC Controller Section

Unless otherwise noted, V_VDD= 48 V; R_DEN= 25.5 kΩ; R_FRS= 60.4 kΩ; R_{I_STP}= 499 kΩ; CLS, T2P, APDO, and

PSRS open; CS, EA_DIS, APD, EMPS, AGND and GND connected to RTN; FB, LINEUV and DTHR connected

to VB; C_VB= C_VBG= 0.1 μF; C_VCC= 1 μF; C_SST= 0.047 μF; R_REF= 49.9 kΩ; 8.5 V ≤ V_VCC≤ 16 V; –40°C ≤ T_J≤

125°C. Positive currents are into pins unless otherwise noted. Typical values are at 25°C.

[V_VSS= V_RTN], all voltages referred to V_RTN, V_AGNDand V_GNDunless otherwise noted.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

DC-DC SUPPLY (VCC)

V_{CUVLO_}

V_VCCrising

8

5.85

2

8.25

6.1

8.5

6.35

2.3

V

R

V_{CUVLO_F}Undervoltage lockout

V_VCCfalling, V_FB= V_RTN

Hysteresis⁽¹⁾

V_{CUVLO_}

2.15

H

Submit Document Feedback

7

Product Folder Links: TPS23731

TPS23731

SLVSER7 – OCTOBER 2020

www.ti.com

7.5 Electrical Characteristics: DC-DC Controller Section (continued)

Unless otherwise noted, V_VDD= 48 V; R_DEN= 25.5 kΩ; R_FRS= 60.4 kΩ; R_{I_STP}= 499 kΩ; CLS, T2P, APDO, and

PSRS open; CS, EA_DIS, APD, EMPS, AGND and GND connected to RTN; FB, LINEUV and DTHR connected

to VB; C_VB= C_VBG= 0.1 μF; C_VCC= 1 μF; C_SST= 0.047 μF; R_REF= 49.9 kΩ; 8.5 V ≤ V_VCC≤ 16 V; –40°C ≤ T_J≤

125°C. Positive currents are into pins unless otherwise noted. Typical values are at 25°C.

[V_VSS= V_RTN], all voltages referred to V_RTN, V_AGNDand V_GNDunless otherwise noted.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

V_VCC= 10 V, V_FB= V_RTN, R_DT= 24.9 kΩ, CP with 2-

kΩ pull up to 30 V

I_RUN

Operating current

1.2

2

2.4

mA

V_APD= 2.5V

V_VDD≥ 28V, V_VCC= 11.7 V

V_VDD= 10.2V, V_VCC= 8.6 V

V_VDD= 10.2V, V_VCC= 6.8 V

21.5

1

30

6

34

17.5

32

I_{VC_ST}

Startup source current

8

16

V_VDD= 10.2 V, V_VCC(0) = 0 V, measure time until

V_{CUVLO_R}

0.25

0.24

0.7

1.15

0.48

ms

t_ST

Startup time, C_VCC= 1 μF

VCC startup voltage

V_VDD= 35 V, V_VCC(0) = 0 V, measure time until

V_{CUVLO_R}

0.35

Measure V_VCCduring startup, I_VCC= 0 mA

Measure V_VCCduring startup, I_VCC= 21.5 mA

11

12.5

14

V_{VC_ST}

V

V_LINEUV< V_LIUVF, Measure V_VCCduring soft-stop, I_VCC

= 0 mA

11

12.5

14

V_{VC_SSTP}VCC soft-stop voltage

V_LINEUV< V_LIUVF, Measure V_VCCduring soft-stop, I_VCC

= 21.5 mA

V_B

Voltage

V_FB= V_RTN, 8.5 V ≤ V_VCC≤ 16 V, 0 ≤ I_VB≤ 5 mA

4.75

5.0

5.25

V

kHz

V

DC-DC TIMING (FRS)

f_SW

Switching frequency

Duty cycle

V_FB= V_RTN, Measure at GATE

V_FB= V_RTN, R_DT= 24.9 kΩ, Measure at GATE

Input threshold

223

74.5%

2

248

78.5%

2.2

273

82.5%

2.4

D_MAX

V_SYNC

Synchronization

FREQUENCY DITHERING RAMP GENERATOR (DTHR)

3 x I_FRS

49.6

µA

V

I_DTRCHCharging (sourcing) current 0.5 V < V_DTHR< 1.5 V

47.2

52.1

3 x I_FRS

49.6

I_DTRDC

Discharging (sinking) current 0.5 V < V_DTHR< 1.5 V

47.2

1.41

52.1

1.60

V_DTUT

V_DTLT

V_DTPP

Dithering upper threshnold

Dithering lower threshold

Dithering pk-pk amplitude

V_DTHRrising until I_DTHR> 0

V_DTHRfalling until I_DTHR< 0

1.513

0.487

1.026

0.43

0.54

V

1.005

1.046

V

ERROR AMPLIFIER (FB, COMP)

V_REFC

I_{FB_LK}

Feedback regulation voltage

1.723

1.75

1.2

1.777

0.5

V

FB leakage current (source or

sink)

V_FB= 1.75 V

μA

Small signal unity gain

bandwidth

G_BW

0.9

MHz

A_OL

Open loop voltage gain

0% duty-cycle threshold

COMP source current

COMP sink current

70

1.35

1

80

db

V

V_ZDC

V_COMPfalling until GATE switching stops

V_FB= V_RTN, V_COMP= 3 V

1.5

1.65

I_COMPH

I_COMPL

mA

V

V_FB= V_VB, V_COMP= 1.25 V

2.1

4

6

V_COMPHCOMP high voltage

V_COMPLCOMP low voltage

V_FB= V_RTN, 15 kΩ from COMP to RTN

V_FB= V_VB, 15 kΩ from COMP to VB

VB

1.1

V

8

Submit Document Feedback

Product Folder Links: TPS23731

TPS23731

SLVSER7 – OCTOBER 2020

www.ti.com

7.5 Electrical Characteristics: DC-DC Controller Section (continued)

Unless otherwise noted, V_VDD= 48 V; R_DEN= 25.5 kΩ; R_FRS= 60.4 kΩ; R_{I_STP}= 499 kΩ; CLS, T2P, APDO, and

PSRS open; CS, EA_DIS, APD, EMPS, AGND and GND connected to RTN; FB, LINEUV and DTHR connected

to VB; C_VB= C_VBG= 0.1 μF; C_VCC= 1 μF; C_SST= 0.047 μF; R_REF= 49.9 kΩ; 8.5 V ≤ V_VCC≤ 16 V; –40°C ≤ T_J≤

125°C. Positive currents are into pins unless otherwise noted. Typical values are at 25°C.

[V_VSS= V_RTN], all voltages referred to V_RTN, V_AGNDand V_GNDunless otherwise noted.

PARAMETER

TEST CONDITIONS

MIN

TYP

100

0.2

MAX UNIT

COMP input resistance, error

amplifier disabled

EA_DIS open

70

130

kΩ

COMP to CS gain

ΔV_CS/ ΔV_COMP, 0 V < V_CS< 0.22 V

0.19

0.21

V/V

SOFT-START, SOFT-STOP (SST, I_STP)

I_SSC

Charge current

SST charging, 6.35 V ≤ V_VCC≤ 16 V

SST discharging, 6.35 V ≤ V_VCC≤ 16 V

7.5

3

10

4

12.5

5

µA

V

I_SSD

Discharge current

Soft-start lower threshold

V_SFST

0.15

1.99

0.2

2.1

0.25

2.21

V_STUOFStartup turn off threshold

V_SSTrising until VCC startup turns off

V

Soft-start offset voltage,

V_FB= V_RTN, V_SSTrising until start of switching

0.2

0.25

0.6

0.3

V

closed-loop mode

V_SSOFS

Soft-start offset voltage, peak V_COMP= V_VB, V_SSTrising until start of switching,

0.55

0.65

V

current mode

EA_DIS open

V_SSCL

Soft-start clamp

2.3

1.5

2.6

2.5

R_{I_STP}= 499 kΩ, V_LINEUV< V_LIUVF

R_{I_STP}= 16.5 kΩ, ,V_LINEUV< V_LIUVF

2

SST discharge current in soft-

stop mode

I_{SSD_SP}

µA

V

52.5

60.6

67.5

V_SSTPEN

End of soft-stop threshold

V_FB= V_RTN, V_LINEUV< V_LIUVF

0.15

0.2

0.25

D

CURRENT SENSE (CS)

V_CSMAXMaximum threshold voltage

t_{OFFD_IL}Current limit turn off delay

V_FB= V_RTN, V_CSrising

V_CS= 0.3 V

0.227

25

0.25

41

0.273

60

V

ns

PWM comparator turn off

t_{OFFD_PW}

delay

V_CS= 0.15 V, EA_DIS open, V_COMP= 2 V

In addtition to t_{OFFD_IL}and t_{OFFD_PW}

25

75

51

41

95

66

60

115

79

ns

Blanking delay

Internal slope compensation

V_FB= V_RTN, Peak voltage at maximum duty cycle,

referred to CS

V_SLOPE

voltage

mV

Peak slope compensation

current

V_FB= V_RTN, I_CSat maximum duty cycle (ac

component)

I_{SL_EX}

14

-3

20

-2

26

-1

μA

Bias current

DC component of CS current

LINE UNDERVOLTAGE, SOFT-STOP (LINEUV)

V_LIUVF

V_LIUVH

V_LINEUVfalling

Hysteresis⁽¹⁾

V_LINEUV= 3 V

2.86

57

2.918

82

2.976

107

1

V

LINEUV falling threshold

voltage

mV

µA

Leakage current

GATE

V_FB= V_RTN, V_VCC= 10 V, V_GATE= 0 V, pulsed

measurement

Peak source current

Peak sink current

0.3

0.6

0.5

0.9

0.8

A

V_FB= V_RTN, V_VCC= 10 V, V_GATE= 10 V, pulsed

measurement

1.45

Rise time⁽²⁾

Fall time⁽²⁾

t_prr10-90, C_GATE= 1 nF , V_VCC= 10 V

t_pff90-10, C_GATE= 1 nF , V_VCC= 10 V

30

15

ns

CLAMPING FET (CP)

R_DS(ON)C

CP FET on resistance

I_CP= 100 mA

1.5

3.3

Ω

L

CLAMPING DIODE (CP)

Submit Document Feedback

9

Product Folder Links: TPS23731

TPS23731

SLVSER7 – OCTOBER 2020

www.ti.com

7.5 Electrical Characteristics: DC-DC Controller Section (continued)

Unless otherwise noted, V_VDD= 48 V; R_DEN= 25.5 kΩ; R_FRS= 60.4 kΩ; R_{I_STP}= 499 kΩ; CLS, T2P, APDO, and

PSRS open; CS, EA_DIS, APD, EMPS, AGND and GND connected to RTN; FB, LINEUV and DTHR connected

to VB; C_VB= C_VBG= 0.1 μF; C_VCC= 1 μF; C_SST= 0.047 μF; R_REF= 49.9 kΩ; 8.5 V ≤ V_VCC≤ 16 V; –40°C ≤ T_J≤

125°C. Positive currents are into pins unless otherwise noted. Typical values are at 25°C.

[V_VSS= V_RTN], all voltages referred to V_RTN, V_AGNDand V_GNDunless otherwise noted.

PARAMETER

TEST CONDITIONS

V_PSRS= 0 V, I_CP= 15 mA

V_PSRS= 0 V, V_CP= 45 V

MIN

TYP

MAX UNIT

V_FCP

CP Diode forward voltage

CP Leakage current

0.45

0.6

0.85

20

V

µA

AUXILIARY POWER DETECTION (APD, APDO)

V_APDEN

V_APDH

V_APDrising

1.42

1.5

1.58

0.115

1

V

APD threshold voltage

Hysteresis⁽¹⁾

0.075

0.095

Leakage current

V_APD= 5 V

µA

V

V_APL

APDO output low voltage

Leakage current

V_APD= 5 V, I_APDO= 1 mA, startup has completed

V_APDO= 10 V

0.27

0.5

1

µA

THERMAL SHUTDOWN

Turnoff temperature

Hysteresis⁽²⁾

145

155

15

165

°C

(1) The hysteresis tolerance tracks the rising threshold for a given device.

(2) These parameters are provided for reference only, and do not constitute part of TI's published device specifications for purposes of TI's

product warranty.

7.6 Electrical Characteristics PoE

Unless otherwise noted, V_VDD= 48 V; R_DEN= 25.5 kΩ; R_FRS= 60.4 kΩ; R_{I_STP}= 499 kΩ; CLS, T2P, APDO, and

PSRS open; CS, EA_DIS, APD, EMPS, AGND and GND connected to RTN; FB, LINEUV and DTHR connected

to VB; C_VB= C_VBG= 0.1 μF; C_VCC= 1 μF; C_SST= 0.047 μF; R_REF= 49.9 kΩ; –40°C ≤ T_J≤ 125°C. Positive

currents are into pins unless otherwise noted. Typical values are at 25°C.

V_VCC-RTN= 0 V, all voltages referred to V_VSSunless otherwise noted.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

PD DETECTION (DEN)

DEN open, V_VDD= 10 V, Not in mark, Measure

I_VDD+ I_RTN

Detection bias current

3.5

6.9

13.9

µA

I_lkg

DEN leakage current

Detection current

V_DEN= V_VDD= 60 V, Float RTN, Measure I_DEN

Measure I_VDD+ I_DEN+ I_RTN, V_VDD= 1.4 V

0.1

5

µA

μA

53.5

391

56.5

58.6

Measure I_VDD+ I_DEN+ I_RTN, V_VDD= 10 V, Not in

mark

398

4

406.2

5

μA

V

Hotswap disable

threshold

V_{PD_DIS}

DEN falling

3

PD CLASSIFICATION (CLS)

13 V ≤ V_DD≤ 21 V,

R_CLS= 806 Ω

R_CLS= 130 Ω

R_CLS= 69.8 Ω

R_CLS= 46.4 Ω

Measure I_VDD+ I_DEN

I_RTN

+

1.9

9.9

2.5

10.6

18.6

27.9

2.9

11.3

19.4

29.3

mA

13 V ≤ V_DD≤ 21 V,

Measure I_VDD+ I_DEN

I_RTN

Classification signature

current

I_CLS

13 V ≤ V_DD≤ 21 V,

Measure I_VDD+ I_DEN

I_RTN

17.6

26.5

13 V ≤ V_DD≤ 21 V,

Measure I_VDD+ I_DEN

I_RTN

10

Submit Document Feedback

Product Folder Links: TPS23731

TPS23731

SLVSER7 – OCTOBER 2020

www.ti.com

7.6 Electrical Characteristics PoE (continued)

Unless otherwise noted, V_VDD= 48 V; R_DEN= 25.5 kΩ; R_FRS= 60.4 kΩ; R_{I_STP}= 499 kΩ; CLS, T2P, APDO, and

PSRS open; CS, EA_DIS, APD, EMPS, AGND and GND connected to RTN; FB, LINEUV and DTHR connected

to VB; C_VB= C_VBG= 0.1 μF; C_VCC= 1 μF; C_SST= 0.047 μF; R_REF= 49.9 kΩ; –40°C ≤ T_J≤ 125°C. Positive

currents are into pins unless otherwise noted. Typical values are at 25°C.

V_VCC-RTN= 0 V, all voltages referred to V_VSSunless otherwise noted.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

13 V ≤ V_DD≤ 21 V,

R_CLS= 32 Ω

Measure I_VDD+ I_DEN

I_RTN

+

37.8

39.9

42

mA

13 V ≤ V_DD≤ 21 V,

Measure I_VDD+ I_DEN

I_RTN

Classification signature

current, 3rd class event

I_CLS

37.8

39.9

42

mA

Classification regulator

lower threshold rising

V_{CL_ON}

V_{CL_H}

V_VDDrising, I_CLS

Hysteresis⁽¹⁾

↑

↓

11.4

0.8

12.2

1.2

13

V

Classification regulator

lower threshold

1.6

V_{CU_OFF}

V_{CU_H}

V_VDDrising, I_CLS

Hysteresis⁽¹⁾

21

22

23

1

V

Classification regulator

upper threshold

0.5

0.77

Mark state reset

threshold

V_MSR

V_VDDfalling

3

6

3.9

10

5

12

1

V

Mark state resistance

Leakage current

2-point measurement at 5 V and 10.1 V

kΩ

μA

V_VDD= 60 V, V_CLS= 0 V, V_DEN= V_VSS, Measure

I_CLS

I_lkg

Long first class event

timing

t_{LCF_PD}

Class 1st event time duration for short MPS

76

81.5

87

ms

RTN (PASS DEVICE)

ON-resistance

0.3

0.55

1.1

Ω

A

I_LIM

Current limit

V_RTN= 1.5 V, pulsed measurement

0.75

100

0.925

V_RTN= 2 V, V_VDD: 20 V → 48 V, measure I_RTN

pulsed measurement

,

I_IRSH

inrush current limit

140

180

mA

Percentage of inrush current.

Inrush delay

80%

80

90%

84

99%

88

Inrush termination

t_{INR_DEL}

ms

V

Foldback voltage

threshold

V_RTNrising

13.5

1.5

14.8

1.8

16.1

V_RTNrising to when current limit changes to

Foldback deglitch time inrush current limit. This applies in normal

operating condition or during auto MPS mode.

2.1

70

ms

μA

Leakage current

V_VDD= V_RTN= 100 V, V_DEN= V_VSS

PSE TYPE INDICATION (T2P)

I_T2P= 1 mA, after 2- or 3-event classification,

startup has completed, V_RTN= 0 V

Output low voltage

0.27

0.5

1

V

Leakage current

V_T2P-RTN= 10 V, V_RTN= 0 V

µA

PD INPUT SUPPLY (VDD)

Undervoltage lockout

threshold

V_{UVLO_R}

V_VDDrising

V_VDDfalling

Hysteresis ⁽¹⁾

35.8

30.5

5.7

37.6

32

39.5

33.6

6.3

V

Undervoltage lockout

threshold

V_{UVLO_F}

Undervoltage lockout

threshold

V_{UVLO_H}

6.0

650

V

40 V ≤ V_VDD≤ 60 V, Startup completed, V_VCC

10 V, Measure I_VDD

=

I_{VDD_ON}

Operating current

1040

µA

Submit Document Feedback

11

Product Folder Links: TPS23731

TPS23731

SLVSER7 – OCTOBER 2020

www.ti.com

7.6 Electrical Characteristics PoE (continued)

Unless otherwise noted, V_VDD= 48 V; R_DEN= 25.5 kΩ; R_FRS= 60.4 kΩ; R_{I_STP}= 499 kΩ; CLS, T2P, APDO, and

PSRS open; CS, EA_DIS, APD, EMPS, AGND and GND connected to RTN; FB, LINEUV and DTHR connected

to VB; C_VB= C_VBG= 0.1 μF; C_VCC= 1 μF; C_SST= 0.047 μF; R_REF= 49.9 kΩ; –40°C ≤ T_J≤ 125°C. Positive

currents are into pins unless otherwise noted. Typical values are at 25°C.

V_VCC-RTN= 0 V, all voltages referred to V_VSSunless otherwise noted.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

RTN, GND and VCC open, V_VDD= 30 V, Measure

I_VDD

I_{VDD_OFF}

MPS

Off-state current

730

µA

MPS total VSS current EMPS open, inrush delay has completed, 0 mA ≤

for Type 1-2 PSE I_RTN≤ 10 mA, measure I_VSS

I_MPSL

10

16.25

26.2%

76

12.5

19

15.5

21.5

26.9%

87

mA

MPS total VSS current EMPS open, inrush delay has completed, 0 mA ≤

I_MPSH

for Type 3-4 PSE

I_RTN≤ 16 mA, measure I_VSS

MPS pulsed current

duty-cycle

EMPS open

26.6%

81.5

225

MPS pulsed mode duty MPS pulsed current ON

cycle for Type 1-2 PSE time

t_MPSL

EMPS open

ms

MPS pulsed current

OFF time

245

MPS pulsed current

duty-cycle, no pulse

stretching

EMPS open

2.9%

7.2

3.0%

7.7

3.1%

8.1

MPS pulsed current ON

time, no pulse

stretching

t_MPSH

ms

MPS pulsed mode duty-

cycle for Type 3-4 PSE

MPS pulsed current

OFF time

EMPS open

238

54

250

57

265

62

ms

MPS pulsed current ON

time stretching limit

THERMAL SHUTDOWN

Turnoff temperature

Hysteresis⁽²⁾

148

158

15

168

°C

(1) The hysteresis tolerance tracks the rising threshold for a given device.

(2) These parameters are provided for reference only.

12

Submit Document Feedback

Product Folder Links: TPS23731

TPS23731

SLVSER7 – OCTOBER 2020

www.ti.com

7.7 Typical Characteristics

12.5

0.96

0.95

0.94

0.93

0.92

0.91

0.9

10

7.5

5

T_J= -40èC

T_J= 25èC

T_J= 125èC

2.5

0

1

2

3

4

VDD-VSS Voltage (V)

5

6

7

8

9

10

-50

-25

0

25

50

75

100

125

Junction Temperature (èC)

D001

D003

Figure 7-1. Detection Bias Current vs Voltage

Figure 7-2. PoE Current Limit vs Temperature

0.5

1000

950

900

850

800

750

700

650

0.45

0.4

0.35

0.3

T_J= -40èC

T_J= 25èC

T_J= 125èC

600

550

500

0.25

0.2

-50

-25

0

25

50

75

100

125

25

30

35

40 45

VDD-VSS Voltage (V)

50

55

60

Junction Temperature (èC)

D004

D005

Figure 7-3. Pass FET Resistance vs Temperature

Figure 7-4. VDD Supply Current vs Voltage

35

34

33

32

31

30

29

28

27

26

25

35

34

33

32

31

30

29

28

27

26

25

V_VCC= 11.7 V

T_J= -40èC

T_J= 25èC

V_VCC= 6.8 V

T_J= -40èC

T_J= 25èC

24

23

22

21

20

24

23

22

21

20

T_J= 125èC

15

20

25

30

VDD-RTN Voltage (V)

35

40

45

50

55

60

10

15

20

25

VDD-RTN Voltage (V)

30

35

40

45

50

55

D006

D007

Figure 7-5. Converter Startup Current vs VDD Input Figure 7-6. Converter Startup Current vs VDD Input

Voltage

Submit Document Feedback

13

Product Folder Links: TPS23731

TPS23731

SLVSER7 – OCTOBER 2020

www.ti.com

13

12.5

12

65

60

55

50

45

40

35

30

25

20

15

10

5

11.5

11

10.5

10

9.5

9

T_J= -40èC

T_J= 25èC

T_J= 125èC

8.5

8

0

3

6

9

12

15

18

21

VCC Sourcing Current (mA)

24

27

30

0

50 100 150 200 250 300 350 400 450 500

I_STP Programmable Resistance (kW)

D008

D009

Figure 7-7. Converter Startup Voltage vs Current

Figure 7-8. Controller SST Soft Stop Sink Current

vs Programmed Resistance

3

2.9

2.8

2.7

2.6

2.5

2.4

2.3

2.2

450

400

R_FRS= 37.4 kW

R_FRS= 60.4 kW

R_FRS= 301 kW

350

300

250

200

150

100

50

2.1

R_FRS= 37.4 kW

2

R_FRS= 60.4 kW

1.9

1.8

1.7

1.6

1.5

R_FRS= 301 kW

0

9

9.75

10.5

11.25 12

VCC Voltage (V)

12.75

13.5

-50

-25

0

25

50

75

100

125

Junction Temperature (èC)

D010

D011

Figure 7-9. Controller Bias Current vs Voltage

Figure 7-10. Switching Frequency vs Temperature

800

81

80.5

80

R_FRS= 37.4 kW

600

400

200

0

R_FRS= 60.4 kW

79.5

R_FRS= 301 kW

79

78.5

78

77.5

77

76.5

76

0

5

10

15

20

25

30

35

40

45

50

-50

-25

0

25

50

75

100

125

Programmable Conductance (10⁶/R_FRS(W^-1

)

Junction Temperature (èC)

D012

D013

Figure 7-11. Switching Frequency vs Programmed Figure 7-12. Maximum Duty Cycle vs Temperature

Resistance

14

Submit Document Feedback

Product Folder Links: TPS23731

TPS23731

SLVSER7 – OCTOBER 2020

www.ti.com

1.76

1.758

1.756

1.754

1.752

1.75

24

23.2

22.4

21.6

20.8

20

1.748

1.746

1.744

1.742

1.74

19.2

18.4

17.6

16.8

16

-50

-25

0

25

50

75

100

125

-50

-25

0

25

50

75

100

125

Junction Temperature (èC)

D014

D015

Figure 7-13. Feedback Regulation Voltage vs

Temperature

Figure 7-14. Current Slope Compensation Current

vs Temperature

100

99.5

99

4

T_J= -40èC

3.6

T_J= 25èC

T_J= 125èC

3.2

2.8

2.4

2

98.5

98

97.5

97

1.6

1.2

0.8

0.4

0

96.5

96

95.5

95

-50

-25

0

25

50

75

100

125

0

0.5

1

1.5

2

COMP Voltage (V)

2.5

3

3.5

4

4.5

5

Junction Temperature (èC)

D016

D019

Figure 7-15. Blanking Period vs Temperature

Figure 7-16. Error Amplifier Source Current

20

18

16

14

12

10

8

100

T_J= -40èC

T_J= 25èC

T_J= 125èC

90

80

70

60

50

40

30

20

10

0

6

T_J= -40èC

T_J= 25èC

T_J= 125èC

4

2

0

-10

-20

100

1k

10k 100k

Frequency (Hz)

1M

5M

0

0.4 0.8 1.2 1.6

2

COMP Voltage (V)

2.4 2.8 3.2 3.6

4

D021

D020

Figure 7-18. Error Amplifier Gain vs Frequency

Figure 7-17. Error Amplifier Sink Current

Submit Document Feedback

15

Product Folder Links: TPS23731

TPS23731

SLVSER7 – OCTOBER 2020

www.ti.com

135

120

105

90

75

60

45

30

15

0

T_J= -40èC

T_J= 25èC

T_J= 125èC

100

1k

10k 100k

Frequency (Hz)

1M

5M

D022

Figure 7-19. Error Amplifier Phase vs Frequency

16

Submit Document Feedback

Product Folder Links: TPS23731

TPS23731

SLVSER7 – OCTOBER 2020

www.ti.com

8 Detailed Description

8.1 Overview

The TPS23731 device is a 45-pin integrated circuit that contains all of the features needed to implement a single

interface IEEE 802.3bt Type 3 Class 1-4 and IEEE802.3at powered device (PD), combined with a current-mode

DC-DC controller optimized for flyback switching regulator design. The TPS23731 applies to flyback converter

applications, also supporting the use of primary side control.

Basic PoE PD functionality supported includes detection, hardware classification, and inrush current limit during

startup. DC-DC converter features include startup function and current mode control operation. The TPS23731

device integrates a low 0.3-Ω internal switch to minimize heat dissipation and maximize power utilization.

A number of input voltage Oring options or input voltage ranges are also supported by use of APD input.

The TPS23731 device contains several protection features such as thermal shutdown, current limit foldback, and

a robust 100-V internal return switch.

Submit Document Feedback

17

Product Folder Links: TPS23731

TPS23731

SLVSER7 – OCTOBER 2020

www.ti.com

8.2 Functional Block Diagram

18

Submit Document Feedback

Product Folder Links: TPS23731

TPS23731

SLVSER7 – OCTOBER 2020

www.ti.com

8.3 Feature Description

See Figure 9-1 for component reference designators (R_CSfor example ), and Electrical Characteristics: DC-DC

Controller Section for values denoted by reference (V_CSMAXfor example). Electrical Characteristic values take

precedence over any numerical values used in the following sections.

8.3.1 CLS Classification

An external resistor (R_CLSin Figure 9-1 ) connected between the CLS pin and VSS provides a classification

signature to the PSE. The controller places a voltage of approximately 1.25 V across the external resistor

whenever the voltage differential between VPD and VSS lies from about 11 V to 22 V. The current drawn by this

resistor, combined with the internal current drain of the controller and any leakage through the internal pass

MOSFET, creates the classification current. Table 8-1 lists the external resistor values required for each of the

PD power ranges defined by IEEE802.3at. The maximum average power drawn by the PD, plus the power

supplied to the downstream load, should not exceed the maximum power indicated in Table 8-1. The TPS23731

supports class 0 – 4 power levels. Holding APD high disables the classification signatures.

Table 8-1. Class Resistor Selection

POWER AT PD PI

CLASS

RESISTOR (Ω)

MINIMUM (W)

0.44

MAXIMUM (W)

12.95

0

1

2

3

4

806

130

69.8

46.4

32

0.44

3.84

6.49

12.95

25.5

8.3.2 DEN Detection and Enable

DEN pin implements two separate functions. A resistor (R_DENin Figure 9-1) connected between VDD and DEN

generates a detection signature whenever the voltage differential between VDD and VSS lies from

approximately 1.4 to 10.9 V. Beyond this range, the controller disconnects this resistor to save power. The IEEE

802.3bt and IEEE 802.3at standards specify a detection signature resistance, R_detectfrom 23.75 kΩ to 26.25 kΩ,

or 25 kΩ ± 5%. TI recommends a resistor of 25.5 kΩ ± 1% for R_DEN

.

Pulling DEN to VSS during powered operation causes the internal hotswap MOSFET and class regulator to turn

off. If the resistance connected between VDD and DEN is divided into two roughly equal portions, then the

application circuit can disable the PD by grounding the tap point between the two resistances, while

simultaneously spoiling the detection signature which prevents the PD from properly re-detecting.

8.3.3 APD Auxiliary Power Detect

The APD pin is used in applications that may draw power either from the Ethernet cable or from an auxiliary

power source. When a voltage of more than about 1.5 V is applied on the APD pin relative to RTN, the

TPS23731 does the following:

•

Internal pass MOSFET is turned off

Classification current is disabled

The LINEUV input is disabled

Maintain Power Signature (MPS) pulsed mode is disabled

T2P and APDO outputs are turned on (low state)

This also gives adapter source priority over the PoE. A resistor divider (R_APD1–R_APD2in Figure 9-1) provides

system-level ESD protection for the APD pin, discharges leakage from the blocking diode (D_Ain Figure 9-1) and

provides input voltage supervision to ensure that switch-over to the auxiliary voltage source does not occur at

excessively low voltages. If not used, connect APD to RTN.

Submit Document Feedback

19

Product Folder Links: TPS23731

TPS23731

SLVSER7 – OCTOBER 2020

www.ti.com

8.3.4 Internal Pass MOSFET

RTN pin provides the negative power return path for the load. It is internally connected to the drain of the PoE

hotswap MOSFET, and the DC-DC controller return. RTN must be treated as a local reference plane (ground

plane) for the DC-DC controller and converter primary to maintain signal integrity.

Once V_VDDexceeds the UVLO threshold, the internal pass MOSFET pulls RTN to VSS. Inrush limiting prevents

the RTN current from exceeding a nominal value of about 140 mA until the bulk capacitance (C_BULKin Figure

9-1) is fully charged. Two conditions must be met to reach the end of inrush phase. The first one is when the

RTN current drops below about 90% of nominal inrush current at which point the current limit is changed to

0.925 A, while the second one is to ensure a minimum inrush delay period of 80 ms (t_{INR_DEL}) from beginning of

the inrush phase. DC-DC converter switching is permitted once both inrush conditions are met, meaning that the

bulk capacitance is fully charged and the inrush period has been completed.

If V_RTN- V_VSSever exceeds about 14.8 V for longer than 1.8 ms, then the PD returns to inrush limiting; note that

in this particular case, the second condition described above about inrush phase duration (80 ms) is not

applicable

8.3.5 T2P and APDO Indicators

The state of T2P is used to provide information relative to the allocated power. Table 8-2 lists T2P state

corresponding to various combinations of PSE Type, PD Class and allocated power. The allocated power is

determined by the number of classification cycles having been received. The PSE may also allocate a lower

power than what the PD is requesting, in which case there is power demotion. The APDO output can also be

used to indicate the presence of auxiliary power adapter via the APD input.

Table 8-2. T2P and Allocated Power Truth Table, with APD Low

NUMBER OF CLASS

CYCLES

PSE ALLOCATED

POWER AT PD (W)

PSE TYPE

PD CLASS

T2P⁽¹⁾

1-4

2

0

1

2

3

4

1

12.95

3.84

6.49

12.95

25.5

HIGH

LOW

1

2

3-4

2,3

(1) If APD is high, both T2P and APDO outputs become low.

During startup, the T2P output is enabled only once the DC-DC controller has reached steady-state, the soft-

start having been completed. This output will return to a high-impedance state in any of the following cases:

•

DC-DC controller is back to soft-start mode

DC-DC controller transitions to soft-stop mode

DC-DC controller shuts off due to reasons including V_VCCfalling below V_{CUVLO_F}, or the PoE hotswap is in

inrush limit while APD is low

•

The device enters thermal shutdown

Note that in all these cases, as long as VDD-to-VSS voltage remains above the mark reset threshold, the

internal logic state of this signal is remembered such that this output will be activated accordingly after the soft-

start has completed. This circuit resets when the VDD-to-VSS voltage drops below the mark reset threshold. The

T2P can be left unconnected if not used.

8.3.6 DC-DC Controller Features

The TPS23731 device DC-DC controller implements a typical current-mode control as shown in Functional Block

Diagram. Features include oscillator, overcurrent and PWM comparators, current-sense blanker, soft-start, soft-

stop and gate driver. In addition, an internal current-compensation ramp generator, frequency synchronization

logic, built-in frequency dithering functionality, thermal shutdown, and start-up current source with control are

provided.

20

Submit Document Feedback

Product Folder Links: TPS23731

TPS23731

SLVSER7 – OCTOBER 2020

www.ti.com

The TPS23731 is optimized for isolated converters, supporting the use of PSR (flyback configuration) and

optocoupler feedback .

To support PSR, the TPS23731 includes an internal error amplifier, and the voltage feedback is from the bias

winding.

If optocoupler feedback is used, the error amplifier is disabled (by use of EA_DIS input). In this case, the

optocoupler output directly drives the COMP pin which serves as a current-demand control to the PWM.

In both cases, the COMP signal is directly fed to a 5:1 internal resistor divider and an offset of V_ZDC/5 (~0.3 V)

which defines a current-demand control for the pulse width modulator (PWM). A V_COMPbelow V_ZDCstops

converter switching, while voltages above (V_ZDC+ 5 × (V_CSMAX+ V_SLOPE)) does not increase the requested peak

current in the switching MOSFET.

The internal start-up current source and control logic implement a bootstrap-type startup. The startup current

source charges C_VCCfrom VDD and maintain its voltage when the converter is disabled or during the soft-start

period, while operational power must come from a converter (bias winding) output.

The bootstrap source provides reliable start-up from widely varying input voltages, and eliminates the continual

power loss of external resistors.

The peak current limit does not have duty cycle dependency unless R_Sis used as shown in Figure 8-2 to

increase slope compensation. This makes it easier to design the current limit to a fixed value.

The DC-DC controller has an OTSD that can be triggered by heat sources including the VB regulator, GATE

driver, bootstrap current source, and bias currents. The controller OTSD turns off VB, the switching FET, resets

the soft-start generator, and forces the VCC control into an undervoltage state.

8.3.6.1 VCC, VB, VBG and Advanced PWM Startup

The VCC pin connects to the auxiliary bias supply for the DC-DC controller. The switching MOSFET gate driver

draws current directly from the VCC pin. VB and VBG outputs are regulated down from VCC voltage, the former

providing power to the internal control circuitry and external feedback optocoupler (when in use), and the latter

providing power to the switching FET gate predriver circuit. A startup current source from VDD to VCC

implements the converter bootstrap startup. VCC must receive power from an auxiliary source, such as an

auxiliary winding on the flyback transformer, to sustain normal operation after startup.

The startup current source is turned on during the inrush phase, charging C_VCCand maintaining its voltage, and

it is turned off only after the DC-DC soft-start cycle has been completed, which occurs when the DC-DC

converter has ramped up its output voltage and V_SSThas exceed approximately 2.1 V (V_STUOF), as shown in

Figure 8-1. Internal loading on VCC, VB and VBG is initially minimal while C_VCCcharges, to allow the converter

to start. Due to the high current capability of the startup source, the recommended capacitance at VCC is

relatively small, typically 1 μF in most applications.

Once V_VCCfalls below its UVLO threshold (V_{CUVLO_F}, approximately 6.1 V), the converter shuts off and the

startup current source is turned back on, initiating a new PWM startup cycle.

If however a V_VCCfall (below approximately 7.1 V) is due to a light load condition causing temporary switching

stop, the startup is immediately and for a short period turned back on to bring VCC voltage back up, with no

converter interruption.

Submit Document Feedback

21

Product Folder Links: TPS23731

TPS23731

SLVSER7 – OCTOBER 2020

www.ti.com

t_inrushmax

PSE

PD

Operational Mode

PSE Inrush

t_inrushmin

VCC Startup Source ON

End of Soft-Start, Startup source

turned off

PD + Power Supply Fully

Operational

HSW cap

recharge

Soft Start

Wait

High current startup is ON for the whole soft-start

cycle to allow low VCC capacitance

Ensures interoperability with

PSE inrush limit

Figure 8-1. Advanced Startup

Note that the startup current source is also turned on while in soft-stop mode.

8.3.6.2 CS, Current Slope Compensation and blanking

The current-sense input for the DC-DC converter should be connected to the high side of the current-sense

resistor of the switching MOSFET. This voltage drives the current limit comparator and the PWM comparator

(see Block Diagram of DC-DC controller). A leading-edge blanking circuit prevents MOSFET turn-on transients

from falsely triggering either of these comparators. During the off time, and also during the blanking time that

immediately follows, the CS pin is pulled to AGND through an internal pulldown resistor.

The current limit comparator terminates the on-time portion of the switching cycle as soon as V_CSexceeds

approximately 250 mV (V_CSMAX) and the leading edge blanking interval has expired. If the converter is not in

current limit, then either the PWM comparator or the maximum duty cycle limiting (D_MAX) circuit terminates the

on time.

Current-mode control requires addition of a compensation ramp to the sensed inductive (transformer or inductor)

current for stability at duty cycles near and over 50%. The TPS23731 provides an internal slope compensation

circuit which generates a current that imposes a voltage ramp at the positive input of the PWM comparator to

suppress sub-harmonic oscillations. This current flows out of the CS pin. If desired, the magnitude of the slope

compensation can be increased by the addition of an external resistor R_S(see Figure 8-2) in series with the CS

pin. It works with ramp current (I_PK= I_SL-EX, approximately 20 μA) that flows out of the CS pin when the MOSFET

is on. The I_PKspecification does not include the approximately 2-μA fixed current that flows out of the CS pin.

The TPS23731 has a maximum duty cycle limit of 78%, permitting the design of wide input-range converters with

a lower voltage stress on the output rectifiers. While the maximum duty cycle is 78%, converters may be

designed that run at duty cycles well below this for a narrower, 36-V to 57-V range.

Most current-mode control papers and application notes define the slope compensation values in terms of

V_PP/T_S(peak ramp voltage / switching period); however, Electrical Characteristics: DC-DC Controller Section

specifies the slope peak (V_SLOPE) based on the maximum duty cycle. Assuming that the desired slope, V_SLOPE-D

(in mV/period), is based on the full period, compute R_Sper Equation 1 where V_SLOPE, D_MAX, and I_SL-EXare from

Electrical Characteristics: DC-DC Controller Section with voltages in mV, current in μA, and the duty cycle is

unitless (for example, D_MAX= 0.78).

V_SLOPE(mV)

:

;

BV_{SLOP E_D}mV F @

W

AC

D_MAX

: ;

R_S3 =

× 1000

I_{SL_EX}(JA)

(1)

22

Submit Document Feedback

Product Folder Links: TPS23731

TPS23731

SLVSER7 – OCTOBER 2020

www.ti.com

GATE

CS

R_S

R_CS

C_S

Figure 8-2. Additional Slope Compensation

The TPS23731 blanker timing is precise enough that the traditional R-C filters on CS can be eliminated. This

avoids current-sense waveform distortion, which tends to get worse at light output loads. There may be some

situations or designers that prefer an R-C approach, for example if the presence of R_Scauses increased noise,

due to adjacent noisy signals, to appear at CS pin. The TPS23731 provides a pulldown on CS (~400 Ω) during

the GATE OFF-time to improve sensing when an R-C filter must be used, by reducing cycle-to-cycle carry-over

voltage on C_S.

Routing between the current-sense resistor and the CS pin should be short to minimize cross-talk from noisy

traces such as the gate drive signal and the CP signal.

8.3.6.3 COMP, FB, EA_DIS, CP, PSRS and Opto-less Feedback

The TPS23731 DC-DC controller implements current-mode control as shown in Functional Block Diagram, using

internal (via pins FB input and COMP output, with EA_DIS pulled low) or external (via COMP input, with EA_DIS

open) voltage control loop error amplifier to define the input reference voltage of the current mode control

comparator which determines the switching MOSFET peak current.

V_COMPbelow V_ZDCcauses the converter to stop switching. The maximum (peak) current is requested at

approximately (V_ZDC+ 5 × (V_CSMAX+ V_SLOPE)). The AC gain from COMP to the PWM comparator is typically 0.2.

In flyback applications and with the internal error amplifier enabled, the TPS23731 DC-DC controller can operate

with feedback from an auxiliary winding of the flyback power transformer to achieve primary side regulation

(PSR), eliminating the need for external shunt regulator and optocoupler. One noteworthy characteristic of this

PSR is that it operates with continuous (DC) feedback, enabling better optimization of the power supply, and

resulting in significantly lower noise sensitivity.

When combined with secondary-side synchronous rectification (with PSRS open), the opto-less operation of the

TPS23731 is achieved with a unique approach which basically consists in actively cancelling (through the use of

CP output) the leading-edge voltage overshoot (causing the feedback capacitor to peak-charge) generated by

the transformer winding. When combined with a correctly designed power transformer, less than ±1.5% load

regulation (typical) over the full output current range becomes achievable in applications making use of

secondary-side synchronous rectifiers. Operation is in continuous conduction mode (CCM), also enabling multi-

output architectures.

Opto-less operation of the TPS23731 also applies (with PSRS pulled low) to single-output flyback converter

applications where a secondary-side diode rectifier is used. In typical 12-V output application and when

combined with a correctly designed power transformer, ~±3% load regulation over a wide (< 5% to 100%) output

current range can be achieved.

In applications where the internal error amplifier is disabled, the COMP pin receives the control voltage typically

from a TL431 or TLV431 shunt regulator driving an optocoupler, using VB pin as a pull up source, although other

configurations are possible.

Submit Document Feedback

23

Product Folder Links: TPS23731

TPS23731

SLVSER7 – OCTOBER 2020

www.ti.com

8.3.6.4 FRS Frequency Setting and Synchronization

The FRS pin programs the (free-running) oscillator frequency, and may also be used to synchronize the

TPS23731 converter to a higher frequency. The internal oscillator sets the maximum duty cycle and controls the

current-compensation ramp circuit, making the ramp height independent of frequency. R_FRSmust be selected

per Equation 2.

15000

R_FRS(k3) =

f_SW(kHz)

(2)

The TPS23731 may be synchronized to an external clock to eliminate beat frequencies from a sampled system,

or to place emission spectrum away from an RF input frequency. Synchronization may be accomplished by

applying a short pulse ( > 25 ns) of magnitude V_SYNCto FRS as shown in Figure 8-3. R_FRSmust be chosen so

that the maximum free-running frequency is just below the desired synchronization frequency. The

synchronization pulse terminates the potential ON-time period, and the OFF-time period does not begin until the

pulse terminates. A short pulse is preferred to avoid reducing the potential ON-time.

Figure 8-3 shows examples of nonisolated and transformer-coupled synchronization circuits. RT reduces noise

susceptibility for the isolation transformer implementation. The FRS node must be protected from noise because

it is high impedance.

Synchronization

Pulse

FRS

Pulse

FRS

47pF

1000pF

T_SYNC

V_SYNC

T_SYNC

1:1

V_SYNC

Figure 8-3. Synchronization

8.3.6.5 DTHR and Frequency Dithering for Spread Spectrum Applications

The international standard CISPR 22 (and adopted versions) is often used as a requirement for conducted

emissions. Ethernet cables are covered as a telecommunication port under section 5.2 for conducted emissions.

Meeting EMI requirements is often a challenge, with the lower limits of Class B being especially hard. Circuit

board layout, filtering, and snubbing various nodes in the power circuit are the first layer of control techniques. A

more detailed discussion of EMI control is presented in Practical Guidelines to Designing an EMI Compliant PoE

Powered Device With Isolated Flyback, SLUA469. Additionally, IEEE 802.3at sections 33.3 and 33.4 and IEEE

802.3bt sections 145.3 and 145.4 have requirements for noise injected onto the Ethernet cable based on

compatibility with data transmission.

A technique referred to as frequency dithering can also be used to provide additional EMI measurement

reduction. The switching frequency is modulated to spread the narrowband individual harmonics across a wider

bandwidth, thus lowering peak measurements.

Fully programmable frequency dithering is a built-in feature of the TPS23731. The oscillator frequency can be

dithered by connecting a capacitor from DTHR to RTN and a resistor from DTHR to FRS. An external capacitor,

C_DTR(Figure 9-1), is selected to define the modulation frequency f_m. This capacitor is being continuously

charged and discharged between slightly less than 0.5 V and slightly above 1.5 V by a current source/sink

equivalent to ~3x the current through FRS pin. C_DTRvalue is defined according to:

3

W

R_FRS(3)

C_DTR

=

2.052 × f_m(Hz)

(3)

24

Submit Document Feedback

Product Folder Links: TPS23731

TPS23731

SLVSER7 – OCTOBER 2020

www.ti.com

f_mshould always be higher than 9 kHz, which is the resolution bandwidth applied during conducted emission

measurement. Typically, f_mshould be set to around 11 kHz to account for component variations.

The resistor R_DTRis used to determine ∆f, which is the amount of dithering, and its value is determined

according to:

0.513 × R_FRS(3)

R_DTR(3) =

%DTHR

(4)

For example, a 13.2% dithering with a nominal switching frequency of 250 kHz results in frequency variation of

±33 kHz.

8.3.6.6 SST and Soft-Start of the Switcher

Converters require a soft-start to prevent output overshoot on startup. In PoE applications, the PD also needs

soft-start to limit its input current at turn on below the limit allocated by the power source equipment (PSE).

For flyback applications using primary-side control, the TPS23731 provides closed loop controlled soft-start,

which applies a slowly rising ramp voltage to a second control input of the error amplifier. The lower of the

reference input and soft-start ramp controls the error amplifier, allowing the output voltage to rise in a smooth

monotonic fashion.

In all other applications where secondary-side regulation is used, the TPS23731 provides a current-loop soft-

start, which controls the switching MOSFET peak current by applying a slowly rising ramp voltage to a second

PWM control input. The lower of COMP-derived current demand and soft-start ramp controls the PWM

comparator. Note that in this case there is usually a (slower) secondary-side soft-start implemented with the

typical TL431 or TLV431 error amplifier to complement the action of the primary-side soft-start.

The soft-start period of the TPS23731 is adjustable with a capacitor between SST and RTN. During soft-start,

C_SST(Figure 9-1) is being charged from less than 0.2 V to 2.45 V by a ~10µA current source. Once V_SSThas

exceeded approximately 2.1 V (V_STUOF), the VCC startup is also turned off.

The actual control range of the primary-side closed-loop soft-start capacitor voltage is between 0.25V and 2V

nominally. Therefore, the soft-start capacitor value must be based on this control range and the required soft-

start period (t_SS) according to:

:

;

I_SSCJA x t_SS(ms)

C_SS(nF) =

(2 F 0.25)

(5)

The actual control range of the current-loop soft-start capacitor voltage is between 0.6V and 1.2V nominally.

Therefore, the soft-start capacitor value must be based on this control range and the required soft-start period

(t_SS) according to:

:

;

I_SSCJA x t_SS(ms)

C_SS(nF) =

(1.2 F 0.6)

(6)

Note that the VCC startup turns off only when 2.1 V is reached, allowing additional time for the secondary-side

soft-start to complete. For more details regarding the secondary-side soft start, refer to Application Information.

8.3.6.7 SST, I_STP, LINEUV and Soft-Stop of the Switcher

The soft-stop feature is provided by the TPS23731 to minimizes stress on switching power components caused

by power shutdown, allowing FET BOM cost reduction. Soft-stop action consists in discharging in a controlled

way the output capacitor of the converter, sending back the energy to the input bulk capacitor.

Once the LINEUV input detects that the input power source has been removed (while APD is also low), the SST

capacitor is discharged with a constant current, ramping down the switching MOSFET peak current. The SST

discharge current (I_{SSD_SP}) is defined with R_{I_STP}according to:

Submit Document Feedback

25

Product Folder Links: TPS23731

TPS23731

SLVSER7 – OCTOBER 2020

www.ti.com

1000

I_{SSD_SP}(JA) =

:

R_{I_STP}kÀ

;

(7)

To accelerate the impact of the soft-stop, the internal peak current limit threshold is also immediately stepped

down to approximately 50 mV at beginning of soft-stop.

8.3.7 Switching FET Driver - GATE

GATE is the gate drive outputs for the DC-DC converter's main switching MOSFET.

GATE's phase turns the main switch on when it transitions high, and off when it transitions low. It is also held low

when the converter is disabled.

8.3.8 EMPS and Automatic MPS

To maintain PSE power in situation of very low I_RTNcondition, the TPS23731 generates a pulsed current through

VSS pin with an amplitude adjusted such that its net current reaches a level high enough to maintain power.

The pulsed current amplitude (I_MPSL, I_MPSH) and duration (t_MPSL, t_MPSH) are automatically selected according to

PSE Type (1-2, 3-4), to maintain PSE power while minimizing power consumption. Auto-stretch feature is also

used to cancel the impact of system conditions (bulk capacitance and PoE cable impedance) on the effective

pulsed current duration. See Figure 8-4, where the illustrated pulsed current is coming out of the VSS pin, while

I_LOADis the DC current going into the RTN pin.

TMPS

Pulse

Stretching

IEEE I_Hold

I_Load

0 mA

IEEE I_Hold

TMPS

Unloaded power

supply

Measured I_VSS

Stretches the pulse if necessary based on measured current

Adds only the extra current to reach I_Hold

Figure 8-4. Auto MPS

Note that prior to entering the MPS mode, a light load condition is detected on RTN pin with a deglitch time

period of approximately 5 ms.

8.3.9 VDD Supply Voltage

VDD connects to the positive side of the input supply. It provides operating power to the PD controller, allows

monitoring of the input line voltage and serves as the source of DC-DC converter startup current. If V_VDDfalls

below its UVLO threshold and goes back above it, or if a thermal shutdown resumes even if V_VDDremains above

its UVLO threshold, the TPS23731 returns to inrush phase.

8.3.10 RTN, AGND, GND

RTN is internally connected to the drain of the PoE hotswap MOSFET, while AGND is the quiet analog reference

for the DC-DC controller return. GND is the power ground used by the flyback power FET gate driver and CP

output, and should be tied to AGND and RTN plane. The AGND / GND / RTN net should be treated as a local

reference plane (ground plane) for the DC-DC control and converter primary. The PAD_G exposed thermal pad

is internally connected to RTN pin.

8.3.11 VSS

VSS is the PoE input-power return side. It is the reference for the PoE interface circuits, and has a current-

limited hotswap switch that connects it to RTN. VSS is clamped to a diode drop above RTN by the hotswap

switch. The PAD_S exposed thermal pad is internally connected to VSS pin. This pad must be connected to VSS

pin to ensure proper operation.

26

Submit Document Feedback

Product Folder Links: TPS23731

TPS23731

SLVSER7 – OCTOBER 2020

www.ti.com

8.3.12 Exposed Thermal pads - PAD_G and PAD_S

PAD_G should be tied to a large RTN copper area on the PCB to provide a low resistance thermal path to the

circuit board.

PAD_S should be tied to a large VSS copper area on the PCB to provide a low resistance thermal path to the

circuit board. TI recommends maintaining a clearance of 0.025” between VSS and high-voltage signals such as

VDD.

8.4 Device Functional Modes

8.4.1 PoE Overview

The following text is intended as an aid in understanding the operation of the TPS23731, but it is not a substitute

for the actual IEEE 802.3bt or 802.3at standards. The IEEE 802.3bt standard is an update to IEEE 802.3-2018,

adding Clause 145 (PoE), including power delivery using all four pairs, high-power options, additional features to

reduce standby power consumption and enhanced classification.

Generally speaking, a device compliant to IEEE 802.3-2012 is referred to as a Type 1 (Class 0-3) or 2 (Class 4)

device, and devices with higher power and enhanced classification is referred to as Type 3 (Class 5, 6) or 4

(Class 7, 8) devices. Type 3 devices will also include Class 0-4 devices that are 4-pair capable. Standards

change and must always be referenced when making design decisions.

The IEEE 802.3at and 802.3bt standards define a method of safely powering a PD (powered device) over a

cable by power sourcing equipment (PSE), and then removing power if a PD is disconnected. The process

proceeds through an idle state and three operational states of detection, classification, and operation. There is

also a fourth operational state used by Type 3 and 4 PSEs, called "connection check", to determine if the PD has

same (single interface) or independent (dual interface or commonly referred to "dual-signature" in the

IEEE802.3bt standard) classification signature on each pairset. The PSE leaves the cable unpowered (idle state)

while it periodically looks to see if something has been plugged in; this is referred to as detection. The low power

levels used during detection and connection check are unlikely to damage devices not designed for PoE. If a

valid PD signature is present, the PSE may inquire how much power the PD requires; this is referred to as

classification. The PSE may then power the PD if it has adequate capacity.

Type 3 or Type 4 PSEs are required to do an enhanced hardware classification of Type 3 or 4 respectively. Type

2 PSEs are required to do Type 1 hardware classification plus a data-layer classification, or an enhanced Type 2

hardware classification. Type 1 PSEs are not required to do hardware or data link layer (DLL) classification. A

Type 3 or Type 4 PD must do respectively Type 3 or Type 4 hardware classification as well as DLL classification.

A Type 2 PD must do Type 2 hardware classification as well as DLL classification. The PD may return the

default, 13-W current-encoded class, or one of four other choices if Type 2, one of six other choices if Type 3,

and one of eight other choices if Type 4. DLL classification occurs after power-on and the Ethernet data link has

been established

Once started, the PD must present the maintain power signature (MPS) to assure the PSE that it is still present.

The PSE monitors its output for a valid MPS, and turns the port off if it loses the MPS. Loss of the MPS returns

the PSE to the idle state. Figure 8-5 shows the operational states as a function of PD input voltage.

Submit Document Feedback

27

Product Folder Links: TPS23731

TPS23731

SLVSER7 – OCTOBER 2020

www.ti.com

Shut-

down

Detect

Classify

Normal Operation

42.5

6.9

0

2.7

10.1 14.5

Mark

20.5

30

57

PI Voltage (V)

37

42

Normal Operation

Figure 8-5. Operational States

The PD input, typically an RJ-45 eight-lead connector, is referred to as the power interface (PI). PD input

requirements differ from PSE output requirements to account for voltage drops and operating margin. The

standard allots the maximum loss to the cable regardless of the actual installation to simplify implementation.

IEEE 802.3-2008 was designed to run over infrastructure including ISO/IEC 11801 class C (CAT3 per TIA/

EIA-568) that may have had AWG 26 conductors. IEEE 802.3at Type 2 and IEEE 802.3bt Type 3 cabling power

loss allotments and voltage drops have been adjusted for 12.5-Ω power loops per ISO/IEC11801 class D (CAT5

or higher per TIA/EIA-568, typically AWG 24 conductors). Table 8-3 shows key operational limits broken out for

the two revisions of the standard.

Table 8-3. Comparison of Operational Limits

POWER LOOP

RESISTANCE

(MAX)

STATIC PD INPUT VOLTAGE

PSE OUTPUT

POWER (MIN)

PSE STATIC OUTPUT

VOLTAGE (MIN)

PD INPUT

POWER (MAX)

STANDARD

POWER ≤ 13 W

POWER > 13 W

IEEE802.3-2012

802.3at (Type 1)

20 Ω

44 V

15.4 W

30 W

13 W

37 V – 57 V

N/A

802.3bt (Type 3)

12.5 Ω

50 V

802.3at (Type 2)

802.3bt (Type 3)

25.5 W

42.5 V – 57 V

802.3bt (Type 3)

802.3bt (Type 4)

6.25 Ω (4-pair)

60 W

90 W

50 V

52 V

51 W

N/A

42.5 V - 57 V

41.2 V - 57 V

71.3 W

The PSE can apply voltage either between the RX and TX pairs (pins 1–2 and 3–6 for 10baseT or 100baseT), or

between the two spare pairs (4–5 and 7–8). Power application to the same pin combinations in 1000/2.5G/5G/

10GbaseT systems is recognized in IEEE 802.3bt. 1000/2.5G/5G/10GbaseT systems can handle data on all

pairs, eliminating the spare pair terminology. Type 1 and 2 PSEs are allowed to apply voltage to only one set of

pairs at a time, while Type 3 and 4 PSEs may apply power to one or both sets of pairs at a time. The PD uses

input diode or active bridges to accept power from any of the possible PSE configurations. The voltage drops

associated with the input bridges create a difference between the standard limits at the PI and the TPS23731

specifications.

A compliant Type 2, 3 or 4 PD has power management requirements not present with a Type 1 PD. These

requirements include the following:

1. Must interpret respectively Type 2, 3 or 4 hardware classification.

2. Must present hardware Class 4 during the first two classfication events, applicable to Type 2 and 4 PDs, as

well as to Type 3 PD with Class level 4 or higher.

3. If Type 3 Class 5-6 or Type 4 single interface PD, it must present hardware Class in the range of 0 to 3 during

the third and any subsequent classification events.

28

Submit Document Feedback

Product Folder Links: TPS23731

TPS23731

SLVSER7 – OCTOBER 2020

www.ti.com

4. Must implement DLL negotiation.

5. Must draw less than 400 mA from 50 ms until 80 ms after the PSE applies operation voltage (power up), if

Type 2 or 3, single interface PD. This covers the PSE inrush period, which is 75 ms maximum.

6. Must draw less than 800 mA total and 600 mA per pairset from 50 ms until 80 ms after the PSE applies

operation voltage (power up), if Type 4 (Class 7-8) single interface PD.

7. Must not draw more than 60 mA and 5 mA any time the input voltage falls below respectively 30 V and 10 V.

8. Must not draw more than 13 W if it has not received at least a Type 2 hardware classification or received

permission through DLL.

9. Must not draw more than 25.5 W if it has not received at least 4 classification events or received permission

through DLL.

10.Must not draw more than 51 W if it has not received at least 5 classification events or received permission

through DLL.

11.Must meet various operating and transient templates.

12.Optionally monitor for the presence or absence of an adapter.

As a result of these requirements, the PD must be able to dynamically control its loading, and monitor T2P for

changes. APDO can also be used in cases where the design needs to know specifically if an adapter is plugged

in and operational.

8.4.2 Threshold Voltages

The TPS23731 has a number of internal comparators with hysteresis for stable switching between the various

states as shown in Figure 8-5. Figure 8-6 relates the parameters in Electrical Characteristics PoE to the PoE

states. The mode labeled idle between classification and operation implies that the DEN, CLS, and RTN pins are

all high impedance. The state labeled Mark, which is drawn in dashed lines, is part of the Type 2-3-4 hardware

class state machine.

PD Powered

Idle

Classification

Mark

V_DD-V_SS

Detection

V_{CU_H}

V_{CU_OFF}

V_{CL_H}

V_{CL_ON}

V_{UVLO_H}

V_MSR

V_{UVLO_R}

Note: Variable names refer to Electrical Characteristic

Table parameters

Figure 8-6. Threshold Voltages

8.4.3 PoE Start-Up Sequence

The waveforms of Figure 8-7 demonstrate detection, classification, and start-up from a Type 2 PSE with Class 4

hardware classification. The key waveforms shown are V_VDD-VSS, V_RTN-VSS, and I_PI. IEEE802.3bt and IEEE

802.3at require a minimum of two detection levels; however, four levels are shown in this example. Four levels

guard against misdetection of a device when plugged in during the detection sequence.

V_RTNto V_SSfalls as the TPS23731 charges C_BULKfollowing application of full voltage. In Figure 8-9, the

converter soft-start is also delayed until the end of inrush period.

Submit Document Feedback

29

Product Folder Links: TPS23731

TPS23731

SLVSER7 – OCTOBER 2020

www.ti.com

DC-DC enabled after

Startup delay

Inrush

I_PI

V_VDD-VSS

Class Mark

Detect

V_RTN-VSS

Time: 50ms/div

Figure 8-7. PoE Start-Up Sequence

8.4.4 Detection

The TPS23731 is in detection mode whenever V_{VDD-V SS}is below the lower classification threshold. When the

input voltage rises above V_{CL_ON}, the DEN pin goes to an open-drain condition to conserve power. While in

detection, RTN is high impedance, almost all the internal circuits are disabled, and the DEN pin is pulled to V_SS

.

An R_DENof 25.5 kΩ (1%), presents the correct signature. It may be a small, low-power resistor because it only

sees a stress of about 5 mW. A valid PD detection signature is an incremental resistance between 23.75 kΩ and

26.25 kΩ at the PI.

The detection resistance seen by the PSE at the PI is the result of the input bridge resistance in series with the

parallel combination of R_DENand the TPS23731 bias loading. The incremental resistance of the input diode

bridge may be hundreds of ohms at the very low currents drawn when 2.7 V is applied to the PI. The input bridge

resistance is partially cancelled by the effective resistance of the TPS23731 during detection.

8.4.5 Hardware Classification

Hardware classification allows a PSE to determine a PD’s power requirements before powering, and helps with

power management once power is applied. Type 2, 3, and 4 hardware classification permits high power PDs to

determine whether the PSE can support its high-power operation. The number of class cycles generated by the

PSE prior to turn on indicates to the PD if it allots the power requested or if the allocated power is less than

requested, in which case there is power demotion.

A Type 2 PD always presents Class 4 in hardware to indicate that it is a 25.5W device. A Class 5 or 6 Type 3 PD

presents Class 4 in hardware during the first two class events and it presents Class 0 or 1, respectively, for all

subsequent class events. A Class 7 or 8 Type 4 PD presents Class 4 in hardware during the first two class

events and it presents Class 2 or 3, respectively, for all subsequent class events. A Type 1 PSE will treat a Class

30

Submit Document Feedback

Product Folder Links: TPS23731

TPS23731

SLVSER7 – OCTOBER 2020

www.ti.com

4 to 8 device like a Class 0 device, allotting 13 W if it chooses to power the PD. A Type 2 PSE will treat a Class 5

to 8 device like a Class 4 device, allotting 25.5W if it chooses to power the PD. A Class 4 PD that receives a 2-

event class, a Class 5 or 6 PD that receives a 4-event class, or a Class 7 or 8 PD that receives a 5-event class,

understands that the PSE has agreed to allocate the PD requested power. In the case where there is power

demotion, the PD may choose to not start, or to start while not drawing more power than initially allocated, and

request more power through the DLL after startup. The standard requires a Type 2, 3 or 4 PD to indicate that it is

underpowered if this occurs. Startup of a high-power PD at lower power than requested implicitly requires some

form of powering down sections of the application circuits.

The maximum power entries in Table 8-1 determine the class the PD must advertise. The PSE may disconnect a

PD if it draws more than its stated class power, which may be the hardware class or a DLL-derived power level.

The standard permits the PD to draw limited current peaks that increase the instantaneous power above the

Table 8-1 limit; however, the average power requirement always applies.

The TPS23731 implements one- to two-event classification. R_CLSresistor value defines the class of the PD. DLL

communication is implemented by the Ethernet communication system in the PD and is not implemented by the

TPS23731.

The TPS23731 disables classification above V_{CU_OFF}to avoid excessive power dissipation. CLS voltage is

turned off during PD thermal limiting or when APD or DEN is active. The CLS output is inherently current-limited,

but should not be shorted to V_SSfor long periods of time.

Figure 8-8 shows how classification works for the TPS23731. Transition from state-to-state occurs when

comparator thresholds are crossed (see Figure 8-5 and Figure 8-6). These comparators have hysteresis, which

adds inherent memory to the machine. Operation begins at idle (unpowered by PSE) and proceeds with

increasing voltage from left to right. A 2-event classification follows the (heavy lined) path towards the bottom,

ending up with a low T2P along the lower branch that is highlighted. Once the valid path to the PSE detection is

broken, the input voltage must transition below the mark reset threshold to start anew.

Between

Ranges

UVLO

Falling

Class

UVLO

Rising

Operating

T2P

open-drain

Between

Ranges

Idle

Detect

TYPE 1 or 3 PSE

Hardware Class

Mark

Reset

Between

Ranges

Mark

PoE Startup Sequence

Between

Ranges

UVLO

Rising

Operating

T2P low

Class

TYPE 2 or 3 PSE

Hardware Class

UVLO

Falling

Figure 8-8. Up to Two-Event Class Internal States

8.4.6 Maintain Power Signature (MPS)

The MPS is an electrical signature presented by the PD to assure the PSE that it is still present after operating

voltage is applied. For a Type 1 or Type 2 PD, a valid MPS consists of a minimum dc current of 10 mA, or a 10-

mA pulsed current for at least 75 ms every 325 ms, and an AC impedance lower than 26.3 kΩ in parallel with

Submit Document Feedback

31

Product Folder Links: TPS23731

TPS23731

SLVSER7 – OCTOBER 2020

www.ti.com

0.05 μF. Only Type 1 and Type 2 PSEs monitor the AC MPS. A Type 1 or Type 2 PSE that monitors only the AC

MPS may remove power from the PD.

To enable applications with stringent standby requirements, IEEE802.3bt introduced a significant change

regarding the minimum pulsed current duration to assure the PSE will maintain power. This applies to all Type 3

and Type 4 PSEs, and the pulse duration is ~10% of what is required for Type 1 and 2 PSEs. The MPS current

amplitude requirement for Class 5-8 PDs have also increased to 16 mA at the PSE end of the ethernet cable.

If the current through the RTN-to-VSS path is very low, the TPS23731 automatically generates the MPS pulsed

current through the VSS pin, with an amplitude adjusted such that its net current reaches a level high enough to

maintain PSE power. The TPS23731 is also able to determine if the PSE is of Type 1-2 or Type 3-4,

automatically adjusting the pulsed current amplitude, duration and duty-cycle, while minimizing power

consumption. Note that the IEEE802.3bt requirement for the PD is applicable at the PSE end of the cable. That

means that depending the cable length and other parameters including the bulk capacitance, a longer pulse

duration may be required to ensure a valid MPS. For that purpose, the TPS23731 provides auto-stretch

capability which is used to cancel the impact of such system conditions on the effective pulsed current duration.

See Figure 8-4.

When APD is pulled high or when DEN is pulled to VSS (forcing the hotswap switch off), the DC MPS will not be

met. A PSE that monitors the DC MPS will remove power from the PD when this occurs.

8.4.7 Advanced Start-Up and Converter Operation

The internal PoE undervoltage lockout (UVLO) circuit holds the hotswap switch off before the PSE provides full

voltage to the PD. This prevents the converter circuits from loading the PoE input during detection and

classification. The converter circuits discharges C_BULK, C_VCC, C_VBand C_VBGwhile the PD is unpowered. Thus

V_VDD-RTNwill be a small voltage until just after full voltage is applied to the PD, as seen in Figure 8-7.

The PSE drives the PI voltage to the operating range once it has decided to power up the PD. When V_VDDrises

above the UVLO turnon threshold (V_UVLO-R, approximately 37.6 V) with RTN high, the TPS23731 enables the

hotswap MOSFET with an approximately 140-mA (inrush) current limit. See the waveforms of Figure 8-9 for an

example. Converter switching is disabled while C_BULKcharges and V_RTNfalls from V_VDDto nearly V_VSS

;

however, the converter start-up circuit is allowed to charge C_VCC(the VB regulator also powers the internal

converter circuits as V_VCCrises). Once the inrush current falls about 10% below the inrush current limit, the PD

current limit switches to the operational level (approximately 925 mA). Additionally, once the inrush period

duration has also exceeded approximately 84 ms (end of inrush phase), the converter switching is allowed to

start, once V_VCCalso goes above its UVLO (approximately 8.25 V).

Continuing the start-up sequence shown in Figure 8-9, once V_VCCgoes above its UVLO , the soft-start (SST)

capacitor is first discharged with controlled current (I_SSD) below nominally 0.2 V (V_SFST) if the discharge was not

already completed, then it is gradually recharged until it reaches ~0.25 V (V_SSOFSin closed-loop mode) at which

point the converter switching is enabled, following the closed loop controlled soft-start sequence. Note that the

startup current source capability is such that it can fully maintain V_VCCduring the converter soft-start without

requiring any significant C_VCCcapacitance, in 48 V input applications. At the end of the soft-start period, more

specifically when SST voltage has exceeded ~2 V (V_STUOF), the startup current source is turned off. V_VCCfalls

as it powers the internal circuits including the switching MOSFET gate. If the converter control-bias output rises

to support V_VCCbefore it falls to V_{CUVLO_F}(~6.1 V), a successful start-up occurs. Figure 8-9 shows a small droop

in V_VCCwhile the output voltage rises smoothly and a successful start-up occurs.

Figure 8-10 also illustrates similar scenario if optocoupler feedback is used instead of PSR. In this case, the

converter switching is enabled when V_SSTexceeds approximately 0.6 V (V_SSOFSin peak current mode).

32

Submit Document Feedback

Product Folder Links: TPS23731

TPS23731

SLVSER7 – OCTOBER 2020

www.ti.com

50V/div

V_VDD-RTN

Converter

starts

PI powered

Inrush

100mA/div

I_PI

V_VCC-RTN

Startup turn off,

T2P enabled

5V/div

V_OUT

Output Voltage

Inrush Delay

V_SST

Soft Start

1V/div

Time: 20ms/div

Figure 8-9. Power Up and Start - Flyback with PSR

Submit Document Feedback

33

Product Folder Links: TPS23731

TPS23731

SLVSER7 – OCTOBER 2020

www.ti.com

50V/div

V_VDD-RTN

Converter

starts

PI powered

Inrush

100mA/div

I_PI

V_VCC-RTN

Startup turn off

5V/div

Secondary

Soft Start

dependent

Output Voltage

V_OUT

Inrush Delay

Primary I_peak

Soft Start

V_SST

1V/div

Time: 20ms/div

Figure 8-10. Power Up and Start - with Opto Feedback

The converter shuts off when V_VCCfalls below its lower UVLO. This can happen when power is removed from

the PD, or during a fault on a converter output rail. When one output is shorted, all the output voltages fall

including the one that powers VCC. The control circuit discharges VCC until it hits the lower UVLO and turns off.

A restart initiates if the converter turns off and there is sufficient VDD voltage. This type of operation is

sometimes referred to as hiccup mode, which when combined with the soft-start provides robust output short

protection by providing time-average heating reduction of the output rectifier.

Figure 8-11 illustrates the situation when there is severe overload at the main output which causes VCC hiccup.

After VCC went below its UVLO due to the overload, the startup source is turned back on. Then, a new soft-start

cycle is reinitiated, the soft-start capacitor being first discharged with controlled current, introducing a short

pause before the output voltage is ramped up.

34

Submit Document Feedback

Product Folder Links: TPS23731

TPS23731

SLVSER7 – OCTOBER 2020

www.ti.com

V_OUToverload

Converter

Turn off then restart

I_PI

200mA/div

5V/div

Startup turn off

V_VCC-RTN

VCC

UVLO

V_SST

Soft Start

1V/div

5V/div

Output Voltage

V_OUT

Time: 10ms/div

Figure 8-11. Restart Following Severe Overload at Main Output of PSR Flyback DC-DC Converter

Also, when a VCC fall occurs, the TPS23731 can differentiate between an overload and a light load condition.

For example a diode-rectified flyback with optocoupled feedback may have its VCC rail to fall in situation of light

load due to temporary switching stop. In this case, the output voltage has to be maintained and a soft-start would

not be acceptable. To address this case, if V_VCCfalls below approximately 7.1 V due to light load, the TPS23731

turns back on the startup immediately and for a short period of time to bring VCC voltage back up, and there is

no soft-start recycling.

Submit Document Feedback

35

Product Folder Links: TPS23731

TPS23731

SLVSER7 – OCTOBER 2020

www.ti.com

I_OUT

V_VCC-RTN

Startup turn on then off

VCUV

Startup turn on

for short time

5V/div

VCC falls due to

switching interruption

at light load

Vout is maintained, no soft

start recycling

V_OUT

10V/div

Time: 10ms/div

Figure 8-12. Startup Operation if VCC Undervoltage is caused by Light Load Condition of Diode-rectified

Flyback DC-DC Converter

If V_VDD-VSSdrops below the lower PoE UVLO (V_{UVLO_F}, approximately 32 V), the hotswap MOSFET is turned off,

but the converter still runs (unless LINEUV input is pulled low). The converter stops if V_VCCfalls below the

V_{CUVLO_F}(~6.1 V), the hotswap is in inrush current limit, the SST pin is pulled to ground, or the converter is in

thermal shutdown.

8.4.8 Line Undervoltage Protection and Converter Operation

When the input power source is removed, there are circumstances where stress may occur on the power

components.

For example, situations where the output voltage capacitor may be able to back drive its secondary-side sync

MOSFET after the flyback converter switching has stopped completely, either temporarily or not. Such situation

could apply at power down or next soft-start.

To address this case, once the LINEUV voltage falls below V_LIUVF, the TPS23731 transitions to soft-stop mode. It

turns on temporarily the startup to maintain V_VCC, then uses the SST control to ramp down the switching

MOSFET peak current. As a result, the converter output is discharged in a controlled way, the energy of the

output capacitor being sent back to the input bulk capacitor. Also note that at beginning of soft-stop, the

TPS23731 temporarily forces the peak current to a low value (V_CSmaximum at approximately 50 mV), until SST

voltage becomes low enough to decrease it further. This advanced feature allows the soft-stop to immediately

start discharging the output capacitor, regardless of the output load level, minimizing any system tradeoffs for

optimum switching MOSFETs protection. See Figure 8-13.

36

Submit Document Feedback

Product Folder Links: TPS23731

TPS23731

SLVSER7 – OCTOBER 2020

www.ti.com

Power

down

VDD

LINEUV

Soft Stop begins

immediately at max

discharge current

VOUT

SST

CS

Figure 8-13. Soft-Stop Operation

Once the soft-stop operation has been completed and to avoid subsequent oscillations caused by the impact of

the energy transfer on the LINEUV voltage, an internal load (~7 mA) is applied on VDD for approximately 160

ms, before the converter is allowed to restart.

8.4.9 PD Self-Protection

IEEE802.3bt includes new PSE output limiting requirements for Type 3 and 4 operation to cover higher power

and 4-pair applications. Type 2, 3 and 4 PSEs must meet an output current vs time template with specified

minimum and maximum sourcing boundaries. The peak output current per each 2-pair may be as high as 50 A

for 10 μs or 1.75 A for 75 ms, and the total peak current becomes twice these values when power is delivered

over 4 pairs. This makes robust protection of the PD device even more important than it was in IEEE

802.3-2012.

The PD section has the following self-protection functions.

•

Hotswap switch current limit

Hotswap switch foldback

Hotswap thermal protection

The internal hotswap MOSFET of the TPS23731 is protected against output faults and input voltage steps with a

current limit and deglitched foldback. High stress conditions include converter output shorts, shorts from VDD to

RTN, or transients on the input line. An overload on the pass MOSFET engages the current limit, with V_RTN-VSS

rising as a result. If V_RTNrises above approximately 14.8 V for longer than approximately 1.8 ms, the current limit

reverts to the inrush limit, and turns the converter off, although there is no minimum inrush delay period (84 ms)

applicable in this case. The 1.8-ms deglitch feature prevents momentary transients from causing a PD reset,

provided that recovery lies within the bounds of the hotswap and PSE protection. Figure 8-14 shows an example

of recovery from a 15-V PSE rising voltage step. The hotswap MOSFET goes into current limit, overshooting to a

relatively low current, recovers to 925-mA full current limit, and charges the input capacitor while the converter

continues to run. The MOSFET did not go into foldback because V_RTN-VSSwas below 14.8 V after the 1.8-ms

deglitch.

Submit Document Feedback

37

Product Folder Links: TPS23731

TPS23731

SLVSER7 – OCTOBER 2020

www.ti.com

I_PI

250mA/div

CBULK

completes charge

while converter

operates

V_VSS-RTN≈ -15V

10V/div

20V/div

V_VDD-VSS

Time: 400us/div

Figure 8-14. Response to PSE Step Voltage

The PD control has a thermal sensor that protects the internal hotswap MOSFET. Conditions like start-up or

operation into a VDD to RTN short cause high power dissipation in the MOSFET. An overtemperature shutdown

(OTSD) turns off the hotswap MOSFET and class regulator, which are restarted after the device cools. The PD

restarts in inrush phase when exiting from a PD overtemperature event.

Pulling DEN to VSS during powered operation causes the internal hotswap MOSFET to turn off. This feature

allows a PD with secondary-side adapter ORing to achieve adapter priority. Take care with synchronous

converter topologies that can deliver power in both directions.

The hotswap switch is forced off under the following conditions:

•

V_APDabove V_APDEN(approximately 1.5 V)

V_{DE N}≤ V_{PD_DIS}when V_VDD-VSSis in the operational range

PD over temperature

V_VDD-VSS< PoE UVLO (approximately 32 V)

8.4.10 Thermal Shutdown - DC-DC Controller

The DC-DC controller has an OTSD that can be triggered by heat sources including the VB and VBG regulators,

GATE driver, startup current source, and bias currents. The controller OTSD turns off VB, VBG, the GATE driver,

and forces the VCC control into an under-voltage state.

8.4.11 Adapter ORing

Many PoE-capable devices are designed to operate from either a wall adapter or PoE power. A local power

solution adds cost and complexity, but allows a product to be used if PoE is not available in a particular

installation. While most applications only require that the PD operate when both sources are present, the

38

Submit Document Feedback

Product Folder Links: TPS23731

TPS23731

SLVSER7 – OCTOBER 2020

www.ti.com

TPS23731 device supports forced operation from either of the power sources. Figure 8-15 illustrates three

options for diode ORing external power into a PD. Only one option would be used in any particular design.

Option 1 applies power to the device input, option 2 applies power between the device PoE section and the

power circuit, and option 3 applies power to the output side of the converter. Each of these options has

advantages and disadvantages. A detailed discussion of the device and ORing solutions is covered in

application note Advanced Adapter ORing Solutions using the TPS23753, (SLVA306).

Low Voltage

Output

DEN

CLS

Power

Circuit

V_SS

RTN

Adapter

Option 2

Adapter

Option 3

Adapter

Option 1

Figure 8-15. ORing Configurations

Preference of one power source presents a number of challenges. Combinations of adapter output voltage

(nominal and tolerance), power insertion point, and which source is preferred determine solution complexity.

Several factors contributing to the complexity are the natural high-voltage selection of diode ORing (the simplest

method of combining sources), the current limit implicit in the PSE, PD inrush, and protection circuits (necessary

for operation and reliability). Creating simple and seamless solutions is difficult if not impossible for many of the

combinations. However, the TPS23731 device offers several built-in features that simplify some combinations.

Several examples demonstrate the limitations inherent in ORing solutions. Diode ORing a 48-V adapter with PoE

(option 1) presents the problem that either source may have the higher voltage. A blocking switch would be

required to assure that one source dominates. A second example is combining a 12-V adapter with PoE using

option 2. The converter draws approximately four times the current at 12 V from the adapter than it does from

PoE at 48 V. Transition from adapter power to PoE may demand more current than can be supplied by the PSE.

The converter must be turned off while C_INcapacitance charges, with a subsequent converter restart at the

higher voltage and lower input current. A third example is use of a 24-V adapter with ORing option 1. The PD

hotswap would have to handle two times the current, and have 1/4 the resistance (be 4 times larger) to dissipate

equal power.

The most popular preferential ORing scheme is option 2 with adapter priority. The hotswap MOSFET is disabled

when the adapter is used to pull APD high, blocking the PoE source from powering the output. This solution

works well with a wide range of adapter voltages, is simple, and requires few external parts. When the AC power

fails, or the adapter is removed, the hotswap switch is enabled. In the simplest implementation, the PD

momentarily loses power until the PSE completes its start-up cycle.

The DEN pin can be used to disable the PoE input when ORing with option 3. This is an adapter priority

implementation. Pulling DEN low, while creating an invalid detection signature, disables the hotswap MOSFET,

and prevents the PD from redetecting. This would typically be accomplished with an optocoupler that is driven

from the secondary side of the converter. Another option 3 alternative which does not require DEN optocoupler is

achievable by ensuring that the auxiliary voltage is always higher then the converter output; in this case, the

PSE power can then be maintained by use of the auto MPS function of the TPS23731.

Submit Document Feedback

39

Product Folder Links: TPS23731

TPS23731

SLVSER7 – OCTOBER 2020

www.ti.com

The IEEE standards require that the PI conductors be electrically isolated from ground and all other system

potentials not part of the PI interface. The adapter must meet a minimum 1500-Vac dielectric withstand test

between the output and all other connections for options 1 and 2. The adapter only needs this isolation for option

3 if it is not provided by the converter.

Adapter ORing diodes are shown for all the options to protect against a reverse-voltage adapter, a short on the

adapter input pins, and damage to a low-voltage adapter. ORing is sometimes accomplished with a MOSFET in

option 3.

40

Submit Document Feedback

Product Folder Links: TPS23731

TPS23731

SLVSER7 – OCTOBER 2020

www.ti.com

9 Application and Implementation

Note

Information in the following applications sections is not part of the TI component specification, and TI

does not warrant its accuracy or completeness. TI’s customers are responsible for determining

suitability of components for their purposes. Customers should validate and test their design

implementation to confirm system functionality.

9.1 Application Information

The TPS23731 supports power supply topologies that require a single PWM gate drive with current-mode

control. Figure 9-1 provides an example of a synchronous FET rectified primary-side-regulated flyback converter.

9.2 Typical Application

T1

TPS23731

V_CC

+

R_CL

C_CL

D_CL

C_BULK

VDD

DEN

V_OUT2

C_OUT2

R_DEN

APDO

T2P

GATE

CS

0.1 ꢀF

58V

CLS

VSS

R_CS

V_OUT1

C_OUT

VCC

COMP

D_CC

C_COMP

R_COMP

I_in

R₁

APD

C_VCC

FB

C_CC2

LINEUV

FRS

R_UV2

D_A

CP

R₂

SST

C_SST

R_DTR

EA_DIS

DTHR

VB

GND I_STP

RTN

PSRS

C_VB

R_APD2

C_DTR

R_FRS

48V

Adapter

R_{I_STP}

Figure 9-1. Basic TPS23731 Implementation

Submit Document Feedback

41

Product Folder Links: TPS23731

TPS23731

SLVSER7 – OCTOBER 2020

www.ti.com

9.2.1 Design Requirements

Selecting a converter topology along with a converter design procedure is beyond the scope of this application

section.

The TPS23731 has the flexibility to be used in high power density flyback topologies such as primary side

regulation synchronous or non-synchronous flyback.

Examples to help in programming the TPS23731 and additional design consideration are shown in Detailed

Design Procedure. For a more specific converter design example, refer to the EVM that is designed for the

design parameters in Table 9-1.

Table 9-1. Design Parameters

PARAMETER

Input voltage

TEST CONDITIONS

MIN TYPICAL

MAX UNIT

Power applied through PoE or adapter

0

30

57

V

Operating voltage

Adapter voltage

After startup

40

57

Rising input voltage at device terminals

Falling input voltage

—

40

Input UVLO

V

30.5

1.4

11.9

38

—

Detection voltage

At device terminals

10.1

23

V

Classification voltage At device terminals

Class 4

Class signature A

42

mA

DCDC Topology

Output Voltage

Output Current

Primary Side Regulated Synch Flyback

5

V

A

End-to-End Efficiency At full load

Switching Frequency

89

%

250

kHz

9.2.1.1 Detailed Design Procedure

9.2.1.1.1 Input Bridges and Schottky Diodes

Using Schottky diodes instead of PN junction diodes for the PoE input bridges will reduce the power loss by

about 30%. These are often used to maximize the efficiency when FET bridge architectures are not used.

Schottky diode leakage current and different input bridge architectures can impact the detection signature.

Setting reasonable expectations for the temperature range over which the detection signature is accurate is the

simplest solution. Adjusting R_DENslightly may also help meet the requirement.

A general recommendation for the input rectifiers are 2 A, 100-V rated discrete or bridge schottky diodes.

The allows the option of either a discrete schottky bridge or a FET-Diode bridge for 1-2% higher overall system

efficiency.

9.2.1.1.2 Input TVS Protection

A TVS, across the rectified PoE voltage must be used. TI recommends a SMAJ58A, or a part with equal to or

better performance, for general indoor applications. If an adapter is connected from V_DDto RTN, as in ORing

option 2 above, voltage transients caused by the input cable inductance ringing with the internal PD capacitance

can occur. Adequate capacitive filtering or a TVS must limit this voltage to be within the absolute maximum

ratings. Outdoor transient levels or special applications require additional protection.

ESD events between the PD power inputs and converter output, cause large stresses in the hotswap MOSFET if

the input TVS becomes reverse biased and transient current around the TPS23731 is blocked. A SMAJ58A is a

good initial selection between RTN (cathode) and VSS (anode).

9.2.1.1.3 Input Bypass Capacitor

The IEEE 802.3bt standard specifies an input bypass capacitor (from V_DDto V_SS) of 0.05 μF to 0.12 μF. Typically

a 0.1-μF, 100-V, 10% ceramic capacitor is used.

42

Submit Document Feedback

Product Folder Links: TPS23731

TPS23731

SLVSER7 – OCTOBER 2020

www.ti.com

9.2.1.1.4 Detection Resistor, R_DEN

The IEEE 802.3bt standard specifies a detection signature resistance, R_DENfrom 23.7 kΩ to 26.3 kΩ, or 25 kΩ ±

5%. Choose an R_DENof 25.5 kΩ.

9.2.1.1.5 Classification Resistor, R_CLS

.

Connect a resistor from to V_SSto program the classification current according to the IEEE 802.3bt standard. The

class power assigned should correspond to the maximum average power drawn by the PD during operation.

Select R_CLSxaccording to Table 8-1.

9.2.1.1.6 APD Pin Divider Network, R_APD1, R_APD2

The APD pin can be used to disable the TPS23731 device internal hotswap MOSFET giving the adapter source

priority over the PoE source. An example calculation is provided, see SLVA306.

9.2.1.1.7 Setting Frequency (R_FRS) and Synchronization

The converter switching frequency is set by connecting R_FRSfrom the FRS pin to AGND.

As an example:

1. Optimal switching frequency (f_SW) for isolated PoE applications is 250 kHz.

2. Compute R_FRSper Equation 2.

3. Select 60.4 kΩ.

The TPS23731 device may be synchronized to an external clock to eliminate beat frequencies from a sampled

system, or to place emission spectrum away from an RF input frequency. Synchronization may be accomplished

by applying a short pulse (T_SYNC) of magnitude V_SYNCto FRS as shown in Figure 8-3. R_FRSshould be chosen so

that the maximum free-running frequency is just below the desired synchronization frequency. The

synchronization pulse terminates the potential on-time period, and the off-time period does not begin until the

pulse terminates. The pulse at the FRS pin should reach between 2.5 V and V_B, with a minimum width of 25 ns

(above 2.5 V) and rise and fall times less than 10 ns. The FRS node should be protected from noise because it

is high-impedance. An R_Ton the order of 100 Ω in the isolated example reduces noise sensitivity and jitter.

9.2.1.1.8 Bias Supply Requirements and C_VCC

Advanced startup in the TPS23731 allows for relatively low capacitance on the bias circuit. It is recommended to

use a 1-µF 10% 25-V ceramic capacitor on C_VCC

.

9.2.1.1.9 APDO, T2P Interface

The APDO, T2P pins are active low, open-drain outputs which give an indication about the PSE allocated power.

Optocouplers can interface these pins to circuitry on the secondary side of the converter. A high-gain

optocoupler and a high-impedance (for example, CMOS) receiver are recommended. Please see the as an

example circuit. Below is an example design calculation.

1. Let V_CC= 12-V, V_OUT= 5-V, = 10-kΩ, V_TPx-OUT(low) = 400-mV maximum.

a. I_TPx-OUT= 0.46 mA.

2. The optocoupler CTR will be needed to determine . A device with a minimum CTR of 300% at 5-mA LED bias

current is selected. CTR will also vary with temperature and LED bias current. The strong variation of CTR

with diode current makes this a problem that requires some iteration using the CTR versus I_DIODEcurve on

the optocoupler data sheet.

a. The approximate forward voltage of the optocoupler diode is 1.1 V from the data sheet.

b. I_TPx-MIN= 1 mA and R_TPx= 10.6 kΩ.

3. Select 10.7-kΩ resistor.

9.2.1.1.10 Output Voltage Feedback Divider, R_AUX, R₁,R₂

R₁, R₂and set the output voltage of the bias winding of the converter.

Submit Document Feedback

43

Product Folder Links: TPS23731

TPS23731

SLVSER7 – OCTOBER 2020

www.ti.com

V_REFCR + R

(

)

1

2

V_VCC

=

R ₂

(8)

9.2.1.1.11 Frequency Dithering for Conducted Emissions Control

For optimum EMI performance, C_DTRand R_DTRshould be calculated as described in DTHR and Frequency

Dithering for Spread Spectrum Applications.

These equations yield C_DTR= 2.2 nF and R_DTR= 235 kΩ where a 237-kΩ standard resistor can be used.

10 Power Supply Recommendations

The TPS23731 converter must be designed such that the input voltage of the converter is capable of operating

within the IEEE 802.3 protocol at the recommended input voltage as shown in Table 8-3 and the minimum

operating voltage of the adapter if applicable.

44

Submit Document Feedback

Product Folder Links: TPS23731

TPS23731

SLVSER7 – OCTOBER 2020

www.ti.com

11 Layout

11.1 Layout Guidelines

The layout of the PoE front end should follow power and EMI/ESD best practice guidelines. A basic set of

recommendations include:

•

Parts placement must be driven by power flow in a point-to-point manner; RJ-45, Ethernet transformer, diode

bridges, TVS and 0.1-μF capacitor, and TPS23731.

•

All leads should be as short as possible with wide power traces and paired signal and return.

There should not be any crossovers of signals from one part of the flow to another.

Spacing consistent with safety standards like IEC60950 must be observed between the 48-V input voltage

rails and between the input and an isolated converter output.

•

The TPS23731 should be located over split, local ground planes referenced to VSS for the PoE input and to

RTN for the switched output.

Large copper fills and traces should be used on SMT power-dissipating devices, and wide traces or overlay

copper fills should be used in the power path.

It is recommended having at least 8 vias (PAD_G) and 5 vias on (PAD_S) connecting the exposed thermal

pad through a top layer plane (2 oz. copper recommended) to a bottom VSS plane (2 oz. copper

recommended) to help with thermal dissipation.

11.2 Layout Example

A detailed PCB layout can be found in the user’s guide of the TPS23731EVM-095 that show the top and bottom

layer and assemblies as a reference for optimum parts placement.

11.3 EMI Containment

•

Use compact loops for dv/dt and di/dt circuit paths (power loops and gate drives).

Use minimal, yet thermally adequate, copper areas for heat sinking of components tied to switching nodes

(minimize exposed radiating surface).

•

Use copper ground planes (possible stitching) and top layer copper floods (surround circuitry with ground

floods).

•

Use 4 layer PCB if economically feasible (for better grounding).

Minimize the amount of copper area associated with input traces (to minimize radiated pickup).

Use Bob Smith terminations, Bob Smith EFT capacitor, and Bob Smith plane.

Use Bob Smith plane as ground shield on input side of PCB (creating a phantom or literal earth ground).

Use of ferrite beads on input (allow for possible use of beads or 0-Ω resistors).

Maintain physical separation between input-related circuitry and power circuitry (use ferrite beads as

boundary line).

•

Possible use of common-mode inductors.

Possible use of integrated RJ-45 jacks (shielded with internal transformer and Bob Smith terminations).

End-product enclosure considerations (shielding).

11.4 Thermal Considerations and OTSD

Sources of nearby local PCB heating should be considered during the thermal design. Typical calculations

assume that the TPS23731 is the only heat source contributing to the PCB temperature rise. It is possible for a

normally operating TPS23731 device to experience an OTSD event if it is excessively heated by a nearby

device.

11.5 ESD

ESD requirements for a unit that incorporates the TPS23731 have a much broader scope and operational

implications than are used in TI’s testing. Unit-level requirements should not be confused with reference design

testing that only validates the ruggedness of the TPS23731.

Submit Document Feedback

45

Product Folder Links: TPS23731

TPS23731

SLVSER7 – OCTOBER 2020

www.ti.com

12 Device and Documentation Support

12.1 Documentation Support

12.1.1 Related Documentation

For related documentation, see the following:

•

IEEE Standard for Information Technology … Part 3: Carrier sense multiple access with collision detection

(CSMA/CD) access method and physical layer specifications, IEEE Computer Society, IEEE 802.3™at

(Clause 33)

•

Information technology equipment – Radio disturbance characteristics – Limits and methods of

measurement, International Electrotechnical Commission, CISPR 22 Edition 5.2, 2006-03

Advanced Adapter ORing Solutions using the TPS23753, Eric Wright, TI, SLVA306

Practical Guidelines to Designing an EMI-Compliant PoE Powered Device With Isolated Flyback, Donald V.

Comiskey, TI, SLUA469

•

12.2 Support Resources

TI E2E^™support forums are an engineer's go-to source for fast, verified answers and design help — straight

from the experts. Search existing answers or ask your own question to get the quick design help you need.

Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do

not necessarily reflect TI's views; see TI's Terms of Use.

12.3 Trademarks

TI E2E^™is a trademark of Texas Instruments.

All other trademarks are the property of their respective owners.

12.4 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled

with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may

be more susceptible to damage because very small parametric changes could cause the device not to meet its published

specifications.

12.5 Glossary

TI Glossary

This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

46

Submit Document Feedback

Product Folder Links: TPS23731

PACKAGE MATERIALS INFORMATION

www.ti.com

18-Dec-2020

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

A0

B0

K0

P1

W

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

TPS23731RMTR

VQFN

RMT

45

3000

330.0

16.4

5.25

7.25

1.45

8.0

16.0

Q1

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

18-Dec-2020

*All dimensions are nominal

Device

Package Type Package Drawing Pins

VQFN RMT 45

SPQ

Length (mm) Width (mm) Height (mm)

367.0 367.0 35.0

TPS23731RMTR

3000

Pack Materials-Page 2

PACKAGE OUTLINE

VQFN - 1 mm max height

RMT0045A

PLASTIC QUAD FLATPACK-NO LEAD

A

5.1

4.9

B

PIN 1 INDEX AREA

7.1

6.9

1 MAX

C

SEATING PLANE

0.08 C

0.05

0.00

2.9±0.1

PKG

(0.1) TYP

14

22

39X 0.4

13

23

1.4

1.3751

2.15±0.1

10

9

47

0.6

PKG

0.2

0.6

29

30

2X

5.2

1.4

2.1±0.1

46

0.5

0.3

35

45X

C

1

PIN 1 ID

(OPTIONAL)

45

36

0.25

0.15

45X

3.6

3.7±0.1

0.1

0.05

A B

C

4225180/A 08/2019

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.

www.ti.com

EXAMPLE BOARD LAYOUT

VQFN - 1 mm max height

RMT0045A

PLASTIC QUAD FLATPACK-NO LEAD

(3.7)

(3.6)

PKG

45X (0.2)

45X (0.6)

36

45

39X (0.4)

1

35

(2.205)

46

(1.4)

(2.1)

(R0.05)

TYP

(0.595)

30

29

PKG

(6.8) (5.2)

(0.2)

(0.55)

(0.6)

9

47

10

(1.375) (2.15)

(2.2)

(1.4)

23

13

(Ø0.2) VIA

TYP

14

22

(2.9)

(4.8)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE: 12X

0.05 MIN

ALL AROUND

0.05 MAX

ALL AROUND

SOLDER MASK

OPENING

METAL

EXPOSED METAL

SOLDER MASK

OPENING

EXPOSED METAL

METAL UNDER

SOLDER MASK

NON- SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

4225180/A 08/2019

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown

on this view. It is recommended that vias under paste be filled, plugged or tented.

www.ti.com

EXAMPLE STENCIL DESIGN

VQFN - 1 mm max height

RMT0045A

PLASTIC QUAD FLATPACK-NO LEAD

(3.6)

PKG

45X (0.2)

45X (0.6)

6X (1.05)

36

45

39X (0.4)

6X (0.94)

35

1

(1.97)

46

(R0.05)

TYP

(0.83)

30

PKG

(6.8) (5.2)

29

(0.2)

(0.6)

9

(0.795)

4X (0.96)

10

13

47

(1.4)

(1.955)

METAL TYP

23

14

22

4X (1.27)

(4.8)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

PAD 46: 76%; PAD 47: 78%

SCALE: 12X

4225180/A 08/2019

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

www.ti.com

IMPORTANT NOTICE AND DISCLAIMER

TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE

DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”

AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY

IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD

PARTY INTELLECTUAL PROPERTY RIGHTS.

These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate

TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable

standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you

permission to use these resources only for development of an application that uses the TI products described in the resource. Other

reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third

party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims,

damages, costs, losses, and liabilities arising out of your use of these resources.

TI’s products are provided subject to TI’s Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on

ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable

warranties or warranty disclaimers for TI products.

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	TPS23731RMTR
厂家：	TEXAS INSTRUMENTS
描述：	TPS23731 IEEE 802.3bt Type 3 Class 1-4 PoE PD with No-Opto Flyback DC-DC Controller 光电二极管
文件：	总53页 (文件大小：2285K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TPS23731RMTR [TI]

相关型号：

TPS23734

TPS23734RMTR

TPS23734RMTT

TPS2375

TPS2375-1

TPS2375-1_17

TPS23750

TPS23750EVM-107

TPS23750EVM-108

TPS23750PWP