TPS23758RJJT [TI]
具有非光电同步反激式直流/直流控制器的 IEEE 802.3at PoE PD | RJJ | 23 | -40 to 125;型号: | TPS23758RJJT |
厂家: | TEXAS INSTRUMENTS |
描述: | 具有非光电同步反激式直流/直流控制器的 IEEE 802.3at PoE PD | RJJ | 23 | -40 to 125 控制器 光电二极管 |
文件: | 总48页 (文件大小:3970K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
TPS23758
ZHCSJO0A – APRIL 2019 – REVISED NOVEMBER 2020
TPS23758 具有非光电同步反激式直流/直流控制器的 IEEE 802.3at PoE PD
1 特性
3 说明
•
适用于 1 类 PoE 的完整 IEEE 802.3at PD 解决方
案
TPS23758 器件结合了以太网供电 (PoE) 供电设备
(PD) 接口、150V 开关功率 FET 和电流模式直流/直流
控制器,并针对反激式拓扑进行了优化。高集成度以及
初级侧调节 (PSR)、展频频率抖动 (SSFD) 和高级启动
使 TPS23758 成为尺寸受限应用的理想之选。PoE 实
现支持 IEEE 802.3at 标准(作为 13W、1 类 PD)。
– 提供以太网联盟 (EA) 标识认证设计
– 可靠的 100V、0.36Ω(典型值)热插拔
MOSFET
具有 0.77Ω(典型值)150V 功率 MOSFET 的集成
PWM 控制器
•
直流/直流控制器的 PSR 功能使用来自辅助绕组的反馈
来控制输出电压,无需外部并联稳压器和光耦合器。经
优化,该器件可采用连续导通模式 (CCM) 工作,并具
有次级侧同步整流功能,从而在多个输出上(例如 5V
和 3.3V 输出)实现出色的整体效率、调节精度和阶跃
负载响应。通常,转换器以 250kHz 的开关频率运行。
– 具有 PSR 的反激式控制器
•
支持 CCM 运行(采用次级侧同步 FET - 多
输出)
• ±1%(典型值,5V 输出)负载调节
(0-100% 负载范围) — 具有同步 FET
– 支持低侧开关降压拓扑
SFFD 和压摆率控制有助于最大限度地减小 EMI 滤波
器的尺寸并降低其成本。高级启动允许使用极小的偏置
电容器,同时可以简化转换器启动和间断设计。
– 具有同步功能的可调开关频率
– 具有高级启动功能的软启动控制
– 可编程压摆率和频率抖动,可增强 EMI 降低水
平
主适配器优先级输入
具有 –40°C 至 125°C 结温范围
微型 6mm x 4mm VSON 封装
初级辅助电源检测 (APD) 引脚可用于确定初级侧电源
适配器的优先级。
•
•
•
直流/直流控制器具有可调节软启动、斜率补偿和消隐
功能。对于非隔离应用,TPS23758 也支持降压拓扑。
2 应用
器件信息(1)
•
符合 IEEE 802.3at 标准的受电设备
• VoIP 电话
监控摄像头
• IP 电话
接入点
封装尺寸(标称值)
器件型号
TPS23758
封装
VSON (24)
6.00mm × 4.00mm
•
(1) 如需了解所有可用封装,请参阅数据表末尾的可订购产品附
录。
•
100
90
80
70
60
50
40
30
20
PoE
DC-DC
10
0
0
0.25 0.5 0.75 1 1.25 1.5 1.75
Load Current (A)
2
2.25
D026
效率与负载电流间的关系, 输出
简化版应用
本文档旨在为方便起见,提供有关 TI 产品中文版本的信息,以确认产品的概要。有关适用的官方英文版本的最新信息,请访问
www.ti.com,其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前,请务必参考最新版本的英文版本。
English Data Sheet: SLVSDW3
TPS23758
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ZHCSJO0A – APRIL 2019 – REVISED NOVEMBER 2020
Table of Contents
7.4 Device Functional Modes..........................................21
8 Application and Implementation..................................30
8.1 Application Information............................................. 30
8.2 Typical Application.................................................... 30
9 Power Supply Recommendations................................37
10 Layout...........................................................................37
10.1 Layout Guidelines................................................... 37
10.2 Layout Example...................................................... 37
11 Device and Documentation Support..........................39
11.1 Related documentation........................................... 39
11.2 支持资源..................................................................39
11.3 Trademarks............................................................. 39
11.4 静电放电警告...........................................................39
11.5 术语表..................................................................... 39
12 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 5
6.1 Absolute Maximum Ratings........................................ 5
6.2 ESD Ratings............................................................... 5
6.3 Recommended Operating Conditions.........................6
6.4 Thermal Information....................................................6
6.5 Electrical Characteristics: DC-DC Controller
Section.......................................................................... 7
6.6 Electrical Characteristics: PoE and Control................ 9
6.7 Typical Characteristics..............................................10
7 Detailed Description......................................................14
7.1 Overview...................................................................14
7.2 Functional Block Diagram.........................................15
7.3 Feature Description...................................................16
Information.................................................................... 39
12.1 Package Option Addendum....................................40
4 Revision History
Changes from Revision * (April 2019) to Revision A (November 2020)
Page
更新了整个文档的表、图和交叉参考的编号格式................................................................................................ 1
使用 Dvb 更新了简化版应用 .............................................................................................................................. 1
•
•
• Added, "...and 6.2-V Zener diode..."...................................................................................................................3
• Added paragraph, "VB is the 5-V bias rail..."....................................................................................................17
• Updated 图 8-1 to include Dvb..........................................................................................................................30
• Added section, "Bias Voltage, CVB and DVB"..................................................................................................31
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5 Pin Configuration and Functions
A1
A4
24
DRAIN
1
2
3
4
5
RSNS
NC
23
CP
GND
SRR
SRF
VCC
TST
21
20
19
18
17
16
15
14
13
VB
APD
CS
6
7
COMP
FB
8
SST
CLS
DEN
VPD
VDD
9
DTHR
FRS
RTN
VSS
10
11
12
A2
A3
图 5-1. Package Pinout
表 5-1. Pin Functions
PIN
I/O
DESCRIPTION
NO.
NAME
1
RSNS
O
O
Switching Power FET source connection. Connect to the external power current sense resistor.
CP provides the clamp for the primary side regulation loop. Connect this pin to the lower end of the
second primary side winding of the transformer.
2
3
4
CP
GND
SRR
Power ground used by the flyback power FET gate driver and CP. Connect to RTN.
—
Switching FET Gate sinking current input, used for EMI control. Connect a resistance from SRR to
GND to control the Vds rate of rise.
I
Switching FET Gate sourcing current input, used for EMI control. Connect a resistance from SRF
to VB to control the Vds rate of fall.
5
6
SRF
VB
I
5-V bias rail for the switching FET gate driver circuit. For internal use only. Bypass with a 0.1-μF
ceramic capacitor and 6.2-V Zener diode to GND pin.
O
Primary auxiliary power detect input. Raise 1.5 V above RTN to disable pass MOSFET. If not used,
connect APD to RTN.
7
8
9
APD
CS
I
I
DC-DC controller current sense input. Connect directly to the external power current sense resistor.
Used for spread spectrum frequency dithering. Connect a capacitor from DTHR to RTN and a
resistor from DTHR to FRS. If dithering is not used, short DTHR to VB pin.
DTHR
O
This pin controls the switching frequency of the DC-DC converter. Tie a resistor from this pin to
RTN to set the frequency.
10
FRS
I/O
11
12
RTN
VSS
RTN is the output of the PoE hotswap and the reference ground for the DC-DC controller.
Negative power rail derived from the PoE source.
—
—
Source of DC-DC converter start-up current. For flyback applications, connect to VPD through a
diode and bypass with a 0.22 µF to RTN. For buck applications, connect directly to VPD.
13
14
VDD
VPD
—
—
Positive input power rail for PoE interface circuit. Derived from the PoE source. Bypass with a 0.1
µF to VSS and protect with a TVS.
Connect a 24.9-kΩ resistor from DEN to VPD to provide the PoE detection signature. Pulling this
15
16
17
DEN
CLS
SST
I/O
O
I
pin to VSS during powered operation causes the internal hotswap MOSFET to turn off.
Connect a resistor from CLS to VSS to program the classification current.
SST sets the soft-start and the hiccup timer for the DC-DC converter. Connect a capacitor from this
pin to RTN to set the DC/DC startup rate.
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表 5-1. Pin Functions (continued)
PIN
I/O
DESCRIPTION
NO.
NAME
Converter error amplifier inverting (feedback) input. It is typically driven by a voltage divider from
the auxiliary winding. Also connect to the COMP compensation network.
18
FB
I
Compensation output of the DC-DC convertor error amplifier. Connect the compensation networks
from this pin to the FB pin to compensate the converter.
19
20
21
COMP
TST
O
Used internally for test purposes only. Leave open.
—
DC/DC converter bias voltage. The internal startup current source and converter bias winding
output power this pin. Connect a 3.3-µF minimum ceramic capacitor to RTN.
VCC
I/O
23
24
NC
No connect pin. Leave open.
—
DRAIN
O
Drain connection to the internal switching power MOSFET of the DC/DC controller.
The exposed thermal pad must be connected to VSS. A large fill area is required to assist in heat
dissipation.
-
PAD
—
—
A1-A4
ANCHORS
Should be soldered to PCB for mechanical performance. These pins are not connected internally.
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6 Specifications
6.1 Absolute Maximum Ratings
Voltage are with respect to VVSS (unless otherwise noted)(1)
MIN
MAX
100
100
6.5
UNIT
VDD, VPD, DEN, GND, RTN(2)
–0.3
–0.3
–0.3
–0.3
–0.3
VDD to RTN
Input voltage
V
APD, FB, CS, all to RTN
SRF to GND
CLS(3)
6.5
6.5
FRS(3), COMP(3), VB(3), SRR(3), DTHR(3), RSNS(3), SST(3), all to
RTN
6.5
–0.3
VCC to RTN
19
150
60
–0.3
–0.3
–0.3
–0.3
Voltage
V
DRAIN to GND
CP to GND
GND to RTN
0.3
VB, VCC
Internally limited
35
Internally limited
Internally limited
Sourcing current
CLS
mA
mA
COMP
RTN
Sinking current
DEN
1
COMP
Internally limited
Switching DRAIN peak current limit
2
IDRAIN
A
A
Switching DRAIN peak current limit, Buck topology with 16% duty-
cycle
3
Peak sourcing
current
CP
1.5
0.5
Peak sinking current CP
TJ(max) Maximum junction temperature
Tstg Storage temperature
A
Internally Limited
150
°C
°C
–65
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2) IRTN = 0 for VRTN > 80 V.
(3) Do not apply voltage to these pins.
6.2 ESD Ratings
VALUE
±2000
±500
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
IEC 61000-4-2 contact discharge(3)
V(ESD)
Electrostatic discharge
V
±8000
±15000
IEC 61000-4-2 air-gap discharge(3)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
(3) ESD per EN61000-4-2, applied between RJ-45 and output ground of the evaluation module. These were the test levels, not the failure
threshold.
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6.3 Recommended Operating Conditions
Voltage with respect to VVSS (unless otherwise noted)
MIN
0
NOM
MAX
57
UNIT
VDD, VPD, RTN, GND
VCC to RTN
0
16
APD to RTN
Input voltage range
CS to RTN
0
VB
2
V
0
DRAIN to GND
CP to GND
0
125
45
0
Sinking current
RTN
350
1.6
2.5
mA
A
DRAIN, RSNS
Peak current limit
DRAIN, RSNS, Buck topology with 16% duty-cycle
Peak sourcing
current
CP
500
100
mA
mA
Peak sinking
current
CP
VB(1)
0.08
0.8
30
0.1
1
Capacitance
μF
VCC
CLS(1)
Resistance
SRF to VB
SRR to GND
100
15
Ω
Synchronization
pulse width input
(when used)
FRS
35
ns
°C
TJ
Operating junction temperature
125
–40
(1) Voltage should not be externally applied to this pin.
6.4 Thermal Information
TPS23758
THERMAL METRIC(1)
RJJ (VSON)
24 PINS
34.7
UNIT
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
24.5
14.5
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
6.4
ψJT
14.5
ψJB
RθJC(bot)
6.4
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
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6.5 Electrical Characteristics: DC-DC Controller Section
Unless otherwise noted, VVDD = 48 V; RDEN = 24.9 kΩ; RFRS = 60.4 kΩ; CLS, RSNS and DRAIN open; CS, APD, and GND
connected to RTN; SRR connected to GND; SRF, FB and DTHR connected to VB; CVB = 0.1 μF; CCC = 1 μF; CSST = 0.022
µF; 8.5 V ≤ VVCC ≤ 16 V; –40°C ≤ TJ ≤ 125°C. Positive currents are into pins unless otherwise noted. Typical values are
at 25°C.
[VVSS = VRTN and VVPD = VVDD] or [VVSS = VRTN = VVPD], all voltages referred to VRTN and VGND unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DC-DC SUPPLY (VCC)
VCUVR
VCUVF
VCUVH
VVCC rising
8
5.85
2
8.25
6.1
8.6
6.25
2.5
V
V
V
Undervoltage lockout
VVCC falling
Hysteresis(1)
2.15
VVCC = 10 V, VFB = VRTN = VRSNS
DRAIN with 2-kΩ pull up to 95 V, CP
with 2-kΩ pull up to 30 V
,
Operating current, converter
switching
IRUN
2.35
2.7
mA
VDD = 10.2 V, VVCC(0) = 0 V
VDD = 35 V, VVCC(0) = 0 V
0.5
0.5
1.0
2.5
1.5
ms
ms
tST
Start-up time, CCC = 1 μF
0.80
Measure VVCC during startup, IVCC
0 mA
=
VVC_ST
VCC startup voltage
11
13
15.5
V
DC-DC TIMING (FRS)
VFB = VRSNS = VRTN, Measure at
DRAIN
fSW
Switching frequency
223
248
273
kHz
VFB = VRSNS = VRTN, Measure at
DRAIN
DMAX
Duty cycle
75%
2
77.5%
2.2
80%
2.4
VSYNC
Synchronization
Input threshold
V
FREQUENCY DITHERING RAMP GENERATOR (DTHR)
3 x IFRS
49.6
µA
µA
µA
µA
V
IDTRCH
Charging (sourcing) current
Discharging (sinking) current
0.5 V < VDTHR < 1.38 V
0.6 V < VDTHR < 1.5 V
47.2
52.1
3 x IFRS
49.6
IDTRDC
47.2
1.41
52.1
1.60
VDTUT
VDTLT
Dithering upper threshold
Dithering lower threshold
Dithering pk-pk amplitude
VDTHR rising until IDTHR > 0
VDTHR falling until IDTHR < 0
1.513
0.487
1.026
0.43
0.54
V
VDTPP
1.005
1.046
V
ERROR AMPLIFIER (FB, COMP)
VREFC
IFB_LK
GBW
Feedback regulation voltage
1.723
1.75
1.777
0.5
V
FB leakage current (source or sink) VFB-RTN = 1.75 V
Small signal unity gain bandwidth
μA
MHz
dB
0.9
70
1.2
90
AOL
Open loop voltage gain
VCOMP falling until DRAIN switching
stops
VZDC
0% duty-cycle threshold
1.35
1.5
1.65
V
ICOMPH
ICOMPL
COMP source current
COMP sink current
VFB = VRTN , VCOMP = 3 V
VFB = VVB , VCOMP = 1.25 V
1
mA
mA
2.1
6
VFB = VVB , 15 kΩ from COMP to
RTN
VCOMPH
VCOMPL
COMP high voltage
4
5
V
COMP low voltage
COMP to CS gain
1.1
V
VFB = VVB , 15 kΩ from COMP to VB
ΔVCS / ΔVCOMP , 0 V < VCS < 0.5 V
0.475
0.5
0.525
V/V
SOFT-START (SST)
ISSC Charge (sourcing) current
ISSD Discharge (sinking) current
SST charging, VSST between lower
and higher threshold
3
3
4
4
5
5
µA
µA
SST discharging, VSST between
lower and higher threshold
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6.5 Electrical Characteristics: DC-DC Controller Section (continued)
Unless otherwise noted, VVDD = 48 V; RDEN = 24.9 kΩ; RFRS = 60.4 kΩ; CLS, RSNS and DRAIN open; CS, APD, and GND
connected to RTN; SRR connected to GND; SRF, FB and DTHR connected to VB; CVB = 0.1 μF; CCC = 1 μF; CSST = 0.022
µF; 8.5 V ≤ VVCC ≤ 16 V; –40°C ≤ TJ ≤ 125°C. Positive currents are into pins unless otherwise noted. Typical values are
at 25°C.
[VVSS = VRTN and VVPD = VVDD] or [VVSS = VRTN = VVPD], all voltages referred to VRTN and VGND unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VSFST
Soft-start lower threshold
0.15
0.2
0.25
V
VSST rising until VCC startup turns
off
VSTUOF
Startup turn off threshold
1.99
2.1
2.21
V
VSSOFS
VSSCL
Soft-start offset voltage
Soft-start clamp
VSST rising until start of switching
0.2
2.3
0.25
0.3
2.6
V
V
CURRENT SENSE (CS)
VCSMAX
Maximum threshold voltage
VFB = VRTN, VCS rising
VCS = 0.65 V
0.5
25
0.55
41
0.6
60
V
tOFFDEL_ILM Current limit turnoff delay
tOFFDEL_PW PWM comparator turnoff delay
Blanking delay
ns
VCS = 0.4 V
25
41
60
In addtition to tOFFDEL
56.5
75
93.5
ns
Peak voltage at maximum duty
cycle, referred to CS
VSLOPE
ISL_EX
Internal slope compensation voltage
120
155
185
mV
VFB = VRTN, ICS at maximum duty
cycle (ac component)
Peak slope compensation current
Bias current
30
42
-5
54
μA
μA
DC component of CS current
-6.7
-3.3
SWITCHING POWER FET (DRAIN, RSNS)
BVDSS
Power FET break-down voltage
Power FET on resistance
150
0.6
V
RDS(ON)
0.77
1
1.28
1.1
Ω
Source-to-drain diode forward
voltage
VSD
IRSNS = 500 mA
V
AUXILIARY POWER DETECTION (APD)
VAPDEN
VAPD rising
1.42
0.28
1.5
0.3
1.58
0.32
1
V
V
APD threshold voltage
VAPDH
Hysteresis(1)
Leakage current
THERMAL SHUTDOWN
Turnoff temperature
Hysteresis(2)
VAPD-RTN = 5 V
µA
145
159
13
165
°C
°C
(1) The hysteresis tolerance tracks the rising threshold for a given device.
(2) These parameters are provided for reference only, and do not constitute part of TI's published device specifications for purposes of TI's
product warranty.
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6.6 Electrical Characteristics: PoE and Control
Unless otherwise noted, VVPD = 48 V; RDEN = 24.9 kΩ; RFRS = 60.4 kΩ; CLS, RSNS and DRAIN open; CS, APD, and GND
connected to RTN; SRR connected to GND; SRF, FB and DTHR connected to VB; CVB = 0.1 μF; CCC = 1 μF; CSST = 0.022
μF; –40°C ≤ TJ ≤ 125°C. Positive currents are into pins unless otherwise noted. Typical values are at 25°C.
Unless otherwise noted, VVPD = VVDD , VVCC = VRTN. All voltages referred to VVSS unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN TYP MAX UNIT
PD DETECTION (DEN)
Detection bias current
DEN leakage current
DEN open, VVPD = 10 V, Measure IVPD + IVDD + IDEN + IRTN
VDEN = VVPD = 57 V, Measure IDEN
3.5 8.3
0.1
13.9
5
µA
µA
μA
μA
V
Ilkg
Measure IVPD + IVDD + IDEN + IRTN , VVPD = 1.4 V
Measure IVPD + IVDD + IDEN + IRTN , VVPD = 10 V
55.5 56.3
60
Detection current
400 407 414.5
VPD_DIS
Hotswap disable threshold
3
4
5
PD CLASSIFICATION (CLS)
1.8 2.14
9.9 10.6
17.6 18.6
26.5 27.9
10.7 12.1
0.6 1.1
2.4
11.3
19.4
29.3
13
RCLS = 649 Ω
13 V ≤ VDD ≤ 21 V,
Measure IVPD + IVDD + IDEN
IRTN
RCLS = 121 Ω
ICLS
Classification current
mA
+
RCLS = 68.1 Ω
RCLS = 45.3 Ω
VCL_ON
VCL_HYS
VCU_OFF
VCU_HYS
Ilkg
Regulator turns on, VVPD rising
Hysteresis(1)
V
V
Classification regulator lower
threshold
1.55
23
Regulator turns off, VVPD rising
Hysteresis(1)
21
22
V
Classification regulator upper
threshold
0.5 0.77
1
V
Leakage current
VVPD = 57 V, VCLS = 0 V, VDEN = VVSS, Measure ICLS
1
μA
RTN (PASS DEVICE)
ON-resistance
0.36
405 550
100 140
11 12.3
0.68
Ω
Current limit
VRTN = 1.5 V, pulsed measurement
VRTN = 2 V, VVPD: 0 V → 48 V, pulsed measurement
VRTN rising
800 mA
220 mA
Inrush current limit
Foldback voltage threshold
Foldback deglitch time
Leakage current
13.6
600
40
V
VRTN rising to when current limit changes to inrush current limit
VVPD = VRTN = 100 V, VDEN = VVSS
150 387
µs
Ilkg
μA
PD INPUT SUPPLY (VPD, VDD)
UVLO_R
VVPD rising
34.7 35.5
4.1 4.5
36.7
4.7
V
V
Undervoltage lockout threshold
UVLO_H
Hysteresis (1)
VCC open, 40 V ≤ VVPD = VVDD ≤ 57 V, Startup completed, Measure IVPD
IVDD
+
Operating current
Off-state current
300
580
330
IVPD_VDD
µA
RTN, GND and VCC open, VVPD = 30 V, Measure IVPD
THERMAL SHUTDOWN
Turnoff temperature
Hysteresis(2)
145 159
13
165
°C
°C
(1) The hysteresis tolerance tracks the rising threshold for a given device.
(2) These parameters are provided for reference only.
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6.7 Typical Characteristics
12.5
570
568
566
564
562
560
TJ = -40èC
TJ = 25èC
TJ = 125èC
10
7.5
5
2.5
0
1
2
3
4
VPD-VSS Voltage (V)
5
6
7
8
9
10
-50
-25
0
25
50
75
100
125
Junction Temperature (èC)
D001
D004
图 6-1. Detection Bias Current vs Voltage
图 6-2. PoE Current Limit vs Temperature
160
158
156
154
152
150
148
146
0.6
0.55
0.5
0.45
0.4
0.35
0.3
0.25
-50
-25
0
25
50
75
100
125
-50
-25
0
25
50
75
100
125
Junction Temperature (èC)
Junction Temperature (èC)
D005
D003
图 6-3. PoE Inrush Current Limit vs Temperature
图 6-4. Pass FET Resistance vs Temperature
650
1.25
1.2
TJ = -40èC
TJ = 25èC
TJ = 125èC
CCC = 1 mF
VVDD = 10.2 V
VVDD = 35 V
600
550
500
450
400
350
300
250
1.15
1.1
1.05
1
0.95
0.9
0.85
0.8
0.75
0.7
25
30
35
40 45
VPD-VSS Voltage (V)
50
55
60
-50
-25
0
25
50
75
100
125
Junction Temperature (èC)
D002
D007
图 6-5. VPD and VDD Supply Current vs Voltage
图 6-6. Converter Startup Time vs Temperature
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6.7 Typical Characteristics (continued)
400
350
300
250
200
150
100
50
3.5
3
2.5
RFRS = 37.4 kW
RFRS = 60.4 kW
RFRS = 301 kW
RFRS = 37.4 kW
RFRS = 60.4 kW
RFRS = 301 kW
2
1.5
1
0
-50
-25
0
25
50
75
100
125
Junction Temperature (èC)
9
9.5 10 10.5 11 11.5 12 12.5 13 13.5 14
VCC Voltage (V)
D008
D029
图 6-8. Switching Frequency vs Temperature
图 6-7. Controller Bias Current vs Voltage
800
600
400
200
0
51
TJ = 25èC
50.5
50
49.5
49
0
5
10
15
20
25
30
35
40
45
50
0.5
0.75
1
DTHR Voltage (V)
1.25
1.5
Programmable Conductance, 106/RFRS (W-1
)
D009
D015
图 6-9. Switching Frequency vs Programmed Resistance
图 6-10. Frequency Dithering Charging Current
51
1.022
TJ = 25èC
1.021
1.02
50.5
50
1.019
1.018
1.017
1.016
1.015
1.014
49.5
49
0.5
0.75
1
DTHR Voltage (V)
1.25
1.5
-50
-25
0
25
50
75
100
125
Junction Temperature (èC)
D016
D017
图 6-11. Frequency Dithering Discharging Current
图 6-12. Frequency Dithering Peak-to-Peak Amplitude
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6.7 Typical Characteristics (continued)
1.76
50
48
46
44
42
40
38
36
1.755
1.75
1.745
1.74
-50
-25
0
25
50
75
100
125
-50
-25
0
25
50
75
100
125
Junction Temperature (èC)
Junction Temperature (èC)
D020
D010
图 6-13. Feedback Regulation Voltage vs Temperature
图 6-14. Current Slope Compensation Current vs Temperature
80
50
78
76
74
72
70
48
46
44
42
40
-50
-25
0
25
50
75
100
125
-50
-25
0
25
50
75
100
125
Junction Temperature (èC)
Junction Temperature (èC)
D011
D013
图 6-15. Blanking Period vs Temperature
图 6-16. Converter PWM Comparator Delay vs Temperature
50
4
TJ = -40èC
TJ = 25èC
TJ = 125èC
48
46
44
42
40
3
2
1
0
-50
-25
0
25
50
75
100
125
0
0.8
1.6
2.4 3.2
COMP Voltage (V)
4
4.8
5.6
Junction Temperature (èC)
D012
D018
图 6-17. Converter Current Limit Delay vs Temperature
图 6-18. Error Amplifier Source Current
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6.7 Typical Characteristics (continued)
12
100
90
80
70
60
50
40
30
20
10
0
TJ = -40èC
TJ = 25èC
TJ = 125èC
10
8
6
4
TJ = -40èC
TJ = 25èC
2
0
TJ = 125èC
-10
-20
0.5
1
1.5
2
2.5
COMP Voltage (V)
3
3.5
4
100
1k
10k 100k
Frequency (Hz)
1M
D019
D023
图 6-19. Error Amplifier Sink Current
图 6-20. Error Amplifier Gain vs Frequency
135
120
105
90
75
60
45
30
15
0
1.4
1.2
1
TJ = -40èC
TJ = 25èC
TJ = 125èC
0.8
0.6
0.4
100
1k
10k 100k
Frequency (Hz)
1M
-50
-25
0
25
50
75
100
125
Junction Temperature (èC)
D024
D014
图 6-21. Error Amplifier Phase vs Frequency
图 6-22. Switching FET Resistance vs Temperature
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7 Detailed Description
7.1 Overview
The TPS23758 device is a 24-pin integrated circuit that contains all of the features needed to implement an
IEEE802.3at Type-1 powered device (PD), combined with a fully integrated 150-V switching power FET and a
current-mode DC-DC controller optimized for flyback switching regulator designs using primary side control. The
TPS23758 applies to flyback converter applications requiring the use of secondary side synchronous rectifiers,
with single or multiple outputs.
Basic PoE PD functionality supported includes detection, hardware classification, and inrush current limit during
startup. DC-DC converter features include startup function and current mode control operation. The TPS23758
device integrates a low 0.36-Ω internal switch to support Type-1 applications.
The TPS23758 features a primary auxiliary power detect (APD) input, providing priority for a primary external
power adapter.
The TPS23758 device contains several protection features such as ƒ, current limit foldback, and a robust 100-V
internal return switch.
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7.2 Functional Block Diagram
VCC
VDD
Regulator
COMP
t
FB
E/A
+
+
50kꢀ
50kꢀ
Vrefc
(1.75V)
disch
t
4 ꢁA
chrg
0.25 V
+
Converter off
from PD
RTN
uvlo
Control
SST
disch
4 ꢁA
chrg
disch
VB
Regulator
RTN
Reference
Current Ramp
+
0.75 V
SRF
40 ꢁA (pk)
t
CS
DRAIN
3.75k ꢀ
Blanking
Control
1
D
Q
+
CLRB
CLK
RSNS
SRR
0.55 V
t
FRS
Oscillator
CP
CP
DTHR
GND
Detection
Comp.
Class
Comp.
4V
12.1V &
11V
VPD
Class
Comp.
VSS
DEN
CLS
22V &
21.2V
1.25V
REG.
400µS
m
12.3V
& 1V
APD
Comp.
APD
1.5V
&1.2V
RTN
Converter OFF
RTN
S
Q
R
Inrush latch
Inrush limit
threshold
1
0
35.5V &
31V
UVLO
Comp.
1
0
Current limit
threshold
OTSD
IRTN sense
High if over
temperauture
VSS
RTN
Signals referenced to VSS unless
otherwise noted
Hotswap
MOSFET
IRTN sense,1 if < 90% of inrush and current limit
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7.3 Feature Description
See 图 8-1 for component reference designators (RCS for example ), and Electrical Characteristics: DC-DC
Controller Section for values denoted by reference (VCSMAX for example). Electrical Characteristic values take
precedence over any numerical values used in the following sections.
7.3.1 CLS Classification
An external resistor (RCLS in 图 8-1) connected between the CLS pin and VSS provides a classification signature
to the PSE. The controller places a voltage of approximately 1.25 V across the external resistor whenever the
voltage differential between VPD and VSS lies from about 11 V to 22 V. The current drawn by this resistor,
combined with the internal current drain of the controller and any leakage through the internal pass MOSFET,
creates the classification current. 表 7-1 lists the external resistor values required for each of the PD power
ranges defined by IEEE802.3at. The maximum average power drawn by the PD, plus the power supplied to the
downstream load, should not exceed the maximum power indicated in Table 7-1. The TPS23758 supports class
0 – 3 power levels.
表 7-1. Class Resistor Selection
POWER AT PD PI
CLASS
RESISTOR (Ω)
MINIMUM (W)
0.44
MAXIMUM (W)
12.95
0
1
2
3
649
121
0.44
3.84
3.84
6.49
68.1
45.3
6.49
12.95
7.3.2 DEN Detection and Enable
DEN pin implements two separate functions. A resistor (RDEN in 图 8-1) connected between VPD and DEN
generates a detection signature whenever the voltage differential between VPD and VSS lies from approximately
1.4 to 11 V. Beyond this range, the controller disconnects this resistor to save power. The IEEE 802.3at standard
specifies a detection signature resistance, RDEN from 23.75 kΩ to 26.25 kΩ, or 25 kΩ ± 5%. TI recommends a
resistor of 24.9 kΩ ± 1% for RDEN
.
Pulling DEN to VSS during powered operation causes the internal hotswap MOSFET and class regulator to turn
off. If the resistance connected between VDD and DEN is divided into two roughly equal portions, then the
application circuit can disable the PD by grounding the tap point between the two resistances, while
simultaneously spoiling the detection signature which prevents the PD from properly re-detecting.
7.3.3 APD Auxiliary Power Detect
The APD pin is used in applications that may draw power either from the Ethernet cable or from an auxiliary
power source. When a voltage of more than about 1.5 V is applied on the APD pin relative to RTN, the
TPS23758 does the following:
• Internal pass MOSFET is turned off
• Classification current is disabled
This also gives adapter source priority over the PoE. If not used, connect APD to RTN.
7.3.4 Internal Pass MOSFET
RTN pin provides the negative power return path for the load. It is internally connected to the drain of the PoE
hotswap MOSFET, and the DC-DC controller return. RTN must be treated as a local reference plane (ground
plane) for the DC-DC controller and converter primary to maintain signal integrity.
Once VVPD exceeds the UVLO threshold, the internal pass MOSFET pulls RTN to VSS. Inrush limiting prevents
the RTN current from exceeding a nominal value of about 140 mA until the bulk capacitance (CBULK in 图 8-1) is
fully charged. Inrush ends when the RTN current drops below about 125 mA. The RTN current is subsequently
limited to about 0.45 A.
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If RTN ever exceeds about 12.3 V for longer than 400 μs, then the PD returns to inrush limiting.
7.3.5 DC-DC Controller Features
The TPS23758 device DC-DC controller implements a typical current-mode control as shown in Functional Block
Diagram. Features include oscillator, overcurrent and PWM comparators, current-sense blanker, soft start, gate
driver and switching power FET. In addition, an internal current-compensation ramp generator, frequency
synchronization logic, built-in frequency dithering functionality, thermal shutdown, and start-up current source
with control are provided.
The TPS23758 is optimized for isolated converters, and it includes an internal error amplifier. The voltage
feedback is from the bias winding. The COMP output of the error amplifier is directly fed to a 2:1 internal resistor
divider and an offset of VZDC/2 (approximately 0.75 V) which defines a current-demand control for the pulse
width modulator (PWM). A VCOMP below VZDC stops converter switching, while voltages above (VZDC + 2 ×
(VCSMAX + VSLOPE)) does not increase the requested peak current in the switching MOSFET.
The internal start-up current source and control logic implement a bootstrap-type startup. The startup current
source charges CCC from VDD and maintain its voltage when the converter is disabled or during the soft-start
period, while operational power must come from a converter (bias winding) output.
The bootstrap source provides reliable start-up from widely varying input voltages, and eliminates the continual
power loss of external resistors.
The peak current limit does not have duty cycle dependency unless RS is used as shown in 图 7-2 to increase
slope compensation. This makes it easier to design the current limit to a fixed value.
The DC-DC controller has an OTSD that can be triggered by heat sources including the power switching FET
and GATE driver. The controller OTSD turns off the switching FET and resets the soft-start generator.
7.3.5.1 VCC, VB and Advanced PWM Startup
The VCC pin connects to the auxiliary bias supply for the DC-DC controller. The switching MOSFET gate driver
draws current directly from the VB pin, which is the output of an internal 5-V regulator fed from VCC. A startup
current source from VDD to VCC implements the converter bootstrap startup. VCC must receive power from an
auxiliary source, such as an auxiliary winding on the flyback transformer, to sustain normal operation after
startup.
The startup current source is turned on during the inrush phase, charging CCC and maintaining its voltage, and it
is turned off only after the DC-DC soft-start cycle has been completed, which occurs when the DC-DC converter
has ramped up its output voltage, as shown in 图 7-1. Internal loading on VCC and VB is initially minimal while
CCC charges, to allow the converter to start. Due to the high current capability of the startup source, the
recommended capacitance at VCC is relatively small, typically 1 μF in most applications.
VB is the 5-V bias rail for the switching FET gate driver circuit. A 0.1-μF bypass capacitor between VB and RTN
is required. Additionally, a 6.2-V Zener diode from VB to RTN is required.
Once VVCC falls below its UVLO threshold, the converter shuts off and the startup current source is turned back
on, initiating a new PWM startup cycle.
High current startup is ON for the whole soft-start
cycle to allow low VCC capacitance
VCC Startup Source ON
End of Soft-Start, Startup source
turned off
PD + Power Supply Fully
Operational
HSW cap
recharge
Soft Start
图 7-1. Advanced Startup
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7.3.5.2 CS, Current Slope Compensation and Blanking
The current-sense input for the DC-DC converter should be connected to the high side of the current-sense
resistor of the switching MOSFET. The current-limit threshold, VCSMAX, defines the voltage on CS above which
the switching FET ON-time is terminated regardless of the voltage on COMP output.
Routing between the current-sense resistor and the CS pin must be short to minimize cross-talk from noisy
traces such as DRAIN and CP, and to a lower degree to SRR and SRF.
Current-mode control requires addition of a compensation ramp to the sensed inductor (flyback transformer)
current for stability at duty cycles near and over 50%. The TPS23758 has a maximum duty cycle limit of 78.5%,
permitting the design of wide input-range flyback converters with a lower voltage stress on the output rectifiers.
While the maximum duty cycle is 78.5%, converters may be designed that run at duty cycles well below this for a
narrower, 36-V to 57-V range. The TPS23758 provides a fixed internal compensation ramp that suffices for most
applications. RS (see 图 7-2) may be used if the internally provided slope compensation is not enough. It works
with ramp current (IPK = ISL-EX, approximately 40 μA) that flows out of the CS pin when the MOSFET is on. The
IPK specification does not include the approximately 5-μA fixed current that flows out of the CS pin.
Most current-mode control papers and application notes define the slope values in terms of VPP/TS (peak ramp
voltage / switching period); however, Electrical Characteristics: DC-DC Controller Section specifies the slope
peak (VSLOPE) based on the maximum duty cycle. Assuming that the desired slope, VSLOPE-D (in mV/period), is
based on the full period, compute RS per 方程式 1 where VSLOPE, DMAX, and ISL-EX are from Electrical
Characteristics: DC-DC Controller Section with voltages in mV, current in μA, and the duty cycle is unitless (for
example, DMAX = 0.78).
VSLOPE (mV)
:
;
BVSLOPE _D mV F @
W
AC
DMAX
: ;
RS 3 =
× 1000
I
(JA)/DMAX
SLEX
(1)
DRAIN
RSNS
CS
RS
RCS
CS
图 7-2. Additional Slope Compensation
Blanking provides an interval between the FET gate drive going high and the current comparator on CS actively
monitoring the input. This delay allows the normal turnon current transient (spike) to subside before the
comparator is active, preventing undesired short duty cycles and premature current limiting.
The TPS23758 blanker timing is precise enough that the traditional R-C filters on CS can be eliminated. This
avoids current-sense waveform distortion, which tends to get worse at light output loads. There may be some
situations or designers that prefer an R-C approach, for example if the presence of RS causes increased noise,
due to adjacent noisy signals, to appear at CS pin. The TPS23758 provides a pulldown on CS (approximately
400 Ω) during the GATE OFF-time to improve sensing when an R-C filter must be used, by reducing cycle-to-
cycle carry-over voltage on CS.
7.3.5.3 COMP, FB, CP and Opto-less Feedback
The TPS23758 DC-DC controller implements current-mode control, using a voltage control loop error amplifier
(pins FB and COMP) to define the input reference voltage of the current mode control comparator which
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determines the switching MOSFET peak current. Loop compensation components are connected between
COMP and FB.
VCOMP below VZDC causes the converter to stop switching. The maximum (peak) current is requested at
approximately (VZDC + 2 × (VCSMAX + VSLOPE)). The AC gain from COMP to the PWM comparator is 0.5.
The TPS23758 DC-DC controller can operate with feedback from an auxiliary winding of the flyback power
transformer, eliminating the need for external shunt regulator and optocoupler. It also operates with continuously
connected feedback, enabling better optimization of the power supply, and resulting in significantly lower noise
sensitivity.
Opto-less operation of the TPS23758 is achieved with a unique approach which basically consists in cancelling
the leading-edge voltage overshoot (causing VCC to peak-charge) generated by the transformer winding. When
combined with a correctly designed power transformer, less than ±2% load regulation over the full output current
range becomes achievable in applications making use of secondary side synchronous rectifiers. Operation is in
continuous conduction mode (CCM), also enabling multi-output architectures.
7.3.5.4 FRS Frequency Setting and Synchronization
The FRS pin programs the (free-running) oscillator frequency, and may also be used to synchronize the
TPS23758 converter to a higher frequency. The internal oscillator sets the maximum duty cycle and controls the
current-compensation ramp circuit, making the ramp height independent of frequency. RFRS must be selected
per 方程式 2.
15000
RFRS (k3) =
fSW (kHz)
(2)
The TPS23758 may be synchronized to an external clock to eliminate beat frequencies from a sampled system,
or to place emission spectrum away from an RF input frequency. Synchronization may be accomplished by
applying a short pulse ( > 35 ns) of magnitude VSYNC to FRS as shown in 图 7-3. RFRS must be chosen so that
the maximum free-running frequency is just below the desired synchronization frequency. The synchronization
pulse terminates the potential ON-time period, and the OFF-time period does not begin until the pulse
terminates. A short pulse is preferred to avoid reducing the potential ON-time.
Figure 7-3 shows examples of nonisolated and transformer-coupled synchronization circuits. RT reduces noise
susceptibility for the isolation transformer implementation. The FRS node must be protected from noise because
it is high impedance.
Synchronization
Synchronization
Pulse
FRS
Pulse
FRS
47pF
47pF
1000pF
TSYNC
VSYNC
TSYNC
1:1
VSYNC
Copyright © 2016, Texas Instruments Incorporated
图 7-3. Synchronization
7.3.5.5 Frequency Dithering for Spread Spectrum Applications
The international standard CISPR 22 (and adopted versions) is often used as a requirement for conducted
emissions. Ethernet cables are covered as a telecommunication port under section 5.2 for conducted emissions.
Meeting EMI requirements is often a challenge, with the lower limits of Class B being especially hard. Circuit
board layout, filtering, and snubbing various nodes in the power circuit are the first layer of control techniques. A
more detailed discussion of EMI control is presented in Practical Guidelines to Designing an EMI Compliant PoE
Powered Device With Isolated Flyback, SLUA469. Additionally, IEEE 802.3at sections 33.3 and 33.4 have
requirements for noise injected onto the Ethernet cable based on compatibility with data transmission.
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A technique referred to as frequency dithering can also be used to provide additional EMI measurement
reduction. The switching frequency is modulated to spread the narrowband individual harmonics across a wider
bandwidth, thus lowering peak measurements.
Frequency dithering is a built-in feature of the TPS23758. The oscillator frequency can be dithered by
connecting a capacitor from DTHR to RTN and a resistor from DTHR to FRS. An external capacitor, CDTR (图
8-1), is selected to define the modulation frequency fm. This capacitor is being continuously charged and
discharged between slightly less than 0.5 V and slightly above 1.5 V by a current source/sink equivalent to
approximately 3x the current through FRS pin. CDTR value is defined according to:
3
W
RFRS (3)
CDTR
=
2.052 × fm (Hz)
(3)
fm should always be higher than 9 kHz, which is the resolution bandwidth applied during conducted emission
measurement. Typically, fm should be set to around 11 kHz to account for component variations.
The resistor RDTR is used to determine ∆f, which is the amount of dithering, and its value is determined
according to:
0.513 × RFRS (3)
RDTR (3) =
%DTHR
(4)
For example, a 13.2% dithering with a nominal switching frequency of 250 kHz results in frequency variation of
±33 kHz.
7.3.5.6 SST and Soft-Start of the Switcher
Converters require a soft-start on the voltage error amplifier to prevent output overshoot on startup. In PoE
applications, the PD also needs soft-start to limit its input current at turnon below the limit allocated by the power
source equipment (PSE).
The TPS23758 provides primary side closed loop controlled soft-start, which applies a slowly rising ramp voltage
to a second control input of the error amplifier. The lower of the reference input and soft-start ramps controls the
error amplifier, allowing the output voltage to rise in a smooth monotonic fashion.
The soft-start period of the TPS23758 is adjustable with a capacitor between SST and RTN. During soft-start,
CSST (图 8-1) is being charged from less than 0.2 V to 2.45 V by a ~4-µA current source. The actual control
range of the closed loop soft-start capacitor voltage is between 0.25 V and 2 V nominally. Therefore, the soft-
start capacitor value must be based on this control range and the required soft-start period (tSS) according to:
ISSC × tSS
CSS
=
(2 V F 0.25 V)
(5)
7.3.6 Internal Switching FET - DRAIN, RSNS, SRF and SRR
The DRAIN and RSNS provide connection to the drain and source of the integrated switching power FET. RSNS
pin is a high current pin and it must have a short connection to the current sense resistor which other end is
directly tied to a plane referenced to the GND pin. Current sensing is done with CS pin, which should be
connected directly to the high side of the current sense resistor.
The internal FET gate driver is powered from VB voltage rail and the return path is through the GND pin. SRF
and SRR pins provide slew rate control of the switching FET. The gate sourcing current is drawn through the
SRF pin which is tied to VB pin through a resistor (0-100 Ω). The gate sinking current circulates through the
SRR pin which is externally tied to the GND pin either via a low-value resistor (0-15 Ω) or a direct connection.
7.3.7 VPD Supply Voltage
VPD pin connects to the positive side of the input supply. It provides operating power to the PD controller and
allows monitoring of the input line voltage. If VVPD falls below its UVLO threshold and goes back above it, or if a
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thermal shutdown resumes while VVPD is already above its UVLO threshold, the TPS23758 returns to inrush
limiting.
7.3.8 VDD Supply Voltage
VDD connects to the source of DC-DC converter startup current. It is connected to VPD for most applications. It
may also be isolated by a diode from VPD to support some PoE priority operation.
7.3.9 GND
GND is the power ground used by the flyback power FET gate driver and CP pin. Connect to the RTN plane. VB
bypassing capacitor should be directly connected to the GND pin.
7.3.10 VSS
VSS is the PoE input-power return side. It is the reference for the PoE interface circuits, and has a current-
limited hotswap switch that connects it to RTN. VSS is clamped to a diode drop above RTN by the hotswap
switch. The exposed thermal PAD must be connected to this pin to ensure proper operation.
7.3.11 Exposed Thermal PAD
The exposed thermal PAD is internally connected to VSS pin. It should be tied to a large VSS copper area on the
PCB to provide a low resistance thermal path to the circuit board. TI recommends maintaining a clearance of
0.025” between VSS and high-voltage signals such as VPD and VDD.
7.4 Device Functional Modes
7.4.1 PoE Overview
The following text is intended as an aid in understanding the operation of the TPS23758, but it is not a substitute
for the actual IEEE 802.3at standard. The IEEE 802.3at standard is an update to IEEE 802.3-2008 clause 33
(PoE), adding high-power options and enhanced classification.
Generally speaking, a device compliant to IEEE 802.3-2008 is referred to as a Type 1 device, and devices with
high power or enhanced classification is referred to as Type 2 devices. The TPS23758 is intended to power Type
1 devices (up to 13 W), and is fully compliant to IEEE 802.3at for hardware classes 0 - 3. Standards change and
must always be referenced when making design decisions.
The IEEE 802.3at standard defines a method of safely powering a PD (powered device) over a cable, and then
removing power if a PD is disconnected. The process proceeds through an idle state and three operational
states of detection, classification, and operation. The PSE leaves the cable unpowered (idle state) while it
periodically looks to see if something has been plugged in; this is referred to as detection. The low power levels
used during detection are unlikely to damage devices not designed for PoE. If a valid PD signature is present,
the PSE may inquire how much power the PD requires; this is referred to as (hardware) classification. Only Type
2 PSEs are required to do hardware classification. The PD may return the default 13-W current-encoded class,
or one of four other choices. The PSE may then power the PD if it has adequate capacity. Once started, the PD
must present the maintain power signature (MPS) to assure the PSE that it is still present. The PSE monitors its
output for a valid MPS, and turns the port off if it loses the MPS. Loss of the MPS returns the PSE to the idle
state. 图 7-4 shows the operational states as a function of PD input voltage.
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Shut-
down
Classify
Normal Operation
Detect
0
2.7
10.1 14.5
20.5
30
PI Voltage (V)
36
57
42
图 7-4. Operational States
The PD input is typically an RJ-45 eight-lead connector which is referred to as the power interface (PI). PD input
requirements differ from PSE output requirements to account for voltage drops in the cable and operating
margin. The IEEE 802.3at standard uses a cable resistance of 20 Ω for Type 1 devices to derive the voltage
limits at the PD based on the PSE output voltage requirements. Although the standard specifies an output power
of 15.4 W at the PSE, only 13 W is available at the PI due to the worst-case power loss in the cable. The PSE
can apply voltage either between the RX and TX pairs (pins 1–2 and 3–6 for 10baseT or 100baseT), or
between the two spare pairs (4–5 and 7–8). Power application to the same pin combinations in 1000baseT
systems is recognized in IEEE 802.3at. 1000baseT systems can handle data on all pairs, eliminating the spare
pair terminology. The PSE may only apply voltage to one set of pairs at a time. The PD uses input diode bridges
to accept power from any of the possible PSE configurations. The voltage drops associated with the input
bridges create a difference between the standard limits at the PI and the TPS23758 specifications.
The PSE is permitted to disconnect a PD if it draws more than its maximum class power over a one second
interval. A Type 1 PSE compliant to IEEE 802.3at is required to limit current to between 400 mA and 450 mA
during powered operation, and it must disconnect the PD if it draws this current for more than 75 ms. Class 0
and 3 PDs may draw up to 400-mA peak currents for up to 50 ms. The PSE may set lower output current limits
based on the declared power requirements of the PD.
7.4.2 Threshold Voltages
The TPS23758 has a number of internal comparators with hysteresis for stable switching between the various
states as shown in 图 7-4. 图 7-5 relates the parameters in Electrical Characteristics: DC-DC Controller Section
and Electrical Characteristics: PoE and Control to the PoE states. The mode labeled idle between classification
and operation implies that the DEN, CLS, and RTN pins are all high impedance.
PD Powered
Idle
Classification
VVPD-VVSS
Detection
VCU_HYS
VCU_OFF
VCL_HYS
VCL_ON
VUVLO_H
1.4 V
VUVLO_R
Note: Variable names refer to Electrical Characteristic
Table parameters
图 7-5. Threshold Voltages
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7.4.3 PoE Start-Up Sequence
The waveforms of 图 7-6 demonstrate detection, classification, and start-up from a Type 1 PSE. The key
waveforms shown are VVPD-VSS, VRTN-VSS, and IPI. IEEE 802.3at requires a minimum of two detection levels;
however, four levels are shown in this example. Four levels guard against misdetection of a device when
plugged in during the detection sequence.
图 7-6. PoE Start-Up Sequence
7.4.4 Detection
The TPS23758 is in detection mode whenever VVPD-V SS is below the lower classification threshold. When the
input voltage rises above VCL_ON, the DEN pin goes to an open-drain condition to conserve power. While in
detection, RTN is high impedance, almost all the internal circuits are disabled, and the DEN pin is pulled to VSS
.
An RDEN of 24.9 kΩ (1%), presents the correct signature. It may be a small, low-power resistor because it only
sees a stress of about 5 mW. A valid PD detection signature is an incremental resistance between 23.75 kΩ and
26.25 kΩ at the PI.
The detection resistance seen by the PSE at the PI is the result of the input bridge resistance in series with the
parallel combination of RDEN and the TPS23758 bias loading. The incremental resistance of the input diode
bridge may be hundreds of ohms at the very low currents drawn when 2.7 V is applied to the PI. The input bridge
resistance is partially cancelled by the effective resistance of the TPS23758 during detection.
7.4.5 Hardware Classification
Hardware classification allows a PSE to determine the power requirements of a PD before starting, and helps
with power management once power is applied. The maximum power entries in 表 7-1 determine the class the
PD must advertise. A Type 1 PD may not advertise Class 4. The PSE may disconnect a PD if it draws more than
its stated Class power. The standard permits the PD to draw limited current peaks; however, the average power
requirement always applies.
Voltage from 14.5 V to 20.5 V is applied to the PD for up to 75 ms during hardware classification. A fixed output
voltage is sourced by the CLS pin, causing a fixed current to be drawn from VPD through RCLS. The total current
drawn from the PSE during classification is the sum of bias and RCLS currents. PD current is measured and
decoded by the PSE to determine which of the five available classes is advertised (see Table 7-1). The
TPS23758 disables classification above VCU_OFF to avoid excessive power dissipation. CLS voltage is turned off
during PD thermal limit or when APD or DEN are active . The CLS output is inherently current-limited, but should
not be shorted to VSS for long periods of time.
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7.4.6 Maintain Power Signature (MPS)
The MPS is an electrical signature presented by the PD to assure the PSE that it is still present after operating
voltage is applied. A valid MPS consists of a minimum DC current of 10 mA (at a duty cycle of at least 75 ms on
every 225 ms) and an AC impedance lower than 26.25 kΩ in parallel with 0.05 μF. The AC impedance is usually
accomplished by the minimum CBULK requirement of 5 μF. When APD or DEN is used to force the hotswap
switch off, the DC MPS is not met. A PSE that monitors the DC MPS will remove power from the PD when this
occurs. A PSE that monitors only the AC MPS may remove power from the PD.
7.4.7 Start-Up and Converter Operation
The internal PoE undervoltage lockout (UVLO) circuit holds the hotswap switch off before the PSE provides full
voltage to the PD. This prevents the converter circuits from loading the PoE input during detection and
classification. The converter circuits discharges CDD, CCC, and CVB while the PD is unpowered. Thus VVDD-RTN
will be a small voltage until just after full voltage is applied to the PD, as seen in 图 7-6.
The PSE drives the PD input voltage to the operating range once it has decided to power up the PD. When VPD
rises above the UVLO turnon threshold (VUVLO-R, approximately 35.5 V) with RTN high, the TPS23758 enables
the hotswap MOSFET with an approximately 140-mA (inrush) current limit. See the waveforms of 图 7-7 for an
example. Converter switching is disabled while CDD charges and VRTN falls from VVDD to nearly VVSS; however,
the converter start-up circuit is allowed to charge CCC. Once the inrush current falls about 10% below the inrush
current limit, the PD control switches to the operational level (approximately 450 mA) and converter switching is
permitted.
Converter switching is allowed if the PD is not in inrush current limit and the VCC under-voltage lockout (VCUVR
)
circuit permits it. Continuing the start-up sequence shown in Figurer 7-7, VVCC rises as the start-up current
source charges CCC and the converter switching is inhibited by the status of the VCC UVLO. The VB regulator
powers the internal converter circuits as VVCC rises.
Once VVCC goes above its UVLO (nominally 8.25 V), the soft-start (SST) capacitor is first discharged with
controlled current (ISSD) below nominally 0.2 V (VSFST) if the discharge was not already completed, then it is
gradually recharged until it reaches ~0.25 V (VSSOFS) at which point the converter switching is enabled following
the closed loop controlled soft-start sequence. Note that the startup current source capability is such that it can
fully maintain VVCC during the converter soft-start without requiring any significant CCC capacitance, in 48 V input
applications. At the end of the soft-start period, more specifically when SST voltage has exceeded ~2 V
(VSTUOF), the startup current source is turned off. VVCC falls as it powers the internal circuits including the
switching MOSFET gate. If the converter control-bias output rises to support VVCC before it falls to VCUVF
(nominally 6.1 V), a successful start-up occurs. Figure 7-7 shows a small droop in VVCC while the output voltage
rises smoothly and a successful start-up occurs.
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50V/div
VVDD-RTN
Converter
starts
PI powered
Inrush
100mA/div
IPI
VVCC-RTN
Startup turn off
5V/div
5V/div
VOUT
OUTPUT VOLTAGE
VSST
SOFT START
1V/div
Time: 10ms/div
图 7-7. Power Up and Start
The converter shuts off when VVCC falls below its lower UVLO. This can happen when power is removed from
the PD, or during a fault on a converter output rail. When one output is shorted, all the output voltages fall
including the one that powers VCC. The control circuit discharges VCC until it hits the lower UVLO and turns off.
A restart initiates if the converter turns off and there is sufficient VDD voltage. This type of operation is
sometimes referred to as hiccup mode, which when combined with the soft-start provides robust output short
protection by providing time-average heating reduction of the output rectifier.
图 7-8 illustrates the situation when there is severe overload at the main output which causes VCC hiccup. After
VCC went below its UVLO due to the overload, the startup source is turned back on. Then, a new soft-start cycle
is reinitiated, the soft-start capacitor being first discharged with controlled current, introducing a short pause
before the output voltage is ramped up.
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VOUT overload
Converter
Turn off then restart
IPI
100mA/div
Startup turn off
VVCC-RTN
VCC
UVLO
5V/div
VOUT
5V/div
OUTPUT VOLTAGE
VSST
SOFT START
1V/div
Time: 10ms/div
图 7-8. Restart Following Severe Overload at Main Output of Flyback DC-DC Converter
If VVPD-VSS drops below the lower PoE UVLO (UVLO_R – UVLO_H, approximately 31 V), the hotswap
MOSFET is turned off, but the converter still runs. The converter stops if VVCC falls below the VCUVF (nominally
6.1 V), the hotswap is in inrush current limit, the SST pin is pulled to ground, VVDD-RTN falls below typically 7.7 V
(approximately 0.75 V hysteresis) or the converter is in thermal shutdown.
7.4.8 PD Self-Protection
The PD section has the following self-protection functions.
• Hotswap switch current limit
• Hotswap switch foldback
• Hotswap thermal protection
The internal hotswap MOSFET is protected against output faults with a current limit and deglitched foldback. The
PSE output cannot be relied on to protect the PD MOSFET against transient conditions, requiring the PD to
provide fault protection. High stress conditions include converter output shorts, shorts from VDD to RTN, or
transients on the input line. An overload on the pass MOSFET engages the current limit, with VRTN-VSS rising as
a result. If VRTN rises above approximately 12.3 V for longer than approximately 400 μs, the current limit reverts
to the inrush limit, and turns the converter off. The 400-μs deglitch feature prevents momentary transients from
causing a PD reset, provided that recovery lies within the bounds of the hotswap and PSE protection. 图 7-9
shows an example of recovery from a 15-V PSE rising voltage step. The hotswap MOSFET goes into current
limit, overshooting to a relatively low current, recovers to 420 mA, full-current limit, and charges the input
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capacitor while the converter continues to run. The MOSFET did not go into foldback because VRTN-VSS was
below 12 V after the 400-μs deglitch.
IPI
200mA/div
CBULK completes
charge while converter
operates
VVSS-RTN ≈ -15V
10V/div
VVPD-VSS
20V/div
Time: 200us/div
图 7-9. Response to PSE Step Voltage
The PD control has a thermal sensor that protects the internal hotswap MOSFET. Conditions like start-up or
operation into a VPD to RTN short cause high power dissipation in the MOSFET. An overtemperature shutdown
(OTSD) turns off the hotswap MOSFET and class regulator, which are restarted after the device cools. The PD
restarts in inrush current limit when exiting from a PD overtemperature event.
Pulling DEN to VSS during powered operation causes the internal hotswap MOSFET to turn off. This feature
allows a PD with secondary-side adapter ORing to achieve adapter priority. Take care with synchronous
converter topologies that can deliver power in both directions.
The hotswap switch is forced off under the following conditions:
• VAPD above VAPDEN (approximately 1.5 V)
• VDE N ≤ VPD_DIS when VVPD-VSS is in the operational range
• PD over temperature
• VVPD-VSS < PoE UVLO (approximately 31 V)
7.4.9 Adapter ORing
Many PoE-capable devices are designed to operate from either a wall adapter or PoE power. A local power
solution adds cost and complexity, but allows a product to be used if PoE is not available in a particular
installation. While most applications only require that the PD operate when both sources are present, the
TPS23758 device supports forced operation from either of the power sources. 图 7-10 illustrates three options
for diode ORing external power into a PD. Only one option would be used in any particular design. Option 1
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applies power to the device input, option 2 applies power between the device PoE section and the power circuit,
and option 3 applies power to the output side of the converter. Each of these options has advantages and
disadvantages. Many of the basic ORing configurations and much of the discussion contained in the application
note Advanced Adapter ORing Solutions using the TPS23753, (SLVA306), apply to the TPS23758.
Low Voltage
Output
DEN
CLS
Power
Circuit
VSS
RTN
Adapter
Option 2
Adapter
Option 3
Adapter
Option 1
图 7-10. ORing Configurations
Preference of one power source presents a number of challenges. Combinations of adapter output voltage
(nominal and tolerance), power insertion point, and which source is preferred determine solution complexity.
Several factors contributing to the complexity are the natural high-voltage selection of diode ORing (the simplest
method of combining sources), the current limit implicit in the PSE, PD inrush, and protection circuits (necessary
for operation and reliability). Creating simple and seamless solutions is difficult if not impossible for many of the
combinations. However, the TPS23758 device offers several built-in features that simplify some combinations.
Several examples demonstrate the limitations inherent in ORing solutions. Diode ORing a 48-V adapter with PoE
(option 1) presents the problem that either source might be higher. A blocking switch would be required to assure
which source was active. A second example is combining a 12-V adapter with PoE using option 2. The converter
draws approximately four times the current at 12 V from the adapter than it does from PoE at 48 V. Transition
from adapter power to PoE may demand more current than can be supplied by the PSE. The converter must be
turned off while CBULK capacitance charges, with a subsequent converter restart at the higher voltage and lower
input current. A third example is use of a 12-V adapter with ORing option 1. The PD hotswap would have to
handle four times the current, and have 1/16 the resistance (be 16 times larger) to dissipate equal power. A
fourth example is that MPS is lost when running from the adapter, causing the PSE to remove power from the
PD. If adapter power is then lost, the PD stops operating until the PSE detects and powers the PD.
The most popular preferential ORing scheme is option 2 with adapter priority. The hotswap MOSFET is disabled
when the adapter is used to pull APD high, blocking the PoE source from powering the output. This solution
works well with a wide range of adapter voltages, is simple, and requires few external parts. When the AC power
fails, or the adapter is removed, the hotswap switch is enabled. In the simplest implementation, the PD
momentarily loses power until the PSE completes its start-up cycle.
The DEN pin can be used to disable the PoE input when ORing with option 3. This is an adapter priority
implementation. Pulling DEN low, while creating an invalid detection signature, disables the hotswap MOSFET,
and prevents the PD from redetecting. This would typically be accomplished with an optocoupler that is driven
from the secondary side of the converter.
The IEEE standards require that the PI conductors be electrically isolated from ground and all other system
potentials not part of the PI interface. The adapter must meet a minimum 1500-Vac dielectric withstand test
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between the output and all other connections for options 1 and 2. The adapter only needs this isolation for option
3 if it is not provided by the converter.
Adapter ORing diodes are shown for all the options to protect against a reverse-voltage adapter, a short on the
adapter input pins, and damage to a low-voltage adapter. ORing is sometimes accomplished with a MOSFET in
option 3.
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8 Application and Implementation
Note
以下应用部分的信息不属于 TI 组件规范,TI 不担保其准确性和完整性。客户应负责确定 TI 组件是否适
用于其应用。客户应验证并测试其设计,以确保系统功能。
8.1 Application Information
The TPS23758 supports power supply topologies that require a single PWM gate drive with current-mode
control. 图 8-1 provides an example of a synchronous FET rectified primary-side-regulated flyback converter.
8.2 Typical Application
图 8-1. Basic TPS23758 Implementation
8.2.1 Design Requirements
Selecting a converter topology along with a design procedure is beyond the scope of this applications section.
The TPS23758 is optimized for primary-side-regulated synchronous FET rectified flyback topologies of 5 V or
lower due to its good balance of high efficiency and output regulation. Typical applications use post regulation to
power the system load's lower voltage rails whereas the TPS23758 allows the elimination of a post regulated
converter like shown in 图 8-1. The TPS23758 can also be used in non-isolated buck topology application like
shown in Figure 8-1.
Examples to help in programming the TPS23758 in a primary-side regulated flyback are shown below. For more
specific converter design examples refer to the TPS23758EVM-080EVM: Evaluation Module for TPS23758.
表 8-1. Design Parameters
PARAMETER
TEST CONDITIONS
MIN
37
TYP
MAX UNIT
POWER INTERFACE
Input voltage
Applied to the PoE Input
Applied to Primary Adapter Input
At device terminals
57
V
V
V
48
Detection voltage
2.7
10.1
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表 8-1. Design Parameters (continued)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
Classification voltage
Classification
At device terminals
14.5
20.5
V
3
140
550
Inrush current-limit
Operating current-limit
DC-TO-DC CONVERTER
Output voltage
mA
mA
5
2.3
34
V
A
VIN = 48 V, ILOAD ≤ ILOAD (max)
37 V ≤ VIN ≤ 57 V
Output current
Output ripple voltage peak-to-peak
VIN = 48 V, ILOAD = 1 A
mV
VIN = 48 V, ILOAD= 230 mA
VIN = 48 V, ILOAD = 1.15 A
VIN = 48 V, ILOAD = 2.3 A
61
Efficiency, end-to-end
85
%
88
Switching frequency
250
kHz
8.2.2 Detailed Design Procedure
8.2.2.1 Input Bridges and Schottky Diodes
Using Schottky diodes instead of PN junction diodes for the PoE input bridges reduces the power dissipation in
these devices by about 30%. There are, however, some things to consider when using them. The IEEE standard
specifies a maximum backfeed voltage of 2.8 V. A 100-kΩ resistor is placed between the unpowered pairs and
the voltage is measured across the resistor. Schottky diodes often have a higher reverse leakage current than
PN diodes, making this a harder requirement to meet. To compensate, use conservative design for diode
operating temperature, select lower-leakage devices where possible, and match leakage and temperatures by
using packaged bridges.
Schottky diode leakage currents and lower dynamic resistances can impact the detection signature. Setting
reasonable expectations for the temperature range over which the detection signature is accurate is the simplest
solution. Increasing RDEN slightly may also help meet the requirement.
Schottky diodes have proven less robust to the stresses of ESD transients than PN junction diodes. After
exposure to ESD, Schottky diodes may become shorted or leak. Care must be taken to provide adequate
protection in line with the exposure levels. This protection may be as simple as ferrite beads and capacitors.
As a general recommendation, use 0.8 A-1 A, 100-V rated discrete or bridge diodes for the input rectifiers.
8.2.2.2 Softstart Capacitor, Css
An approximately 10-ms softstart period is recommended, so using 方程式 5, a 22-nF softstart capacitor (Css) is
used
8.2.2.3 Protection, D1
A TVS, D1, across the rectified PoE voltage per 图 8-1 must be used. A SMAJ58A, or equivalent, is
recommended for general indoor applications. Adequate capacitive filtering or a TVS must limit input transient
voltage to within the absolute maximum ratings. Outdoor transient levels or special applications require
additional protection.
8.2.2.4 Capacitor, C1
The IEEE 802.3at standard specifies an input bypass capacitor (from VDD to VSS) of 0.05 μF to 0.12 μF.
Typically a 0.1-μF, 100-V, 10% ceramic capacitor is used.
8.2.2.5 Detection Resistor, RDEN
The IEEE 802.3at standard specifies a detection signature resistance, RDEN between 23.7 kΩ and 26.3 kΩ, or
25 kΩ ± 5%. Typically a 24.9 kΩ ± 1% is used.
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8.2.2.6 Classification Resistor
Connect a resistor from CLS to VSS to program the classification current according to the IEEE 802.3at
standard. The class power assigned should correspond to the maximum average power drawn by the PD during
operation. Select RCLS according to 表 7-1.
8.2.2.7 Bulk Capacitance, CBULK
The bulk capacitance, CBULK must furnish input transients during heavy loads and long cable length conditions. It
also helps with stability on the DC/DC converter. It is recommended to use a minimum 10-uF, electrolytic
capacitor.
8.2.2.8 Output Voltage Feedback Divider, RAUX, R1,R2
R1, R2 and set the output voltage of the bias winding of the converter.
VREFC R + R
(
)
1
2
VVCC
=
R 2
(6)
when Aux_D is LOW.
when Aux_D is HIGH.
8.2.2.9 Setting Frequency, RFRS
The converter switching frequency in PWM mode is set by connecting resistor, RFRS from the FRS pin to RTN.
For a converter that requires a 250-kHz switching frequency and using 方程式 7
15000
15000
250 kHz
RFRS kW =
=
= 60 kW
(
)
fSW kHz
(7)
A standard 60.4-kΩ resistor should be used.
8.2.2.10 Frequency Dithering, RDTR and CDTR
For optimum EMI performance, CDTR and RDTR should be selected as described in Frequency Dithering for
Spread Spectrum Applications in 方程式 8 and 方程式 9.
3
3
RFRS
W
( )
60.4 kW
CDTR nF =
=
= 2.2 nF
(
)
2.052 ì 11000 Hz
2.052 ì fm Hz
(8)
(9)
0.513 ì RFRS
W
( )
0.513 ì60.4kW
RDTR W =
( )
=
= 235 kW
A standard 237-kΩ resistor should be used.
8.2.2.11 Bias Voltage, CVB and DVB
VB requires a 0.1 μF capacitor, CVB, to RTN. DVB , a 6.2V Zener diode to RTN, is also required.
Note: DVB on VB is optional in 13W applications when no class resistor is used.
8.2.2.12 Transformer design, T1
The turns ratio and primary inductance are important parameters to consider in a flyback transformer. The turns
ratio act to limit the max duty cycle and reduce stress on the secondary components while the primary
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inductance sets the current ripple. In CCM operation, the higher inductance allows for a reduced current ripple
which can help with EMI performance and noise.
For primary-side regulated flyback converters, the transformer construction is important to maintain good
regulation on the secondary output. It is recommended to use LDT1018 for 5-V applications.
8.2.2.13 Current Sense Resistor, RCS
RCS should be chosen based on the peak primary current at the desired output current limit.
VCSMAX
R CS
=
IPk-Pr imary
(10)
8.2.2.14 Current Slope Compensation, RS
RS may be used if the internally provided slope compensation is not enough. The down slope of the reflected
secondary current through the current sense resistor at each switching period is determined and a percentage
(typically 50%-75%) of it will define Vslope. If necessary, using LDT1018, it is recommended to start with 251 mV
and use 方程式 11.
»
…
…
ÿ
Ÿ
≈
’
VSLOPE mV
(
)
»
…
ÿ
Ÿ
⁄
≈
’
155 mV
78.5%
VSLOPE mV - ∆
÷
÷
◊
(
)
251mV -
D
∆
÷
◊
∆
DMAX
Ÿ
⁄
«
«
R S W =
( )
ì 1000 =
ì 1000 = 1kW
42 mA
78.5%
ISL mA
(
)
EX
DMAX
(11)
8.2.2.15 Bias Supply Requirements, CCC, DCC
Advanced startup in the TPS23758 allows for relatively low capacitance on the bias circuit. It is recommended to
use a 1-uF, 10%, 25-V ceramic capacitors on CCC. DCC can be a low cost, general-purpose diode. It is
recommended to use MMSD4148 diode (100 V, 200 mA).
8.2.2.16 Switching Transformer Considerations, RVCC and CCC2
RVCC helps to reduce peak charging from the bias winding. Reduced peak charging becomes especially
important when tuning hiccup mode operation during output overload. A typical value for RVCC in Type 1 PoE PD
applications while maintaining a suitable load regulation is 10 ohms.
8.2.2.17 Primary FET Clamping, RCL, CCL, and DCL
The stored energy in the leakage inductance of the power transformer can cause ringing during the primary FET
turnoff. The snubber must be chosen to mitigate primary FET overshoot and oscillation while maintaining high
overall efficiency.
It is recommended to use 39 kΩ (125 mW) for RCL and 0.1 uF (100 V) for CCL.
DCL should be an ultra-fast diode with a short forward recovery time allowing the snubber to turn on quickly. The
200-V / 1-A rated diode with a recovery time approximately 25 ns or better is recommended.
8.2.2.18 Converter Output Capacitance, COUT
The output capacitor is considered as part of the overall stability of the converter, the output voltage ripple, and
the load transient response. The output capacitor needs to be selected based on the most stringent of these
criteria. The minimum capacitance is typically determined by the output voltage ripple shown in 方程式 12.
IOUT A ì D
( )
max
COUT
>
VRipple V ì f
Hz
SW
(12)
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where Dmax is the calculated operating max duty cycle shown in 方程式 13.
VOUT ì NPS
D max
=
VIN min + V
ì NPS
(
)
OUT
(13)
For strict load transient requirements, the COUT cap may need to be increased. The TPS23758EVM-080 uses
three 100 uF ceramic capacitors for an optimized load transient response.
8.2.2.19 Synchronous Rectifier, QR
The output synchronous FET rectifier must have a small Rds(on) and total gate charge (Qc). Consideration must
be given to a safe operating area during output overload conditions.
For a 5-V output, CSD17579Q3A in a high thermal performance package (30-V reverse voltage, 11-A continuous
drain current max, 11.5-nC total gate charge @ 10 Vgs) is used in the TPS23758EVM-080
Some synchronous flyback topologies in certain operating conditions can benefit from added protection across
the synchronous FET. It is recommended to add a zener DR across the synch FET that can be populated when
needed.
8.2.2.20 Synchronous Rectifier Clamp, DZ
DZ clamps the gate voltage of the synchronous rectifier. It is recommended to use two MMSZ5242B-7-F zener
diodes (12 V, 500 mW) for DZ.
8.2.2.21 Synchronous Rectifier Gate Diode, DG
DG is used for fast turn off of the synchronous rectifier. It is recommended to use MMSD4148T1G (100 V, 200
mA, SOD-123) for DG.
8.2.2.22 Sync Rectifier Slew Rate Control, RG
RG is used to adjust the turn on slew rate of the synchronous rectifier. It is recommended to use a 10 Ω resistor
in an 0402 package with a 63-mW power rating
8.2.2.23 Slew rate control, RSRF and RSRR
RSRF and RSRR minimize primary drain-source oscillations and help optimize EMI performance at high
frequencies, the value chosen should be within the recommend operating conditions table in Recommended
Operating Conditions. It is recommended to start with 10 ohms for RSRF and 10 ohms for RSRR then adjust
accordingly during bench and EMI testing.
8.2.2.24 Shutdown at Low Temperatures, DVDD and CVDD
For applications operating near –10°C or less, there may be some extra switching cycles during removal of the
PoE input or during shutdown. It is acceptable for most applications; however, for a more monotonic shutdown of
the output voltage during power removal, it is recommended to use DVDD and CVDD as shown in 图 8-2. DVDD
can be MMSD4148 and CVDD can be 0.22-uF, 100-V capacitor.
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DVDD
CVDD
+
CBULK
VDD
VPD
C1
D1
TPS23755
VSS
图 8-2. DVDD and CVDD Configuration for Low Temperature Conditions
8.2.3 Application Curves
图 8-3. TPS23758 Startup to TPS23880 PSE
图 8-4. TPS23758 PSR Flyback Startup to Full Load
图 8-6. Slew Rate Adjust SRR = 10 Ω
图 8-5. TPS23758 Output Short and Recovery
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图 8-7. Slew Rate Adjust SRR = 0 Ω
图 8-8. Slew Rate Adjust SRF = 0 Ω
5
4.95
4.9
4.85
0.23 A
2.3 A
图 8-10. Slew Rate Adjust SRF = 100 Ω
4.8
-40
-20
0
20
40
60
80
100
Temp (A)
d001
图 8-9. Output Regulation vs. Ambient Temperature
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9 Power Supply Recommendations
The TPS23758 converter should be designed such that the input voltage of the converter is capable of operating
within the IEEE802.3at recommended input voltage as shown in 图 7-4 and the minimum operating voltage of
the adapter if applicable.
10 Layout
10.1 Layout Guidelines
The TPS23758 IC’s layout footprint shown in the Example Board Layout should be strictly followed. The below
list are key highlights for layout consideration around the TPS23758.
• Pin 22 of the TPS23758 is omitted from the IC to ensure high voltage clearance from Pin 24 (DRAIN).
Therefore, the Pin 22 footprint should be removed when laying out the TPS23758.
• It is recommended having at least 8 vias (VSS) connecting the exposed thermal pad through a top layer
plane (2 oz copper recommended) to a bottom VSS plane (2 oz. copper recommended) to help with thermal
dissipation.
• The Pin24 of the TPS23758 should be near the power transformer and the current sense resistor should be
close to Pin 1 of the TPS23758 to minimize the primary loop.
The layout of the PoE front end should follow power and EMI or ESD best-practice guidelines. A basic set of
recommendations includes:
• Parts placement must be driven by power flow in a point-to-point manner; RJ-45, Ethernet transformer, diode
bridges, TVS and 0.1-μF capacitor, and TPS23758 converter input bulk capacitor.
• Make all leads as short as possible with wide power traces and paired signal and return.
• No crossovers of signals from one part of the flow to another are allowed.
• Spacing consistent with safety standards like IEC60950 must be observed between the 48-V input voltage
rails and between the input and an isolated converter output.
• Use large copper fills and traces on SMT power-dissipating devices, and use wide traces or overlay copper
fills in the power path.
The DC-to-DC converter layout benefits from basic rules such as:
• Having at least 4 vias (VDD) near the power transformer pin connected to VDD through multiple layer planes
to help with thermal dissipation of the power transformer.
• Having at least 6 vias (secondary ground) near the power transformer pin connected to secondary ground
through multiple layer planes to help with thermal dissipation of the power transformer.
• Pair signals to reduce emissions and noise, especially the paths that carry high-current pulses, which include
the power semiconductors and magnetics.
• Minimize the trace length of high current power semiconductors and magnetic components.
• Where possible, use vertical pairing.
• Use the ground plane for the switching currents carefully.
• Keep the high-current and high-voltage switching away from low-level sensing circuits including those outside
the power supply.
• Maintain proper spacing around the high-voltage sections of the converter.
10.2 Layout Example
图 10-1 and 图 10-2 show the top and bottom layer and assemblies of the TPS23758EVM-080 as a reference for
optimum parts placement.
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图 10-1. Top Side and Routing
图 10-2. Bottom Side Placement and Routing
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11 Device and Documentation Support
11.1 Related documentation
For related documentation, see the following:
• Texas Instruments, Practical Guidelines to Designing an EMI-Compliant PoE Powered Device With Isolated
Flyback, application report
• Texas Instruments, TPS23758EVM-080: Evaluation Module, user's guide
11.2 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料,可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范,并且不一定反映 TI 的观点;请参阅
TI 的《使用条款》。
11.3 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
11.4 静电放电警告
静电放电 (ESD) 会损坏这个集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理
和安装程序,可能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级,大至整个器件故障。精密的集成电路可能更容易受到损坏,这是因为非常细微的参
数更改都可能会导致器件与其发布的规格不相符。
11.5 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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12.1 Package Option Addendum
Packaging Information
Package
Type
Package
Drawing
Package
Qty
Lead/Ball
Finish(4)
Orderable Device
PTPS23758RJJR
TPS23758RJJR
Status (1)
ACTIVE
ACTIVE
Pins
23
Eco Plan (2)
MSL Peak Temp (3)
Call TI
Op Temp (°C)
–40 to 125
–40 to 125
Device Marking(5) (6)
VSON
RJJ
RJJ
3000
3000
TBD
Call TI
PPS23758
TPS23758
Green (RoHS
& no Sb/Br)
VSON
VSON
23
CU NIPDAU
Level-2-260C-1 YEAR
Green (RoHS
& no Sb/Br)
TPS23758RJJR
ACTIVE
RJJ
23
250
CU NIPDAU
Level-2-260C-1 YEAR
TPS23758
–40 to 125
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PRE_PROD Unannounced device, not in production, not available for mass market, nor on the web, samples not available.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
space
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest
availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the
requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified
lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used
between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1%
by weight in homogeneous material)
space
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
space
(4) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the
finish value exceeds the maximum column width.
space
(5) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device
space
(6) Multiple Device markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Device Marking for that device.
Important Information and Disclaimer: The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by
third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable
steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain
information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
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PACKAGE OUTLINE
RJJ0023B
VSON - 1 mm max height
S
C
A
L
E
2
.
5
0
0
PLASTIC QUAD FLATPACK - NO LEAD
4.1
3.9
A
B
PIN 1 INDEX AREA
6.1
5.9
C
1 MAX
SEATING PLANE
0.08 C
0.05
0.00
4X (0.4)
4X ( 0.25)
1.9 0.1
(0.2) TYP
20X 0.4
A3
13
A2
12
4X (0.45)
EXPOSED
THERMAL PAD
5.5 0.1
2X
SYMM
25
4.4
0.25
0.15
23X
0.1
C B A
24
A4
1
0.05
A1
PIN 1 ID
SYMM
0.5
0.3
23X
10X (0.2)
8X (0.4)
2X (1.6)
4223621/B 06/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
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EXAMPLE BOARD LAYOUT
RJJ0023B
VSON - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(2)
(1.9)
10X (0.2)
A4
SYMM
4X ( 0.25)
23X (0.6)
A1
23X (0.2)
1
24
4X (2.675)
(
0.2) TYP
VIA
20X (0.4)
25
SYMM
(5.5)
(1.32)
TYP
SOLDER MASK
OPENING
(R0.05) TYP
ALL PAD CORNERS
13
12
METAL UNDER
SOLDER MASK
A2
A3
(0.45) TYP
8X
(0.4)
4X (1.725)
(0.6)
TYP
(3.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 15X
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
SOLDER MASK
OPENING
METAL
EXPOSED
METAL
EXPOSED
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4223621/B 06/2017
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
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EXAMPLE STENCIL DESIGN
RJJ0023B
VSON - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
8X (0.85)
4X ( 0.25)
23X (0.6)
A1
A4
1
24
23X (0.2)
8X (1.12)
4X (2.675)
20X (0.4)
SOLDER MASK
OPENING
25
SYMM
(5.94)
(0.66) TYP
(R0.05) TYP
(1.32) TYP
METAL UNDER
SOLDER MASK
12
13
A3
A2
10X (0.46)
(0.525) TYP
4X (1.725)
SYMM
(3.8)
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
THERMAL PAD 25: 73%
SCALE:20X
4223621B 06/2017
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS23758RJJR
TPS23758RJJT
ACTIVE
ACTIVE
VSON
VSON
RJJ
RJJ
23
23
3000 RoHS & Green
250 RoHS & Green
NIPDAUAG
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 125
-40 to 125
TPS23758
TPS23758
NIPDAUAG
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
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10-Mar-2021
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS23758RJJT
VSON
RJJ
23
250
180.0
12.4
4.25
6.25
1.15
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
10-Mar-2021
*All dimensions are nominal
Device
Package Type Package Drawing Pins
VSON RJJ 23
SPQ
Length (mm) Width (mm) Height (mm)
213.0 191.0 35.0
TPS23758RJJT
250
Pack Materials-Page 2
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