TPS2388 [TI]

2 线对、2 类、8 通道 PoE PSE;


型号：	TPS2388
厂家：	TEXAS INSTRUMENTS
描述：	2 线对、2 类、8 通道 PoE PSE
文件：	总87页 (文件大小：2555K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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TPS2388

ZHCSGR0A –FEBRUARY 2015–REVISED AUGUST 2017

TPS2388 IEEE 802.3at 8 通道以太网供电 PSE 控制器

1 特性

3 说明

•

完全符合 IEEE 802.3at 标准

TPS2388 是一款 8 通道电源设备 (PSE) 控制器，旨在

根据 IEEE 802.3at-2012 标准（或 802.3at）向以太网

电缆提供电力。PSE 控制器可以检测具有有效签名的

通电器件 (PD)，根据分类确定电源要求，以及通过单

事件（1 类）或双事件（2 类）物理分类应用电源。

TPS2388 还能够灵活地支持 UPoE 和其他非标准负

载。

端口重映射

1 位和 3 位快速端口关断输入

“永不受骗”4 点检测

1 类和 2 类 PD 分类

具有折返功能的可编程电流限制

直流断开检测

灵活的处理器控制运行模式

利用端口重映射和器件引脚，设计人员可以实现 2 层

PCB 设计并简化从上一代 PSE 器件进行的迁移。借助

外部 FET 架构，设计人员可以进一步平衡尺寸、效

率、散热和解决方案成本要求。电流折返可在启动和过

载情况期间降低外部 MOSFET 上的热应力，从而允许

使用较便宜的 FET。

–

半自动

手动

•

14 位端口电流和电压监控

–

100ms 滚动端口电流平均

2% 电流感应精度

具有开尔文感应功能的 0.255Ω 感应电阻器

快速关断 (OSS) 输入可以为要求立即禁用多个端口的

应用提供多达八个级别的逐端口关断。

I²C 通信

–

用于实现失效防护运行的 I²C 看门狗

器件信息⁽¹⁾

可选择 8 位和 16 位访问模式

•

–40°C 至 125°C 工作温度

56 引线 VQFN 封装

器件型号

TPS2388

封装

VQFN (56)

封装尺寸（标称值）

8.00mm x 8.00mm

(1) 如需了解所有可用封装，请参阅产品说明书末尾的可订购产品

附录。

2 应用

•

企业交换机和路由器

SoHo 交换机和路由器

PoE 直通电源模块

网络录像机 (NVR)

简化电路原理图

+48 V

+3.3 V

VDD

100 nF

100 V

PORT

VPWR

SCL

DRAINn

SDAO

TPS2388

GATn

SENn

SDAI

INT

255 mO

KSENSx

AGND

DGND

Note: Only port n shown

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

English Data Sheet: SLUSC25

TPS2388

ZHCSGR0A –FEBRUARY 2015–REVISED AUGUST 2017

www.ti.com.cn

8.3 Feature Description................................................. 18

8.4 Device Functional Modes........................................ 20

8.5 Programming .......................................................... 21

8.6 Register Maps......................................................... 24

Application and Implementation ........................ 64

9.1 Application Information............................................ 64

9.2 Typical Application ................................................. 66

特性.......................................................................... 1

应用.......................................................................... 1

说明.......................................................................... 1

修订历史记录 ........................................................... 2

Pin Configuration and Functions......................... 3

5.1 Detailed Pin Description............................................ 4

Specifications......................................................... 6

6.1 Absolute Maximum Ratings ...................................... 6

6.2 ESD Ratings ............................................................ 6

6.3 Recommended Operating Conditions....................... 6

6.4 Thermal Information.................................................. 7

6.5 Electrical Characteristics........................................... 7

6.6 Timing Requirements ............................................. 10

6.7 Switching Characteristics........................................ 11

6.8 Typical Characteristics............................................ 12

Parameter Measurement Information ................ 14

7.1 Timing Diagrams..................................................... 14

Detailed Description ............................................ 16

8.1 Overview ................................................................. 16

8.2 Functional Block Diagram ....................................... 17

10 Power Supply Recommendations ..................... 72

10.1 VDD....................................................................... 72

10.2 VPWR ................................................................... 72

11 Layout................................................................... 72

11.1 Layout Guidelines ................................................. 72

11.2 Layout Example .................................................... 73

12 器件和文档支持 ..................................................... 74

12.1 接收文档更新通知 ................................................. 74

12.2 社区资源................................................................ 74

12.3 商标....................................................................... 74

12.4 静电放电警告......................................................... 74

12.5 Glossary................................................................ 74

13 机械、封装和可订购信息....................................... 75

4 修订历史记录

日期

修订版本

说明

2017 年 8 月

首次公开发布的产品说明书。

TPS2388

www.ti.com.cn

ZHCSGR0A –FEBRUARY 2015–REVISED AUGUST 2017

5 Pin Configuration and Functions

RTQ Package

VQFN 56 Pins

Top View

GAT1

GAT8

SEN1

DRAIN1

KSENSA

DRAIN2

SEN2

SEN8

DRAIN8

KSENSD

DRAIN7

SEN7

GAT2

GAT3

GAT7

GAT6

Thermal Pad

SEN3

SEN6

DRAIN3

DRAIN6

KSENSB 11

KSENSC

DRAIN5

SEN5

DRAIN4

SEN4

GAT4

GAT5

Pin Functions

I/O

DESCRIPTION

NAME

NO.

48–51

I²C A1-A4 address lines. These pins are internally pulled up to VDD.

Analog ground. Connect to GND plane and exposed thermal pad.

Used for internal test purposes, no bypass capacitor is needed.

Digital ground. Connect to GND plane and exposed thermal pad.

A1-4

AGND

—

ATST_DCPL0

DGND

—

3, 5, 10, 12, 31,

33, 38, 40

DRAIN1-8

DTST_DCPL1

GAT1-8

Port 1-8 output voltage monitor.

Used for internal test purposes, no bypass capacitor is needed.

Port 1-8 gate drive output.

1, 7, 8, 14, 29,

35, 36, 42

INT

Interrupt output. This pin asserts low when a bit in the interrupt register is asserted. This output is open-drain.

Kelvin point connection for SEN1-4

KSENSA/B

KSENSC/D

4, 11

32, 39

Kelvin point connection for SEN5-8

TPS2388

ZHCSGR0A –FEBRUARY 2015–REVISED AUGUST 2017

www.ti.com.cn

Pin Functions (continued)

I/O

DESCRIPTION

NAME

NO.

No connect pins. These pins are internally biased at 1/3 and 2/3 of VPWR in order to control the voltage

gradient from VPWR. Leave open.

15, 16, 18, 19

—

No connect pin. Leave open.

OSS

Port 1-8 fast shutdown. This pin is internally pulled down to DGND.

The DGND and AGND terminals must be connected to the exposed thermal pad for proper operation.

Reset input. When asserted low, the TPS2388 is reset. This pin is internally pulled up to VDD.

Reserved. No connect pins. Leave open.

Thermal pad

RESET

Resv

—

27, 28, 52

—

Serial clock input for I²C bus.

SCL

Serial data input for I²C bus. This pin can be connected to SDAO for non-isolated systems.

SDAI

Serial data output for I²C bus. This pin can be connected to SDAI for non-isolated systems. This output is open-

drain.

SDAO

2, 6, 9, 13, 30,

34, 37, 41

SEN1-8

Port 1-8 current sense input.

TEST0-3

VDD

23, 24, 25, 26

I/O Used internally for test purposes only. Leave open.

—

Digital supply. Bypass with 0.1 µF to DGND pin.

VPWR

Analog 48-V positive supply. Bypass with 0.1 µF to AGND pin.

5.1 Detailed Pin Description

The following descriptions refer to the pinout and the functional block diagram.

DRAIN1-DRAIN8: Port 1-8 output voltage monitor and detect sense. Used to measure the port output voltage,

for port voltage monitoring, port power good detection and foldback action. Detection probe currents also flow

into this pin.

The TPS2388 uses an innovative 4-point technique to provide reliable PD detection. The discovery is performed

by sinking two different current levels via the DRAINn pin, while the PD voltage is measured from VPWR to

DRAINn. The 4-point measurement provides the capability to avoid powering a capacitive or legacy load. Also,

while in semiauto mode, if prior to starting a new detection cycle the port voltage is >2.5 V, an internal 100-kΩ

resistor is connected in parallel with the port and a 400-ms detect backoff period is applied to allow the port

capacitor to be discharged before the detection cycle starts.

There is an internal resistor between each DRAINn pin and VPWR in any operating mode except during

detection or while the port is ON. If the port n is not used, DRAINn can be left floating or tied to AGND.

GAT1-GAT8: Port 1-8 gate drive output is used for external N-channel MOSFET gate control. At port turn on, it

is driven positive by a low current source to turn the MOSFET on. GATn is pulled low whenever any of the input

supplies are low or if an overcurrent timeout has occurred. GATn is also pulled low if its port is turned off by use

of manual shutdown inputs. Leave floating if unused.

For a robust design, a current foldback function limits the power dissipation of the MOSFET during low resistance

load or a short-circuit event. During inrush, the foldback mechanism measures the port voltage across VPWR

and DRAINn to reduce the current limit threshold as shown in Figure 17.

When I_CUTthreshold is exceeded while a port is on, a timer starts. During that time, linear current limiting ensures

the current does not exceed I_LIMcombined with current foldback action. When the timer reaches its t_OVLD(or

t_STARTif at port turn on) limit, the part shuts off. When the port current goes below I_CUT, the counter counts down

at a rate 1/16^thof the increment rate and it must reach a count of 0 before the port can be turned on again.

The fast overload protection is for major faults like a direct short. This forces the MOSFET into current limit in

less than a microsecond.

The circuit leakage paths between the GATn pin and any nearby DRAINn pin, GND or Kelvin point connection

must be minimized (<250 nA), to ensure correct MOSFET control.

INT: This interrupt output pin asserts low when a bit in the interrupt register is asserted. This output is open-

drain.

KSENSA, KSENSB, KSENSC, KSENSD: Kelvin point connection used to perform a differential voltage

measurement across the associated current sense resistors.

TPS2388

www.ti.com.cn

ZHCSGR0A –FEBRUARY 2015–REVISED AUGUST 2017

Detailed Pin Description (continued)

Each KSENS is shared between two neighbor SEN pins as following: KSENSA with SEN1 and SEN2, KSENSB

with SEN3 and SEN4, KSENSC with SEN5 and SEN6, KSENSD with SEN7 and SEN8. To optimize the

accuracy of the measurement, take care with the PCB layout to minimize the impact of the PCB traces'

resistance.

OSS: Fast shutdown, active high. This pin is internally pulled down to DGND, with an internal 1-µs to 5-µs

deglitch filter.

The Port Power Priority/ICUT Disable register is used to determine which port is shut down in response to an

external assertion of the OSS fast shutdown signal. The turn off procedure is similar to a port reset using Reset

command (1Ah register).

RESET: Reset input, active low. When asserted, the TPS2388 resets, turning off all ports and forcing the

registers to their power-up state. This pin is internally pulled up to VDD, with internal 1-µs to 5-µs deglitch filter.

The designer can use an external RC network to delay the turn-on. There is also an internal power-on-reset

which is independent of the RESET input.

NOTE

During the first 5 ms after RESET has been asserted, if a port is turned on using the

Power Enable command (0x19), TI recommends to wait for the expiration of that 5-ms

initial period before sending any subsequent Detect/Class Restart or Detect/Class Enable

command.

SCL: Serial clock input for I²C bus.

SDAI: Serial data input for I²C bus. This pin can be connected to SDAO for non-isolated systems.

SDAO: Open-drain I²C bus output data line. Requires an external resistive pull-up. The TPS2388 uses separate

SDAO and SDAI lines to allow optoisolated I²C interface. SDAO can be connected to SDAI for non-isolated

systems.

A4-A1: I²C bus address inputs. These pins are internally pulled up to VDD. See Pin Status Register for more

details.

SEN1-8: Port current sense input relative to KSENSn (see KSENSn description). A differential measurement is

performed using KSENSA-D Kelvin point connection. Monitors the external MOSFET current by use of a 0.255-Ω

current sense resistor connected to DGND. Used by current foldback engine and also during classification. Can

be used to perform load current monitoring via A/D conversion.

Note that a classification is done while using the external MOSFET so that doing a classification on more than

one port at same time is possible without overdissipation in the TPS2388. For the current limit with foldback

function, there is an internal 2-µS analog filter on the SEN1-8 pins to provide glitch filtering. For measurements

through an A/D converter, an anti-aliasing filter is present on the SEN1-8 pins. This includes the port-powered

current monitoring, port policing, and DC disconnect.

If the port is not used, tie SENn to AGND.

VDD: 3.3-V logic power supply input.

VPWR: High voltage power supply input. Nominally 48 V.

TPS2388

ZHCSGR0A –FEBRUARY 2015–REVISED AUGUST 2017

www.ti.com.cn

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)

(1)

MIN

–0.3

MAX

UNIT

VPWR

VDD

Input voltage

OSS, RESET, A1-A4

SEN1-8,⁽²⁾KSENSA, KSENSB, KSENSC, KSENSD

GATE1-8^{(3) (4)}

SDAI, SDAO ⁽⁵⁾, SCL, INT

Output voltage

Voltage

(5) (6)

DRAIN1-8

TEST0-3, ATST_DCPL0, DTST_DCPL1⁽⁵⁾

AGND

0.3

260

150

Sink current

INT, SDAO

°C

Lead temperature 1.6 mm (1/16-inch) from case for 10 seconds

T_stgStorage temperature

–65

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) SEN1-8 are tolerant to 15-V transients to avoid fault propagation when a MOSFET fails in short-circuit

(3) Application of voltage is not implied; these are internally driven pins.

(4) If the external MOSFET fails short between its drain and gate, the GATE pin may internally permanently disconnect to prevent cascade

damage. The three other ports continue to operate.

(5) Do not apply external voltage sources directly

(6) Short transients (µs range) up to 80 V are allowed

6.2 ESD Ratings

VALUE

±2000

±500

UNIT

Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins⁽¹⁾

Charged device model (CDM), per JEDEC specification JESD22-C101, all pins⁽²⁾

Electrostatic

discharge

V_(ESD)

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN NOM

MAX UNIT

V_VDD

3.3

3.6

V_VPWR

Voltage slew rate on VPWR

Operating junction temperature

Operating free-air temperature

V/µs

°C

T_J

–40

125

T_A

°C

TPS2388

www.ti.com.cn

ZHCSGR0A –FEBRUARY 2015–REVISED AUGUST 2017

6.4 Thermal Information

TPS2388

UNIT

THERMAL METRIC⁽¹⁾

VQFN (56 PINS)

R_θJA

Junction-to-ambient thermal resistance

25.3

9.7

R_θJC(top)

R_θJB

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

3.7

°C/W

0.2

ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

ψ_JB

3.7

0.5

R_θJC(bot)

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

6.5 Electrical Characteristics

–40°C ≤ T_J≤ 125°C unless otherwise noted. V_VDD= 3.3 V, V_VPWR= 48 V, V_DGND= V_AGND, DGND, KSENSA, KSENSB,

KSENSC, and KSENSD connected to AGND, and all outputs are unloaded, unless otherwise noted. PoEPn = 0. Positive

currents are into pins. R_S= 0.255 Ω, to KSENSA (SEN1 or SEN2), to KSENSB (SEN3 or SEN4), to KSENSC (SEN5 or

SEN6) or to KSENSD (SEN7 or SEN8). Typical values are at 25°C. All voltages are with respect to AGND, unless otherwise

noted. Operating registers loaded with default values, unless otherwise noted.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

INPUT SUPPLY VPWR

V_VPWR= 50 V

12.5

100

17.5

18.5

µA

I_VPWR

VPWR current consumption

V_VPWR< 8 V

V_{UVLOPW_F}

V_{UVLOPW_R}

V_{PUV_F}

VPWR UVLO falling threshold

VPWR UVLO rising threshold

VPWR undervoltage falling threshold

14.5

15.5

VPUV threshold

V_VPWR= 50 V

26.5

TOTAL DEVICE POWER DISSIPATION

P_TVPWR and VDD consumption

INPUT SUPPLY VDD

0.67

I_VDD

VDD Current consumption

2.25

2.6

2.4

V_{UVDD_F}

V_{UVDD_R}

V_{UVDD_HYS}

V_{UVW_F}

VDD UVLO falling threshold

VDD UVLO rising threshold

Hysteresis VDD UVLO

For port deassertion

2.1

2.45

2.75

0.35

2.8

VDD UVLO warning threshold

2.6

3.0

DETECTION

First detection point, V_VPWR– V_DRAINn= 0 V

145

235

160

270

190

300

Second detection point, V_VPWR– V_DRAINn= 0

I_DISC

Detection current

µA

High-current detection point, V_VPWR

V_DRAINn= 0 V

–

490

540

585

V_detect

Open-circuit detection voltage

Rejected resistance low range

Rejected resistance high range

Accepted resistance range

Shorted port threshold

V_VPWR– V_DRAINn

23.5

0.86

R_{REJ_LOW}

R_{REJ_HI}

R_ACCEPT

R_SHORT

R_OPEN

kΩ

Ω

100

26.5

360

Open port threshold

400

kΩ

TPS2388

ZHCSGR0A –FEBRUARY 2015–REVISED AUGUST 2017

www.ti.com.cn

Electrical Characteristics (continued)

–40°C ≤ T_J≤ 125°C unless otherwise noted. V_VDD= 3.3 V, V_VPWR= 48 V, V_DGND= V_AGND, DGND, KSENSA, KSENSB,

KSENSC, and KSENSD connected to AGND, and all outputs are unloaded, unless otherwise noted. PoEPn = 0. Positive

currents are into pins. R_S= 0.255 Ω, to KSENSA (SEN1 or SEN2), to KSENSB (SEN3 or SEN4), to KSENSC (SEN5 or

SEN6) or to KSENSD (SEN7 or SEN8). Typical values are at 25°C. All voltages are with respect to AGND, unless otherwise

noted. Operating registers loaded with default values, unless otherwise noted.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

CLASSIFICATION

V_VPWR– V_DRAINn, V_SENn≥ 0 mV,

V_CLASS

Classification voltage

15.5

18.5

20.5

I_port≥ 180 µA

I_{CLASS_Lim}

Classification current limit

VVPWR – VDRAINn = 0 V

Class 0-1

Class 1-2

I_{CLASS_TH}

Classification threshold current

Class 2-3

Class 3-4

Class 4-Class overcurrent

4 mA ≥ Iport ≥ 180 µA, VVPWR – VDRAINn

V_VPWR– V_DRAINn= 0 V

V_MARK

I_{MARK_Lim}

GATE

V_GOH

Mark voltage

Mark sinking current limit

Gate drive voltage

V_GATEn, I_GATE= –1 µA

V_GATEn= 5 V

12.5

190

Gate sinking current with Power-on Reset, OSS

detected or port turn off command

I_GO-

100

V_GATEn= 5 V, V_SENn≥ V_short(or Vshort2X if

2X mode)

I_{GO short–}

Gate sinking current with port short-circuit

Gate sourcing current

100

190

µA

I_GO+

V_GATEn= 0V

DRAIN INPUT

V_PGT

Power Good threshold

Shorted FET threshold

Measured at V_DRAINn

1.0

2.13

V_SHT

Any operating mode except during detection

or while the port is ON, including in device

RESET state

R_DRAIN

Resistance from DRAINn to VPWR

DRAINn pin bias current

100

190

120

kΩ

I_DRAIN

A/D CONVERTER

V_VPWR– V_DRAINn= 30 V, port ON

µA

t_CONV

Conversion time, current measurement

All ranges, each port

0.64

0.82

0.8

0.96

1.2

t_{CONV_V}

Conversion time, voltage measurement

1.03

Gap between adjacent current measurement

integrations

5% × t_CONV

t_GAP

5% ×

t_{INT_CUR}

Gap between adjacent current averaged results

ADC_BW

t_{INT_CUR}

t_{INT_DET}

t_{INT_portV}

t_{INT_inV}

ADC integration bandwidth (–3 db)

Current measurement

320

102

Integration (averaging) time, current

Integration (averaging) time, detection

Integration (averaging) time, port voltage

Integration (averaging) time, input voltage

Each port, port ON current

13.1

122

16.6

Port powered

3.25

4.12

4.9

3.25

4.12

At V_VPWR– V_DRAINn= 57 V

At V_VPWR– V_DRAINn= 44 V

At port current = 770 mA

At port current = 7.5 mA

At V_VPWR= 57 V

15097

11654

12363

100

15565

12015

12616

123

16032 Counts

12375 Counts

12868 Counts

150 Counts

15955 Counts

12316 Counts

Powered port voltage conversion scale factor and

accuracy

Powered port current conversion scale factor and

accuracy

15175

11713

–3%

15565

12015

Input voltage conversion scale factor and accuracy

At V_VPWR= 44 V

δ_V/V_port

Voltage reading accuracy

At 44 to 57 V

σ_V

Voltage reading repeatability

Full scale reading

At 50 mA

–18

7.5

–3%

δ_I/I_port

Current reading accuracy

At 770 mA

-2%

σ_I

Current reading repeatability

Full scale reading

–7.5

TPS2388

www.ti.com.cn

ZHCSGR0A –FEBRUARY 2015–REVISED AUGUST 2017

Electrical Characteristics (continued)

–40°C ≤ T_J≤ 125°C unless otherwise noted. V_VDD= 3.3 V, V_VPWR= 48 V, V_DGND= V_AGND, DGND, KSENSA, KSENSB,

KSENSC, and KSENSD connected to AGND, and all outputs are unloaded, unless otherwise noted. PoEPn = 0. Positive

currents are into pins. R_S= 0.255 Ω, to KSENSA (SEN1 or SEN2), to KSENSB (SEN3 or SEN4), to KSENSC (SEN5 or

SEN6) or to KSENSD (SEN7 or SEN8). Typical values are at 25°C. All voltages are with respect to AGND, unless otherwise

noted. Operating registers loaded with default values, unless otherwise noted.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

15 kΩ ≤ R_port≤ 33 kΩ, C_port≤ 0.25 µF, at 44

to 57 V

δ_R/R_port

Resistance reading accuracy

–7%

PORT CURRENT SENSE

V_DRAINn= 0 V, POL(3:0) = 0001b

V_DRAINn= 0 V, POL(3:0) = 0010b

V_DRAINn= 0 V, POL(3:0) = 0111b

V_DRAINn= 0 V, POL(3:0) = 1111b

9.6

14.53

38.76

77.5

10.2

15.3

40.8

81.6

10.8

16.06

42.84

85.6

V_CUT

I_CUTlimit

V_DRAINn= 0 V, POL(3:0) = 0000b,

PoEPn = 1

77.5

81.6

85.6

V_DRAINn= 0 V, POL(3:0) = 1111b,

PoEPn = 1

222.8

–6.3%

–5%

234.6

246.3

6.3%

δ_V/V_police

δ_icut/I_CUT

Police setting resolution

I_CUTtolerance

All settings except POL(3:0) = 0000b

and 0001b while PoEPn = 0

V_VPWR– V_DRAINn= 1 V

V_VPWR– V_DRAINn= 10 V

V_VPWR– V_DRAINn= 30 V

V_VPWR– V_DRAINn= 55 V

V_DRAINn= 1 V

114.7

V_Inrush

I_Inrushlimit, 1x or 2x mode

102

114.7

V_DRAINn= 13 V

114.7

V_LIM

I_LIMlimit in 1x mode

V_DRAINn= 30 V

V_DRAINn= 48 V

V_DRAINn= 1 V

260

127

270.3

140

285

V_DRAINn= 10 V

153

V_LIM2X

I_LIMlimit in 2X mode (PoEPn = 1)

V_DRAINn= 30 V

V_DRAINn= 48 V

V_short

V_short2X

I_bias

I_shortthreshold in 1X mode and during inrush

I_shortthreshold in 2X mode

234

357

–2.5

1.275

306

408

Threshold for GATE to be less than 1 V,

2 µS after application of pulse

Sense pin bias current

Port ON or during class

µA

V_IMIN

DC disconnect threshold

2.55

DIGITAL INTERFACE AT V_VDD= 3.3 V

V_IH

V_IL

Digital input high

Digital input low

2.1

0.9

Input voltage hysteresis (SCL, SDAI, A1-A4, RESET,

OSS)

V_{IT_HYS}

0.17

Digital output Low, SDAO

Digital output Low, INT

Pullup resistor to VDD

At 9 mA

0.4

V_OL

At 3 mA

R_pullup

R_pulldown

RESET, A1-A4, TEST0

OSS

kΩ

Pulldown resistor to DGND

kΩ

TEST1, 2

THERMAL SHUTDOWN

Shutdown temperature

Hysteresis

Temperature rising

135

146

°C

T_SD

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MAX UNIT

6.6 Timing Requirements

MIN

TYP

f_SCL

SCL clock frequency

400

kHz

µs

t_LOW

t_HIGH

LOW period of the clock

HIGH period of the clock

1.3

0.6

µs

SDAO, 2.3 → 0.8 V, Cb = 10 pF,

10 kΩ pull-up to 3.3 V

250

t_fo

SDAO output fall time

SCL capacitance

SDAO, 2.3 → 0.8 V, Cb = 400 pF,

1.3 kΩ pull-up to 3.3 V

C_I2C

C_{I2C_SDA}SDAI, SDAO capacitance (each)

t_SU,DATWData set-up time (Write operation)

100

600

SDAO, Cb = 10 pF,

1.3 kΩ pull-up to 3.3V

t_SU,DATRData set-up time (Read operation)

t_HD,DATWData hold time (Write operation)

t_HD,DATRData hold time (Read operation)

150

µs

600

250

300

200

t_fSDA

t_rSDA

t_r

Input fall times of SDAI

Input rise times of SDAI

Input rise time of SCL

Input fall time of SCL

2.3 → 0.8 V

0.8 → 2.3 V

2.3 → 0.8 V

t_f

t_BUF

Bus free time between a STOP and START condition

Hold time after (repeated) Start condition

Repeated Start condition set-up time

Stop condition set-up time

1.3

0.6

t_HD,STA

t_SU,STA

t_SU,STO

Time to internally register an Interrupt fault,

from port turn off

t_{FLT_INT}

Fault to INT assertion

500

µs

t_DG

Suppressed spike pulse width, SDAI and SCL

RESET input minimum pulse width (deglitch time)

µs

t_RDG

t_{bit_OSS}

3-bit OSS bit period

MbitPrty = 1

Idle time between consecutive shutdown

code transmission in 3-bit mode

t_{OSS_IDL}

MbitPrty = 1

µs

t_{r_OSS}

t_{f_OSS}

Input rise time of OSS in 3-bit mode

Input fall time of OSS in 3-bit mode

0.8 → 2.3 V, MbitPrty = 1

2.3 → 0.8 V, MbitPrty = 1

300

3.3

t_{WDT_I2C}I²C Watchdog trip delay

1.1

2.2

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6.7 Switching Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

5.5%

TYP

MAX UNIT

δI_fault

Duty cycle of Iport with current fault

6.7%

TOVLD = 00

TOVLD = 01

TOVLD = 10

TOVLD = 11

140

t_OVLD

ICUT time limit (DCUTn = 0)

100

200

280

ICUT Interrupt time limit when ICUT is disabled I_CUTlimit exceeded but not I_LIM, TLIM = 01, PoEPn =

t_{ICUT_INT}

t_LIM/2t_LIM/2+ 6

(DCUTn = 1)⁽¹⁾

ILIM time limit

TLIM = 00, PoEPn = 1

TLIM = 01, PoEPn = 1

TLIM = 10, PoEPn = 1

TLIM = 11, PoEPn = 1

TSTART = 00

t_LIM

14.5

11.5

9.5

15.75

12.5

10.5

t_START

Maximum current limit duration in port start-up

Detection duration, 4-point discovery

TSTART = 01

TSTART = 10

100

275

300

140

425

500

100

t_DET

Time to complete a detection

V_VPWR– V_DRAINn> 2.5 V

V_VPWR– V_DRAINn< 2.5 V

350

400

Detect backoff pause between discovery

attempts

t_{DET_BOFF}

From command or PD attachment to port detection

complete

t_{DET_DLY}

t_CLE

Detection delay

590

Classification duration, first and second class

event

Semiauto mode. From detection complete

6.5

Semiauto mode. From detection complete

Manual mode. From beginning of class

Semiauto mode. From Class 4 complete

6.5

Classification duration, 1-event physical layer

class timing

t_pdc

t_ME

Mark Duration, first and second mark event

Port Power-On delay, semiauto mode

From end of detection to port turn on using IEEE

power enable

200

t_pon

From port turn on command to port turn on

completed, four ports

Port Power-On delay, manual mode

Reset time duration from RESET pin

µs

t_RESET

t_ed

Error delay timing. Delay before next attempt to

power a port following power removal due to

error condition

ICUT , ILIM or IInrush fault, semiauto mode

0.8

1.2

TMPDO = 00

TMPDO = 01

TMPDO = 10

TMPDO = 11

300

400

100

200

800

t_MPDO

PD maintain power signature dropout time limit

150

600

t_MPS

PD maintain power signature time for validity

Gate turn off time from 1-bit OSS input

µs

From OSS to V_GATEn< 1 V, V_SENn= 0 V, MbitPrty =

t_{D_off_OSS}

From Start bit falling edge to V_GATEn< 1 V, V_SENn= 0

V, MbitPrty = 1

t_{OSS_OFF}

Gate turn off time from 3-bit OSS input

104

µs

t_{P_off_CMD}

t_{P_off_RST}

Gate turn off time from port off command

Gate turn off time with RESET

From port off command to V_GATEn< 1 V, V_SENn= 0 V

From RESET low to V_GATEn< 1 V, V_SENn= 0 V

V_DRAINn= 1 V , From V_SENnpulsed to 0.425 V

300

µs

Gate turn off time from SENn input

0.9

t_{D_off_SEN}

t_POR

µs

Gate turn off time from SENn input (PoEPn = 1) V_DRAINn= 1 V , From V_SENnpulsed to 0.62 V

Device power-on reset delay

(1) The t_{ICUT_INT}maximum value shown in the table only applies to a low percentage (< 10%) of occurence. The rest of the time, it becomes

t_LIM/2 + 2 ms.

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6.8 Typical Characteristics

6.5

T_J= -40èC

T_J= 25èC

T_J= 125èC

Port ON

9.5

PortBOGFF

8.5

5.5

T_J= -40èC

T_J= 25èC

T_J= 125èC

7.5

2.7

2.8

2.9

3.1

3.2

3.3

3.4

3.5

3.6

VPWR (V)

VDD (V)

D001

D002

Figure 1. VPWR Current Consumption vs VPWR

Figure 2. VDD Current Consumption vs VDD

16.5

2.4

2.35

2.3

15.5

2.25

2.2

14.5

2.15

2.1

-40

-20

100

120

-40

-20

100

120

Junction Temperature (èC)

D003

D004

Figure 3. VPWR UVLO Falling Threshold vs Junction

Temperature

Figure 4. VDD UVLO Falling Threshold vs Junction

Temperature

1.9

1.8

1.7

1.6

2.9

2.8

2.7

2.6

-40

-20

100

120

-40

-20

100

120

Junction Temperature (èC)

D005

D006

Figure 5. VDD UVLO Warning Threshold vs Junction

Temperature

Figure 6. DC Disconnect Threshold (V_IMIN) vs Junction

Temperature

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Typical Characteristics (continued)

110

109

108

107

106

105

T_J= -40èC

T_J= 25èC

T_J= 125èC

-40

-20

100

120

Classification Current (mA)

Junction Temperature (èC)

D007

D008

Figure 7. Classification Voltage (V_CLASS) vs Port

Classification Current

Figure 8. Current Limit 1x Threshold (V_LIM) vs Junction

Temperature

280

120

110

100

278

276

274

272

270

-40

-20

100

120

Junction Temperature (èC)

Port Voltage (V)

D009

D010

Figure 9. Current Limit 2x Threshold (V_LIM2X) vs Junction

Temperature

Figure 10. Inrush Current Limit Threshold (V_Inrush) vs Port

Voltage

300

250

200

150

100

FET V_DS(V)

D011

Figure 11. Foldback Current Limit Threshold (V_LIM, V_LIM2X) vs Port MOSFET Voltage

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7 Parameter Measurement Information

7.1 Timing Diagrams

t_rSDA

SDAI/

SDAO

t_fSDA

t_fo

t_BUF

t_SU,DAT

t_f

t_r

t_LOW

SCL

t_HIGH

t_SU,STO

t_HD,DAT

t_SU,STA

t_HD,STA

Stop Condition

Start Condition

Repeated

Start Condition

Figure 12. I²C Timings

Port turn-on

Class

V_CLASS

Four-point

detection

V_PORT

t_pdc

t_pon

t_DET

Figure 13. Detection, 1-Event Classification and Turn On

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Timing Diagrams (continued)

Port turn-on

Class

V_CLASS

Four-point

detection

V_MARK

Mark

V_PORT

0 V

t_ME

t_DET

t_CLE

t_pon

Figure 14. Detection, 2-Event Classification and Turn On

V_LIM

V_CUT

SEN

0 V

GATE

0 V

t_OVLD

Figure 15. Overcurrent Fault Timing

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8 Detailed Description

8.1 Overview

The TPS2388 is an eight-port PSE for power over Ethernet applications. Each of the eight ports provides

detection, classification, protection, and shut down in compliance with the IEEE 802.3at standard.

Basic PoE features include the following:

•

Performs high-reliability 4-point load detection

Performs classification including type-2 (two-finger) of up to Class 4 loads

Enables power with protective foldback current limiting, and adjustable I_CUTthreshold

Shuts down in the event of fault loads and shorts

Performs maintain power signature function to ensure removal of power if load is disconnected

Undervoltage lockout occurs if VPWR falls below VPUV_F (typical 26.5 V).

Enhanced features include the following:

•

Port re-mapping capability

8- and 16-bit access mode selectable

1- and 3-bit port shutdown priority

Port turn ON command automatically supports IEEE TPON specification (0x23 register or 0x19 and 0x40

Following a power-off command, disconnect, or shutdown due to a start, ICUT, or ILIM fault, the port powers

down. Following port power off due to a power off command or disconnect, the TPS2388 restarts a detection

cycle if commanded to do so. If the shutdown is due to a start, ICUT, or ILIM fault, the TPS2388 first enters into

a cool-down period, at the end of this period the TPS2388 is able to restart the detection cycle.

Using the turn ON command supporting TPON, the TPS2388 will not automatically apply power to a port under

the following circumstances:

•

The detect status is not resistance valid.

If the classification status is overcurrent, class mismatch, or unknown.

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8.2 Functional Block Diagram

VDD

VPWR

1/3

2/3

1/3

Legend

2/3

2.5V

REF

1.8V Logic

5V Logic

1.8V LDO

VDD UVLO

12V Regulator

5V Regulator

VPWR

VPWR Divider

14MHz Internal

Oscillator

Internal

Rails Good

5 or 12V Analog

80V Analog

CLK OK

2.5V Precision Reference

8V OTP Supply

VPWR

1.8V Logic Supply

Firmware Controlled

Update from register File

2.5V

REF

11.5V

5.0V

CPU Watchdog

RST Block

Clock

Distribution

7.5/

2.8MHz

CLK

to blks

CLK OK

8051 WARP

VPWR

RST

to blks

Port 2-8 Analog Control Functions

Port 1 Analog Control Functions

RESETB

OSS

1024 ByteCode

LOAD

Substitution OTP

with 1024/3 Patch

Space

TCLK

OSS/

Foldback Schedulers

POR

JTAG

(1-4)

TMS

TCLK

TDO

JTAG

DRAINx

GATEx

De-bugger

Ilim

32K

VIA ROM

Fast Ishort Protection

dv/dt ramping control

Rapid Overload recovery

2X Power

Class Current Limit

Class Port Voltage Control

Enable

Scan + Digital

Test

Timer 0

Timer 1

DRIVER

Prog

Mem

Bus

Fuse-able

CPU

Pad Field for EXT Flash

8 data, 14 address,

Enable, Testmode

Disconnect

A1-A4

7 bit address Select

SENx

GND, 1.8V, 10 ProbeIO

FW Registers

SFR

BUS

SDAI

SDAO

SCL

128 Byte

SFR

(80-FF)

With BIST

256 Byte

CPU SRAM

(00-FF)

0.255

IRAM

Bus

I2C Interface

320Hz LPF

IPORT

ICLASS

BIT

KSENSEx

14-23 Bit

ADC

(Current)

SCL Watchdog

REMAP

External Data

Memory Bus

Variable Averager

INT

Interrupt

Controller

Common Functions for Ports 5-8

Common Functions for Ports1-4

OTP TRIM

56 Byte

Vdisco

V48

PORT DIFF AMP

4:1 MUX

Load at Power up

into holding latches

Vport

DRAIN1-4

Vds

14-23 Bit

ADC

(Voltage)

Variable Averager

OSS

VEE

Temp

BIT

V48

PTAT DIODES

Clock/128 and WD

IDET

Analog BIT MUX

DTEST

Digital Test Mux

A/D Timing/Foldback + I2C Signals

Analog

ATEST

Analog Test

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8.3 Feature Description

8.3.1 Port Remapping

The TPS2388 provides port remapping capability, from the logical ports to the physical ports/pins.

The remapping is between any port of a 4-port group (1 to 4, 5 to 8).

The following example is applicable to 0x26 register = 00111001, 00111001b.

•

Logical port 1 (5) ↔ Physical port 2 (6)

Logical port 2 (6) ↔ Physical port 3 (7)

Logical port 3 (7) ↔ Physical port 4 (8)

Logical port 4 (8) ↔ Physical port 1 (5)

NOTE

The device ignores any remapping command unless all four ports are in off mode.

If the TPS2388 receives an incorrect configuration, it simply ignores the incorrect configuration and keeps the

configuration unchanged. The ACK is also sent as usual at the end of communication. For example, if the same

code is received for more than one port, then a read back of the Re-Mapping register (0x26) would be the last

valid configuration.

Also note that if an IC reset command (1Ah register) is received, the port remapping configuration is kept

unchanged. However, if there is a Power-on Reset or if the RESET pin is activated, the Re-Mapping register is

reinitialized to a default value.

8.3.2 Port Power Priority

The TPS2388 supports 1- and 3-bit shutdown priority, selectable with the MbitPrty bit of General Mask register

(0x17).

The 1-bit shutdown priority works with the Port Power Priority (0x15) register. An OSSn bit with a value of 1

indicates that the corresponding port will be treated as low priority, while a value of 0 corresponds to a high

priority. As soon as the OSS input goes high, the low-priority ports are turned off.

The 3-bit shutdown priority works with the Multi Bit Power Priority (0x27/28) register, which holds the priority

settings. A port with “000” code in this register has highest priority. Port priority reduces as the 3-bit value

increases, with up to 8 priority levels. See Figure 16.

The port priority is defined as the following:

•

OSS code ≤ Priority setting (0x27/28 register): OSS code turns off the port

OSS code > Priority setting (0x27/28 register): OSS code has no impact on the port

Shutdown Code

START bits

3.3 V

0 V

SC 1

SC 2

SC 0

OSS

IDLE

t_{f_OSS}

t_{OSS_IDL}

t_{r_OSS}

t_{bit_OSS}

one-bit

duration

t_{OSS_OFF}

GATE

Figure 16. Multi-Bit Priority Port Shutdown if Lower-Priority Port

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Feature Description (continued)

NOTE

Prior to setting the MbitPrty bit from 0 to 1, make sure the OSS input is in the idle (low)

state for a minimum of 200 µs, to avoid any port misbehavior related to loss of

synchronization with the OSS bit stream.

NOTE

The OSS input has an internal 1-µs to 5-µs deglitch filter. From the idle state, a pulse with

a longer duration is interpreted as a valid start bit. Ensure that the OSS signal is noise

free.

8.3.3 A/D Converter

The TPS2388 features ten multi-slope integrating converters. Each of the first eight converters is dedicated to

current measurement for one port and is operated independently to perform measurements in any of the

following modes: classification and port powered. When the port is powered, the converter is used for current

(100-ms averaged) monitoring, port policing, and DC disconnect. Each of the last two converters are shared

within a group of four ports for discovery (16.6-ms averaged), port powered voltage monitoring, Power Good

status, and FET short detection. It is also used for general-purpose measurements including input voltage (1 ms)

and temperature.

The A/D converter type used in the TPS2388 differs from other similar types of converters in that it converts

while the input signal is being sampled by the integrator, providing inherent filtering over the conversion period.

The typical conversion time of the current converters is 800 µs, while it is 1 ms for the other converters.

Powered-device detection is performed by averaging 16 consecutive samples providing significant rejection of

noise at 50-Hz or 60-Hz line frequency. While a port is powered, digital averaging is used to provide a port

current measurement integrated over a 100-ms time period. Note also that an anti-aliasing filter is present for

port powered current monitoring.

NOTE

During port-powered mode, port current conversions are performed continuously. Also, in

port-powered mode, the t_STARTtimer must expire before any current or voltage A/D

conversion can begin.

8.3.4 I²C Watchdog

An I²C Watchdog timer is available on the TPS2388 device. The timer monitors the I²C, SCL line for clock edges.

When enabled, a timeout of the watchdog resets the I²C interface along with any active ports. This feature

provides protection in the event of a hung software situation or I²C bus hang-up by slave devices. In the latter

case, if a slave is attempting to send a data bit of 0 when the master stops sending clocks, then the slave could

get stuck driving the data line low indefinitely. Because the data line is being driven low, the master cannot send

a STOP to clean up the bus. Activating the I²C watchdog feature of the TPS2388 would clear this deadlocked

condition. If the timer of 2 seconds expires, the ports latch off and the WD Status bit is set. Note that WD Status

will be set even if the watchdog is not enabled. WD Status can only be cleared by a reset or writing a 0 to the

WDS status bit location. The 4-bit watchdog disable field shuts down this feature when a code of 1011b is

loaded. This field is preset to 1011b whenever the TPS2388 is initially powered. Also see I2C WATCHDOG

8.3.5 Foldback Protection

The TPS2388 features two types of foldback protection mechanisms for complete MOSFET protection. During

inrush at port turn on, the foldback is based on the port voltage as shown in Figure 17. Note that the inrush

current profile remains the same, whatever the state of the PoEPn bit in the PoE Plus register.

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Feature Description (continued)

After the port has been turned on and the Power Good is valid, a dual-slope foldback is used, providing

protection against partial and total short-circuit at port output, while still being able to maintain the PD powered

during normal transients at the PSE input voltage. Note that setting the PoEPn bit selects the 2× curve and

clearing it selects the 1× curve. See Figure 18.

1.2

1.1

0.45

0.4

IEEE 802.3af

PoE+

0.35

0.3

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0.25

0.2

0.15

0.1

0.05

Port Voltage (V)

FET Vds (V)

D030

D031

Figure 17. Foldback during Inrush (at Port Turn On): I_LIM

vs V_port

Figure 18. Foldback when the Port is Already ON: I_LIMvs

V_drain

8.4 Device Functional Modes

8.4.1 Port Operating Modes

8.4.1.1 Semiauto

The port performs detection and classification (if valid detection occurs) continuously. Registers are updated

each time a detection or classification occurs. The port power is not automatically turned on. Power Enable or

IEEE Power Enable command is required to turn on the port.

8.4.1.2 Manual

The port performs the functions indicated by its registers one time when commanded. There is no automatic

state change.

8.4.1.3 Power Off

The port is powered off and does not autonomously perform a detection, classification, or power-on. In this

mode, Status and Enable bits for the associated port are reset.

8.4.2 Detection

To eliminate the possibility of false detection, the TPS2388 uses a TI proprietary 4-point detection method to

determine the signature resistance of the PD device. False detection of a 25-kΩ signature can occur with 2-point

detection type PSEs in noisy environments or if the load is highly capacitive.

Both detection 1 and detection 2 are merged into a single detection function which is repeated. Detection 1

applies I1 (160 μA) to a port, waits 60 ms, then measures the port voltage V1 with the integrating ADC. Detection

2 applies I2 (270 μA) to a port, waits 60 ms, then measures the port voltage V2. The process is repeated a

second time. Multiple comparisons and calculations are performed on all four measurement point combinations

to eliminate the effects of a non-linear or hysteretic PD signature. The resulting port signature is then sorted into

the appropriate category.

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Device Functional Modes (continued)

NOTE

The detection resistance measurement result is also available in the Port Detect

Resistance register.

8.4.3 Classification

Hardware classification (class) is performed by supplying a voltage and sampling the resulting current. To

eliminate the high power of a classification event from occurring in the power controller chip, the TPS2388 makes

use of the external power FET for classification.

During classification, the voltage on the gate node of the external MOSFET is part of a linear control loop. The

control loop applies the appropriate MOSFET drive to maintain a differential voltage between VPWR and DRAIN

of 17.5 V. During classification the voltage across the sense resistor in the source of the MOSFET is measured

and converted to a class level within the TPS2388. If a load short occurs during classification, the MOSFET gate

voltage is quickly reduced to a linearly controlled, short-circuit value for the duration of the class event.

Classification results may be read through the I²C Detection Event and Port n Status Registers. The TPS2388

also supports two-event classification for type 2 PDs, using the IEEE Power Enable register.

8.4.4 DC Disconnect

Disconnect is the automated process of turning off power to the port. When the port is unloaded or at least falls

below minimum load, it is necessary to turn off power to the port and restart detection. In DC disconnect, the

voltage across the sense resistors is measured. When enabled, the DC disconnect function monitors the sense

resistor voltage of a powered port to verify the port is drawing at least the minimum current to remain active. The

TDIS timer counts up whenever the port current is below a 7.5-mA threshold. If a timeout occurs, the port is shut

down and the corresponding disconnect bit in the Fault Event Register is set. The TDIS counter is reset each

time the current goes continuously higher than the disconnect threshold for nominally 15 ms.

The TDIS duration is set by the TMPDO Bits of the Timing Configuration register (0x16).

8.5 Programming

8.5.1 I²C Serial Interface

The TPS2388 features a 3-wire I²C interface, using SDAI, SDAO, and SCL. Each transmission includes a Start

condition sent by the master, followed by the device address (7-bit) with R/W bit, a register address byte, then

one or two data bytes and a Stop condition. The recipient also sends an acknowledge bit following each byte

transmitted. Also, SDAI/SDAO is stable while SCL is high except during a Start or Stop condition.

Figure 19 and Figure 20 illustrate read and write operations through I²C interface, using configuration A or B (see

Table 19 for more details). The 'parametric' read operation is applicable to A/D conversion results. The TPS2388

also features quick access to the latest addressed register through I²C bus. This means that when a Stop bit is

received, the register pointer is not automatically reset.

It is also possible to perform a write operation to many TPS2388 devices at the same time. The slave address

during this broadcast access is 0x7F, as shown in Pin Status Register. Depending on which configuration (A or

B) is selected, a global write proceeds as following:

•

Config A: Both 4-port devices (1 to 4 and 5 to 8) are addressed at same time.

Config B: The whole device is addressed.

TPS2388

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Programming (continued)

R/W

Bit

Address

Pins

Address

Pins

R/W

Bit

Non-Parametric

Read Cycle

SDAI

A4 A3 A2 A1 A0 R/W

C5 C4 C3 C2

1 A4 A3 A2 A1 A0 ^R/W

D7 D6 D5 D4 D3 D2 D1 D0

Command Code

Slave Address

R/W=0

Slave Address

R/W=1

Data from

Slave to Host

SDAO

D7 D6 D5 D4 D3 D2 D1 D0

R/W

Bit

Address

Pins

Address

Pins

R/W

Bit

Parametric

Read Cycle

R/W

D7 D6 D5 D4 D3 D2 D1 D0

A4 A3 A2 A1 A0 R/W

C5 C4 C3 C2

A4 A3 A2 A1 A0

SDAI

Command Code

Slave Address

R/W=0

Slave Address

R/W=1

LSByte Data from

Slave to Host

MSByte Data from

Slave to Host

D7 D6 D5 D4 D3 D2 D1 D0

SDAO

R/W

Bit

Address

Pins

Write Cycle

A4 A3 A2 A1 A0 R/W

D7 D6 D5 D4 D3 D2 D1 D0

SDAI

Slave Address

R/W=0

Data from

Host to Slave

Command Code

SDAO

Quick Read Cycle

(latest addressed register)

Address

Pins

R/W

Bit

SDAI

A4 A3 A2 A1 A0 R/W

D7 D6 D5 D4 D3 D2 D1 D0

Slave Address

R/W=1

Data from

Slave to Host

SDAO

D7 D6 D5 D4 D3 D2 D1 D0

Figure 19. I²C interface Read and Write Protocol – Configuration A

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Programming (continued)

R/W

Bit

Non-Parametric

Read Cycle

Address

Pins

R/W

Bit

Address

Pins

SDAI

D7 D6 D5 D4 D3 D2 D1 D0

A4 A3 A2 A1

R/W

C5 C4 C3 C2

A4 A3 A2 A1

R/W

D7 D6 D5 D4 D3 D2 D1 D0

Command Code

Slave Address

R/W=0

Slave Address

R/W=1

Port 4-1 Data from

Slave to Host

Port 8-5 Data from

Slave to Host

SDAO

D7 D6 D5 D4 D3 D2 D1 D0

R/W

Bit

Address

Pins

Address

Pins

R/W

Bit

Parametric

Read Cycle

R/W

A4 A3 A2 A1 0

D7 D6 D5 D4 D3 D2 D1 D0

A4 A3 A2 A1

R/W

C5 C4 C3 C2

SDAI

Command Code

Port 4-1

LSByte Data from

Slave to Host

...

Slave Address

R/W=0

Slave Address

R/W=1

Port 4-1

MSByte Data from

Slave to Host

D7 D6 D5 D4 D3 D2 D1 D0

SDAO

D7 D6 D5 D4 D3 D2 D1 D0

SDAI

Port 8-5

LSByte Data from

Slave to Host

Port 8-5

MSByte Data from

Slave to Host

...

D7 D6 D5 D4 D3 D2 D1 D0

SDAO

R/W

Bit

Address

Pins

Write Cycle

SDAI

A4 A3 A2 A1

R/W

D7 D6 D5 D4 D3 D2 D1 D0

Slave Address

R/W=0

Port 4-1 Data from

Host to Slave

Port 8-5 Data from

Host to Slave

Command Code

SDAO

Figure 20. I²C interface Read and Write Protocol – Configuration B

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8.6 Register Maps

8.6.1 Complete Register Set

Table 1. Main Registers

Command Name

Data

Byte

Cmd

Code

I²C

R/W

RST State

Bits Description

INTERRUPTS

00h

INTERRUPT

1000,0000b⁽¹⁾

1000,0000b

SUPF

STRTF

STMSK

IFAULT

IFMSK

CLASC

CLMSK

DETC

DISF

PGC

PEC

01h

INTERRUPT MASK

R/W

SUMSK

DEMSK

DIMSK

PGMSK

PEMSK

EVENT

02h

CoR

Power Good status change

Power Enable status change

POWER EVENT

0000,0000b

0111,0000b⁽²⁾

03h

PGC4

CLSC4

DISF4

PGC3

PGC2

CLSC2

DISF2

PGC1

CLSC1

DISF1

PEC4

DETC4

ICUT4

PEC3

PEC2

Detection

DETC2

PEC1

DETC1

ICUT1

04h

Classification

CLSC3

DETECTION EVENT

FAULT EVENT

05h

06h

CoR

DETC3

Disconnect occurred

DISF3

ILIM fault occurred

ICUT fault occurred

07h

CoR

ICUT3

ICUT2

08h

START fault occurred

START/ILIM EVENT

SUPPLY EVENT

09h

CoR

ILIM4

TSD

ILIM3

ILIM2

ILIM1

VPUV

STRT4

Rsvd

STRT3

STRT2

STRT1

Rsvd

0Ah

VDUV

VDWRN

Rsvd

0Bh

CoR

STATUS

0Ch

0Dh

0Eh

PORT 1 STATUS

PORT 2 STATUS

PORT 3 STATUS

PORT 4 STATUS

POWER STATUS

PIN STATUS

0000,0000b

0,A[4:0],0,0

Rsvd

PG4

CLASS Port 1

CLASS Port 2

CLASS Port 3

CLASS Port 4

PG2

DETECT Port 1

DETECT Port 2

DETECT Port 3

DETECT Port 4

0Fh

10h

PG3

PG1

PE4

PE3

PE2

PE1

11h

Rsvd

SLA4

SLA3

SLA2

SLA1

SLA0

Rsvd

CONFIGURATION

12h

13h

OPERATING MODE

R/W

0000,0000b

Port 4 Mode

Port 3 Mode

Port 2 Mode

Port 1 Mode

DISCONNECT ENABLE

Rsvd

CLE4

OSS4

Rsvd

CLE3

OSS3

Rsvd

CLE2

OSS2

Rsvd

CLE1

OSS1

DCDE4

DETE4

DCUT4

DCDE3

DETE3

DCUT3

DCDE2

DETE2

DCUT2

DCDE1

DETE1

DCUT1

DETECT/CLASS

ENABLE

14h

R/W

0000,0000b

15h

16h

17h

PWRPR/ICUT DISABLE

TIMING CONFIG

R/W

0000,0000b

1000,0000b

TLIM

TSTART

TOVLD

TMPDO

Rsvd

GENERAL MASK

INTEN

Rsvd

nbitACC

MbitPrty

CLCHE

DECHE

(1) SUPF bit reset state shown is at Power up only

(2) VDUV, VPUV and VDWRN bits reset state shown is at Power up only

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ZHCSGR0A –FEBRUARY 2015–REVISED AUGUST 2017

Table 1. Main Registers (continued)

Command Name

Data

Byte

Cmd

Code

I²C

R/W

RST State

Bits Description

PUSH BUTTONS

18h

19h

1Ah

DETECT/CLASS Restart

0000,0000b

RCL4

POFF4

CLRAIN

RCL3

POFF3

CLINP

RCL2

POFF2

Rsvd

RCL1

POFF1

RESAL

RDET4

RDET3

PWON3

RESP3

RDET2

PWON2

RESP2

RDET1

PWON1

RESP1

POWER ENABLE

RESET

PWON4

RESP4

GENERAL/SPECIALIZED

1Bh

1Ch

1Eh

1Fh

23h

24h

25h

CoR

R/W

Mf[4:0],IC[2:0]

0000,0000b

1111,1111b

0000,0000b

MFR ID

Reserved

IC Version

Reserved

POLICE 21 CONFIG

POLICE 43 CONFIG

IEEE Power Enable

POLICE Port 2

POLICE Port 4

T2PON3

POLICE Port 1

POLICE Port 3

T1PON3 T1PON2

T2PON4

T2PON2

T2PON1

T1PON4

T1PON1

Power-on FAULT

RE-MAPPING

0000,0000b

PF Port 4

PF Port 3

PF Port 2

PF Port 1

CoR

Physical re-map Logical Port Physical re-map Logical Port

26h

27h

28h

R/W

1110,0100b

0000,0000b

Physical re-map Logical Port 4

Physical re-map Logical Port 1

Multi-bit Power Priority

Rsvd

Port 2

Rsvd

Port 1

Port 3

Multi-bit Power Priority

Port 4

Rsvd

29h-2Bh

2Ch

Reserved

R/W

0000,0000b

Rsvd

TEMPERATURE

Temperature (bits 7 to 0)

Input Voltage: LSByte

2Eh

INPUT VOLTAGE

2Fh

Rsvd

Input Voltage: MSByte (bits 13 to 8)

EXTENDED REGISTER SET – PORT PARAMETRIC MEASUREMENT

30h

31h

32h

33h

0000,0000b

Port 1 Current: LSByte

Port 1 Current: MSByte (bits 13 to 8)

Port 1 Voltage: LSByte

Port 1 Voltage: MSByte (bits 13 to 8)

PORT 1 CURRENT

PORT 1 VOLTAGE

Rsvd

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Table 2. Main Registers

Command Name

Cmd

Code

Data

Byte

I²C R/W

RST State

Bits Description

34h

35h

36h

37h

38h

39h

3Ah

3Bh

3Ch

3Dh

3Eh

3Fh

0000,0000b

Port 2 Current: LSByte

PORT 2 CURRENT

PORT 2 VOLTAGE

PORT 3 CURRENT

PORT 3 VOLTAGE

PORT 4 CURRENT

PORT 4 VOLTAGE

Rsvd

PoEP4

Rsvd

PoEP3

Port 2 Current: MSByte (bits 13 to 8)

Port 2 Voltage: LSByte

Port 2 Voltage: MSByte (bits 13 to 8)

Port 3 current: LSByte

Port 3 Current: MSByte (bits 13 to 8)

Port 3 Voltage: LSByte

Port 3 Voltage: MSByte (bits 13 to 8)

Port 4 current: LSByte

Port 4 Current: MSByte (bits 13 to 8)

Port 4 Voltage: LSByte

Port 4 Voltage: MSByte (bits 13 to 8)

CONFIGURATION/OTHERS

40h

41h

42h

43h

PoE PLUS

R/W

0000,0000b

RRRR,RRRRb

0001,0110b

110,sr[4:0]

PoEP2

Rsvd

PoEP1

Rsvd

TPON

WDS

FIRMWARE REVISION

I2C WATCHDOG

DEVICE ID

Firmware Revision

R/W

Rsvd

Watchdog Disable

Silicon Revision number

Device ID number

PORT SIGNATURE MEASUREMENTS

P1 DETECT

44h

0000,0000b

Port 1 Resistance

Port 2 Resistance

Port 3 Resistance

RESISTANCE

P2 DETECT

45h

RESISTANCE

P3 DETECT

46h

RESISTANCE

P4 DETECT

47h

0000,0000b

Port 4 Resistance

Reserved

RESISTANCE

48h-6Fh Reserved

R/W

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Table 3. Registers Configuration A vs B

Cmd

Code

Bits Description

Configuration A

Configuration B

00h

01h

02h

03h

04h

05h

06h

07h

08h

09h

0Ah

0Bh

0Ch

0Dh

0Eh

0Fh

10h

INTERRUPT

INT bits P1-4, P5-8

MSK bits P1-4, P5-8

Separate mask and interrupt result per group of 4 ports.

The Supply event bit is repeated twice.

INTERRUPT MASK

POWER EVENT

DETECTION EVENT

FAULT EVENT

PGC_PEC P4-1, P8-5

CLS_DET P4-1, P8-5

DIS_ICUT P4-1, P8-5

ILIM_STR P4-1, P8-5

TSD, VDUV, VDUW, VPUV

Separate event byte per group of 4 ports.

START/ILIM EVENT

SUPPLY EVENT

Both 8-bit registers (port 1 to 4 and port 5 to 8) must show the same result.

Clearing at least one VPUV/VDUV also clears the other one.

PORT 1 STATUS

PORT 2 STATUS

PORT 3 STATUS

PORT 4 STATUS

POWER STATUS

CLS&DET1_CLS&DET5

CLS&DET2_CLS&DET6

CLS&DET3_CLS&DET7

CLS&DET4_CLS&DET8

PG_PE P4-1, P8-5

Separate Status byte per port

Separate status byte per group of 4 ports

Both 8-bit registers (port 1 to 4 and port 5 to 8) must show

the same result, except that A0 = 0 (port 1 to 4) or 1 (port 5

to 8).

Both 8-bit registers (port 1 to 4 and port 5 to 8) must show

the same result, including A0 = 0.

11h

PIN STATUS

A4-A1,A0

12h

13h

14h

15h

OPERATING MODE

MODE P4-1, P8-5

Separate Mode byte per group of 4 ports.

DISCONNECT ENABLE

DETECT/CLASS ENABLE

PWRPR/ICUT DISABLE

DCDE P4-1, P8-5

Separate DC disconnect enable byte per group of 4 ports.

Separate Detect/Class Enable byte per group of 4 ports.

Separate OSS/DCUT byte per group of 4 ports.

CLE_DETE P4-1, P8-5

OSS_DCUT P4-1, P8-5

TLIM_TSTRT_TOVLD_TMPDO P4-1,

P8-5

16h

TIMING CONFIG

Separate Timing byte per group of 4 ports.

Separate byte per group of 4 ports.

n-bit access: Setting this in at least one of the virtual quad register space is enough to enter Config B mode. To go back to

config A, clear both.

17h

GENERAL MASK

P4-1, P8-5 including n-bit access

MbitPrty: Setting this in at least one of the virtual quad register space is enough to enter 3-bit shutdown priority. To go back

to 1-bit shutdown, clear both MbitPrty bits.

18h

19h

DETECT/CLASS Restart

POWER ENABLE

RCL_RDET P4-1, P8-5

POF_PWON P4-1, P8-5

Separate DET/CL RST byte per group of 4 ports

Separate POF/PWON byte per group of 4 ports

Separate byte per group of 4 ports, Clear Int pin and Clear All Separate byte per group of 4 ports. However, if any of the

int.

following bit is set for one 4-port group, the corresponding

action is applied to both 4-port groups: Reset IC, Clear Int

pin, and Clear All Int.

1Ah

1Bh

RESET

P4-1, P8-5

However, If at least one of the IC reset bits is set – the whole

chip has a POR.

Both 8-bit registers (port 1 to 4 and port 5 to 8) must show the same result unless modified through I²C.

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Table 3. Registers Configuration A vs B (continued)

Cmd

Code

Bits Description

Configuration A

Configuration B

1Eh

1Fh

23h

24h

25h

POLICE 21 CONFIG

POLICE 43 CONFIG

IEEE Power Enable

POL2&1, POL6&5

POL4&3, POL8&7

T2P_T1P P4-1, P8-5

Separate Policing byte per group of 2 ports.

Separate IEEE Power Enable byte per group of 2 ports

Separate Power-on FAULT byte per group of 4 ports

Separate Remapping byte per group of 4 ports.

Power-on FAULT

PF P4-1, P8-5

26h

PORT REMAPPING

TEMPERATURE

Logical P4-1, P8-5

TEMP P1-4, P5-8

Reinitialized only if POR or RESET pin. Kept unchanged if 0x1A IC reset or CPU watchdog reset.

2Ch

2Eh

2Fh

Both 8-bit registers (port 1 to 4 and port 5 to 8) must show the same result.

INPUT VOLTAGE

VPWR P1-4, P5-8

Both 8-bit registers (port 1 to 4 and port 5 to 8) must show the same result.

Separate 2-byte per group of 4 ports.

30h

Separate 2-byte per group of 4 ports

2-byte Read at 0x30 gives I1

4-byte Read at 0x30 gives I1, I5.

PORT 1 CURRENT

I1, I5

31h

32h

33h

34h

35h

36h

37h

38h

39h

3Ah

3Bh

3Ch

3Dh

3Eh

3Fh

40h

41h

N/A

2-byte Read at 0x31 gives I5.

2-byte Read at 0x32 gives V1

4-byte Read at 0x32 gives V1, V5.

Separate 2-byte per group of 4 ports

PORT 1 VOLTAGE

PORT 2 CURRENT

PORT 2 VOLTAGE

PORT 3 CURRENT

PORT 3 VOLTAGE

PORT 4 CURRENT

PORT 4 VOLTAGE

V1, V5

I2, I6

N/A

2-byte Read at 0x33 gives V5.

2-byte Read at 0x34 gives I2

4-byte Read at 0x34 gives I2, I6.

Separate 2-byte per group of 4 ports

N/A

2-byte Read at 0x35 gives I6.

2-byte Read at 0x36 gives V2

4-byte Read at 0x36 gives V2, V6.

Separate 2-byte per group of 4 ports

V2, V6

I3, I7

N/A

2-byte Read at 0x37 gives V6.

2-byte Read at 0x38 gives I3

4-byte Read at 0x38 gives I3, I7.

Separate 2-byte per group of 4 ports

N/A

2-byte Read at 0x39 gives I7.

2-byte Read at 0x3A gives V3

4-byte Read at 0x3A gives V3, V7.

Separate 2-byte per group of 4 ports

V3, V7

I4, I8

N/A

2-byte Read at 0x3B gives V7.

2-byte Read at 0x3C gives I4

4-byte Read at 0x3C gives I4, I8.

Separate 2-byte per group of 4 ports

N/A

2-byte Read at 0x3D gives I8.

2-byte Read at 0x3E gives V4

4-byte Read at 0x3E gives V4, V8.

Separate 2-byte per group of 4 ports

V4, V8

N/A

2-byte Read at 0x3F gives V8.

TPON setting: separate setting per group of 4 ports.

Separate PoEP config byte per group of 4 ports.

PoE PLUS

PoEP_TPON, P4-1, P8-5

FRV P1-4, P5-8

FIRMWARE REVISION

Both 8-bit registers (port 1 to 4 and port 5 to 8) must show the same result.

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ZHCSGR0A –FEBRUARY 2015–REVISED AUGUST 2017

Table 3. Registers Configuration A vs B (continued)

Cmd

Code

Bits Description

Configuration A

Configuration B

IWD3-0: if at least one of the two 4-port settings is different than 1011b, the watchdog is enabled for all 8 ports.

WDS: Both 8-bit registers (port 1 to 4 and port 5 to 8) must show the same WDS result. Each WDS bit needs to be cleared

individually through I²C.

42h

I2C WATCHDOG

P1-4, P5-8

Both 8-bit registers (port 1 to 4 and port 5 to 8) must show the same result unless modified through I²C.

43h

44h

45h

46h

47h

DEVICE ID

DID_SR P1-4, P5-8

RDET1, RDET5

RDET2, RDET6

RDET3, RDET7

RDET4, RDET8

PORT 1 RESISTANCE

PORT 2 RESISTANCE

PORT 3 RESISTANCE

PORT 4 RESISTANCE

Separate byte per port.

Detection resistance always updated, detection good or bad.

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8.6.2 INTERRUPT Register

COMMAND = 00h with 1 Data Byte, Read only

Active high, each bit corresponds to a particular event that occurred. Each bit can be individually reset by doing a

read at the corresponding event register address, or by setting bit 7 of Reset register.

Any active bit of Interrupt register activates the INT output if its corresponding Mask bit in INTERRUPT Mask

Figure 21. INTERRUPT Register Format

SUPF

R-1

STRTF

R-0

IFAULT

R-0

CLASC

R-0

DETC

R-0

DISF

R-0

PGC

R-0

PEC

R-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 4. INTERRUPT Register Field Descriptions

Bit

Field

Type Reset Description

SUPF

Indicates that a Supply Event Fault occurred

SUPF = TSD || VDUV || VPUV

1 = At least one Supply Event Fault occurred

0 = No such event occurred

STRTF

IFAULT

CLASC

DETC

DISF

Indicates that a t_STARTFault occurred on at least one port.

STRTF = STRT1 || STRT2 || STRT3 || STRT4

1 = t_STARTFault occurred for at least one port

0 = No t_STARTFault occurred

Indicates that a t_OVLDor t_LIMFault occurred on at least one port.

IFAULT = ICUT1 || ICUT2 || ICUT3 || ICUT4 || ILIM1 || ILIM2 || ILIM3 || ILIM4

1 = t_OVLDand/or t_LIMFault occurred for at least one port

0 = No t_OVLDnor t_LIMFault occurred

Indicates that at least one classification cycle occurred on at least one port

CLASC = CLSC1 || CLSC2 || CLSC3 || CLSC4

1 = At least one classification cycle occurred for at least one port

0 = No classification cycle occurred

Indicates that at least one detection cycle occurred on at least one port

DETC = DETC1 || DETC2 || DETC3 || DETC4

1 = At least one detection cycle occurred for at least one port

0 = No detection cycle occurred

Indicates that a disconnect event occurred on at least one port.

DISF = DISF1 || DISF2 || DISF3 || DISF4

1 = Disconnect event occurred for at least one port

0 = No disconnect event occurred

PGC

Indicates that a power good status change occurred on at least one port.

PGC = PGC1 || PGC2 || PGC3 || PGC4

1 = Power good status change occurred on at least one port

0 = No power good status change occurred

PEC

Indicates that a power enable status change occurred on at least one port

PEC = PEC1 || PEC2 || PEC3 || PEC4

1 = Power enable status change occurred on at least one port

0 = No power enable status change occurred

TPS2388

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ZHCSGR0A –FEBRUARY 2015–REVISED AUGUST 2017

8.6.3 INTERRUPT MASK Register

COMMAND = 01h with 1 Data Byte, Read/Write

Each bit corresponds to a particular event or fault as defined in the Interrupt register.

Writing a 0 into a bit will mask the corresponding event/fault from activating the INT output.

Note that the bits of the Interrupt register always change state according to events or faults, regardless of the

state of the state of the Interrupt Mask register.

Note that the INTEN bit of the General Mask register must also be set in order to allow an event to activate the

INT output.

Figure 22. INTERRUPT MASK Register Format

SUMSK

R/W-1

STMSK

R/W-0

IFMSK

R/W-0

CLMSK

R/W-0

DEMSK

R/W-0

DIMSK

R/W-0

PGMSK

R/W-0

PEMSK

R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 5. INTERRUPT MASK Register Field Descriptions

Bit

Field

Type Reset Description

SUMSK

R/W

Supply Event Fault mask bit.

1 = Supply Event Fault will activate the INT output.

0 = Supply Event Fault will have no impact on INT output.

t_STARTFault mask bit.

STMSK

IFMSK

1 = t_STARTFault will activate the INT output.

0 = t_STARTFault will have no impact on INT output.

tOVLD or LIM Fault mask bit.

1 = t_OVLDand/or t_LIMFault occurrence will activate the INT output

0 = t_OVLDand/or t_LIMFault occurrence will have no impact on INT output

Classification cycle mask bit.

CLMSK

DEMSK

DIMSK

PGMSK

PEMSK

1 = Classification cycle occurrence will activate the INT output.

0 = Classification cycle occurrence will have no impact on INT output.

Detection cycle mask bit.

1 = Detection cycle occurrence will activate the INT output.

0 = Detection cycle occurrence will have no impact on INT output.

Disconnect event mask bit.

1 = Disconnect event occurrence will activate th INT output.

0 = Disconnect event occurrence will have no impact on INT output.

Power good status change mask bit.

1 = Power good status change will activate the INT output.

0 = Power good status change will have no impact on INT output.

Power enable status change mask bit.

1 = Power enable status change will activate the INT output.

0 = Power enable status change will have no impact on INT output.

SPACE

NOTE

If SUMSK = 0, a VPWR undervoltage Event Fault (VPUV) will also not shut off ports, as

long as VPWR is above the VPWR UVLO threshold.

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8.6.4 POWER EVENT Register

COMMAND = 02h with 1 Data Byte, Read only

COMMAND = 03h with 1 Data Byte, Clear on Read

Active high, each bit corresponds to a particular event that occurred.

Each bit xxx1-4 represents an individual port.

A read at each location (02h or 03h) returns the same register data with the exception that the Clear on Read

command clears all bits of the register.

If this register is causing the INT pin to be activated, this Clear on Read will release the INT pin.

Any active bit will have an impact on the Interrupt register as indicated in the Interrupt register description.

Figure 23. POWER EVENT Register Format

PGC4

R-0

PGC3

R-0

PGC2

R-0

PGC1

R-0

PEC4

R-0

PEC3

R-0

PEC2

R-0

PEC1

R-0

CR-0

LEGEND: R/W = Read/Write; R = Read only; ; CR = Clear on Read, -n = value after reset

Table 6. POWER EVENT Register Field Descriptions

Bit

Field

Type Reset Description

7–4

PGC4–PGC1

R or

Indicates that a power good status change occurred.

1 = Power good status change occurred

0 = No power good status change occurred

Indicates that a power enable status change occurred.

1 = Power enable status change occurred

3–0

PEC4–PEC1

R or

0 = No power enable status change occurred

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8.6.5 DETECTION EVENT Register

COMMAND = 04h with 1 Data Byte, Read only

COMMAND = 05h with 1 Data Byte, Clear on Read

Active high, each bit corresponds to a particular event that occurred.

Each bit xxx1-4 represents an individual port.

A read at each location (04h or 05h) returns the same register data with the exception that the Clear on Read

command clears all bits of the register. These bits are cleared when port n is turned off.

If this register is causing the INT pin to be activated, this Clear on Read will release the INT pin.

Any active bit will have an impact on the Interrupt register as indicated in the Interrupt register description.

Figure 24. DETECTION EVENT Register Format

CLSC4

R-0

CLSC3

R-0

CLSC2

R-0

CLSC1

R-0

DETC4

R-0

DETC3

R-0

DETC2

R-0

DETC1

R-0

CR-0

LEGEND: R/W = Read/Write; R = Read only; ; CR = Clear on Read, -n = value after reset

Table 7. DETECTION EVENT Register Field Descriptions

Bit

Field

Type Reset Description

7–4

CLSC4–CLSC1

R or

Indicates that at least one classification cycle occurred if the CLCHE bit in General Mask

set.

1 = At least one classification cycle occurred (if CLCHE = 0) or a change of class

occurred (CLCHE = 1)

0 = No classification cycle occurred (if CLCHE = 0) or no change of class occurred

(CLCHE = 1)

3–0

DETC4–DETC1

R or

Indicates that at least one detection cycle occurred if the DECHE bit in General Mask

bit is set.

1 = At least one detection cycle occurred (if DECHE = 0) or a change in detection

occurred (DECHE = 1)

0 = No detection cycle occurred (if DECHE = 0) or no change in detection occurred

(DECHE = 1)

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8.6.6 FAULT EVENT Register

COMMAND = 06h with 1 Data Byte, Read only

COMMAND = 07h with 1 Data Byte, Clear on Read

Active high, each bit corresponds to a particular event that occurred.

Each bit xxx1-4 represents an individual port.

A read at each location (06h or 07h) returns the same register data with the exception that the Clear on Read

command clears all bits of the register. These bits are cleared when port n is turned off.

If this register is causing the INT pin to be activated, this Clear on Read will release the INT pin.

Any active bit will have an impact on the Interrupt register as indicated in the Interrupt register description.

Figure 25. FAULT EVENT Register Format

DISF4

R-0

DISF3

R-0

DISF2

R-0

DISF1

R-0

ICUT4

R-0

ICUT3

R-0

ICUT2

R-0

ICUT1

R-0

CR-0

LEGEND: R/W = Read/Write; R = Read only; ; CR = Clear on Read, -n = value after reset

Table 8. FAULT EVENT Register Field Descriptions

Bit

Field

Type Reset Description

7–4

DISF4–DISF1

R or

Indicates that a disconnect event occurred.

1 = Disconnect event occurred

0 = No disconnect event occurred

Indicates that a t_OVLDFault occurred.

1 = t_OVLDFault occurred

3–0

ICUT4–ICUT1

R or

0 = No t_OVLDFault occurred

Note that if ICUT is disabled for a port, this port will not be automatically turned off during an ICUT fault

condition. However, the ICUT fault flag will still be operational, with a fault timeout equal to t_LIM/ 2.

Also, if a Clear on Read is done at the Fault Event register, not only the ICUTn bit is reset, but the associated

port ICUT counter is also reset.

Note that this has no impact on TLIM counter at all.

In any other case, ICUT fault is related to TOVLD fault timer as usual and there is no counter reset during clear

on read operation.

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8.6.7 START/ILIM EVENT Register

COMMAND = 08h with 1 Data Byte, Read only

COMMAND = 09h with 1 Data Byte, Clear on Read

Active high, each bit corresponds to a particular event that occurred.

Each bit xxx1-4 represents an individual port.

A read at each location (08h or 09h) returns the same register data with the exception that the Clear on Read

command clears all bits of the register. These bits are cleared when port n is turned off.

If this register is causing the INT pin to be activated, this Clear on Read will release the INT pin.

Any active bit will have an impact on the Interrupt register as indicated in the Interrupt register description.

Note: When a Start Fault is reported after the IEEE Power Enable command is used, if the PECn bit in Power

Event register is set, then there is an Inrush fault. If PECn bit is not set, then the Power-On Fault register

indicates the cause of the fault.

Figure 26. START/ILIM EVENT Register Format

ILIM4

R-0

ILIM3

R-0

ILIM2

R-0

ILIM1

R-0

STRT4

R-0

STRT3

R-0

STRT2

R-0

STRT1

R-0

CR-0

LEGEND: R/W = Read/Write; R = Read only; ; CR = Clear on Read, -n = value after reset

Table 9. START/ILIM EVENT Register Field Descriptions

Bit

Field

Type Reset Description

7–4

ILIM4–ILIM1

R or

Indicates that a t_LIMfault occurred, which means the port has limited its output current to

I_LIMor the folded back I_LIMfor more than t_LIM

1 = t_LIMfault occurred

0 = No t_LIMfault occurred

3–0

STRT4–STRT1

R or

Indicates that a t_STARTfault occurred at port turn on. Also indicates if a class or detection

error occurred during a port turn on using the IEEE Power Enable command.

1 = t_STARTfault or class/detect error occurred

0 = No t_STARTfault or class/detect error occurred

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8.6.8 SUPPLY EVENT Register

COMMAND = 0Ah with 1 Data Byte, Read only

COMMAND = 0Bh with 1 Data Byte, Clear on Read

Active high, each bit corresponds to a particular event that occurred.

Each bit D3, D2, D1, and D0 are reserved for future use.

A read at each location (0Ah or 0Bh) returns the same register data with the exception that the Clear on Read

command clears all bits of the register.

If this register is causing the INT pin to be activated, this Clear on Read will release the INT pin.

Any active bit will have an impact on the Interrupt register as indicated in the Interrupt register description.

Figure 27. SUPPLY EVENT Register Format

TSD

VDUV

VDWRN

VPUV

–

LEGEND: R/W = Read/Write; R = Read only; ; CR = Clear on Read, -n = value after reset

Table 10. SUPPLY EVENT Register Field Descriptions

Bit

Field

Type

POR Description

TSD

R or

Indicates that a thermal shutdown occurred. When there is thermal shutdown, all ports are

turned off and are put in OFF mode. The TPS2388 internal circuitry continues to operate

however, including the A/D converters. Note that at as soon as the internal temperature has

decreased below the low threshold, the ports can be turned back ON regardless of the

status of the TSD bit.

1 = Thermal shutdown occurred

0 = No thermal shutdown occurred

VDUV

R or

Indicates that a VDD UVLO occurred.

1 = VDD UVLO occurred

0 = No VDD UVLO occurred

VDWRN

VPUV

R or

Indicates that the VDD has fallen under the UVLO warning threshold.

1 = VDD UV Warning occurred

0 = No VDD UV warning occurred

R or

Indicates Indicates that a VPWR undervoltage occurred.

1 = VPWR undervoltage occurred

0 = No VPWR undervoltage occurred

Note: Pulling RESET input low will not clear VDUV or VPUV.

When VPWR undervoltage occurs, all ports are shut off if SUMSK = 1. If VPWR UVLO or VDD UVLO occurs,

there is power-on reset. Note also that turning OFF a port when VPWR undervoltage occurs also clears the

corresponding bits in Fault Event register (DISFn, ICUTn), Start Event register (STRTn), Port n Status register

(CLASS Pn, DETECT Pn), DETECT/CLASS ENABLE register (CLEn, DETEn) and Power-on Fault register

(PFn). The corresponding PGCn and PECn bits of Power Event register will also be set if there is a change. The

corresponding PEn and PGn bits of Power Status Register are also updated accordingly.

NOTE

A clear on Read will not effectively clear VDUV bit as long as the VPWR undervoltage

condition is maintained.

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NOTE

If SUMSK = 0, a VPWR undervoltage Event Fault (VPUV) will not shut off ports, as long

as VPWR is above the VPWR UVLO threshold.

NOTE

During VPWR undervoltage, the Detection Event register (CLSCn, DETCn) is not cleared,

unless VPWR also falls below the VPWR UVLO falling threshold.

NOTE

If VPWR UVLO or VDD UVLO occurs, the I²C interface stops operating, and SDAO is

forced low.

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8.6.9 PORT 1 STATUS Register

COMMAND = 0Ch with 1 Data Byte, Read Only

Figure 28. PORT 1 STATUS Register Format

–

CLASS P1

R-0

DETECT P1

R-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

8.6.10 PORT 2 STATUS Register

COMMAND = 0Dh with 1 Data Byte, Read Only

Figure 29. PORT 2 STATUS Register Format

–

CLASS P2

R-0

DETECT P2

R-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

8.6.11 PORT 3 STATUS Register

COMMAND = 0Eh with 1 Data Byte, Read Only

Figure 30. PORT 3 STATUS Register Format

–

CLASS P3

R-0

DETECT P3

R-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

8.6.12 PORT 4 STATUS Register

COMMAND = 0Fh with 1 Data Byte, Read Only

Figure 31. PORT 4 STATUS Register Format

–

CLASS P4

R-0

DETECT P4

R-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Bit Descriptions: These bits represent the most recent classification and detection results for port n. These bits

are cleared when port n is turned off.

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Table 11. PORT STATUS Register Field Descriptions

Type Reset

Description

–

Reserved

6–4 CLASS Pn

Most recent classification result on port n.

The selection is as following:

CLASS Pn

Class Status

Unknown

Class 1

Class 2

Class 3

Class 4

Reserved – read as Class 0

Class 0

Overcurrent

3–0 DETECT Pn

Most recent detection result on port n.

The selection is as following:

DETECT Pn

Class Status

Unknown

Short-circuit

Reserved

Too Low

Valid

Too High

Open Circuit

Reserved

MOSFET fault

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8.6.13 POWER STATUS Register

COMMAND = 10h with 1 Data Byte, Read only

Each bit represents the actual power status of a port.

Each bit xx1-4 represents an individual port..

These bits are cleared when port n is turned off, including if the turn off is caused by a fault condition.

Figure 32. POWER STATUS Register Format

PG4

R-0

PG3

R-0

PG2

R-0

PG1

R-0

PE4

R-0

PE3

R-0

PE2

R-0

PE1

R-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 12. POWER STATUS Register Field Descriptions

Bit

Field

Type Reset Description

7–4

PG4–PG1

Each bit, when at 1, indicates that the port is on and that the voltage at DRAINn pin has

gone below the power good threshold during the port turn on.

These bits are latched high once the turn on is complete and can only be cleared when the

port is turned off or at RESET/POR.

1 = Power is good

0 = Power is not good

3–0

PE4–PE1

Each bit indicates the ON/OFF state of the corresponding port.

1 = Port is on

0 = Port is off

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8.6.14 Pin Status Register

COMMAND = 11h with 1 Data Byte, Read Only

Figure 33. Pin Status Register Format

SLA4

A4 pin

SLA3

A3 pin

SLA2

A2 pin

SLA1

A1 pin

SLA0

0/1⁽¹⁾

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

(1) If Configuration A, it can be 0 or 1. If configuration B, it is 0.

Table 13. Pin Status Register Field Descriptions

Bit

Field

Type Reset Description

6-2

SLA4-SLA0

See I²C device address, as defined while using pins A4-A1. SLA0 is internally defined as 0 or 1.

above

BINARY DEVICE ADDRESS

ADDRESS PINS

DESCRIPTION

Broadcast access

Slave 0

0/1

GND

HIGH

GND

HIGH

GND

HIGH

GND

HIGH

GND

HIGH

GND

HIGH

GND

HIGH

GND

HIGH

GND

HIGH

GND

HIGH

GND

HIGH

GND

HIGH

GND

HIGH

GND

HIGH

GND

HIGH

Slave 15

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8.6.15 OPERATING MODE Register

COMMAND = 12h with 1 Data Byte, Read/Write

Figure 34. OPERATING MODE Register Format

P4M1

R/W-0

P4M0

R/W-0

P3M1

R/W-0

P3M0

R/W-0

P2M1

R/W-0

P2M0

R/W-0

P1M1

R/W-0

P1M0

R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 14. OPERATING MODE Register Field Descriptions

Bit

Field

Type

Reset

Description

Each pair of bits configures the operating mode per port.

The selection is as following:

P4M1–P4M0

P3M1–P3M0

P2M1–P2M0

P1M1–P1M0

R/W

Operating Mode

OFF

Manual

Semiauto

In OFF mode, the port is OFF and there is no detection nor classification. In Manual mode,

there is no automatic state change. In semiauto mode, detection and class are automated but

not the port power on.

Note that while in OFF mode, the corresponding bits are cleared: Detection Event register

(CLSCn, DETCn), Fault Event register (DISFn, ICUTn), Start Event register (STRTn), Port n

Status register (CLASS Pn, DETECT Pn), Detect/Class Enable register (CLEn, DETEn) and

Power-on Fault register (PFn). The corresponding PEn and PGn bits of Power Status Register

are also updated accordingly. The corresponding PGCn and PECn bits of Power Event

Also, a change of mode from semiauto to manual mode or OFF mode will cancel any ongoing

cooldown time period.

8.6.16 DISCONNECT ENABLE Register

COMMAND = 13h with 1 Data Byte, Read/Write

Bit Descriptions: Defines the disconnect detection mechanism for each port.

Figure 35. DISCONNECT ENABLE Register Format

–

DCDE4

R/W-0

DCDE3

R/W-0

DCDE2

R/W-0

DCDE1

R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 15. DISCONNECT ENABLE Register Field Descriptions

Bit

7–4

3–0

Field

Type Reset Description

—

R/W

DCDE4–DCDE1 R/W

DC disconnect enable. DC disconnect consists in measuring the port DC current at SENn,

starting a timer (TDIS) if this current is below a threshold and turning the port off if a time-

out occurs. Also, the corresponding disconnect bit (DISFn) in the FAULT EVENT register is

set accordingly. The TDIS counter is reset each time the current goes continuously higher

than the disconnect threshold for nominally 15 msec. The counter does not decrement

below zero.

Look at the TIMING CONFIGURATION register for more details on how to define the TDIS

time period.

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8.6.17 DETECT/CLASS ENABLE Register

COMMAND = 14h with 1 Data Byte, Read/Write

Bit Descriptions:

Detection and classification enable for each port.

When in Manual mode, setting a bit means that only one cycle (detection or classification) is performed for

the corresponding port. The bit is automatically cleared by the time the cycle has been completed.

Note that similar result can be obtained by writing to the Detect/Class Restart register.

It is also cleared if a port turn off (Power Enable register) is issued.

When in semiauto mode, as long as the port is kept off, detection and classification are performed

continuously, as long as the class and detect enable bits are kept set, but the class will be done only if the

detection was valid. A Detect/Class Restart PB command can also be used to set the CLEn and DETEn bits,

if in semiauto mode.

During t_OVLD, t_LIMor t_STARTcool down cycle, any Detect/Class Enable command for that port will be delayed until

end of cool-down period. Note that at the end of cool down cycle, one or more detection/class cycles are

automatically restarted as described previously, if the class and/or detect enable bits are set.

Figure 36. DETECT/CLASS ENABLE Register Format

CLE4

R/W-0

CLE3

R/W-0

CLE2

R/W-0

CLE1

R/W-0

DETE4

R/W-0

DETE3

R/W-0

DETE2

R/W-0

DETE1

R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 16. DETECT/CLASS ENABLE Register Field Descriptions

Bit

7–4

3–0

Field

Type Reset Description

CLE4-CLE1

DETE4-DETE1

R/W

Classification enable bits.

Detection enable bits.

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8.6.18 Port Power Priority/ICUT Disable Register Name

COMMAND = 15h with 1 Data Byte, R/W

Figure 37. Port Power Priority/ICUT Disable Register Format

OSS4

R/W-0

OSS3

R/W-0

OSS2

R/W-0

OSS1

R/W-0

DCUT4

R/W-0

DCUT3

R/W-0

DCUT2

R/W-0

DCUT1

R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 17. Port Power Priority/ICUT Disable Register Field Descriptions

Bit

Field

Type

Reset Description

7–4

OSS4-OSS1

R/W

Port power priority bits, one bit per port, if 1-bit shutdown priority has been selected. It is

used to determine which port is shut down in response to an external assertion of the

OSS fast shutdown signal. The turn off procedure (including register bits clearing) is

similar to a port reset using Reset command (1Ah register), except that it does not cancel

any ongoing fault cool down time count.

1 = When the OSS signal is asserted, the corresponding port is powered off.

0 = OSS signal has no impact on the port.

3–0

DCUT4-DCUT1 R/W

ICUT disable for each port. Used to prevent removal of the associated port’s power due to

an ICUT fault, regardless of the programming status of the Timing Configuration register.

Note that there is still monitoring of ILIM faults.

1: Port’s ICUT is disabled. This means that an ICUT fault alone will not turn off this

port.

0: Port’s ICUT is enabled. This enables port turn off if there is ICUT fault.

Note that if ICUT is disabled for a port, this port will not be automatically turned off during

an ICUT fault condition. However, the ICUT fault flag will still be operational, with a fault

timeout equal to t_LIM/2.

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8.6.19 TIMING CONFIGURATION Register

COMMAND = 16h with 1 Data Byte, Read/Write

Bit Descriptions: These bits define the timing configuration for all four ports.

Note: the PGn and PEn bits (Power Status register) are cleared when there is a TLIM, TOVLD, TMPDO, or

TSTART fault condition.

Figure 38. TIMING CONFIGURATION Register Format

TLIM

TSTART

TOVLD

TMPDO

R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 18. TIMING CONFIGURATION Register Field Descriptions

Bit

Field

Type Reset

R/W 0

Description

ILIM fault timing, which is the output current limit time duration before port turn off.

7 –6 TLIM

This timer is active and increments to the settings defined below after expiration of the TSTART time

window and when the port is limiting its output current to I_LIM. If the ILIM counter is allowed to reach

the programmed time-out duration specified below, the port will be powered off. The 1-second cool

down timer is then started, and the port can not be turned-on until the counter has reached

completion.

In other circumstances (ILIM time-out has not been reached), while the port current is below I_LIM, the

same counter decrements at a rate 1/16th of the increment rate. The counter does not decrement

below zero. The ILIM counter is also cleared in the event of a port turn off due to a Power Enable or

Port Reset command, a DC disconnect event or the OSS input.

Note that in the event the TLIM setting is changed while this timer is already active for a port, this

timer is automatically reset then restarted with the new programmed time-out duration.

Note that at the end of cool down cycle, when in semiauto mode, a detection cycle is automatically

restarted if the detect enable bit is set. Also note that the cool down time count is immediately

canceled with a port reset command, or if the OFF or Manual mode is selected.

When a PoEPn bit in PoE Plus register is deasserted, the t_LIMused for the associated port is always

the nominal value (about 60 ms).

If PoEPn bit is asserted, then t_LIMfor associated port is programmable with the following selection:

TLIM

Nominal t_LIM(ms)

5-4

TSTART

R/W

START fault timing, which is the maximum allowed overcurrent time during inrush. If at the end of

TSTART period the current is still limited to I_Inrush, the port is powered off.

(or

TINRUSH)

This is followed by a 1-second cool down period, during which the port can not be turned-on

Note that at the end of cool down cycle, when in semiauto mode, a detection cycle is automatically

restarted if the class and detect enable bits are set.

Note that in the event the TSTART setting is changed while this timer is already active for a port,

this new setting is ignored and will be applied only next time the port is turned ON.

The selection is as following:

TSTART Nominal t_START(ms)

120

Reserved

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Table 18. TIMING CONFIGURATION Register Field Descriptions (continued)

Bit

Field

Type Reset

R/W 0

Description

3–2 TOVLD

ICUT fault timing, which is the overcurrent time duration before port turn off. This timer is active and

increments to the settings defined below after expiration of the TSTART time window and when the

port current meets or exceeds I_CUT, or when it is limited by the current foldback. If the ICUT counter

is allowed to reach the programmed time-out duration specified below, the port will be powered off.

The 1-second cool down timer is then started, and the port can not be turned-on until the counter

has reached completion.

In other circumstances (ICUT time-out has not been reached), while the port current is below I_CUT

the same counter decrements at a rate 1/16th of the increment rate. The counter does not

decrement below zero. The ICUT counter is also cleared in the event of a port turn off due to a

Power Enable or Port Reset command, a DC disconnect event or the OSS input

Note that in the event the TOVLD setting is changed while this timer is already active for a port, this

timer is automatically reset then restarted with the new programmed time-out duration.

Note that at the end of cool down cycle, when in semiauto mode, a detection cycle is automatically

restarted if the detect enable bit is set. Also note that the cool down time count is immediately

canceled with a port reset command, or if the OFF or Manual mode is selected.

Note that if a DCUTn bit is high in the Port Power Priority/ICUT Disable register, the ICUT fault

timing for the associated port is disabled. This means that this port will not be turned off if there is

only ICUT fault.

The selection is as following:

TOVLD

Nominal t_OVLD(ms)

120

240

1–0 TMPDO

R/W

Disconnect delay, which is the time to turn off a port once there is a disconnect condition, and if the

dc disconnect detect method has been enabled.

The TDIS counter is reset each time the current goes continuously higher than the disconnect

threshold for nominally 15 ms.

The counter does not decrement below zero.

The selection is as following:

TMPDO Nominal t_MPDO(ms)

360

180

720

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8.6.20 GENERAL MASK Register

COMMAND = 17h with 1 Data Byte, Read/Write

Figure 39. GENERAL MASK Register Format

–

INTEN

R/W-1

nbitACC

R/W-0

MbitPrty

R/W-0

CLCHE

R/W-0

DECHE

R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 19. GENERAL MASK Register Field Descriptions

Bit

Field

Type Reset Description

INTEN

R/W

INT pin mask bit. Writing a 0 will mask any bit of Interrupt register from activating the INT

output, whatever the state of the Interrupt Mask register. Note that activating INTEN has no

impact on the event registers.

1 = Any unmasked bit of Interrupt register can activate the INT output

0 = INT output cannot be activated

–

R/W

nbitACC

1 = Configuration B. This means 16-bit access with a single device address.

0 = Configuration A. This means 8-bit access, while the 8-port device is treated as 2

separate 4-port devices with 2 consecutive slave addresses.

MbitPrty

R/W

Multi Bit Priority bit. Used to select between 1-bit shutdown priority and 3-bit shutdown

priority.

1 = 3-bit shutdown priority. Register 0x27 and 0x28 need to be followed for port

priority and OSS action.

0 = 1-bit shutdown priority. Register 0x15 needs to be followed for port priority and

OSS action

Note: If the MbitPrty bit needs to be changed from 0 to 1, make sure the OSS input is in the

idle (low) state for a minimum of 200 µsec prior to setting the MbitPrty bit, to avoid any port

misbehavior related to loss of synchronization with the OSS bit stream.

CLCHE

DECHE

R/W

Class change Enable bit. When set, the CLSCn bits in Detection Event register only

indicates when the result of the most current classification operation differs from the result

of the previous one.

1 = CLSCn bit is set only when a change of class occurred for the associated port.

0 = CLSCn bit is set each time a classification cycle occurred for the associated port.

Detect Change Enable bit. When set, the DETCn bits in Detection Event register only

indicates when the result of the most current detection operation differs from the result of

the previous one.

1 = DETCn bit is set only when a change in detection occurred for the associated port.

0 = DETCn bit is set each time a detection cycle occurred for the associated port.

–

R/W

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8.6.21 DETECT/CLASS RESTART Register

COMMAND = 18h with 1 Data Byte, Write Only

Push button register.

Each bit corresponds to a particular cycle (detect or class restart) per port. Each cycle can be individually

triggered by writing a 1 at that bit location, while writing a 0 does not change anything for that event.

In Manual mode, a single cycle (detect or class restart) will be triggered while in Semiauto mode, it sets the

corresponding bit in the Detect/Class Enable register.

A Read operation will return 00h.

During t_OVLD, t_LIMor t_STARTcool down cycle, any Detect/Class Restart command for that port will be accepted but

the corresponding action will be delayed until end of cool-down period.

Figure 40. DETECT/CLASS RESTART Register Format

RCL4

W-0

RCL3

W-0

RCL2

W-0

RCL1

W-0

RDET4

W-0

RDET3

W-0

RDET2

W-0

RDET1

W-0

LEGEND: R/W = Read/Write; R = Read only; W = Write only; -n = value after reset

Table 20. DETECT/CLASS RESTART Register Field Descriptions

Bit

7–4

3–0

Field

Type Reset Description

RCL4–RCL1

RDET4–RDET1

Restart classification bit

Restart detection bits

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8.6.22 POWER ENABLE Register

COMMAND = 19h with 1 Data Byte, Write Only

Push button register.

Used to force a port(s) turn on or turn off in any mode except OFF mode. If TPON bit in the PoE Plus register is

low, or if the PSE controller is configured in Manual mode, writing a 1 at that PWONn bit location will immediately

turn on the associated port, regardless of the classification and detection status and regardless of the IEEE802.3

TPON timing specification. This is also the case if TPON is set and DETn bit is 0, in semiauto mode.

If TPON bit in the PoE Plus register is set, and DETn bit (DETECT/CLASS ENABLE register) is set and while in

semiauto mode, writing a 1 at a PWONn bit will turn on the associated port but only if the IEEE802.3 TPON

timing specification can be met and if the detection is valid (and class is valid if enabled). TPON specification is

the time from the completion of a valid detection cycle to port turn ON.

If TPON specification cannot be met, a new detection cycle is restarted, followed by a classification cycle if

enabled, at the end of which the port is turned on, but only if a valid detection is returned and the IEEE802.3

TPON specification can be met. For this case, there is no additional attempt to turn on the port until this push

button is reasserted. If the last detection result is not valid, the port is not turned on.

Note that in semiauto, as long as the port is kept off, detection and classification are performed continuously, if

the corresponding class and detect enable bits are set.

Writing a 1 at POFFn location turns off the associated port.

Note that writing a 1 at POFFn and PWONn of same port during the same write operation turns the port off.

Also note that t_OVLD, t_LIM, t_START, and disconnect events have priority over the power on command. During t_OVLD

t_LIM, or t_STARTcool down cycle, any port turn on using Power Enable command will be ignored and the port will be

kept off.

Turning OFF a port with this command also clears the corresponding bits in Detection Event register (CLSCn,

DETCn), Fault Event register (DISFn, ICUTn), Start Event register (STRTn, ILIMn), Port n Status register

(CLASS Pn, DETECT Pn), DETECT/CLASS ENABLE register (CLEn, DETEn) and Power-on Fault register

(PFn). The corresponding PGCn and PECn bits of Power Event register will also be set if there is a change. The

corresponding PEn and PGn bits of Power Status Register are also updated accordingly.

Figure 41. POWER ENABLE Register Format

POFF4

W-0

POFF3

W-0

POFF2

W-0

POFF1

W-0

PWON4

W-0

PWON3

W-0

PWON2

W-0

PWON1

W-0

LEGEND: R/W = Read/Write; R = Read only; W = Write only; -n = value after reset

Table 21. POWER ENABLE Register Field Descriptions

Bit

7–4

3–0

Field

Type Reset Description

POFF4–POFF1

PWON4–PWON1

Port power off bits

Port power on bits

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8.6.23 RESET Register

COMMAND = 1Ah with 1 Data Byte, Write Only

Push button register.

Writing a 1 at a bit location triggers an event while a 0 has no impact. Self-clearing bits.

Figure 42. RESET Register Format

–

CLRAIN

W-0

CLINP

W-0

RESAL

W-0

RESP4

W-0

RESP3

W-0

RESP2

W-0

RESP1

W-0

LEGEND: R/W = Read/Write; R = Read only; W = Write only; -n = value after reset

Table 22. RESET Register Field Descriptions

Bit

Field

Type Reset Description

CLRAIN

Clear all interrupts bit. Writing a 1 to CLRAIN clears all event registers and all bits in the

Interrupt register. It also releases the INT pin

CLINP

When set, it releases the INT pin without any impact on the Event registers nor on the

Interrupt register.

–

RESAL

Reset all bits when RESAL is set. Results in a state equivalent to a power-up reset. Note

that the VDUV and VPUV bits (Supply Event register) follow the state of VDD and VPWR

supply rails.

3–0

RESP4–RESP1

Reset port bits. Used to force an immediate port(s) turn off in any mode, by writing a 1 at

the corresponding RESPn bit location(s).

Turning OFF a port with this command also clears the corresponding bits in Detection

Event register (CLSCn, DETCn), Fault Event register (DISFn, ICUTn), Start Event register

(STRTn, ILIMn), Port n Status register (CLASS Pn, DETECT Pn), DETECT/CLASS

ENABLE register (CLEn, DETEn) and Power-on Fault register (PFn). Note that the port can

be turned back on immediately after a port reset; this means that any ongoing cool down

cycle becomes immediately terminated once a port reset is received.

The corresponding PGCn and PECn bits of Power Event register will also be set if there is

a change. The corresponding PEn and PGn bits of Power Status Register are also updated

accordingly.

8.6.24 ID Register

COMMAND = 1Bh with 1 Data Byte, Read/Write

Figure 43. ID Register Format

MFR ID

R/W-0

ICV

R/W-0

R/W-1

R/W-0

R/W-1

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 23. ID Register Field Descriptions

Bit

Field

Type Reset Description

7–3

MFR ID

R/W 01010 Manufacture Identification number (0101,0)

2–0

ICV

R/W

011b IC version number (011)

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8.6.25 Police 21 Configuration Register

COMMAND = 1Eh with 1 Data Byte, Read/Write

Replaces the ICUT mechanism. The threshold is defined with the Police bits and the PoE Plus register.

Figure 44. Police 21 Register Format

POL2_3

R/W-1

POL2_2

R/W-1

POL2_1

R/W-1

POL2_0

R/W-1

POL1_3

R/W-1

POL1_2

R/W-1

POL1_1

R/W-1

POL1_0

R/W1

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

8.6.26 Police 43 Configuration Register

COMMAND = 1Fh with 1 Data Byte, Read/Write

Replaces the ICUT mechanism. The threshold is defined with the Police bits and the PoE Plus register.

Figure 45. Police 43 Register Format

POL4_3

R/W-1

POL4_2

R/W-1

POL4_1

R/W-1

POL4_0

R/W-1

POL3_3

R/W-1

POL3_2

R/W-1

POL3_1

R/W-1

POL3_0

R/W1

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 24. Police 43 Register Field Descriptions

Bit

Field

Type Reset Description

7–0

POLn_3-

POLn_0

R/W

4-bit nibble defining I_CUTthreshold. The result varies depending on the PoE Plus port bit.

The equation defining the I_CUTthreshold is:

I_CUT= (N × IC_STEP) + IC_OFFS

Where, when assuming 0.255-Ω Rsense resistor is used:

IC_STEP= 20 mA (1 W resolution if at 50 V) when the associated port’s PoE Plus bit is 0

IC_STEP= 40 mA (2 W resolution if at 50 V)when the associated port’s PoE Plus bit is 1

and:

IC_OFFS= 20 mA when the associated port’s PoE Plus bit is 0

IC_OFFS= 320 mA (16 W if at 50 V) when the associated port’s PoE Plus bit is 1

Note:

When a PoEPn bit is set in PoE Plus register, the corresponding POLn bits are initially

changed to 0x0.

When a PoEPn bit is reset in PoE Plus register, the corresponding POLn bits are initially

changed to 0xF.

In both cases, the port police current threshold is the same value.

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8.6.27 IEEE Power Enable Register

COMMAND = 23h with 1 Data Byte, Write Only

Used to do a port(s) turn on during semiauto mode. This command is ignored if in manual mode. Note that if at

completion of this command the addressed port is not turned on, the corresponding bits in the Detect/Class

Enable register (register 14h) are being set, which means that detection and classification are performed

continuously, as long as the class and detect enable bits are kept set.

Writing a 1 at a TmPONn bit will turn on the associated port but only if the IEEE802.3 TPON timing specification

can be met. TPON specification is the time from the completion of a valid detection cycle to port turn ON.

If TPON specification cannot be met, a new detection cycle is restarted, followed by a classification cycle, at the

end of which the port is turned on, but only if a valid detection and classification is returned. For this case, there

is no additional attempt to turn on the port until this push button is reasserted.

Note that a port turn on will be performed only after both its current detection and classification cycle are

completed

Note that writing a 1 at T1PONn and T2PONn of same port during the same write operation is interpreted as a

T1PONn.

The corresponding PGCn and PECn bits of Power Event register will also be set depending on the result, while

the CLSCn and DETCn bits of Detection Event register will be set based on the result and the CLCHE and

DECHE bits in the General Mask register.

Also note that t_OVLD, t_LIM, t_START, and disconnect events are prioritary over the power on command. During t_OVLD

t_LIM, or t_STARTcool down cycle, any port turn on using IEEE Power Enable command will be ignored and the port

will be kept off.

Figure 46. IEEE Power Enable Register Format

Type 2 IEEE Power Enable Pushbutton

Type 1 IEEE Power Enable Pushbutton

T2PON4

W-0

T2PON3

W-0

T2PON2

W-0

T2PON1

W-0

T1PON4

W-0

T1PON3

W-0

T1PON2

W-0

T1PON1

W-0

LEGEND: R/W = Read/Write; R = Read only; W = Write only; -n = value after reset

Table 25. IEEE Power Enable Register Field Descriptions

Bit

Field

Type Reset Description

7–4 T2PON4–T2PON1

If class 4 is detected during the first event classification, a second event classification is

performed. If the last detection result is not valid or last classification result yields “over

current” or is different from the first classification event result, the port is not turned on, and

the STRTn bit in Start/Ilim Event register is set, while the corresponding fault code in the

Power-on Fault register is written.

When power-on is complete and if class 4 has been detected, the corresponding PoEPn bit

in PoE Plus register is set and the value of the corresponding Police Configuration register is

set to 640 mA (08h code). This is done within 5 ms of completion of inrush.

3–0 T1PON4–T1PON1

Indicates only a single-event classification is performed, even if a class 4 PD is detected.

If the last detection result is not valid or last classification result yields “over current”, the port

is not turned on, and the STRTn bit in Start/Ilim Event register is set, while the

corresponding fault code in the Power-on Fault register is written.

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8.6.28 Power-on Fault Register

COMMAND = 24h with 1 Data Byte, Read Only

COMMAND = 25h with 1 Data Byte, Clear on Read

Figure 47. Power-on Fault Register Format

PF4

PF3

PF2

PF1

R-0

CR-0

LEGEND: R/W = Read/Write; R = Read only; W = Write only; CR = Clear on Read; -n = value after reset

Table 26. Power-on Fault Register Field Descriptions

Bit Field

Type

Reset

Description

7–0 PF4–PF1

R or CR

Represents the fault status of the classification and detection for port n, following an IEEE Power

Enable command. These bits are cleared when port n is turned off.

PFn: the selection is as follows:

Fault Code

Power-on Fault Description

No fault

Invalid detection

Classification overcurrent

Classification mismatch

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8.6.29 PORT RE-MAPPING Register

COMMAND = 26h with 1 Data Byte, Read/Write

Figure 48. PORT RE-MAPPING Register Format

Physical Port # of Logical Port 4 Physical Port # of Logical Port 3 Physical Port # of Logical Port 2 Physical Port # of Logical Port 1

R/W-1 R/W-1 R/W-1 R/W-0 R/W-0 R/W-1 R/W-0 R/W-0

LEGEND: R/W = Read/Write; R = Read only; W = Write only; CR = Clear on Read; -n = value after reset

Table 27. PORT RE-MAPPING Register Field Descriptions

Bit Field

Type

Reset

Description

7–0 Physical Port

# of Logical

Port n

R/W

1/0

Used to re-map ports logically due to physical board constraints. Re-mapping is between any port

of a 4-port group (1-4, 5-8). All ports of a group of four must be in OFF mode prior to receiving the

port re-mapping command, otherwise the command will be ignored. By default there is no re-

mapping.

Each pair of bits corresponds to the logical port assigned.

The selection per port is as follows:

Re-Map

Code

Physical Port

Package Pins

Drain1,Gat1,Sen1

Drain2,Gat2,Sen2

Drain3,Gat3,Sen3

Drain4,Gat4,Sen4

When there is no re-mapping the default value of this register is 1110,0100. The 2 MSbits with a

value 11 indicate that logical port 4 is mapped onto physical port 4, the next 2 bits, 10, suggest

logical port 3 is mapped onto physical port 3 and so on.

Note: Code duplication is not allowed – that is, Same code cannot be written into the remapping

bits of more than one port – if such a value is received, it will be ignored and the chip will stay with

existing configuration.

Note: Port remapping configuration is kept unchanged if 0x1A IC reset command is received.

NOTE

After port remapping, TI recommends to do at least one

detection-classification cycle before next port turn on.

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8.6.30 Port 21 Multi Bit Priority Register

COMMAND = 27h with 1 Data Byte, Read/Write .

Figure 49. Port 21 Register Format

–

MBP2_2

R/W-0

MBP2_1

R/W-0

MBP2_0

R/W-0

MBP1_2

R/W-0

MBP1_1

R/W-0

MBP1_0

R/W–0

R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

8.6.31 Port 43 Multi Bit Priority Register

COMMAND = 28h with 1 Data Byte, Read/Write

Figure 50. Port 43 Register Format

–

MBP4_2

R/W-0

MBP4_1

R/W-0

MBP4_0

R/W-0

MBP3_2

R/W-0

MBP3_1

R/W-0

MBP3_0

R/W–0

R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 28. Port 43 Register Field Descriptions

Bit Field

Type Reset Description

R/W

7–0 MBPn_2-0

MBPn_2-0: Multi Bit Port power priority bits, three bits per port, if 3-bit shutdown priority has been

selected (MbitPrty in General Mask register is high). It is used to determine which port(s) is (are) shut

down in response to a serial shutdown code received at the OSS shutdown input. A port with 000

code has highest priority. Port priority reduces as the 3-bit value increases.

The turn off procedure (including register bits clearing) is similar to a port reset using Reset command

(1Ah register), except that it does not cancel any ongoing fault cool down time count.

The port priority is defined as followings:

OSS code ≤ MBPn_2-0 : when the OSS code is received, the corresponding port is powered off.

OSS code > MBPn_2-0 : OSS code has no impact on the port

MBPn_2-0 0x27/28

Multi Bit Priority Condition for Port Off

Highest

OSS = ‘000’

OSS = ‘000’ or ‘001’

OSS ≤ ‘010’

OSS ≤ ‘011’

OSS ≤ ‘100’

OSS = any code except ‘111’

OSS = any code

Lowest

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8.6.32 TEMPERATURE Register

COMMAND = 2Ch with 1 Data Byte, Read Only

Figure 51. TEMPERATURE Register Format

TEMP7

R-0

TEMP6

R-0

TEMP5

R-0

TEMP4

R-0

TEMP3

R-0

TEMP2

R-0

TEMP1

R-0

TEMP0

R-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 29. TEMPERATURE Register Field Descriptions

Bit

Field

Type

Reset

Description

7–0

TEMP7–TEMP0

Bit Descriptions: Data conversion result. The I²C data transmission is a 1-byte transfer.

8-bit Data conversion result of temperature, from –20°C to 125°C. The update rate is

around once per second.

The equation defining the temperature measured is:

T = –20 + N × T_STEP

Where T_STEPis defined below as well as the full scale value:

Mode

Full Scale Value

T_STEP

Any

146.2°C

0.652°C

8.6.33 INPUT VOLTAGE Register

COMMAND = 2Eh with 2 Data Byte (LSByte first, MSByte second), Read only

Figure 52. INPUT VOLTAGE Register Format

LSB:

VPWR7

R-0

VPWR6

R-0

VPWR5

R-0

VPWR4

R-0

VPWR3

R-0

VPWR2

R-0

VPWR1

R-0

VPWR0

R-0

MSB:

–

VPWR13

R-0

VPWR12

R-0

VPWR11

R-0

VPWR10

R-0

VPWR9

R-0

VPWR8

R-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 30. INPUT VOLTAGE Register Field Descriptions

Bit

Field

Type

Reset

Description

13–0 VPWR13- VPWR0

Bit Descriptions: Data conversion result. The I²C data transmission is a 2-byte transfer.

14-bit Data conversion result of input voltage.

The equation defining the voltage measured is:

V = N × V_STEP

Where V_STEPis defined below as well as the full scale value:

Mode Full Scale Value

Any 60 V

V_STEP

3.662 mV

Note that the measurement is made between VPWR and AGND.

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8.6.34 PORT 1 CURRENT Register

COMMAND = 30h with 2 Data Byte, (LSByte First, MSByte second), Read Only

Figure 53. PORT 1 CURRENT Register Format

LSB:

MSB:

I1_7

R-0

I1_6

R-0

I1_5

R-0

I1_4

R-0

I1_3

R-0

I1_2

R-0

I1_1

R-0

I1_0

R-0

–

I1_13

R-0

I1_12

R-0

I1_11

R-0

I1_10

R-0

I1_9

R-0

I1_8

R-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

8.6.35 PORT 2 CURRENT Register

COMMAND = 34h with 2 Data Byte, (LSByte First, MSByte second), Read Only

Figure 54. PORT 2 CURRENT Register Format

LSB:

MSB:

I2_7

R-0

I2_6

R-0

I2_5

R-0

I2_4

R-0

I2_3

R-0

I2_2

R-0

I2_1

R-0

I2_0

R-0

–

I2_13

R-0

I2_12

R-0

I2_11

R-0

I2_10

R-0

I2_9

R-0

I2_8

R-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

8.6.36 PORT 3 CURRENT Register

COMMAND = 38h with 2 Data Byte, (LSByte First, MSByte second), Read Only

Figure 55. PORT 3 CURRENT Register Format

LSB:

MSB:

I3_7

R-0

I3_6

R-0

I3_5

R-0

I3_4

R-0

I3_3

R-0

I3_2

R-0

I3_1

R-0

I3_0

R-0

–

I3_13

R-0

I3_12

R-0

I3_11

R-0

I3_10

R-0

I3_9

R-0

I3_8

R-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

8.6.37 PORT 4 CURRENT Register

COMMAND = 3Ch with 2 Data Byte, (LSByte First, MSByte second), Read Only

Figure 56. PORT 4 CURRENT Register Format

LSB:

MSB:

I4_7

R-0

I4_6

R-0

I4_5

R-0

I4_4

R-0

I4_3

R-0

I4_2

R-0

I4_1

R-0

I4_0

R-0

–

I4_13

R-0

I4_12

R-0

I4_11

R-0

I4_10

R-0

I4_9

R-0

I4_8

R-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

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Table 31. PORT 4 CURRENT Register Field Descriptions

Bit

Field

Type

Reset

Description

13-0 In_13- In_0

Bit Descriptions: Data conversion result. The I²C data transmission is a 2-byte transfer.

Note that the conversion is done using a TI proprietary multi-slope integrating converter.

14-bit Data conversion result of current for port n. The update rate is around once per 100 ms in

port powered state.

The equation defining the current measured is:

I = N × I_STEP

Where I_STEPis defined below as well as the full scale value, according to the operating mode:

Mode

Full Scale Value

I_STEP

Port Powered and

Classification

1 A (with 0.255 Ω

61.035 µA

Rsense)

Note: in any of the following cases, the result through I²C interface is automatically 0000

port is in OFF mode

port is OFF while in semiauto mode and detect/class is not enabled

port is OFF while in semiauto mode and detection result is incorrect

In manual mode, if detect/class has been enabled at least once, the register retains the result of

the last measurement

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8.6.38 PORT 1 VOLTAGE Register

COMMAND = 32h with 2 Data Byte, (LSByte First, MSByte second), Read Only

Figure 57. PORT 1 VOLTAGE Register Format

LSB:

V1_7

R-0

V1_6

R-0

V1_5

R-0

V1_4

R-0

V1_3

R-0

V1_2

R-0

V1_1

R-0

V1_0

R-0

MSB:

–

V1_13

R-0

V1_12

R-0

V1_11

R-0

V1_10

R-0

V1_9

R-0

V1_8

R-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

8.6.39 PORT 2 VOLTAGE Register

COMMAND = 36h with 2 Data Byte, (LSByte First, MSByte second), Read Only

Figure 58. PORT 2 VOLTAGE Register Format

LSB:

V2_7

R-0

V2_6

R-0

V2_5

R-0

V2_4

R-0

V2_3

R-0

V2_2

R-0

V2_1

R-0

V2_0

R-0

MSB:

–

V2_13

R-0

V2_12

R-0

V2_11

R-0

V2_10

R-0

V2_9

R-0

V2_8

R-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

8.6.40 PORT 3 VOLTAGE Register

COMMAND = 3Ah with 2 Data Byte, (LSByte First, MSByte second), Read Only

Figure 59. PORT 3 VOLTAGE Register Format

LSB:

V3_7

R-0

V3_6

R-0

V3_5

R-0

V3_4

R-0

V3_3

R-0

V3_2

R-0

V3_1

R-0

V3_0

R-0

MSB:

–

V3_13

R-0

V3_12

R-0

V3_11

R-0

V3_10

R-0

V3_9

R-0

V3_8

R-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

8.6.41 PORT 4 VOLTAGE Register

COMMAND = 3Eh with 2 Data Byte, (LSByte First, MSByte second), Read Only

Figure 60. PORT 4 VOLTAGE Register Format

LSB:

V4_7

R-0

V4_6

R-0

V4_5

R-0

V4_4

R-0

V4_3

R-0

V4_2

R-0

V4_1

R-0

V4_0

R-0

MSB:

–

V4_13

R-0

V4_12

R-0

V4_11

R-0

V4_10

R-0

V4_9

R-0

V4_8

R-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

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Table 32. PORT 4 VOLTAGE Register Field Descriptions

Bit

Field

Type

Reset

Description

13-0

Vn_13- Vn_0

Bit Descriptions: Data conversion result. The I²C data transmission is a 2-byte transfer.

The equation defining the voltage measured is:

V = N × V_STEP

Where V_STEPis defined below as well as the full scale value:

Mode

Full Scale Value

V_STEP

Port Powered

60 V

3.662 mV

Note that a powered port voltage measurement is made between VPWR and DRAINn.

Note: if a port is OFF, the result through I²C interface is automatically 0000.

8.6.42 PoE Plus Register

COMMAND = 40h with1 Data Byte Read/Write

Figure 61. PoE Plus Register Format

–

PoEP4

R/W-0

PoEP3

R/W-0

PoEP2

R/W-0

PoEP1

R/W-0

TPON

R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 33. PoE Plus Register Field Descriptions

Bit

Field

Type

Reset

Description

7–4 PoEP4- PoEP1

R/W

When set, this activates the PoE Plus mode for a port which increases its I_LIMand I_SHORT

levels to around 2 ½ times their normal settings, as shown in Figure 18. Also the PoE Plus bit

is used with the Police Configuration register to define I_CUTthreshold. See Police

Configuration register for more details on the subject. Note that the fault timer starts when the

I_LIMor I_CUT(if ICUT is enabled) threshold is exceeded. Also see the Port Power Priority/ICUT

Disable register.

Notes:

1) At port turn on, the inrush current profile remains the same, whatever the state of the

PoEPn bit, as shown in Figure 17.

2) When a PoEPn bit is set, the corresponding POLn bits in Police Configuration register are

initially changed to 0x0. When a PoEPn bit is reset, the corresponding POLn bits in Police

Configuration register are initially changed to 0xF. In both cases, the port police current

threshold is the same value.

3) When a PoEPn bit is deasserted, the t_LIMused for the associated port is always the

nominal value (~60 ms). If PoEPn bit is asserted, then t_LIMfor associated port is

programmable as defined in the Timing Configuration register.

4) If a port is turned on by use of the Type 2 IEEE Power Enable Pushbutton, the PSE does

the following. When power-on is complete and if class 4 has been detected, the

corresponding PoEPn bit is set and the value of the corresponding Police Configuration

TPON

R/W

When set, if DETn bit (DETECT/CLASS ENABLE register) is set and while in semiauto mode,

writing a 1 at a PWONn bit in the Power Enable register will turn on a port after the current

detection (and class is valid if enabled) cycle is completed but only if the IEEE802.3 TPON

timing specification can be met. TPON specification is the time from the completion of a valid

detection cycle to port turn ON.

If TPON specification cannot be met, a new detection cycle is restarted, followed by a

classification cycle, at the end of which the port is turned on, but only if a valid detection is

returned. For this case, there is no additional attempt to turn on the port until this push button

is reasserted.

If TPON bit is low, writing a 1 at a PWONn bit in the Power Enable register will turn on the

associated port immediately, regardless of IEEE802.3 TPON timing specification and

regardless of the detection result.

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8.6.43 FIRMWARE REVISION

COMMAND = 41h with 1 Data Byte, Read Only

Figure 62. FIRMWARE REVISION Register Format

FRV

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 34. FIRMWARE REVISION Register Field Descriptions

Bit

Field

Type Reset Description

7–0

FRV

Firmware Revision number

8.6.44 I2C WATCHDOG Register

COMMAND = 42h with 1 Data Byte, Read/Write

The I²C watchdog timer monitors the I²C clock line in order to prevent hung software situations that could leave

ports in a hazardous state. The timer can be reset by either edge on SCL input. If the watchdog timer expires, all

ports will be turned off and WDS bit will be set. The nominal watchdog time-out period is 2 seconds.

Figure 63. I2C WATCHDOG Register Format

–

IWDD3

R/W-1

IWDD2

R/W-0

IWDD1

R/W-1

IWDD0

R/W-1

WDS

R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 35. I2C WATCHDOG Register Field Descriptions

Bit

Field

Type Reset Description

I²C Watchdog disable. When equal to 1011b, the watchdog is masked. Otherwise, it is

umasked and the watchdog is operational.

4–1

IWDD3–IWDD0

R/W 1011b

WDS

R/W

I²C Watchdog timer status, valid even if the watchdog is masked. When set, it means that

the watchdog timer has expired without any activity on I²C clock line. Writing 0 at WDS

location clears it. Note that when the watchdog timer expires and if the watchdog is

unmasked, all ports are also turned off.

When the ports are turned OFF due to I²C watchdog, the corresponding bits in Detection Event register (CLSCn,

DETCn), Fault Event register (DISFn, ICUTn), Start Event register (STRTn, ILIMn), Port n Status register

(CLASS Pn, DETECT Pn), DETECT/CLASS ENABLE register (CLEn, DETEn) and Power-on Fault register (PFn)

are also cleared.

The corresponding PGCn and PECn bits of Power Event register will also be set if there is a change. The

corresponding PEn and PGn bits of Power Status Register are also updated accordingly.

NOTE

If the I²C watchdog timer has expired, the Temperature and Input voltage registers will

stop being updated until the WDS bit is cleared. The WDS bit must then be cleared to

allow these registers to work normally.

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8.6.45 DEVICE ID Register

COMMAND = 43h with 1 Data Byte, Read Only

Figure 64. DEVICE ID Register Format

DID

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 36. DEVICE ID Register Field Descriptions

Bit

7–5

4–0

Field

DID

Type Reset Description

110b Device ID number (110)

Silicon Revision number

8.6.46 PORT 1 DETECT RESISTANCE Register

COMMAND = 44h with 1 Data Byte, Read Only

Figure 65. PORT 1 DETECT RESISTANCE Register Format

R1_7

R-0

R1_6

R-0

R1_5

R-0

R1_4

R-0

R1_3

R-0

R1_2

R-0

R1_1

R-0

R1_0

R-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

8.6.47 PORT 2 DETECT RESISTANCE Register

COMMAND = 45h with 1 Data Byte, Read Only

Figure 66. PORT 2 DETECT RESISTANCE Register Format

R2_7

R-0

R2_6

R-0

R2_5

R-0

R2_4

R-0

R2_3

R-0

R2_2

R-0

R2_1

R-0

R2_0

R-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

8.6.48 PORT 3 DETECT RESISTANCE Register

COMMAND = 46h with 1 Data Byte, Read Only

Figure 67. PORT 3 DETECT RESISTANCE Register Format

R3_7

R-0

R3_6

R-0

R3_5

R-0

R3_4

R-0

R3_3

R-0

R3_2

R-0

R3_1

R-0

R3_0

R-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

8.6.49 PORT 4 DETECT RESISTANCE Register

COMMAND = 47h with 1 Data Byte, Read Only

Figure 68. PORT 4 DETECT RESISTANCE Register Format

R4_7

R-0

R4_6

R-0

R4_5

R-0

R4_4

R-0

R4_3

R-0

R4_2

R-0

R4_1

R-0

R4_0

R-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

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Table 37. PORT 4 DETECT RESISTANCE Register Field Descriptions

Bit

Field

Type

Reset

Description

7-0

Rn_7- Rn_0

8-bit data conversion result of detection resistance for port n.

Most recent 2-point Detection Resistance measurement result. The I²C data transmission is a

1-byte transfer.

Note that the register content is not cleared at port turn off.

The equation defining the resistance measured is:

R = N × R_STEP

Where R_STEPis defined below as well as the full scale value:

Useable Resistance Range

R_STEP

2 kΩ to 50 kΩ

195.3125 Ω

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9 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

9.1 Application Information

9.1.1 Introduction to PoE

Power-over-Ethernet (PoE) is a means of distributing power to Ethernet devices over the Ethernet cable using

either data or spare pairs. PoE eliminates the need for power supplies at the Ethernet device. Common

applications of PoE are security cameras, IP Phones and PDA chargers. The host or mid-span equipment that

supplies power is the power source equipment (PSE). The load at the Ethernet connector is the powered device

(PD). PoE protocol between PSE and PD controlling power to the load is specified by IEEE Std 802.3at-2009.

Transformers are used at Ethernet host ports, mid-spans and hubs, to interface data to the cable. A DC voltage

can be applied to the center tap of the transformer with no effect on the data signals. As in any power

transmission line, a relatively high 48 V is used to keep current low, minimize the effect of IR drops in the line

and preserve power to the load. Standard POE delivers approximately 13 W to a type 1 PD, and 25.5 W to a

type 2 PD.

9.1.2 TPS2388 Application

The TPS2388 is an 8-port, IEEE 802.3at PoE PSE controller and can be used in high port count semiauto or fully

micro-controller managed applications (The MSP430G2553 micro-controller is recommended for most

applications). Subsequent sections describe detailed design procedures for applications with different

requirements including host control.

The schematic of Figure 71 depicts semiauto mode operation of the TPS2388, providing functionality to power

PoE loads. In Figure 71 the TPS2388 can do the following:

1. Performs load detection.

2. Performs classification including type-2 (two-finger) of up to Class 4 loads.

3. Enables power with protective foldback current limiting, and POLICE (I_CUT) value.

4. Shuts down in the event of fault loads and shorts.

5. Performs Maintain Power Signature function to insure removal of power if load is disconnected.

6. Undervoltage lock out occurs if VPWR falls below VPUV_F (typical 26.5 V).

Following a power-off command, disconnect or shutdown due to a start, ICUT or ILIM fault, the port powers

down. Following port power off due to a power off command or disconnect, the TPS2388 will restart a detection

cycle if commanded to do so through I²C bus. If the shutdown is due to a start, ICUT or ILIM fault, the TPS2388

enters into a cool-down period during which any Detect/Class Enable Command for that port will be delayed. At

the end of cool down cycle, one or more detection/class cycles are automatically restarted if the class and/or

detect enable bits are set.

9.1.3 Kelvin Current Sensing Resistor

Load current in each PSE port is sensed as the voltage across a low-end current-sense resistor with a value of

255 mΩ. For more accurate current sensing, kelvin sensing of the low end of the current-sense resistor is

provided through pins KSENSA for ports 1 and 2, KSENSB for ports 3 and 4, KSENSC for ports 5 and 6 and

KSENSD for ports 7 and 8.

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Application Information (continued)

+48V

+3.3V

VDD

VPWR

100 nF

PORT

100V

SCL

DRAINn

SDAO

TPS2388

GATn

SENn

SDAI

INT

255 mO

KSENSx

AGND

DGND

Note: only port n shown

Figure 69. Kelvin Current-Sense Connection

9.1.4 Connections on Unused Ports

On unused ports, it is recommended to ground the SENx pin and leave the GATx pin open. DRAINx pins can be

grounded or left open (leaving open may slightly reduce power consumption). Figure 70 shows an example of an

unused PORT4.

11 KSENSB KSENSA

13 SEN4

12 DRAIN4

14 GAT4

GAT1

DRAIN1

SEN1

Q_P1

255mW

Port 4 not used

Figure 70. Unused PORT4 Connections

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9.2 Typical Application

This typical application shows an eight port, semiauto mode application using MSP430 microcontroller. Operation

in any mode requires I²C host support. The TPS2388 provides useful telemetry in multi-port applications to aid in

implementing port power management.

VPWR

VDD

TPS2388RTQ

C_VDD

C_VPWR

VPWR

43 VDD

VPWR 17

44 RESET

53 SCL

RJ45

XFMR

RJ45

XFMR

D_P2A

D_P3A

C_P2

C_P3

A1 48

A2 49

F_P2

F_P3

54 SDAI

55 SDAO

45 INT

Q_P2

Q_P3

A3 50

A4 51

R_S2A

R_S2B

R_S3B

R_S3A

46 DGND

AGND 21

SEN3

10 DRAIN3

GAT3

GAT2

DRAIN2

SEN2

R_S1A

R_S1B

R_S4B

R_S4A

11 KSENSB KSENSA

Q_P1

Q_P4

13 SEN4

12 DRAIN4

14 GAT4

GAT1

DRAIN1

SEN1

F_P1

F_P4

RJ45

C_P1

C_P4

D_P1A

D_P4A

XFMR

VDD

VPWR

R_RST

R_INT

R_SCL

R_SDA

I2C Host

Device

56 OSS

VPWR

RJ45

XFMR

RJ45

XFMR

D_P6A

D_P7A

C_P6

C_P7

F_P6

F_P7

Q_P6

Q_P7

R_S6A

R_S6B

R_S7B

R_S7A

37 SEN7

38 DRAIN7

36 GAT7

GAT6 35

DRAIN6 33

SEN6 34

R_S5A

R_S5B

R_S8B

R_S8A

39 KSENSD KSENSC 32

Q_P5

Q_P8

41 SEN8

40 DRAIN8

42 GAT8

GAT5 29

DRAIN5 31

SEN5 30

F_P5

F_P8

RJ45

XFMR

RJ45

XFMR

C_P5

C_P8

D_P5A

D_P8A

VPWR

Figure 71. Eight Port Semiauto Mode Application

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Typical Application (continued)

9.2.1 Design Requirements

The RESET pin may be connected to the micro-controller if an external RESET is required or connected directly

to VDD. TPS2388 devices are used in the eight port configuration and are managed by the I²C host device. The

I²C address for TPS2388 is programmed using the A4..A1 pins.

9.2.2 Detailed Design Procedure

9.2.2.1 Power Pin Bypass Capacitors

•

C_VPWR: 0.1 μF, 100 V, X7R ceramic at pin 17 (VPWR)

C_VDD: 0.1 μF, 50 V, X7R ceramic at pin 43 (VDD)

9.2.2.2 Per Port Components

•

C_Pn: 0.1-μF, 100-V, X7R ceramic between VPWR and Pn-

R_SnA/ R_SnB: The port current sense resistors are a combination of two 0.51-Ω, 1% resistors in parallel (0.255

Ω). Dual 0.51-Ω, 1%, 0.25-W resistors in an 0805 SMT package are recommended. If a nominal 640 mA

Policing (I_CUT) threshold is selected, the maximum power dissipation for the resistor pair becomes

approximately 115 mW (~57 mW each).

•

Q_Pn: The port MOSFET can be a small, inexpensive device with average performance characteristics. BV_DSS

should be 100 V minimum. Target a MOSFET R_DS(on)at V_GS= 10 V of between 50 mΩ and 150 mΩ. The

MOSFET GATE charge (Q_G) and input capacitance (C_ISS) should be less than 50 nC and 2000 pF

respectively. The maximum power dissipation for Q_Pnwith RDS(on) = 100 mΩ at 640 mA nominal policing

(I_CUT) threshold is approximately 45 mW.

•

F_Pn: The port fuse should be a slow blow type rated for at least 60 VDC and above ~2 x I_CUT(max). The cold

resistance should be below 200 mΩ to reduce the DC losses. The power dissipation for FPn with a cold

resistance of 180 mΩ at maximum I_CUTis approximately 81 mW.

D_PnA: The port TVS should be rated for the expected port surge environment. D_PnAshould have a minimum

reverse standoff voltage of 58 V, peak pulse power rating of 600 W, and a maximum clamping voltage of less

than 95 V at the expected peak surge current

9.2.2.3 System Level Components (not shown in the schematic diagrams)

The system TVS and bulk VPWR capacitance work together to protect the PSE system from surge events which

could cause VPWR to surge above 70 V. The TVS and bulk capacitors should be placed on the PCB such that

all TPS2388 ports are adequately protected.

•

TVS: The system TVS should have a minimum reverse standoff voltage of 58 V and a peak pulse power

rating of 600 W or 1500 W depending on the total number of system ports and amount of bulk VPWR

capacitance used. Together with the VPWR bulk capacitance, the TVS must prevent the VPWR rail from

exceeding 70 V.

•

Bulk Capacitor: The system bulk capacitor(s) should be rated for 100 V and can be of aluminum electrolytic

type. Two 47-μF capacitors can be used for each TPS2388 on board.

Distributed Capacitance:In higher port count systems, it may be necessary to distribute 1-uF, 100-V, X7R

ceramic capacitors across the 48-V power bus. One capacitor per each TPS2388 pair is recommended.

Digital I/O Pullup Resistors: RESET and A1-A4 are internally pulled up to VDD, while OSS is internally

pulled down, each with a 50-kΩ (typical) resistor. A stronger pull-up/down resistor can be added externally

such as a 10 kΩ, 1%, 0.063 W type in a SMT package. SCL, SDAI, SDAO, and INT require external pull-up

resistors within a range of 1 kΩ to 10 kΩ depending on the total number of devices on the bus .

•

Ethernet Data Transformer (per port): The Ethernet data transformer must be rated to operate within the

IEEE802.3at standard in the presence of the DC port current conditions. The transformer is also chosen to be

compatible with the Ethernet PHY. The transformer may also be integrated into the RJ45 connector and cable

terminations.

RJ45 Connector (per port): The majority of the RJ45 connector requirements are mechanical in nature and

include tab orientation, housing type (shielded or unshielded), or highly integrated. An integrated RJ45

consists of the Ethernet data transformer and cable terminations at a minimum. The integrated type may also

contain the port TVS and common mode EMI filtering.

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Typical Application (continued)

•

Cable Terminations (per port): The cable terminations typically consist of series resistor (usually 75 Ω) and

capacitor (usually 10 nF) circuits from each data transformer center tap to a common node which is then

bypassed to a chassis ground (or system earth ground) with a high-voltage capacitor (usually 1000 pF to

4700 pF at 2 kV).

9.2.3 Application Curves

Figure 72. Startup With Valid PD (25 kΩ and 0.1 μF), Class

Figure 73. Startup With Valid PD (25 kΩ and 0.1 μF), Class

Figure 74. Detection With Invalid PD (15 kΩ and 0.1 μF)

Figure 75. Detection With Invalid PD (Open Circuit)

Figure 76. Detection With Invalid PD (25 kΩ and 10 μF)

Figure 77. 2-Event Class and Startup With Valid PD

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Typical Application (continued)

Figure 78. Powering Up into a 100-μF Load

Figure 79. All Ports Power-On With TPON Bit Set

Figure 80. All Ports Fast Shutdown from OSS Input

Figure 81. Ports Fast Shutdown from 3-Bit OSS Input

Figure 82. Overcurrent (ICUT) Timeout

Figure 83. Rapid Response to a 1-Ω Short - 802.3af Mode

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Typical Application (continued)

Figure 84. Rapid Response to a 1-Ω Short - PoE+ Mode

Figure 85. Response to a 50-Ω Load - 802.3af Mode

Figure 86. Response to a 25-Ω Load - PoE+ Mode

Figure 87. Current Limit Timeout - 802.3af Mode, 85-Ω

Load

Figure 88. Current Limit 15-ms Timeout - PoE+ Mode, 45-Ω

Figure 89. Inrush Fault Timeout - 100-Ω Load

Load

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Typical Application (continued)

Figure 90. Current Limit Timeout Restart Delay

Figure 91. Response to 8-mA to 6-mA Load, DC

Disconnect Enabled

DRAIN

PD classified

Searching for PD

DRAIN

PD detected

GATE

Figure 93. Detection, 2-Event Class and Port Turn On

Figure 92. Detection With Open Circuit

GATE

CLS1 MRK1 CLS2 MRK2

DRAIN

SENSE

DRAIN

SENSE

I-PORT

Inrush

current

Load

current

Two-event class

(class 4 current)

I-PORT

Figure 95. 2-Event Class and Port Turn On

Figure 94. 2-Event Class and Port Turn On

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10 Power Supply Recommendations

10.1 VDD

The recommended VDD supply voltage requirement is 3.3 V, ±0.3 V. TPS2388 requires approximately 6 mA

typical and 12 mA maximum from the VDD supply. The VDD supply can be generated from VPWR with a buck-

type regulator (LM5007 or LM5019 based) for a higher port count PSE using multiple TPS2388 devices operating

in semiauto mode. The power supply design must ensure the VDD rail rises monotonically through the VDD

UVLO thresholds without any droop under the UVLO_fall threshold as the loads are turned on. This is

accomplished with proper bulk capacitance across the VDD rail for the expected load current steps over worst

case design corners. Furthermore, the combination of decoupling capacitance and bulk storage capacitance

must hold the VDD rail above the UVLO_fall threshold during any expected transient outages once power is

applied.

10.2 VPWR

The recommended VPWR supply voltage requirement is 44 V to 57 V. A power supply with a nominal 48-V or

54-V output can support both type 1 and type 2 PD requirements. The output current required from the VPWR

supply depends on the number and type of ports required in the system. The TPS2388 can be configured for

type 1 and type 2 ports and the current limit is set proportionally. I_CUTis programmable, for example for a type 1

port it can be 380 mA , ±5%, while for a type 2 port it can be 640 mA, ±5%. Size the VPWR supply accordingly

for the number and type of ports to be supported. As an example, the VPWR power supply rating should be

greater than 3.2 A for eight type 1 ports or greater than 5.5 A for eight type 2 ports, assuming maximum port and

standby currents.

11 Layout

11.1 Layout Guidelines

11.1.1 Port Current Kelvin Sensing

KSENSA is shared between SEN1 and SEN2, KSENSB is shared between SEN3 and SEN4, KSENSC is shared

between SEN5 and SEN6, and KSENSD is shared between SEN7 and SEN8. To optimize the accuracy of the

measurement, the PCB layout must be done carefully to minimize impact of PCB trace resistance. Refer to as an

example.

Figure 96. Kelvin Sense Layout Example

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11.2 Layout Example

R_S1A

R_S8A

KSENSD

KSENSA

Q_P1

Q_P8

R_S1B

R_S8B

Q_P2

Q_P7

TPS2388RTQ

Q_P3

Q_P6

KSENSC

F_P3

KSENSB

R_S4A

R_S5A

D_P3A

Q_P4

Q_P5

C_P2

C_P3

R_S4B

GND

R_S5B

Figure 97. Eight Port Layout Example (Top Side)

11.2.1 Component Placement and Routing Guidelines

11.2.1.1 Power Pin Bypass Capacitors

•

C_VPWR: Place close to pin 17 (VPWR) and connect with low inductance traces and vias according to

Figure 97.

•

C_VDD: Place close to pin 43 (VDD) and connect with low inductance traces and vias according to Figure 97

11.2.1.2 Per-Port Components

•

R_SnA/ R_SnB: Place according to in a manner that facilitates a clean Kelvin connection with KSENSEA/B/C/D.

Q_Pn: Place Q_Pnaround the TPS2388 as illustrated in Figure 97. Provide sufficient copper from Q_Pndrain to

F_Pn.

•

F_Pn, C_Pn, D_PnA, D_PnB: Place this circuit group near the RJ45 port connector (or port power interface if a

daughter board type of interface is used as illustrated in Figure 97). Connect this circuit group to Q_Pndrain or

GND (TPS2388- AGND) using low inductance traces.

TPS2388

ZHCSGR0A –FEBRUARY 2015–REVISED AUGUST 2017

www.ti.com.cn

12 器件和文档支持

12.1 接收文档更新通知

要接收文档更新通知，请导航至 TI.com 上的器件产品文件夹。单击右上角的通知我进行注册，即可每周接收产品

信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。

12.2 社区资源

下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，

并且不一定反映 TI 的观点；请参阅 TI 的《使用条款》。

TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在

e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。

设计支持

TI 参考设计支持可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。

12.3 商标

E2E is a trademark of Texas Instruments.

All other trademarks are the property of their respective owners.

12.4 静电放电警告

ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可

能会损坏集成电路。

ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可

能会导致器件与其发布的规格不相符。

12.5 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

TPS2388

www.ti.com.cn

ZHCSGR0A –FEBRUARY 2015–REVISED AUGUST 2017

13 机械、封装和可订购信息

以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。这些数据如有变更，恕不另行通知

和修订此文档。如欲获取此产品说明书的浏览器版本，请参阅左侧的导航。

TPS2388

ZHCSGR0A –FEBRUARY 2015–REVISED AUGUST 2017

www.ti.com.cn

PACKAGE OUTLINE

RTQ0056H

VQFN - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

8.1

7.9

PIN 1 INDEX AREA

8.1

7.9

1 MAX

SEATING PLANE

0.08 C

0.05

0.00

2X 6.5

(0.2) TYP

5.9 0.05

EXPOSED

THERMAL PAD

52X 0.5

6.5

0.3

56X

0.2

PIN 1 ID

(OPTIONAL)

0.1

C A

0.5

0.3

56X

0.05

4222809/A 03/2016

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

www.ti.com

TPS2388

www.ti.com.cn

ZHCSGR0A –FEBRUARY 2015–REVISED AUGUST 2017

EXAMPLE BOARD LAYOUT

RTQ0056H

VQFN - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

(

5.9)

SYMM

56X (0.6)

56X (0.25)

(1.32)

52X (0.5)

SYMM

10X

(1.38)

(7.8)

(

0.2) TYP

VIA

(R0.05)

TYP

10X (1.38)

6X (1.32)

(7.8)

LAND PATTERN EXAMPLE

SCALE:12X

0.07 MAX

ALL AROUND

0.07 MIN

ALL SIDES

SOLDER MASK

OPENING

METAL

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

NON SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK

DEFINED

SOLDER MASK DETAILS

4222809/A 03/2016

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown

on this view. It is recommended that vias under paste be filled, plugged or tented.

www.ti.com

TPS2388

ZHCSGR0A –FEBRUARY 2015–REVISED AUGUST 2017

www.ti.com.cn

EXAMPLE STENCIL DESIGN

RTQ0056H

VQFN - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

16X ( 1.18)

(1.38) TYP

(R0.05) TYP

56X (0.6)

56X (0.25)

52X (0.5)

(1.38)

TYP

SYMM

(7.8)

METAL

TYP

SYMM

(7.8)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD

64% PRINTED SOLDER COVERAGE BY AREA

SCALE:12X

4222809/A 03/2016

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

www.ti.com

PACKAGE OPTION ADDENDUM

www.ti.com

10-Dec-2020

PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

TPS2388RTQR

TPS2388RTQT

ACTIVE

QFN

RTQ

2000 RoHS & Green NIPDAU | NIPDAUAG Level-3-260C-168 HR

250 RoHS & Green NIPDAU Level-3-260C-168 HR

-40 to 125

TPS2388RTQ

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

10-Dec-2020

Addendum-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

31-Oct-2019

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

TPS2388RTQR

TPS2388RTQT

QFN

RTQ

2000

250

330.0

180.0

16.4

8.3

1.1

12.0

16.0

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

31-Oct-2019

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

TPS2388RTQR

TPS2388RTQT

QFN

RTQ

2000

250

367.0

210.0

367.0

185.0

38.0

35.0

Pack Materials-Page 2

GENERIC PACKAGE VIEW

RTQ 56

8 x 8, 0.5 mm pitch

VQFN - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

Images above are just a representation of the package family, actual package may vary.

Refer to the product data sheet for package details.

4224653/A

www.ti.com

PACKAGE OUTLINE

RTQ0056E

VQFN - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

8.15

7.85

PIN 1 INDEX AREA

8.15

7.85

1.0

0.8

SEATING PLANE

0.08 C

0.05

0.00

2X 6.5

5.7 0.1

SYMM

(0.2) TYP

EXPOSED

THERMAL PAD

SYMM

2X 6.5

5.7 0.1

52X 0.5

PIN 1 ID

0.30

0.18

56X

0.5

0.3

0.1

C A B

56X

0.05

4224191/A 03/2018

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

www.ti.com

EXAMPLE BOARD LAYOUT

RTQ0056E

VQFN - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

(5.7)

(2.6) TYP

SEE SOLDER MASK

DETAIL

(1.35) TYP

56X (0.6)

56X (0.24)

52X (0.5)

(2.6) TYP

(R0.05) TYP

(1.35) TYP

SYMM

(7.8)

(5.7)

(

0.2) TYP

VIA

SYMM

(7.8)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE: 10X

0.07 MIN

ALL AROUND

0.07 MAX

ALL AROUND

METAL UNDER

SOLDER MASK

METAL EDGE

EXPOSED METAL

SOLDER MASK

OPENING

EXPOSED

METAL

SOLDER MASK

OPENING

NON SOLDER MASK

DEFINED

SOLDER MASK DEFINED

(PREFERRED)

SOLDER MASK DETAILS

4224191/A 03/2018

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown

on this view. It is recommended that vias under paste be filled, plugged or tented.

www.ti.com

EXAMPLE STENCIL DESIGN

RTQ0056E

VQFN - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

(0.675) TYP

(1.35) TYP

56X (0.6)

56X (0.24)

52X (0.5)

(1.35) TYP

(R0.05) TYP

(0.675) TYP

(7.8)

SYMM

16X (1.15)

SYMM

16X (1.15)

(7.8)

SOLDER PASTE EXAMPLE

BASED ON 0.125 MM THICK STENCIL

SCALE: 10X

EXPOSED PAD 57

65% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE

4224191/A 03/2018

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

www.ti.com

重要声明和免责声明

TI 均以“原样”提供技术性及可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资

源，不保证其中不含任何瑕疵，且不做任何明示或暗示的担保，包括但不限于对适销性、适合某特定用途或不侵犯任何第三方知识产权的暗示

担保。

所述资源可供专业开发人员应用TI 产品进行设计使用。您将对以下行为独自承担全部责任：(1) 针对您的应用选择合适的TI 产品；(2) 设计、

验证并测试您的应用；(3) 确保您的应用满足相应标准以及任何其他安全、安保或其他要求。所述资源如有变更，恕不另行通知。TI 对您使用

所述资源的授权仅限于开发资源所涉及TI 产品的相关应用。除此之外不得复制或展示所述资源，也不提供其它TI或任何第三方的知识产权授权

许可。如因使用所述资源而产生任何索赔、赔偿、成本、损失及债务等，TI对此概不负责，并且您须赔偿由此对TI 及其代表造成的损害。

TI 所提供产品均受TI 的销售条款 (http://www.ti.com.cn/zh-cn/legal/termsofsale.html) 以及ti.com.cn上或随附TI产品提供的其他可适用条款的约

束。TI提供所述资源并不扩展或以其他方式更改TI 针对TI 产品所发布的可适用的担保范围或担保免责声明。IMPORTANT NOTICE

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TPS2388 [TI]

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