TPS2419PW [TI]
N+1 and ORing Power Rail Controller with Enable; N + 1或运算电源轨控制器启用
| 型号： | TPS2419PW |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | N+1 and ORing Power Rail Controller with Enable |
| 文件： | 总21页 (文件大小：493K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPS2419
www.ti.com
SLVS998A –FEBRUARY 2010–REVISED MARCH 2010
N+1 and ORing Power Rail Controller with Enable
Check for Samples: TPS2419
1
FEATURES
•
•
•
•
•
•
•
•
•
Control External FET for N+1 and ORing
DESCRIPTION
Controls Buses From 3 V to 16.5 V
External Enable
The TPS2419 controller, in conjunction with an
external N-channel MOSFET, provides the reverse
current protection of an ORing diode with the
efficiency of a MOSFET. The TPS2419 can be used
to combine multiple power supplies to a common bus
in an N+1 configuration, or to combine redundant
input power buses.
N-Channel MOSFETControl
Rapid Device Turnoff Protects Bus Integrity
Programmable Turn-Off Threshold
Soft Turn on Reduces Bus Transients
Industrial Temperature Range: –40°C to 85°C
8-Pin TSSOP and SOIC Packages
Applications for the TPS2419 include a wide range of
systems including servers and telecom. These
applications often have either N+1 redundant power
supplies, redundant power buses, or both. Redundant
power sources must have the equivalent of a diode
OR to prevent reverse current during faults and
hotplug.
APPLICATIONS
•
•
•
•
N+1 Power Supplies
Server Blades
Telecom Systems
High Availability Power Modules
Accurate voltage sensing and
turn-off threshold allows operation to be tailored for a
wide range of implementations and bus
a programmable
characteristics. The TPS2419 brings out an enable
pin which allows the system to force the MOSFET off
under light-load, high noise conditions.
Table 1. Family Features
'2410
'2411
'2412
'2413
'2419
Enable input
√
√
√
√
Linear gate control
√
ON/OFF gate
control
√
√
√
√
Enable
EN
Turnoff
√
comparator
filtering
Voltage monitoring
√
√
√
√
MOSFET fault
monitoring
Status pin
√
√
√
√
Independent
Supply Pin
√
√
Figure 1. Typical Application
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2010, Texas Instruments Incorporated
TPS2419
SLVS998A –FEBRUARY 2010–REVISED MARCH 2010
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
PRODUCT INFORMATION(1)
MOSFET GATE
CONTROL
DEVICE
TEMPERATURE
PACKAGE(1)
MARKING
PW (TSSOP-8)
D (SO-8)
TPS2419
–40°C to 85°C
ON/OFF
TPS2419
(1) For package and ordering information, see the Package Option Addendum at the end of this
document, or see the TI Web site at www.ti.com.
ABSOLUTE MAXIMUM RATINGS(1)
over recommended operating junction temperature range, voltages are referenced to GND (unless otherwise noted)
VALUE
UNIT
V
A, C voltage
–0.3 to 18
7.5
A above C voltage
C above A voltage
GATE, BYP voltage(2)
BYP to A voltage
V
18
V
–0.3 to 30
–0.3 to 13
0.3
V
V
GATE above BYP voltage
RSET(2) voltage
V
–0.3 to 7
–0.3 to 5.5
Indefinite
2
V
EN
V
GATE short to A or C or GND
Human body model
Charged device model
Maximum junction temperature
kV
V
ESD
TJ
500
Internally limited
°C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Voltage should not be applied to these pins.
DISSIPATION RATINGS
POWER RATING
PACKAGE
qJA – Low k °C/W
qJA – High k °C/W
High k
TA = 85°C (mW)
PW (TSSOP)
D (SO)
258
176
159
250
410
97.5
2
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SLVS998A –FEBRUARY 2010–REVISED MARCH 2010
RECOMMENDED OPERATING CONDITIONS
voltages are referenced to GND (unless otherwise noted)
MIN
NOM
MAX
16.5
5
UNIT
V
A, C
Input voltage range(1)
Operational voltage
0
A to C
EN
V
Input voltage range
0
1.5
5
V
R(RSET)
C(BYP)
TJ
Resistance range(2)
Capacitance Range(2)
∞
kΩ
pF
°C
800
–40
2200
10k
125
Operating junction temperature
(1) V(C) must exceed 2.5 V for normal operation and 3 V to meet gate drive specification
(2) Voltage should not be applied to these pins.
ELECTRICAL CHARACTERISTICS(1)
Common conditions (unless otherwise noted) are: [3 V ≤ ( V(A), V(C) ) ≤ 18 V ] , C(BYP) = 2200 pF, R(RSET) = open, EN = 2 V,
GATE = open, –40°C ≤ TJ ≤ 125°C, positive currents into pins, typical values are at 25°C, all voltages with respect to GND.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
A, C
V(C) rising
Hysteresis
2.25
2.5
V
Supply UVLO
0.25
0.66
0.1
| I(A) |, Gate in active region
1
A current
mA
| I(A) |, Gate saturated high
Worst case, gate in active region, V(AC) ≤ 0.1 V
Gate saturated high, V(AC) ≤ 0.1 V
4.25
1.2
6
C current
mA
EN
Threshold voltage
Hysteresis
V(EN) rising
1.25
1.3
29
1.35
1
V
mV
V(AC) = 0.1 V, V(EN)↑ : 1.1 V → 1.4 V, measure
period to V(GATE) = 0.25 V
0.65
0.3
Response time
ms
V(AC) = 0.1 V, V(EN)↓: 1.4 V → 1.1 V, measure
period to V(GATE) = V(ON) - 0.25 V
0.6
1
Leakage current (source or sink)
TURN ON
V(EN) = 0.5 V
mA
Forward turn-on voltage - VON
TURN OFF
V(A-C)
58
65
71
mV
Gate sinks > 10 mA at V(GATE-A) = 2 V
V(A-C) falling, R(RSET) = open
1
-17
3
-13.25
-142
5
-10
Turn-off threshold voltage
mV
V(A-C) falling, R(RSET) = 28.7 kΩ
V(A-C) falling, R(RSET) = 3.24 kΩ
-170
-114
V(A) = 12 V, V(A-C): 20 mV → –20 mV,
V(GATE-A) begins to decrease
Turn-off delay
Turn-off time
70
ns
ns
V(A) = 12 V, C(GATE-GND) = 0.01 mF, V(A-C)
20 mV → –20 mV, measure the period to
:
130
V(GATE) = V(A)
(1) Parameters with only typical values are provided for reference only, and do not constitute part of TI's published device specifications for
purposes of TI's product warranty.
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ELECTRICAL CHARACTERISTICS (1) (continued)
Common conditions (unless otherwise noted) are: [3 V ≤ ( V(A), V(C) ) ≤ 18 V ] , C(BYP) = 2200 pF, R(RSET) = open, EN = 2 V,
GATE = open, –40°C ≤ TJ ≤ 125°C, positive currents into pins, typical values are at 25°C, all voltages with respect to GND.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
GATE
V(C) = 3 V, V(A-C) = 200 mV
6
9
7
10.2
290
8
V
Gate positive drive voltage, V(GATE-A)
Gate source current
5 V ≤ VC ≤ 18 V, V(A-C) = 200 mV
V(A-C) = 200 mV, V(GATE-A) = 4 V
V(A-C) = –0.1 V
11.5
250
350
mA
V(GATE) = 8 V
1.75
1.25
7.5
2.35
1.75
12.5
A
Turn-off pulsed current, I(GATE)
Sustain turn-off current, I(GATE)
V(GATE) = 5 V
Period
ms
V(A-C) = –0.1 V, 3 V ≤ VC ≤ 18 V,
2 V ≤ V(GATE) ≤ 18 V
15
19.5
mA
MISCELLANEOUS
Thermal shutdown temperature
Thermal hysteresis
Temperature rising, TJ
135
10
°C
°C
FUNCTIONAL BLOCK DIAGRAM
A
VDD
10V
Charge Pump
and Bias Supply
HVUV
BYP
TURNON
COMP.
+
-
A
VON
C
Q
S
R
Q
0.5V
GATE
+
-
3mV
en
RSET
TURNOFF
COMP.
en
-
VDD
+
en
Thermal Shutdown
(135ºC)
C
MULTISTAGE
PULLDOWN
1.3V
EN
RSVD
GND
VBIAS
en
Bias and
Control
VDD
HVUV
4
Copyright © 2010, Texas Instruments Incorporated
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SLVS998A –FEBRUARY 2010–REVISED MARCH 2010
PW and D PACKAGE
(TOP VIEW)
BYP
A
8
5
1
4
RSET
EN
RSVD
GND
C
GATE
TERMINAL FUNCTIONS
TERMINAL
I/O
DESCRIPTION
NAME
NO.
Connect a resistor to ground to program the turn-off threshold. Leaving RSET open results in a slightly
positive V(A-C) turn-off threshold.
RSET
1
I
I
EN
2
3
4
5
Pull EN above 1.3 V to permit normal ORing operation. A low on EN holds GATE low.
RSVD
GND
GATE
PWR This pin must be connected to GND.
PWR Device ground.
O
Connect to the gate of the external MOSFET. Controls the MOSFET to emulate a low forward-voltage diode.
Voltage sense input that connects to the simulated diode cathode, and also serves as the bias supply for the
gate drive charge pump and internal controls. Connect to the MOSFET drain in the typical configuration.
C
6
I
Voltage sense input that connects to the simulated diode anode, and also serves as the reference for the
charge-pump bias supply on BYP. Connect to the MOSFET source in the typical configuration.
A
7
8
I
BYP
I/O
Connect a capacitor from BYP to A to filter the gate drive supply voltage.
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DETAILED DESCRIPTION
The following descriptions refer to the pinout and the functional block diagram.
A, C: The A pin serves as the simulated diode anode and the C as the cathode. GATE is driven high when V(A-C)
exceeds 65 mV. A strong GATE pull-down is applied when V(A-C) is less than the programmable turn-off threshold
(see RSET). These two thresholds serve as a hysteretic GATE control with the ON/OFF state preserved until the
next (opposite) threshold cross.
The internal charge pump output, which provides bias power to the comparators and voltage to drive GATE, is
referenced to A. Some charge pump current appears on A.
C is both the cathode voltage sense and the bias supply for the gate-drive charge pump and other internal
circuits. This pin must be connected a source that is 3 V or greater when the external MOSFET is to be turned
on.
A 0.01-mF minimum bypass capacitor to GND is recommended for both A and C inputs. A and C connections to
the bypass capacitor and the controlled MOSFET should be short and low impedance.
The inputs are protected from excess differential voltage by a clamp diode and series resistance. If C falls below
A by more than about 0.7 V, a small current flows out of C. Configurations which permit C to be more than 6 V
lower than A should be avoided.
BYP: BYP is the internal charge pump output, and the positive supply voltage for internal comparator circuits and
GATE driver. A capacitor must be connected from BYP to A. While the capacitor value is not critical, a 2200-pF
ceramic is recommended. Traces to this part must be kept short and low impedance to provide adequate filtering.
Shorting this pin to a voltage below A damages the TPS2419.
EN: A voltage greater than 1.3 V on EN permits the TPS2419 to operate in its normal ORing mode. A voltage
below the lower threshold forces GATE to remain low, however EN going high will not automatically turn GATE
ON. EN going low when GATE is high engages the sustain current pulldown. EN should not be driven higher
than its recommended maximum voltage.
GATE: Gate controls the external N channel MOSFET gate. GATE is driven positive with respect to A by a driver
operating from the voltage on BYP. A time-limited high current discharge source pulls GATE to GND when the
turn-off comparator is activated. The high-current discharge is followed by a sustaining pull-down. The turn-off
circuits are disabled by the thermal shutdown, leaving a resistive pull-down to keep the gate from floating. The
gate connection should be kept low impedance to maximize turn-off current.
GND: This is the input supply reference. GND should have a low impedance connection to the ground plane. It
carries several Amperes of rapid-rising discharge current when the external MOSFET is turned off, and also
carries significant charge pump currents.
RSET: A resistor connected from this pin to GND sets the V(A-C) turn-off comparator threshold. The threshold is
slightly positive when the RSET pin is left open. Current drawn by the resistor programs the turn-off voltage to
increasing negative values. The TPS2419 must have a negative threshold programmed to avoid an unstable
condition at light load. The expression for R(RSET) in terms of the turn-off voltage ( V(OFF)= V(A) - V(C)) follows.
æ
ç
ç
è
ö
÷
÷
ø
-470.02
- 0.00314
R
=
(RSET)
V
(OFF)
(1)
The units of the numerator are (V × V/A). V(OFF) is positive for V(A) greater than V(C), V(OFF) is less than 3 mV, and
R(RSET) is in ohms.
RSVD: Connect to ground.
6
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TYPICAL CHARACTERISTICS
TURNOFF THRESHOLD
vs
PULSED GATE SINKING CURRENT
vs
TEMPERATURE
GATE VOLTAGE
3.0
5.0
4.5
R
= Open
(RSET)
T
= -40oC
J
2.5
2.0
4.0
3.5
T
= 25oC
J
T
= 85oC
J
1.5
1.0
0.5
0.0
3.0
2.5
2.0
T = 125oC
J
1.5
1.0
0
2
4
6
8
10
−40 −20
0
20
40
60
80
100 120
V
− V
− Junction Temperature − oC
(GATE - GND)
T
J
Figure 2.
Figure 3.
TURNON DELAY
I(C)
vs
vs
V(C)
V(C)
(POWER APPLIED UNTIL GATE IS ACTIVE)
(GATE SATURATED HIGH)
60
50
3.0
2.5
2.0
T
= -40oC
J
T
= 25oC
40
30
20
J
T
= 125oC
J
T
= 25oC
J
1.5
1.0
0.5
0.0
T
= -40oC
J
T
= 125oC
J
10
0
2
4
6
8
10
12
14
16
18
2
4
6
8
10
− V
12
14
16
18
V
− V
V
C
DD
Figure 4.
Figure 5.
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TYPICAL CHARACTERISTICS (continued)
TURN ON VOLTAGE
vs
ENABLETHRESHOLD
vs
TEMPERATURE
TEMPERATURE
65.5
65.4
1.32
1.31
1.3
65.3
65.2
65.1
65
EN Rising
1.29
1.28
1.27
1.26
1.25
EN Hysteresis ~ 29 mV
EN Falling
64.9
64.8
64.7
64.6
64.5
-40 -20
0
20
40
60
- Temperature - °C
80
100 120
-40 -20
0
20
40
60
- Junction Temperature - °C
80
100 120
T
T
J
J
Figure 6.
Figure 7.
EXAMPLE TURNON AND TURNOFF
Turn on
Threshold
GATE drives 10 nF to GND
VC = 12 V, RSET = 61.9 WW
VA-C
Turn off
Threshold
VGATE
Time 1ms/DIV
Figure 8.
8
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TYPICAL CHARACTERISTICS (continued)
EXAMPLE TURNOFF
GATE drives 10 nF to GND
IGATE
VC = 12 V, RSET = 61.9 WW
Turn off
Threshold
VA-C
VGATE = VA
VGATE
135 ns
Time 100ns/DIV
Figure 9.
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APPLICATION INFORMATION
OVERVIEW
The TPS2419 is designed to allow an output ORing in N+1 power supply applications (see Figure 11), and an
input-power bus ORing in redundant source applications (see Figure 12). The TPS2419 and external MOSFET
emulate a discrete diode to perform this unidirectional power combining function. The advantage to this
emulation is lower forward voltage drop and higher efficiency.
The TPS2419 turns the MOSFET on and off like a comparator with hysteresis as shown in Figure 10. GATE is
driven high when V(A-C) exceeds 65 mV, and driven low if V(A-C) falls below the RSET programmed turn-off
threshold. Operation of the TPS2419 is demonstrated in Figure 8 where an ac-coupled square wave is applied
from A to C. Figure 8 shows the condition where the MOSFET gate is initially at GND, and V(A-C) is less than 65
mV. When the turn-on threshold is exceeded, the TPS2419 turns on the MOSFET gate, and charges it to V(BYP)
.
The gate stays high even though V(A-C) is less than the turn-on threshold. The TPS2419 pulls the gate to GND
when V(A-C) falls below the turn-off threshold.
System designs should account for the inherent delay between a TPS2419 circuit becoming forward biased, and
the MOSFET actually turning ON. The delay is the result of the MOSFET gate capacitance charge from ground
to its threshold voltage by the 290 mA gate current. If there are no additional sources holding a common ORed
rail voltage up, the MOSFET internal diode will conduct and maintain voltage on the ORed output. The ORed
input supply will experience a momentary large current draw as the MOSFET turns on, shorting the internal diode
and charging the bus capacitance.
Gate
ON
Gate
OFF
V
(AC)
Programmable
Fast Turn-off
Threshold Range
Figure 10. TPS2419 Operation
The operation of the TPS2419 is summarized in Table 2.
Table 2. Operation as a Function of V(AC)
V(A-C) ≤ Turnoff Threshold(1)
Turnoff Threshold(1) ≤ V(A-C) ≤ 65 mV
V(A-C) > 65 mV
Depends on previous state(1)
(Hysteresis region)
TPS2419
Gate pulled to GND
GATE pulled high (ON)
(1) Turnoff threshold is established by the value of RSET.
N+1 POWER SUPPLY – TYPICAL CONNECTION
The N+1 power supply configuration shown in Figure 11 is used where multiple power supplies are paralleled for
either higher capacity, redundancy or both. If it takes N supplies to power the load, adding an extra identical unit
in parallel permits the load to continue operation in the event that any one of the N supplies fails. The supplies
are ORed together, rather than directly connected to the bus, to isolate the converter output from the bus when it
is plugged-in or fails short. Thus, the TPS2419 with an external MOSFET emulates the function of the ORing
diode.
ORed supplies are usually designed to share power by various means, although the desired operation could
implement an active and standby concept. Sharing approaches include both passive, or voltage droop, and
active methods. Not all of the output ORing devices may be ON depending on the sharing control method, bus
loading, distribution resistances, and tolerances.
10
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Implementation
Concept
Power
Bus
DC/DC
Converter
Input
Voltage
EN
DC/DC
Converter
Figure 11. N+1 Power Supply Example
INPUT ORing – TYPICAL CONNECTION
Figure 12 shows how redundant buses may be ORed to a common point to achieve higher reliability. It is
possible to have both MOSFETs ON at once if the bus voltages are matched, or the combination of tolerance
and regulation causes both TPS2419 circuits to see a forward voltage. The ORing MOSFET will disconnect the
lower-voltage bus, protecting the remaining bus from potential overload by a fault.
Backplane
Power Buses
Implementation
Concept
Common
Buses
DC/DC
Converter
Hotswap
LOAD
EN
EN
Plug-In Unit
Figure 12. Example ORing of Input Power Buses
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SYSTEM DESIGN AND NOISE ISSUES
In noisy system environments, the low impedance of a MOSFET coupled with a default positive turn off threshold
voltage might result in unwanted ON/OFF GATE cycling. Ideally the best way to approach the problem is with a
clean layout and noise free system design. Since design constraints limit the ability to improve this, the following
suggestions can be employed with the TPS2419.
•
Set the turn off threshold negative using the RSET pin. This is required to operate at light load, but does
permit reverse current.
•
If current monitoring is used in the system, take advantage of the shunt resistor and connect the A and C pins
across the shunt and FET. This increases the sense resistance, reducing noise sensitivity by increasing the
signal levels while reducing the permitted reverse current.
•
Disable the device using EN under light load conditions.
RECOMMENDED OPERATING RANGE
The maximum recommended bus voltage is lower than the absolute maximum voltage ratings on A and C, solely
to provide some margin for transients on the bus. The TPS2419 will operate properly up to the absolute
maximum voltage ratings on A and C.
Most power systems experience transient voltages above or below the normal operating level. Short transients,
or voltage spikes, may be clamped by the ORing MOSFET to an output capacitor and/or voltage rail depending
on the system design. Protection may be required on the input or output if the system design does not inherently
limit transient voltages between the TPS2419 absolute maximum ratings (positive or negative).
Protection for positive transients that would exceed the absolute maximum limits may be accomplished with a
TVS diode (transient voltage suppressor) clamp to ground, or a diode clamp to a safe voltage rail. If a TVS is
required, it must protect to the absolute maximum ratings at the worst case clamping current. Protection for
negative transients that would drive pins (e.g. C) below the absolute maximum limits may be accomplished with a
diode clamp to ground. Limit transient current in or out of the TPS2419 to less than 50 mA. Transients can also
be controlled by bus capacitance or composite snubber/clamps such as a zener-blocked large capacitor with a
discharge resistor in parallel.
MOSFET SELECTION AND R(RSET)
MOSFET selection criteria include voltage rating, voltage drop, power dissipation, size, and cost. The voltage
rating consists of both the ability to withstand the rail voltage with expected transients, and the gate breakdown
voltage. The MOSFET gate rating should exceed be the maximum of the controlled rail voltage or 11.5 V.
While rDS(on) is often chosen with the power dissipation, voltage drop, size and cost in mind, there are several
other factors to be concerned with in ORing applications. When using a TPS2419 with RSET programmed to a
negative voltage, the permitted static reverse current is equal to the turn-off threshold divided by the MOSFET's
rDS(on). While this current may actually be desirable in some systems, the amount may be controlled by selection
of rDS(on) and RSET. The practical range of rDS(on) for a single MOSFET runs from the low milliohms to 40 mΩ for
a single MOSFET.
MOSFETs may be paralleled for lower voltage drop (power loss) at high current. Current sharing depends on the
resistance match including both the rDS(on), connection resistance, and thermal coupling.
The TPS2419 may only be operated without an RSET programming resistor if the loading provides a V(A-C)
greater than 3 mV. A negative turnoff threshold reduces sensitivity to false tripping due to noise on the bus, but
permits larger static reverse current. Installing a resistor from RSET to ground creates a negative shift in the
turn-off threshold per Equation 2.
æ
ç
ç
è
ö
÷
÷
ø
-470.02
- 0.00314
R
=
(RSET)
V
(OFF)
(2)
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SLVS998A –FEBRUARY 2010–REVISED MARCH 2010
To obtain a -10 mV turnoff ( V(A) is less than V(C) by 10 mV ), R(RSET) = (–470.02/ ( –0.01–0.00314) ) ≈ 35.7 kΩ. If
a 10 mΩ rDS(on) MOSFET was used, the reverse turnoff current would be calculated as follows.
V
(THRESHOLD)
I
=
(TURN_OFF)
r
DS(on)
-10 mV
10 mW
I
I
=
=
(TURN_OFF)
- 1 A
(TURN_OFF)
(3)
The sign indicates that the current is reverse, or flows from the MOSFET drain to source ( C to A ).
The turn-off speed of a MOSFET is influenced by the effective gate-source and gate-drain capacitance CISS).
Since these capacitances vary a great deal between different vendor parts and technologies, they should be
considered when selecting a MOSFET where the fastest turn-off is desired.
GATE DRIVE, CHARGE PUMP AND C(BYP)
Gate drive of 290 mA typical is generated by an internal charge pump and current limiter. Make sure to use low
impedance traces and good bypass on A and C to avoid having the large charge pump currents interfere with
voltage sensing. The GATE drive voltage is referenced to V(A) as GATE will only be driven high when V(A) > V(C)
.
The capacitor on BYP (bypass) must be used in order to form a quiet supply for the internal high-speed
comparator.
Gate Drive Resistance and Output Transients
The strong gate (pulsed) pull-down current can turn the ORing MOSFET(s) off in the 100 - 200 ns time frame.
While this serves to rapidly stop the reverse current buildup, it has a side effect of inducing a voltage transient on
the input bus, the output bus, and ground. One transient source is the GATE turn-off current itself, which excites
parasitic L-C tank circuits. A second transient source is the energy stored in power bus inductance driving a
voltage surge and ringing as reverse MOSFET current is interrupted. Both of these effects can be reduced by
limiting the GATE discharge current with a series resistor in the 10 Ω to 200 Ω range. This both reduces the peak
discharge current, and slows the MOSFET turnoff, reducing the di/dt. A careful tradeoff of peak reverse current
and the effects of the voltage transient may be required.
An example of turnoff speed with and without GATE resistance is illustrated by the circuit of Figure 13. Figure 14
and Figure 15 show GATE, the MOSFET gate, and VC-ac for similar turnoff transients and gate resistors of 0 Ω
and 51 Ω. A substancial reduction in noise is shown for a difference of 90ns in actual current termination. These
techniques may be used in conjunction with clamping and snubbing techniques discussed in RECOMMENDED
OPERATING RANGE. Figure 13 also demonstrates the filtering discussed in the next section.
0.47mF
VIN
VOUT
M1, M2
CSD16401
RSET
“1”
EN
Figure 13. Circuit for Gate Resistor Waveforms
Copyright © 2010, Texas Instruments Incorporated
13
Product Folder Link(s): TPS2419
TPS2419
SLVS998A –FEBRUARY 2010–REVISED MARCH 2010
www.ti.com
Configuration: 2 x ( CSD16401,
TI with 0W gate resistors)
V
C Output
MOSFET
stops conducting
VGATE_MOSFET
VGATE_2419
Time 50ns/DIV
Figure 14. Gate Turnoff Waveforms with RGATE = 0Ω
Configuration: 2 x ( CSD16401,
TI with 51W in gate)
V
C Output
MOSFET
stops conducting
VGATE_MOSFET
VGATE_2419
Time 50ns/DIV
Figure 15. Gate Turnoff Waveforms with RGATE = 51Ω
14
Copyright © 2010, Texas Instruments Incorporated
Product Folder Link(s): TPS2419
TPS2419
www.ti.com
SLVS998A –FEBRUARY 2010–REVISED MARCH 2010
Input Filtering
Voltage transients, converter switching noise and ripple, and ringing due to current interruptions can potentially
cause undesired on-off cycling, especially at very light loads. This includes voltage gradients (especially at MHz
frequencies) across the ground plane effecting the apparent V(A) and V(C). The effects of these unwanted signals
can be reduced by providing input filtering as shown in Figure 16 and Figure 13. There are two potential
problems that the filter might have to help with, 1) internally generated switching noise, and 2) fast ringing
transients caused by nearby power system events. Case 2 (in Figure 16) filtering is better at suppressing internal
switching noise and Case 1 is better for large bus transients in the megahertz range. The "Z" element in CASE 1
is a high-impedance ferrite bead with low resistance to limit the dc voltage error. The L-C filter limits the apparent
V(A) voltage swings during high-speed transients. The L-C in series with A also causes a phase delay in sensed
steady-state switching noise, creating an apparent additional V(AC)
.
The filter capacitors should be located close to the TPS2419's GND pin and be connected to GND by a solid
plane. The A-C capacitor should be located directly across the TPS2419 pins. These values were empirically
chosen in a particular test setup and may have to be tuned for different systems.
The waveform of Figure 17 shows turnon in the presence of 135 mVpp ripple by the circuit of Figure 13. The
ORing circuit was loaded with 10 kΩ parallel to 0.1 µF, and had only a -4.5 mV turnoff threshold. This condition is
often difficult to turn on into due to the V(A-C) difference that occurs when the MOSFET diode peak charges the
output. The output voltage was monitored with the oscilloscope probe ac-coupled, causing visual artifacts due to
the probe settling time. The increase in output ripple is evident as the dynamic impedance of the MOSFET diode
is shorted by the channel resistance.
Selection of the A and C sense points can also play a role in limiting unwanted turnoff events. Sensing voltages
at bus bypass capacitors may benefit operation by limiting the apparent switching and transient noise.
The TPS2419 uses C as both a voltage sense and power pin. Placing resistance in this lead will cause a
reduction in V(C) due to IxR voltage drop, changing the apparent turnon and turnoff thresholds.
CASE 2
CASE 1
FROM “GATE”
FROM “GATE”
Z = 600W,
0.1W, 2A
0.47mF
0.47mF
TO “A”
TO “C”
0.47mF
TO “C”
1W
TO “A”
0.47mF
0.47mF
0.47mF
Figure 16. Input Filtering Configurations
Copyright © 2010, Texas Instruments Incorporated
15
Product Folder Link(s): TPS2419
TPS2419
SLVS998A –FEBRUARY 2010–REVISED MARCH 2010
www.ti.com
135mVPP
VC Output
VC = 12 V,
Load = 10 kW || 0.1mF
VA-C
Note slight (-) offset
in differential probe
15V
10V
VGATE
Time 10ms/DIV
Figure 17. Turnon with Noisy Power Rail
SUMMARIZED DESIGN PROCEDURE
The following is a summarized design procedure:
1. Noise voltage and impedance at the A and C pins should be kept low. A minimum 0.01 mF or more may be
required.
2. Select C(BYP) as 2200 pF, X7R, 25-V or 50-V ceramic capacitor.
3. Select the MOSFET based on considerations of voltage drop, power dissipated, voltage ratings, and gate
capacitance. See sections: MOSFET Selection and RSET.
4. Select R(RSET) based on which MOSFET was chosen and reverse current considerations – see MOSFET
Selection and RSET.
5. Make sure to connect RSVD to ground
Layout Considerations
1. The TPS2419, MOSFET, and associated components should be used over a ground plane.
2. The GND connection should be short and wide, with multiple vias to ground.
3. A and C bypass capacitors should be adjacent to the pins with a minimal ground connection length to the
plane.
4. The GATE connection should be short and wide (e.g., 0.025" minimum).
5. Route the A and C sense lines away from noisy sources, and avoid large ground bounce between the
MOSFET and TPS2419.
6. R(SET) should be kept immediately adjacent to the TPS2419 with short leads.
7. C(BYP) should be kept immediately adjacent to the TPS2419 with short leads.
16
Copyright © 2010, Texas Instruments Incorporated
Product Folder Link(s): TPS2419
TPS2419
www.ti.com
SLVS998A –FEBRUARY 2010–REVISED MARCH 2010
REVISION HISTORY
Changes from Original (February 2010) to Revision A
Page
•
•
Changed the data sheet From: Preview To: Production Data .............................................................................................. 1
Changed the Overview section - paragraph 2 From: MOSFET gate is initially low, and V(AC) is less than 64 mV. To:
MOSFET gate is initially at GND, and V(A-C) is less than 65 mV. ........................................................................................ 10
•
•
Changed the Overview section - paragraph 2, From: The TPS2419 turns on the MOSFET gate, and charges it to
V(BYP) once the turn-on threshold is exceeded. To: When the turn-on threshold is exceeded, the TPS2419 turns on
the MOSFET gate, and charges it to V(BYP) ........................................................................................................................ 10
Changed the Overview section - paragraph 3 From: The ORed input supply will experience a momentary large load
as the MOSFET turns on, shorting the internal diode and charging the bus capacitance. To: The ORed input supply
will experience a momentary large current draw as the MOSFET turns on, shorting the internal diode and charging
the bus capacitance. ........................................................................................................................................................... 10
•
Changed the RECOMMENDED OPERATING RANGE section, paragraph 1 From: The TPS2419 will operate
properly up to the absolute maximum voltage ratings on A, C, and VDD. To: The TPS2419 will operate properly up to
the absolute maximum voltage ratings on A and C. ........................................................................................................... 12
Copyright © 2010, Texas Instruments Incorporated
17
Product Folder Link(s): TPS2419
PACKAGE OPTION ADDENDUM
www.ti.com
24-Mar-2010
PACKAGING INFORMATION
Orderable Device
TPS2419D
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SOIC
D
8
8
8
8
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TPS2419DR
SOIC
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TPS2419PW
TPS2419PWR
TSSOP
TSSOP
PW
PW
150 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
M
0,10
0,65
14
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
8
14
16
20
24
28
DIM
3,10
2,90
5,10
4,90
5,10
4,90
6,60
6,40
7,90
9,80
9,60
A MAX
A MIN
7,70
4040064/F 01/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
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