TPS2459RHBR [TI]
具有 ORing 和 I2C 的 3V 至 15V 热插拔控制器 | RHB | 32 | -40 to 85;
| 型号： | TPS2459RHBR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有 ORing 和 I2C 的 3V 至 15V 热插拔控制器 | RHB | 32 | -40 to 85 控制器 电源管理电路 电源电路 |
| 文件： | 总44页 (文件大小：977K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPS2459
www.ti.com ............................................................................................................................................................................................ SLUS917–FEBRUARY 2009
12-V/3.3-V Hot Swap and ORing Controller with I2C™
and Load Current Monitor for AdvancedMC™
1
FEATURES
APPLICATIONS
•
•
•
•
•
ATCA Carrier Boards
MicroTCA™Power Modules
AdvancedMC™ Slots
Systems Using 12-V and 3.3-V Channels
Base Stations
23
•
ATCA AdvancedMC™ Compliant
•
•
•
•
Full Power Control for an AdvancedMC™
Module
Independently Programmable 12-V Current
Limit and Fast Trip
3.3-V and 12-V FET ORing Control for
MicroTCA™
DESCRIPTION
12-V Output Shuts Off If 3.3-V Output Shuts
Off
The TPS2459 hot-plug controller performs all
necessary power interface functions for an
AdvancedMC™ (Advanced Mezzanine Card). A fully
integrated 3.3-V channel provides inrush control,
over-current protection, and FET ORing. A 12-V
channel provides the same functions using external
FETs and sense resistors. The 3.3-V current limit is
factory set to AdvancedMC™ compliant levels while
the 12-V current limit is programmed using external
sense resistors. The accurate current sense
comparators of the TPS2459 satisfy the narrow
ATCA™ AdvancedMC™ current limit requirements.
•
•
•
•
•
•
Internal 3.3-V Current Limit and ORing
I2C™ Power Good and Fault Reporting
I2C™ Programmable Fault Times and Limits
FET Status Bits for 3.3-V and 12-V Channels
Load Current Monitors for 12-V and 3.3-V
32-Pin QFN Package
TYPICAL APPLICATION
0.005 W
12 V
12 V
V
IN
422 W
AdvancedMCTM
15
14
13
12
11
6
8
3.3 V
IN12 SENP SET
SENM PASS BLK OUT12 OUT3 17
3.3 V
16 IN3
22
V
IN
PG12
4
7
VDD3
FLT12
28 EN12
26 EN3
Status Outputs
PG3 20
FLT3 19
Enable
{
{
TPS2459
10 OREN
6810 W
3320 W
2
3
SDA
SCL
2
SUM12
5
I C Interface
SUM3 21
1
VINT
A0 A1 A2
30 18 25
GND
UDG-09031
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
3
AdvancedMC, MicroTCA are trademarks of PCI Industrial Computer Manufacturers Group.
I2C is a trademark of Phillips.
PRODUCT PREVIEW information concerns products in the
formative or design phase of development. Characteristic data and
other specifications are design goals. Texas Instruments reserves
the right to change or discontinue these products without notice.
Copyright © 2009, Texas Instruments Incorporated
TPS2459
SLUS917–FEBRUARY 2009............................................................................................................................................................................................ www.ti.com
ORDERING INFORMATION
DEVICE
TEMPERATURE
PACKAGE
ORDERING CODE
MARKING
TPS2459
-40°C to 85°C
QFN-32
TPS2459RHB
TPS2459
ABSOLUTE MAXIMUM RATINGS(1)
over –40°C ≤ TJ ≤ 85°C (unless otherwise noted)
VALUE
0 to 30
0 to 17
0 to 5
UNIT
BLK, PASS
IN12, OUT12, SENM, SENP, SET
EN3, EN12, IN3, OUT3, OREN, SCL, SDA, SUM, VDD,
V
AGND, GND
–0.3 to 0.3
A0, A1, A2
0 to VINT
Human Body Model
Charged Device Model
SUMx
2
0.5
ESD
kV
5
VINT
–1 to 1
250
mA
OUT3 continuous current
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only. Functional operation of the device under any conditions beyond those indicated under recommended operating conditions is
neither implied nor guaranteed. Exposure to absolute maximum rated conditions for extended periods of time may affect device
reliability.
DISSIPATION RATINGS
PACKAGE
θJA HIGH-K (°C/W)
θJA LOW-K (°C/W)
QFN32 - RHB
34
93
RECOMMENDED OPERATING CONDITIONS
over –40°C ≤ TJ ≤ 85°C (unless otherwise noted)
PARAMETER
MIN
8.5
3
TYP
12
MAX
UNIT
VIN12
VIN3
12-V input supply
15
4
3.3
3.3
V
3.3-V input supply
VVDD3
IOUT3
ISUMx
3
4
3.3-V output current
165
1000
1
mA
Summing pin current
100
10
µA
PASS pin board leakage current
VINT bypass capacitance
Operating junction temperature range
-1
1
250
125
nF
°C
TJ
-40
2
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TPS2459
www.ti.com ............................................................................................................................................................................................ SLUS917–FEBRUARY 2009
ELECTRICAL CHARACTERISTICS
over –40°C ≤ TJ ≤ 85°C, VIN3 =VVDD3 = 3.3 V, VIN12 = VSENP = VSENM = VSETP = 12 V, VEN3=VEN12=logic 1 or open, VAGND
=
VGNDA = VGNDB = 0 V, VSUM12 = 6.8 kΩ to GND, , VSUM3 = 3.3 kΩ to GND. All other pins OPEN, all I2C™ bits at different values,
all voltages referenced to GND. (unless otherwise noted)
PARAMETER
CONDITIONS
MIN
TYP
MAX UNITS
ENABLE INPUTS
Threshold voltage, falling edge
Hysteresis
1.2
20
5
1.3
50
8
1.4
80
15
15
5
V
mV
Pullup current
VEN =VOREN = 0 V
VEN12 =VOREN = 17 V
6
mA
mS
Input bias current
VEN3 = 5 V
1
3.3-V Turn off time
EN3 deasserts to VVOUT3 < 1.0 V, COUT = 0 µF
10
EN12 deasserts to VVOUT12 < 1.0 V, COUT = 0 µF, CQGATE
= 35 nF
12-V Turn off time
20
POWER GOOD COMPARATORS
PG12, falling OUT12
10.2
2.7
10.5
2.8
130
50
10.8
2.9
Threshold voltage
Hysteresis
V
PG3, falling OUT3
PG12, measured at OUT12
PG3, measured at OUT3
mV
INTERNAL 2.35-V RAIL
Output voltage
0 V < IVINT < 50 µA
2.0
2.3
2.8
V
FAULT TIMER
Minimum fault time
Fault time bit weight
Retry duty cycle
3FT[4:0] = 12FT[4:0] = 00001B
D = tFAULT/tDELAY
1
0.5
1.5
ms
1.4%
1.6%
1.5
12-V SUMMING NODE
10.8 V ≤ VSENM ≤ 13.2 V, VSENP = (VSENM + 50 mV),
measure VSET– VSENM
Input referred offset
–1.5
0.66
mV
Summing threshold
Leakage current
12CL[3:0] = 1111B, VPASS = 15 V
VSET =(VSENM – 10 mV)
0.675
50
0.69
1
V
mA
12-V CURRENT LIMIT
RSUM = 6.8 kΩ, RSET = 422 Ω, increase ILOAD and
measure VSENP – VSENM when VPASS = 15 V
Current limit threshold
47.5
52.5
mV
Sink current in current limit
Fast trip threshold
IPASS measured at VSUM = 1 V and VPASS = 12 V
Measure VSENP – VSENM
20
80
40
120
300
2.1
mA
mV
ns
100
200
1.6
Fast turn-off delay
20 mV overdrive, CPASS = 0 pF, tp50-50
VOUT = 6 V
Bleed-down resistance
Bleed-down threshold
1.1
75
kΩ
mV
100
130
VPASS - VIN when timer starts, while VPASS falling due to
overcurrent
Timer start threshold
5
6
7
V
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ELECTRICAL CHARACTERISTICS (continued)
over –40°C ≤ TJ ≤ 85°C, VIN3 =VVDD3 = 3.3 V, VIN12 = VSENP = VSENM = VSETP = 12 V, VEN3=VEN12=logic 1 or open, VAGND
=
VGNDA = VGNDB = 0 V, VSUM12 = 6.8 kΩ to GND, , VSUM3 = 3.3 kΩ to GND. All other pins OPEN, all I2C™ bits at different values,
all voltages referenced to GND. (unless otherwise noted)
PARAMETER
CONDITIONS
MIN
TYP
MAX UNITS
12-V UVLO
UVLO rising
IN12 rising
IN12 falling
8.1
8.5
0.5
8.9
V
UVLO hysteresis
12-V BLOCKING
Turn-on threshold
Turn-off threshold
Turn-off delay
0.44
0.59
Measure VSENP – VVOUT
5
10
–3
15
mV
0
Measure VSENP – VVOUT
–6
20-mV overdrive, CBLK = 0 pF, tP50-50
200
300
ns
12-V GATE DRIVERS (PASS, BLK)
Output voltage
VVIN12 = VVOUT12 = 10 V
21.5
20
0.5
6
23
30
1
24.5
40
V
Sourcing current
VVIN12 = VVOUT12 = 10 V, VPASS= VBLK = 17 V
Fast turnoff, VPASS = VBLK = 14 V
4 V ≤ VPASS = VBLK ≤ 25 V
mA
A
Sinking current
14
20
10
25
26
mA
kΩ
µs
Pulldown resistance
Fast turn-off duration
Startup time
In OTSD ( at 150°C )
14
5
15
IN12 rising to PASS and BLK sourcing
0.25
ms
3.3-V SUMMING NODE
Summing threshold
3.3-V CURRENT LIMIT
On-resistance
655
675
695
mV
IOUT3 = 150 mA
290
195
300
750
400
100
500
225
mΩ
Current limit
RSUM3 = 3.3 kΩ , VVOUT3 = 0 V
170
240
mA
Fast trip threshold
Fast turn-off delay
Bleed-down resistance
Bleed-down threshold
3.3-V UVLO
400
IOUT3= 400 mA, tP50-50
VOUT3= 1.65 V
1300
500
ns
Ω
280
75
130
mV
UVLO rising
IN3 rising
IN3 falling
2.65
200
2.75
240
2.85
300
V
UVLO hysteresis
3.3-V BLOCKING
Turn-on threshold
Turn-off threshold
mV
Measure VIN3 – VOUT3
Measure VIN3 – VOUT3
5
10
–3
15
0
mV
mV
–5
VIN3 = 3.3 V, VOUT3 = 3.5 V, ROUT3 = 100 Ω to GND,
VORON = 1. Remove 3.5 V from OUT3. Measure time from
VOUT3 decreasing thru 2.9 V to VOUT3 = 3.2 V
ORing turn-on delay time
Fast turnoff delay time
300
250
350
µs
20 mV overdrive, tP50-50
350
15
ns
(1)
Safety gate pulldown current
Slew IN3x, Out3x, 5-V in 1 µs
mA
SUPPLY CURRENTS (IIN+ISENP+ISENM+ISET+IVDD
)
Both channels enabled
Both channels disabled
THERMAL SHUTDOWN
IOUT3A = IOUT3B= 0
3.1
2.0
4
mA
°C
2.8
Whole-chip shutdown
temperature
TJ rising, IOUT3A = IOUT3B= 0 A
140
130
150
3.3-V channel shutdown
temperature
TJ rising, IOUT3A or IOUT3B in current limit
Whole chip or 3.3-V channel
140
10
Hysteresis
(1) When setting an address bit to a logic 1 the pin should be connected to VINT.
4
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www.ti.com ............................................................................................................................................................................................ SLUS917–FEBRUARY 2009
ELECTRICAL CHARACTERISTICS (continued)
over –40°C ≤ TJ ≤ 85°C, VIN3 =VVDD3 = 3.3 V, VIN12 = VSENP = VSENM = VSETP = 12 V, VEN3=VEN12=logic 1 or open, VAGND
=
VGNDA = VGNDB = 0 V, VSUM12 = 6.8 kΩ to GND, , VSUM3 = 3.3 kΩ to GND. All other pins OPEN, all I2C™ bits at different values,
all voltages referenced to GND. (unless otherwise noted)
PARAMETER
CONDITIONS
MIN
TYP
MAX UNITS
I2C™ SERIAL INTERFACE (SDA, SCL, A0, A1, A2)
Lower logic threshold
Upper logic threshold
Input pullup resistance
Input pulldown resistance
Input open-circuit voltage
Threshold voltage, rising
Threshold voltage, falling
Hysteresis
A0, A1, A2
A0, A1, A2
A0, A1, A2, (VAx – 0 V)
A0, A1, A2, (VAx – VVINT
IA = 0 V
0.33
1.32
400
200
0.5
0.35
1.35
700
350
0.8
0.37
1.38
1000
550
1.0
V
V
kΩ
kΩ
V
(2)
)
SDA, SCL
SDA, SCL
SDA, SCL
SDA, SCL
SCL
2.3
V
1.0
V
165
mV
µA
kHz
V
Leakage
1
400
0.4
Input clock frequency
Low-level output voltage
Input clock low duration
Input clock high duration
Data setup time
ISDA = 3 mA
SCL
1.3
0.6
100
300
21
µs
µs
ns
ns
SCL
SDA
Data hold time
SDA
900
250
250
50
SDA, 2.3 V–1.0 V, CBUS = 10 pF
SDA, 2.3 V–1.0 V, CBUS = 400 pF
SDA, pulse width suppressed
CSDA, CSCL
Output fall time
ns
60
Deglitch time
Capacitance
0
ns
10
pF
(2) When setting an address bit to a logic 1 the pin should be connected to VINT.
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TPS2459 FUNCTIONAL BLOCK DIAGRAMS
12-V Channel Circuitry
RSENSE
RSET
SENP
SET
SENM
PASS
BLK
OUT12
pgat\
100 mv
12dis
+
30 uA
30 uA
ogat
Q
Pump
IN12
10 us
10 us
Fault
Timer
Vcp
~25 v
CT12
Vcp
FLT12
to I2C
EN12
PG3\
+
to I2C
SUM12
675 mV x (12xCL/1111)
pgat\
RSUM
6810
10 mv
-3 mv
vpg
PG12
100 us
+
+
R
Q
+
ogat
OUT
out12
S
Q
12OR
[R3:7]
OREN
Optional Oring FET for Redundant Power Feed Systems
6
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3.3-V Channel Circuitry
0.1 W
IN3
OUT3
2.8 V
96 W
gat
en
30 mv
30 us
+
PG3
12dis
30 uA
Q
Pump
VDD3
Fault
Timer
PG3
to I2C
vcpx
vcpx
~25 v
FLT3
30 us
EN3
Control
Logic
SUM3
FLT3
to I2C
RSUM
3300
+
vthoc - [ 675 mV nominal ]
Circuitry Common to Both Channels
IN12A
VINT
en
por
IN12B
IN3A
PREREG
POR
IN3B
2.2 V
I2C
OUT12A
OUT12B
OUT3A
OUT3B
SDA
SCL
A0-2
AGND
GNDA
GNDB
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DEVICE INFORMATION
TPS2459
(Top View)
32 31 30 29 28 27 26 25
24
23
22
21
20
19
18
17
GNDS
AGND
VINT
SDA
1
2
3
4
5
6
7
8
VDD3
SUM3
PG3
SCL
3-V
Inputs
PG12
SUM12
BLK
12-V
Inputs
TM
PowerPAD
FLT3
A1
FLT12
OUT12
OUT3
9
10 11 12 13 14 15 16
12-V Inputs
Figure 1.
TERMINAL FUNCTIONS
PIN
NO.
NAME
A0
I/O
DESCRIPTION
30
18
25
I
I
I
I2C™ address programming bit, LSB
I2C™ address programming bit, LSB+1
I2C™ address programming bit, LSB+2
A1
A2
Analog ground. Ground pin for the analog circuitry insideBypass capacitor connection point for internal supply
the TPS2459.
AGND
23
—
12-V blocking transistor gate drive. Gate drive pin for the 12-V channel BLK FET. This pin sources 30 µA to
turn the FET on. An internal clam prevents this pin from rising more than 14.5 V above OUT12. Setting the
OREN pin high holds the BLK pin low.
BLK
6
O
12-V enable. (active high). Pulling this pin low turns off the 12-V channel by pulling both BLK and PASS low.
An internal 200-kΩ resistor pulls this pin up to VINT when disconnected.
EN12
EN3
28
26
7
I
3-V enable. (active high) Pulling this pin low turns off the 3-V channel by pulling the gate of the internal pass
FET to GND. An internal 200-kΩ resistor pulls this pin up to VINT when disconnected.
I
12-V fault output (active low) Open-drain output indicating that channel 12 has remained in current limit long
enough to time out the fault timer and shut the channel down. asserted when 12-V fault timer runs out
FLT12
FLT3
O
O
3-V fault output (active low) Open-drain output indicating that channel 3 has remained in current limit long
enough to time out the fault timer and shut the channel down. asserted when 3-V fault timer runs out
19
GNDA
GNDB
GNDE
GNDN
GNDS
IN3
29
9
—
—
12-V power ground.
27
31
24
16
15
32
Ground.
I
I
3-V input. Supply pin for the 3-V channel internal pass FET.
12-V input. Supply pin for 12-V channel internal circuitry.
No connection.
IN12
NC
—
8
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TERMINAL FUNCTIONS (continued)
PIN
NO.
NAME
I/O
DESCRIPTION
12-V blocking transistor enable. (active high). Pulling this pin high (or allowing it to float high) allows the 12-V
channel ORing function to operate normally. Pulling this pin low disables the 12-V ORing function by pulling
the BLK pin low. An internal 200-kΩ resistor pulls this pin up to VINT when disconnected.
OREN
10
I
OUT12
OUT3
8
I/O
I/O
12-V output. Senses the output voltage of the 12-V channel.
3-V output. Output of the 3-V channel internal pass FET.
17
12-V pass transistor gate drive. This pin sources 30 µA to turn the FET on. An internal clamp prevents this pin
from rising more than 14.5 V above IN12.
PASS
PG12
PG3
12
4
O
O
O
12-V power good output,asserts when VOUT12 > VPG12 ( active low) . Open-drain output indicating that channel
12 output voltage has dropped below the PG threshold, which nominally equals 10.5 V.
3-V power good output, asserts when VOUT3 > 2.8 V ( active low) . Open-drain output indicating that channel 3
output voltage has dropped below the PG threshold, which nominally equals 2.85 V.
20
SCL
3
2
I
Serial clock input for the I2C™ data line. (See TPS2459 I2C™ Interface section for details.
Bidirectional I2C™ data line. (See TPS2459 I2C™ Interface section for details.
SDA
I/O
SENM
SENP
12
14
I
I
12-V current limit sense. Senses the voltage on the low side of the 12-V channel current sense resistor.
12-V input sense. Senses the voltage on the high side of the 12-V channel current sense resistor.
12-V current limit set. A resistor connected from this pin to SENP sets the current limit level in conjunction with
the current sense resistor and the resistor connected to the SUM12 pin, as described in 12-V thresholds,
setting current limit and fast overcurrent trip section.
SET
13
5
I
12-V summing node. A resistor connected from this pin to ground forms part of the channel x current limit. As
the current delivered to the load increases, so does the voltage on this pin. When the voltage on this pin
reaches 675 mV, the current limit amplifier acts to prevent the current from further increasing.
SUM12
I/O
3-V summing node. A resistor connected from this pin to ground forms part of the channel x current limit. As
the current delivered to the load increases, so does the voltage on this pin. When the voltage on this pin
reaches 675 mV, the current limit amplifier acts to prevent the current from further increasing.
SUM3
VDD3
VINT
21
22
1
I/O
I
3-V charge pump input
Bypass capacitor connection point for internal supply. This pin connects to the internal 2.35-V rail. A 0.1-µF
capacitor must be connected from this pin to ground. Do not connect other external circuitry to this pin
except the address programming pins, as required.
I/O
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TYPICAL CHARACTERISTICS
ORING TURN-OFF THRESHOLD
vs
JUNCTION TEMPERATURE
ORING TURN-ON THRESHOLD
vs
JUNCTION TEMPERATURE
12
11
10
9
0
–1
–2
–3
–4
8
–5
-50
0
50
100
150
-50
0
50
100
150
TJ – Junction Temperature – °C
TJ – Junction Temperature – °C
Figure 2.
Figure 3.
12-V TURN OFF VOLTAGE THRESHOLD
12-V TURN ON THRESHOLD
vs
JUNCTION TEMPERATURE
vs
JUNCTION TEMPERATURE
0
12.0
11.5
11.0
10.5
10.0
9.5
-1
-2
-3
-4
-5
9.0
8.5
8.0
-50
0
50
100
150
-50
0
50
100
150
TJ – Junction Temperature – °C
TJ – Junction Temperature – °C
Figure 4.
Figure 5.
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TYPICAL CHARACTERISTICS (continued)
12-V INPUT CURRENT
vs
JUNCTION TEMPERATURE
3-V INPUT CURRENT
vs
JUNCTION TEMPERATURE
2.4
2.3
2.2
2.1
2.0
0.26
V
= 12 V
IN
0.25
0.24
0.23
0.22
0.21
0.20
-50
0
50
100
150
-50
0
50
100
150
TJ – Junction Temperature – °C
TJ – Junction Temperature – °C
Figure 6.
Figure 7.
12-V INPUT CURRENT
vs
INPUT VOLTAGE
12-V CURRENT LIMIT THRESHOLD VOLTAGE
vs
JUNCTION TEMPERATURE
2.45
2.40
51.0
50.8
V
= 12 V
IN
2.35
2.30
50.6
50.4
2.25
2.20
50.2
50.0
2.15
2.10
10
11
12
13
14
-50
0
50
100
150
TJ – Junction Temperature – °C
VIN – Input Voltage – V
Figure 8.
Figure 9.
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TYPICAL WAVEFORMS
Figure 10. OUT3 Startup Into 22-Ω, (150 mA), 150-µF Load
Figure 11. OUT3 Load Stepped from 165 mA to 240 mA
.
.
.
.
Figure 12. OUT3 Short Circuit Under Full Load, (165 mA),
Figure 13. OUT3 Short Circuit Under Full Load, (165 mA),
Zoom View
Wide View
.
.
.
.
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TYPICAL WAVEFORMS (continued)
Figure 14. OUT3 Startup Into Short Circuit
Figure 15. OUT12 Startup Into 500-Ω, 830-µF Load
.
.
.
.
Figure 16. OUT12 Startup Into 80-W, 830-µF Load
Figure 17. OUT12 Short Circuit Under Full Load, (6.7 A),
.
Wide View
.
.
.
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TYPICAL WAVEFORMS (continued)
Figure 18. OUT12 Short Circuit Under Full Load, (6.7 A),
Figure 19. OUT12 Startup Into Short Circuit
Zoom View
.
.
.
.
Figure 20. OUT12 Overloaded While Supplying 6.7 A
.
.
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Control and Status Registers
Seven 8-bit registers are used to control and read the status of the TPS2459. Registers 3 and 4 control the 12-V
channel. Rregister 5 controls the 3-V channel. Register 6 contains eight general configuration bits. Read-only
registers 7, 8, and 9 report back system status to the I2C™ controller. All ten registers use the I2C™ protocol and
are organized as follows shown in Table 1.
Table 1. Top Level Register Functions
FUNCTION
VOLTAGE (V)
REGISTE
R
DESCRIPTION
READ WRITE
3.3
12
Set 12-V current limit, power good level, and OR
functions
3
√
√
√
√
4
5
6
7
8
9
√
√
√
√
√
√
Set 12-V fault time, enable, and bleed-down functions
Set 3-V fault time, enable, and bleed-down functions
System configuration controls
√
√
√
√
√
√
√
√
Fault and PG outputs
Overcurrent and fast trip indicators are latched
Channel status indicators
√
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Summary of Registers
Table 2. Summary of Registers
BIT
NAME
DEFAULT
DESCRIPTION
12-V CHANNEL CONFIGURATION
REGISTER 3 READ/WRITE
0
1
2
3
4
5
6
7
12CL0
12CL1
12CL2
12CL3
12PG0
12PG1
12HP
1
1
1
1
1
1
0
1
Clearing bit reduces 12-V current limit and fast threshold by 5%.
Clearing bit reduces 12-V current limit and fast threshold by 10%.
Clearing bit reduces 12-V current limit and fast threshold by 20%.
Clearing bit reduces 12-V current limit and fast threshold by 40%.
Clearing bit reduces 12-V power good threshold by 600 mV.
Clearing bit reduces 12-V power good threshold by 1.2 V.
Setting bit shifts 12 OR VTURNOFF from –3 mV to +3 mV nominal.
Clearing bit turns off 12-V ORing FET by pulling BLK low.
12-V CHANNEL CONFIGURATION
12OR
REGISTER 4 READ/WRITE
0
1
2
3
4
5
6
7
12FT0
12FT1
12FT2
12FT3
12FT4
12EN
12UV
12DS
1
0
0
0
0
0
0
0
Setting bit increases 12-V fault time by 0.5 ms.
Setting bit increases 12-V fault time by 1 ms.
Setting bit increases 12-V fault time by 2 ms.
Setting bit increases 12-V fault time by 4 ms.
Setting bit increases 12-V fault time by 8 ms.
Clearing bit disables 12-V by pulling PASSB and BLKB to 0 V.
Setting bit prevents enabling unless OUT12 < bleed-down threshold.
Clearing bit disconnects OUT12 bleed-down resistor.
3.3-V CHANNEL CONFIGURATION
REGISTER 5 READ/WRITE
0
1
2
3
4
5
6
7
3FT0
3FT1
3FT2
3FT3
3FT4
3EN
1
0
0
0
0
0
0
0
Setting bit increases 3 V fault time by 0.5 ms.
Setting bit increases 3 V fault time by 1 ms.
Setting bit increases 3 V fault time by 2 ms.
Setting bit increases 3 V fault time by 4 ms.
Setting bit increases 3 V fault time by 8 ms.
Clearing bit disables 3 V.
3UV
Setting bit prevents enabling unless OUT3B < bleed-down threshold.
Clearing bit disconnects OUT3B bleed-down resistor.
SYSTEM CONFIGURATION
3DS
REGISTER 6 READ/WRITE
0
PPTEST
0
0
12-V pulldown test pin. Setting pin pulls the PASS and BLK pins to 0 V.
Clearing bit latchs off channels after over-current fault. Setting bit allows channels to
automatically attempt restart after fault.
1
FLTMODE
2
3
ENPOL
3ORON
0
0
Setting bit makes EN3 and EN12 pins active low.
Setting bit enables 3-V channel to prevent reverse current flow.
Non Redundant System in rush control bit. Setting bit allows increased inrush current in
12-V channel .
4
12VNRS
0
5
6
DISA
spare
0
0
This bit must be set to 1
Setting bit allows the 12-V channels to operate despite loss of 3.3-V. This bit should be low
for µTCA and AMC applications
7
DCC
0
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Table 2. Summary of Registers (continued)
BIT
NAME
DEFAULT
DESCRIPTION
REGISTER 7 READ ONLY
LATCHED CHANNEL STATUS INDICATORS, CLEARED ON READ
0
1
spare
—
2
3
4
5
6
7
12PG
12FLT
3PG
0
0
0
0
Latches high when OUT12 goes from above VTH_PG to below VTH_PG.
Latches high when 12 fault timer has run out.
Latches high when OUT3 goes from above VTH_PG to below VTH_PG.
Latches high when 3-V fault timer has run out.
3FLT
REGISTER 8 READ ONLY
LATCHED OVERCURRENT INDICATORS, CLEARED ON READ
0
1
spare
—
2
3
4
5
6
7
12OC
12FTR
3OC
0
0
0
0
Latches high when 12-V channel goes into over-current.
Latches high if 12-V fast trip threshold exceeded.
Latches high when 3-V enters over-current.
3FTR
Latches high if 3-V fast trip threshold exceeded.
UNLATCHED FET STATUS INDICATORS
REGISTER 9 READ ONLY
0
1
2
3
4
5
6
7
spare
spare
spare
12BS
12PS
3BS
–
–
–
–
High indicates BLK commanded high.
Low indicates (VPASS > VOUT + 6 V).
Low indicates VIN3 > VOUT3
.
spare
3GS
–
Low indicates 3 V channel gate is driven on VGATE > ( VIN + 1.75 V ).
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DETAILED DESCRIPTION OF REGISTERS
Table 3. Register 3: 12-V Channel Configuration (Read/Write)
BIT
0
NAME
12CL0
12CL1
12CL2
12CL3
12PG0
12PG1
12HP
DEFAULT
DESCRIPTION
1
1
1
1
1
1
0
1
Clearing bit reduces 12-V current limit and fast threshold by 5%.
Clearing bit reduces 12-V current limit and fast threshold by 10%.
Clearing bit reduces 12-V current limit and fast threshold by 20%.
Clearing bit reduces 12-V current limit and fast threshold by 40%.
Clearing bit reduces 12-V power good threshold by 600 mV.
Clearing bit reduces 12-V power good threshold by 1.2 V.
Setting bit shifts 12-V OR VTURNOFF from –3 mV to +3 mV nominal.
Clearing bit turns off 12-V ORing FET by pulling BLK low.
1
2
3
4
5
6
7
12OR
12CL[3:0]
12PG[1:0]
12HP
These four bits adjust the 12-V current limit and fast trip threshold using the I2CTM interface. Setting the bits to 1111B places
the 12-V current limit at its maximum level, corresponding to 675 mV at SUM12. The fast trip threshold then equals 100 mV.
Clearing all bits reduces the current limit and fast trip threshold to 25% of these maximums.
These two bits adjust the 12-V power good threshold. Setting the bits to 11B places the power good threshold at its maximum
level of 10.5 V . Setting the bits to 00B places the threshold at its minimum level of 8.7 V. The lower thresholds may prove
desirable in systems that routinely experience large voltage droops.
Setting this bit moves the 12-V ORing turn off threshold from –3 mV to +3 mV. A positive threshold prevents reverse current
from flowing through the channel, but it may cause the ORing FET to repeatedly cycle on-and-off if the load is too light to
maintain the required positive voltage drop across the combined resistance of the external FETs and the sense resistor. For
further information, see Adjusting ORing Turn Off Threshold For High Power Loads section.
12OR
Clearing this bit forces the BLK pin low, keeping the 12-V ORing FET off. Clearing this bit does not prevent current from
flowing through the FET’s body diode.
.
Table 4. Register 4: 12-V Channel Configuration (Read/Write)
BIT
0
NAME
12FT0
12FT1
12FT2
12FT3
12FT4
12EN
DEFAULT
DESCRIPTION
Setting bit increases 12-V fault time by 0.5 ms.
1
0
0
0
0
0
0
0
1
Setting bit increases 12-V fault time by 1 ms.
2
Setting bit increases 12-V fault time by 2 ms.
3
Setting bit increases 12-V fault time by 4 ms.
4
Setting bit increases 12-V fault time by 8 ms.
5
Clearing bit disables 12-V by pulling PASS and BLK to 0 V.
Setting bit prevents enabling unless OUT12 < bleed-down threshold.
Clearing bit disconnects OUT12 bleed-down resistor.
6
12UV
7
12DS
12FT[4:0]
These five bits adjust the 12-V channel fault time. The least-significant bit has a nominal weight of 0.5 ms, so fault times
ranging from 0.5 ms (for code 00001B) to 15.5 ms (for code 11111B) can be programmed. In general the shortest fault time
that fully charges downstream bulk capacitors without generating a fault should be used. Once the load capacitors have fully
charged, the fault time can be reduced to provide faster short circuit protection. See Setting Fault Time section.
12EN
This bit serves as a master enable for the 12-V channel. Setting the bit allows the 12-V channel to operate normally. Clearing
the bit disables the channel by pulling PASS and BLK low.
12UV
Setting this bit prevents 12-V channel from turning on until VOUT12 falls below the bleed-down threshold of 100 mV. This
feature ensures that downstream devices reset by requiring their supply voltage to fall to nearly zero before the channel can
enable them.
12DS
Clearing this bit disconnects the bleed-down resistor that otherwise connects from OUT12 to ground. Systems using
redundant power supplies should clear 12DS to prevent the bleed-down resistor from continuously sinking current.
.
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Table 5. Register 5: 3.3-V Channel Configuration (Read/Write)
BIT
0
NAME
3FT0
3FT1
3FT2
3FT3
3FT4
3EN
DEFAULT
DESCRIPTION
Setting bit increases 3-V fault time by 0.5 ms.
1
0
0
0
0
0
0
0
1
Setting bit increases 3-V fault time by 1 ms.
Setting bit increases 3-V fault time by 2 ms.
Setting bit increases 3-V fault time by 4 ms.
Setting bit increases 3-V fault time by 8 ms.
Clearing bit disables 3-V.
2
3
4
5
6
3UV
Setting bit prevents enabling unless OUT3 < bleed-down threshold.
Clearing bit disconnects OUT3 bleed-down resistor.
7
3DS
3FT[4:0]
These five bits adjust the 3-V channel fault time. The least-significant bit has a nominal weight of 0.5 ms, so fault times
ranging from 0.5 ms (for code 00001B) to 15.5 ms (for code 11111B) can be programmed. In general the shortest fault time
that fully charges downstream bulk capacitors without generating a fault should be used. See the Setting Fault Time section.
3EN
This bit serves as a master enable for the 3-V channel. Setting this bit allows the 3-V channel to operate normally, provided
the EN3 pin is also asserted. Clearing this bit disables the channel by removing gate drive to the internal pass FET,
regardless of the state of the EN3 pin.
3UV
Setting this bit prevents the 3-V channel from turning on until VOUT3 falls below the bleed-down threshold of 100 mV. This
feature ensures that downstream devices reset by requiring their supply voltage to fall to nearly zero before the channel can
enable them.
3DS
Clearing this bit disconnects the bleed-down resistor that otherwise connects from OUT3 to ground. Systems using redundant
power supplies should clear 3DS to prevent the bleed-down resistor from continuously sinking current.
.
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Table 6. Register 6: System Configuration (Read/Write)
BIT
NAME
DEFAULT
DESCRIPTION
0
PPTEST
0
12V pulldown test pin. Asserting this pulls the PASS and BLK pins to 0 V.
Clearing bit forces channels to latch off after over-current fault. Setting bit allows channels
to automatically attempt restart after fault.
1
FLTMODE
0
Setting bit makes EN3 and EN12 pins active low.Setting bit makes external ENx pins active
low; clearing bit makes pins active high. (Actually, setting this bit reverses polarity of
ENPOL R14[5] which will nominally be set as active low).
2
ENPOL ENP
0
Setting bit enables 3.3-V channel to prevent reverse current flow.Clearing bit disables 3A
and 3B ORing.
3
4
3ORON
12VNRS
0
0
Non-redundant system inrush control bit. Setting bit allows increased inrush current in 12-V
channel
5
6
DISA
spare
0
0
This bit must be set to 1.
Setting bit allows the 12-V channel to operate despite loss of 3.3 V. For µTCA and AMC
applications this bit should be low.
7
DCC
0
PPTEST
This bit is used for testing the fast turnoff feature of the PASS and BLK pins. Setting this bit enables the fast turnoff drivers for
all four pins. Clearing this bit restores normal operation. PPTEST allows the fast turnoff drivers to operate at full current
indefinitely, whereas they would normally operate for only approximately 15 µs. While using PPTEST the energy dissipated in
the fast turnoff drivers must be externally limited to 1 mJ per driver to prevent damage to the TPS2459.
FLTMODE Setting this bit allows a channel to attempt an automatic restart after an overcurrent condition has caused it to time out and
shut off. The retry period equals approximately 100 times the programmed fault time. The FLTMODE bit affects all four
channels. If cross-connection is enabled (DCC = 0), a fault on the 3.3-V channel turns off the 12-V channel. If the 3.3-V
channel automatically restarts because FLTMODE = 1, the 12-V channel remains disabled until its enable bit (12EN) is cycled
off and on.
ENPOL
3ORON
Setting this bit makes the EN12 and EN3 pins active low.
Setting this bit allows the 3.3-V ORing function to operate normally. Clearing this bit prevents a VOUT3 > VIN3 condition from
turning off the 3 V channel and forces 3A / 3B ORing to behave as if IN3A >> OUT3A, and IN3B >> OUT3B... This bit is
typically cleared for non-redundant systems.
12VNRS
Setting this bit increases the current limit for the 12-V channel to its maximum value during the initial inrush period that
immediately follows the enabling of the channel. During inrush, the current limit behaves as if 12CL[3:0] = 1111B. After the
current drops below this limit, signifying the end of the inrush period, the current limit returns to normal operation. This
function is intended for use in non-redundant systems with capacitive loads. Setting this bit forces the 12-V current limiters to
behave as though the current limit adjust bits R0[3:0], R3[3:0] are set to 1111 right after EN asserts and will persist until the
channel comes out of current limit or the fault timer times out, whichever comes first.
DISA
DCC
This bit must be set to 1.
Setting this bit disables cross-connection. If DCC = 0, when the 3.3-V channel experiences a fault, both it and the 12-V
channel turn off. If DCC = 1, then the 12-V channel continues to operate even if the 3.3-V channel experiences a fault.
X
Table 7. Register 7: Latched Channel Status Indicators (Read-only, cleared on read)
BIT
0
NAME
spare
spare
spare
spare
12PG
12FLT
3PG
DEFAULT
DESCRIPTION
1
–
2
3
4
0
0
0
0
Latches high when OUT12 goes from above VTH_PG to below VTH_PG.
Latches high when 12-V fault timer has run out.
5
6
Latches high when OUT3 goes from above VTH_PG to below VTH_PG.
Latches high when 3 V fault timer has run out.
7
3FLT
12PG
This bit is set if the voltage on OUT12 drops below the power-good threshold set by the 12PG[1:0] bits, and it remains set
until Register 7 is read.
12FLT
3PG
This bit is set if the fault timer on the 12-V channel has run out, and it remains set until Register 7 is read.
This bit is set if the voltage on OUT3 drops below the power-good threshold, and it remains set until Register 7 is read.
This bit is set if the fault timer on the 3.3-V channel runs out, and it remains set until Register 7 is read.
3FLT
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Table 8. Register 8: Latched Status Indicators (Read-only, cleared on read)
BIT
0
NAME
spare
spare
spare
spare
12OC
12FTR
3BOC
3BFTR
DEFAULT
DESCRIPTION
1
–
2
3
4
0
0
0
0
Latches high when 12-V channel enters overcurrent.
Latches high if 12-V fast trip threshold exceeded.
Latches high when 3 V channel enters over-current.
Latches high if 3 fV ast trip threshold exceeded.
5
6
7
12OC
12FTR
3OC
3FTR
X
This bit is set if the voltage on the PASS pin drops below the timer start threshold, signifying a current limit condition. This bit
remains set until Register 8 is read.
This bit is set if the voltage across the sense resistor for th 12-V channel exceeds the fast trip threshold. This bit remains set
until Register 8 is read.
This bit is set if the gate-to-source voltage on the 3 V channel pass FET drops low enough to start the fault timer. This bit
remains set until Register 8 is read.
This bit is set if the current through the 3 V channel exceeds the fast trip threshold. This bit remains set until Register 8 is
read.
Table 9. Register 9: Unlatched Status Indicators (Read-only)
BIT
0
NAME
spare
spare
spare
12BS
12PS
3BS
DEFAULT
DESCRIPTION
1
–
2
3
–
–
–
High indicates BLK commanded high.
Low indicates VPASS > VOUT + 6 V.
4
5
Low indicates VIN3 > VOUT3.
6
spare
3GS
7
–
Low indicates channel 3 gate is driven on (VGATE > VIN + 1.75 V).
12BS
12PS
This bit goes high when the 12-V ORing logic commands the BLK pin high ( 25 V ) and the BLK FET should be on.
This bit goes low when the 12-V PASS pin is above the timer start threshold (OUT12 + 7 V), indicating that the 12-V PASS
FET should be on.
3BS
This bit goes low when the 3 V ORing logic commands the 3 V pass FET on, indicating that a reverse blocking condition does
not exist.
3GS
This bit goes low when the 3 V FET gate-to-source voltage exceeds 1.75 V, indicating that the 3 V FET should be on.
X
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APPLICATION INFORMATION
The TPS2459 has been designed to simplify compliance with the PICMG-AMC.R2.0 and PICMG-MTCA.0
specifications. These specifications were developed by the PCI Industrial Computer Manufacturers Group
(PICMG). These two specifications are derivations of the PICMG-ATCA (Advanced Telecommunication
Computing Architecture) specification originally released in December, 2002.
PICMG-AMC Highlights
•
•
•
•
•
•
•
•
•
AMC – Advanced Mezzanine Cards
Designed to Plug into ATCA Carrier Boards
AdvancedMC™ Focuses on Low Cost
1 to 8 AdvancedMC™ per ATCA Carrier Board
3.3-V Management Power – Maximum Current Draw of 150 mA
12-V Payload Power – Converted to Required Voltages on AMC
Maximum 80 W Dissipation per AdvancedMC™
Hotswap and Current Limiting and must be Present on Carrier Board
For details, see www.picmg.org/
PICMG-MTCA Highlights
•
•
•
•
•
•
•
MTCA – MicroTelecommunications Computing Architecture
Architecture for Using AMCs without an ATCA Carrier Board
Up to 12 AMCs per System, plus Two MicroTCA Carrier Hub (MCH)s, plus Two Cooling Units (CU)s
Focuses on Low Cost – Commoditizes the Hardware
All Functions of ATCA Carrier Board must be Provided
MicroTCA is also known as MTCA, mTCA, µTCA or uTCA
For details, see www.picmg.org/
Introduction
The TPS2459 controls a 12-V power path and a 3.3-V power path in a 32-pin QFN package. An I2C™ interface
enables the implementation using one small integrated circuit, but it also provides many opportunities for design
customization. The following sections describe the main functions of the TPS2459 and provide guidance for
designing systems around this device.
Control Logic and Power-On Reset
The TPS2459 circuitry, including the I2C™ interface, draws power from an internal bus fed by a preregulator. A
capacitor attached to the VINT pin provides decoupling and output filtering for this preregulator. It can draw
power from either of the two inputs (IN12, IN3) or from either of two outputs (OUT12, OUT3). This feature allows
the internal circuitry to function regardless of which channels receive power, or from what source. The two
external FET drive pins (PASS, BLK) are held low during startup to ensure that the 12-V channel remains off.
The internal 3.3-V channel is also held off. When the voltage on the internal VINT rail exceeds approximately 1
V, the power-on reset circuit loads the internal registers with the default values listed in Detailed Description of
Registers section.
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Enable Functions
Table 10 lists the specific conditions required to enable the two channels of the TPS2459. The 3.3-V channel has
an active-high enable pin with a 200-kΩ internal pullup resistor. The enable pin must be pulled high, or allowed to
float high, to enable the channel. The I2C™ interface includes an enable bit for each of the two channels. The bit
corresponding to a channel must be set to enable the channel. Both channels also include bleed-down threshold
comparators. Setting the bleed-down control bit ensures that a channel cannot turn on until its output voltage
drops below about 100 mV. This feature supports applications in which removal and restoration of power
re-initializes the state of downstream loads. The 12-V channel also includes a cross-connection feature to
support PICMG.AMC™ and MicroTCA™ requirements. When enabled, this feature ensures that when the 3.3-V
output drops below 2.85 V, the 12-V channel automatically shuts off. This feature can be disabled by setting the
DCC bit in Register 6.
Table 10. Enable Requirements
CHANNEL
ENABLE PINS ENABLE BITS
BLEED DOWN
CROSS CONNECTION
(V)
3.3
12
EN3 > 1.4 V
3EN = 1
OUT3 > 0.1 V or 3UV = 0
OUT12 > 0.1 V or 12UV = 0
EN12 > 1.4 V
12EN = 1
3PG = 0 or DCC = 1
Fault, Powergood, Overcurrent and FET Status Bits
The TPS2459 I2C™ interface includes six status bits for each channel, for a total of 12 bits. These status bits
occupy registers 7, 8, and 9. Table 11 summarizes the locations of these bits.
Table 11. Location
REGISTER[BIT]
NAME
PG
FUNCTION
12-V
3-V
CHANNEL CHANNEL
Powergood
R7[4]
R7[5]
R8[4]
R8[5]
R9[3]
R9[4]
–
R7[6]
R7[7]
R8[6]
R8[7]
FLT
Overcurrent time-out fault
Momentary overcurrent
Overcurrent fast trip
12-V block FET status
12-V pass FET status
3-V block status
OC
FTR
12BS
12PS
3BS
3GS
–
R9[5]
3-V gate status
R9[7]
Current Limit and Fast Trip Thresholds
Both channels monitor current by sensing the voltage across a resistor. The 3.3-V channel uses an internal
sense resistor with a nominal value of 290 mΩ. The 12-V channel uses an external sense resistor that typically
lies in the range of 4 mΩ to 10 mΩ. Each channel features two distinct thresholds: a current limit threshold and a
fast trip threshold.
The current limit threshold sets the regulation point of a feedback loop. If the current flowing through the channel
exceeds the current limit threshold, then this feedback loop reduces the gate-to-source voltage imposed on the
pass FET. This causes the current flowing through the channel to settle to the value determined by the current
limit threshold. For example, when a module first powers up, it draws an inrush current to charge its load
capacitance. The current limit feedback loop ensures that this inrush current does not exceed the current limit
threshold.
The current limit feedback loop has a finite response time. Serious faults such as shorted loads require a faster
response in order to prevent damage to the pass FETs or voltage sags on the supply rails. A comparator
monitors the current flowing through the sense resistor, and if it ever exceeds the fast trip threshold it
immediately shuts off the channel. Then it will immediately attempt a normal turn on which allows the current limit
feedback loop time to respond. The fast trip threshold is normally set 2 to 5 times higher than the current limit.
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3.3-V Current Limiting
The 3.3-V management power channel includes an internal pass FET and current sense resistor. The
on-resistance of the management channel (including pass FET, sense resistor, metallization resistance, and
bond wires) typically equals 290 mΩ and never exceeds 500 mΩ. The AdvancedMC™ specification allows a total
of 1 Ω between the power source and the load. The TPS2459 never consumes more than half of this
requirement.
3.3-V Fast Trip Function
The 3.3-V fast trip function protects the channel against short-circuit events. If the current through the channel
exceeds a nominal value of 300 mA, then the TPS2459 immediately disables the internal pass transistor and
then allows it to slowly turn back on into current limiting.
3.3-V Current Limit Function
The 3.3-V current limit function internally limits the current to comply with the AdvancedMC™ and MicroTCA™
specifications. External resistor RSUM3 allows the user to adjust the current limit threshold. The nominal current
limit threshold ILIMIT is shown in Equation 1.
650V
I
=
LIMIT
R
SUM3
(1)
A 3320-Ω resistor gives a nominal current limit of ILIMIT = 195 mA which complies with AdvancedMC™ and
MicroTCA™ specifications. This resistance corresponds to an EIA 1% value. Alternatively, a 3.3-kΩ resistor also
suffices. Whenever the 3.3-V channel enters current limit, its fault timer begins to operate (see Fault Timer
Programming section).
3.3-V Over-Temperature Shutdown
The 3.3-V over-temperature shutdown is enabled if the 3.3 V channel remains in current limit while the die
temperature exceeds approximately 140°C. When this occurs, the channel operating in current limit turns off until
the chip cools by approximately 10°C.
3.3-V ORing
The 3.3-V channel limits reverse current flow by sensing the input-to-output voltage differential and turning off the
internal pass FET when this differential drops below –3 mV. This corresponds to a nominal reverse current flow
of 10 mA. The pass FET turns back on when the differential exceeds +10 mV. These thresholds provide a
nominal 13 mV of hysteresis to help prevent false triggering. This feature allows the implementation of redundant
power supplies (also known as supply ORing).
If the 3.3-V channel does not use redundant supplies, the 3ORON bit can be cleared to disable the ORing
circuitry. This precaution eliminates the chance that transients might trigger the ORing circuitry and upset system
operation.
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12-V Fast Trip and Current Limiting
Figure 21 shows a simplified block diagram of the circuitry associated with the fast trip and current limit circuitry
in the 12-V channel, which requires an external N-channel pass FET and three external resistors. These resistors
allow the user to independently set the fast trip threshold and the current limit threshold, as described below.
R
SENSE
12 V
V
IN
R
SET
SET
SENP
SENM
PASS
OUT12
13
14
12
11
8
100 mV
30 mA
+
Fast Trip Comparator
A1
SUM12
5
675 mV
+
A2
R
SUM
TPS2459
UDG-09040
Figure 21. 12-V Channel Threshold Circuitry
12-V Fast Trip Function
The 12-V fast trip function protects the channel against short-circuit events. If the voltage across external resistor
RSENSE exceeds the fast trip threshold, then the TPS2459 immediately disables the pass transistor. The 12CL
bits set the magnitude of the fast trip threshold. When 12CL = 1111B, the fast trip threshold nominally equals 100
mV. The fast trip current IFT corresponding to this threshold is shown in Equation 2.
100mV
I
=
FT
R
SENSE
(2)
The recommended value of (RSENSE = 5 mΩ) sets the fast trip threshold at 20 A for 12CL = 1111B. This choice of
sense resistor corresponds to the maximum 19.4 A inrush current allowed by the MicroTCA™ specification.
12-V Current Limit Function
The 12-V current limit function regulates the PASS pin voltage to prevent the current through the channel from
exceeding ILIMIT. The current limit circuitry includes two amplifiers, A1 and A2, as shown in Figure 21. Amplifier A1
forces the voltage across external resistor RSET to equal the voltage across external resistor RSENSE. The current
that flows through RSET also flows through external resistor RSUM, generating a voltage on the 12SUM pin is
shown in Equation 3.
æ
ç
è
ö
÷
ø
R
´R
SUM
SENSE
V
=
´I
SENSE
12SUM
R
SET
(3)
Amplifier A2 senses the voltage on the 12SUM pin. As long as this voltage is less than the reference voltage on
its positive input (nominally 0.675 V for 12CL = 1111B), the amplifier sources current to PASS. When the voltage
on the 12SUM pin exceeds the reference voltage, amplifier A2 begins to sink current from PASS. The
gate-to-source voltage of pass FET MPASS drops until the voltages on the two inputs of amplifier A2 balance.
The current flowing through the channel then nominally is shown in Equation 4.
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æ
ç
è
ö
÷
ø
R
SET
I
=
´ 0.675V
LIMIT
R
´R
SENSE
SUM
(4)
The recommended value of RSUM is 6810 Ω. This resistor should never equal less than 675 Ω to prevent
excessive currents from flowing through the internal circuitry. Using the recommended values of RSENSE = 5 mΩ
and RSUM = 6810 Ω gives Equation 5.
0.0198 A
æ
ç
è
ö
÷
ø
ILIMIT
=
´ RSET
W
(5)
A system capable of powering an 80-W AdvancedMC™ module consumes a maximum of 8.25 A according to
MicroTCA™ specifications. The above equation suggests RSET = 417 Ω. The nearest 1% EIA value equals 422
Ω. The selection of RSET for MicroTCA™ power modules is described in the Redundant vs. Non-redundant Inrush
Current Limiting section.
12-V Inrush Slew Rate Control
Although it is possible to slow the gate slew rate, it is very unlikely that would be necessary since the TPS2459
limits inrush current at turn on. The limit level is programmed by the user.
As normally configured, the turn-on slew rate of the 12-V channel output voltage VOUT is shown in Equation 6.
DV
I
SRC
OUT
@
Dt
C
g
(6)
where
•
•
ISRC equals the current sourced by the PASS pin (nominally 30 µA)
Cg equals the effective gate capacitance
For purposes of this computation, the effective gate capacitance approximately equals the reverse transfer
capacitance, CRSS. To reduce the slew rate, increase Cg by connecting additional capacitance from PASS to
ground. Place a resistor of at least 1000 Ω in series with the additional capacitance to prevent it from interfering
with the fast turn off of the FET.
R
SENSE
IN12
OUT12
R > 1 kW
C
11
PASS
TPS2459
UDG-09033
Figure 22. RC Slew Rate Control
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Redundant vs. Non-Redundant Inrush Current Limiting
The TPS2459 can support redundant and non-redundant systems. Redundant systems generally use a single
fixed current limit, as described above. Non-redundant systems often allow a higher current limit during inrush to
compensate for the lack of a redundant supply. The MicroTCA™ standard allows up to 19.4 A for up to 200 ms
in non-redundant systems, while limiting individual supplies in redundant systems to 9.1 A at all times. Designers
can optimize the performance of the system for either application by properly setting the 12VNRS bit that controls
inrush limiting. The ability to change the inrush profile using 12VNRS makes it possible to reconfigure a controller
for redundant or non-redundant operation with a single bit. This is particularly useful for MicroTCA Power
Modules which may be deployed in redundant or non-redundamnt systems.
The 12VNRS bit affects the value of the 12CL bits during inrush. Setting 12VNRS causes the current limit
threshold and fast trip threshold to behave as if 12CL = 1111B during inrush. Once the current flowing through
the channel falls below the current limit threshold, the current limit threshold and fast trip threshold correspond to
the actual values of the 12CL bits.
Figure 23 illustrates the behavior of the 12VNRS bit. Figure A shows that setting the 12CL bits to 1111B results
in a current limit equal to IMAX. Figure 6B shows how the 12CL bits affect the current limit when the 12VNRS bit
is cleared. Setting 12CL = 0111B reduces the current limit to 60% of IMAX. Figure C shows how the 12CL bits
affect the current limit when the 12VNRS bit is set. The current limit initially equals IMAX, but as soon as the
current drops below this level, the current limit resets to 60% of IMAX and remains there so long as the channel
remains enabled.
I
MAX
If 12xCL[3:0] = 1111B,
12VNRS has no effect
60% I
MAX
t
t
t
FAULT
FAULT
FAULT
12 VNRS = x
12 VNRS = 0
12 VNRS = 1
0
0
t – Time
(A)
t – Time
(B)
t – Time
(C)
A. 12xCL[3:0] = 111B
B. The characteristics shown represent the current limit level versus time. It is not a representation of current versus
time.
Figure 23. Current Limits in Redundant and Non-Redundant Systems(A)(B)
Current Limiting Design Examples
Example One
Set up a 12-V channel input voltage to start into an 80-W load and charge a 1600-µF capacitor in less than 3 ms.
Set an operational ILIMIT of 8.25 A ±10%.
Equation 7 calculate how much current is needed for capacitor charging and powering the load.
I
= I
+I
= 6.4A + 6.67A = 13.7A
STARTUP
CHARGE
LOAD
(7)
where
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C´ V 1600mF´12V
=
I
=
= 6.4A
CHARGE
t
0.003s
•
•
PLOAD
80 W
12 V
ILOAD
=
=
= 6.67 A
VLOAD
Next, use Equation 8 to calculate RSET for an ILIMIT of 13.7 A.
´R ´R
I
(
)
SUM
LIMIT
SENSE
R
=
= 691 W
SET
0.675
(8)
where
•
•
RSUM = 6810 Ω
RSENSE = 5 Ω
The closest 1% value is 698 Ω. The ILIMIT can be calculated in Equation 9.
0.675 ´ RSET
ILIMIT
=
= 13.83 A
RSENSE ´ RSUM
(9)
If R3[3:0] are set to 0111 and R6[4] = 1 the current limit drops to 60% of the programmed maximum after
dropping out of current limit following inrush. The operational current limit is calcualted in Equation 10.
I
= 0.6´I
= 0.6´13.83A = 8.3A
LIMIT
INRUSH
(10)
The new 8.38-A current limit is within the specification of 8.25 A ±10 %. Note. These calculations use all nominal
values and neglect di/dt rates at turn on.
Example Two
Set up 12-A to startup into an 80-W load and charge a 1600 µF at not more than 17-A nominal. Then drop to an
operational ILIMIT of 8.25 A ±10%.
ISTARTUP = 17 A
The correct RSET must be found to set maximum ILIMIT to less than 17 A.
I
(
´ RSENSE ´ RSUM
)
LIMIT
RSET
=
= 857 W
0.675
where
•
•
RSUM = 6810 Ω
RSENSE = 5 Ω
The closest 1% value is 845 Ω.
0.675´R
SET
I
=
= 16.75A
LIMIT
R
´R
SUM
SENSE
(11)
Neglecting the current slew time, charge the 1600-µF capacitor in 1.9 ms.
If R3[3:0] are set to 0101 and R6[4] = 1 the current limit drops to 50% of the programmed maximum after
dropping out of current limit following inrush. The operational current limit is calculated in Equation 12.
I
= 0.5´I
= 0.5´16.75A = 8.38A
LIMIT
INRUSH
(12)
The new 8.38-A current limit is within the specification of 8.25 A ±10 %.
Note. These calculations use all nominal values.
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Table 12. Configuring 12-V Current Limits in Non-Redundant Systems
ILIMIT (A) – INRUSH
12VNRS
CBULK CHARGE TIME
(ms)
FAULT TIME
(ms)
ILIMIT (A)
OPERATIONAL
12VNRS = 1
12CLx
[3:0]
PLOAD
(W)
RSET
R6[4]=0
8.17
R6[4]=1
8.17
800 µF
6.4
1600 µF
12.8
800 µF
1600 µF
412
698
845
1111
111
8.17
8.3
80
80
80
8.5
2
17
3.5
3
13.84
16.75
8.3
1.34
0.95
2.68
101
8.38
8.38
1.9
1.5
12-V ORing Operation for Redundant Systems
The 12-V channels use external pass FETs to provide reverse blocking. The TPS2459 pulls the BLK pin high
when the input-to-output differential voltage VIN12–OUT12 exceeds a nominal value of 10 mV, and it pulls the pin
low when this differential falls below a nominal value of –3 mV. These thresholds provide a nominal 13 mV of
hysteresis to help prevent false triggering.
The source of the blocking FET connects to the source of the pass FET, and the drain of the blocking FET
connects to the load. This orients the body diode of the blocking FET such that it conducts forward current and
blocks reverse current. The body diode of the blocking FET does not normally conduct current because the FET
turns on when the voltage differential across it exceeds 10 mV.
Applications that do not use the blocking FET should clear the associated 12OR bit to turn off the internal
circuitry that drives the BLK pin. (See Figure 24).
R
SENSE
12 V
V
IN
R
SET
14
13
12
11
6
8
SENP SET
SENM
PASS
BLK
OUT12
TPS2459
UDG-09035
Figure 24. ORing Thresholds
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12-V ORing for High-Power Loads
The 12HP bit adjusts the ORing turn-off threshold of the 12-V channel. Clearing the bit sets the ORing turn-off
threshold to the default nominal value of -3 mV. Setting the bit shifts the threshold up by 6 mV to a nominal value
of +3 mV (Figure 8). Shifting the turn-off threshold to a positive value ensures that the blocking FET shuts off
before any reverse current flows.
A light load may not draw sufficient current to keep the input-to-output differential VIN12-OUT12 above 3 mV.
When this happens, the blocking FET shuts off and then the differential voltage increases until it turns back on.
This process endlessly repeats, wasting power and generating noise. Therefore 12HP should only be set for
high-power loads that satisfy the relationship.
10mV
I
>
LOAD
R
+ R
+ R
DS on PASS DS on BLK
SENSE
( )
( )
where
•
•
•
•
ILOAD is the current drawn by the load
RSENSE is the value of the sense resistor
RDS(on)PASS is the maximum on-resistance of the pass FET
RDS(on)BLK equals the maximum on-resistance of the blocking FET
For example, if RSENSE = RHSFET = RORFET = 5 mΩ, then a high-power load must always draw at least 667 mA.
Most, although not all, AdvancedMC™ loads can benefit from using the high-power bit 12HP.
Figure 25 shows the different ORing thresholds in high power and low power applications.
25 V
25 V
GND
GND
V
V
OR
OR
12 HP = 0
12 HP = 1
UDG-09034
Figure 25.
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Internal Bleed-Down Resistors and Bleed-Down Thresholds
The TPS2459 includes two features intended to support downstream loads that require removal and
reapplication of power to properly reset their internal circuitry. Disabling and re-enabling a channel of the
TPS2459 does not necessarily reset such a load because the capacitance attached to the output bus may not
fully discharge.
The TPS2459 includes two bleed-down comparators that monitor the OUT12 and OUT3 pins. The I2C™ interface
includes two bits (3DS and 12DS) that enable these comparators. Enabling a bleed-down comparator prevents
the corresponding channel from turning on until the output voltage drops below about 100 mV. This precaution
ensures that the output rail drops so low that all downstream loads properly reset.
In case the downstream load cannot quickly bleed-off charge from the output capacitance, the TPS2459 also
includes bleed-down resistors connected to each output rail through pins OUT12 and OUT3. Internal switches
connect these resistors from their corresponding rails to ground when the channels are disabled, providing that
one sets the appropriate bit in the I2C™ interface. These bits are named 12UV and 3UV. Clearing these bits
ensures that the corresponding resistors never connect to their buses.
If redundant supplies connect to an output, clear the corresponding bleed-down threshold and bleed-down
resistor bits. Failing to clear the bleed-down threshold bit prevents the channel from enabling, while the
redundant supply continues to hold up the output rail. Failing to clear the bleed-down resistor bit causes current
to continually flow through the resistor when the TPS2459 is disabled and the redundant supply holds up the
output bus.
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Multiswap Operation in Redundant Systems
TheTPS2459 features an additional mode of operation called Multiswap redundancy. This technique does not
require a microcontroller, making it simpler and faster than the redundancy schemes described in the
MicroTCA™standard. Multiswap is especially attractive for AdvancedMC™ applications that require redundancy
but need not comply with the MicroTCA™ power module standard.
To implement Multiswap redundancy, connect the SUM pins of the redundant channels together and tie a single
RSUM resistor from this node to ground. The current limit thresholds now apply to the sum of the currents
delivered by the redundant supplies. When implementing Multiswap redundancy on 12-V channels, all of the
channels must use the same values of resistors for RSENSE and RSET
.
Figure 26 and Figure 27 compare the redundancy technique advocated by the MicroTCA™ specification with
Multiswap redundancy. MicroTCA™ redundancy independently limits the current delivered by each power
source. The current drawn by the load cannot exceed the sum of the current limits of the individual power
sources. Multiswap redundancy limits the current drawn by the load to a fixed value regardless of the number of
operational power sources. Removing or inserting power sources within a Multiswap system does not affect the
current limit seen by the load.
Power Source 1
Power Source 2
Power Source 1
Power Source 2
TPS2459
TPS2459
TPS2459
TPS2459
SUM12
SUM3
21
SUM12
SUM3
21
SUM12
SUM3
21
SUM12
SUM3
21
7
7
5
5
R
R
SUM3
mC
mC
R
R
SUM3
SUM12
SUM12
R
R
SUM3
SUM12
Backplane
Backplane
UDG-09036
UDG-09036
Figure 26. µTCA Redundancy
Figure 27. Multiswap Redundancy
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Fault Timer Programming
Both of the TPS2459 channels include a fault timer. The timer begins operating whenever the channel enters
current limit. If the channel remains in current limit so long that the fault timer runs out, then the channel turns off
the pass FET and reports a fault condition by means of the xFLT bit in the I2C™ interface.
The fault timers are independently programmable from 0.5 to 32 ms in steps of 0.5 ms using the appropriate xFT
bits. A code of xFT = 00001B corresponds to the minimum programmable time of 0.5 ms. The code xFT =
00000B corresponds to an extremely short time interval of no practical use. The locations of the fault timer
programming bits are shown in Table 13.
Table 13. Fault Time Control Bits
FAULT TIME (ms)
CHANNEL
VOLTAGE (V)
8
4
2
1
0.5
12
R4[4]
R5[4]
R4[3]
R5[3]
R4[2]
R5[2]
R4[1]
R5[1]
R4[0]
R5[0]
REGISTER[
BIT]
3.3
Select the shortest fault times sufficient to allow down-stream loads and bulk capacitors to charge. Shorter fault
times reduce the stresses imposed on the pass FETs under fault conditions. This consideration may allow the
use of smaller and less expensive pass FETs for the 12-V channels.
The TPS2459 supports two modes of fault timer operation. Clearing the FLTMODE bit causes a channel to latch
off whenever its fault timer runs out. The channel remains off until it has been disabled and re-enabled (see
Enable Functions section). The TPS2459 operates in this manner by default. Setting the FLTMODE bit causes a
faulted channel to automatically attempt to turn back on after a delay roughly one hundred times the fault time.
This process repeats until either the fault disappears or the user disables the channel. The pass FET for a 12-V
channel with a shorted output must therefore continuously dissipate.
P
@ 0.01´ V
´I
FAULT
IN12 CL
(13)
where
•
•
VIN12 equals the voltage present at the input of the 12-V channel
ICL equals the current limit setting for this channel (the inrush current if 12VNRS is set)
When used in MicroTCA Power Modules it is very important to protect the OUT12 pin by connecting a Schottky
diode from the OUT12 pin to GND. The relatively long and uncontrolled load line lengths to the AdvancedMC
modules make it quite likely that shutting off while under load causes an inductive transient to pull the OUT12 pin
below -0.3 V. Pulling OUT12 below this level can disrupt proper device operation.
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TPS2459 I2C™ Interface
The TPS2459 digital interface meets the specifications for an I2C™ bus operating in the high-speed mode. The
interface to recognize any one of 27 separate I2C™ addresses can be configured using the A0, A1, and A2 pins
(Table 14 I2C™ Addressing). These pins accept any of three distinct voltage levels. Connecting a pin to ground
generates a low level (L). Connecting a pin to VINT generates a high level (H). Leaving a pin floating generates a
no-connect level (NC).
Table 14. I2C™ Addressing
EXTERNAL PINS
I2C™ (DEVICE) ADDRESS
A2
L
A1
A0
DEC
8
HEX
8
BINARY
1000
L
L
L
L
L
NC
H
9
9
1001
L
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
0A
0B
0C
0D
0E
0F
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
20
21
22
1010
L
NC
NC
NC
H
L
1011
L
NC
H
1100
L
1101
L
L
1110
L
H
NC
H
1111
L
H
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111
100000
100001
100010
NC
NC
NC
NC
NC
NC
NC
NC
NC
H
L
L
L
NC
H
L
NC
NC
NC
H
L
NC
H
L
H
NC
H
H
L
L
H
L
NC
H
H
L
H
NC
NC
NC
H
L
H
NC
H
H
H
L
H
H
NC
H
H
H
The I2C™ hardware interface consists of two wires known as serial data (SDA) and serial clock (SCL). The
interface is designed to operate from a nominal 3.3-V supply. SDA is a bidirectional wired-OR bus that requires
an external pullup resistor, typically a 2.2-kΩ resistor connected from SDA to the 3.3-V supply.
The I2C™ protocol assumes one device on the bus acts as a master and another device acts as a slave. The
TPS2459 supports only slave operation with two basic functions called register write and register read.
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Register Write
Figure 28 shows the format of a register write. First, the master issues a start condition, followed by a seven-bit
I2C™ address. Next, the master writes a zero to signify that it wishes to conduct a write operation. Upon
receiving an acknowledge from the slave, the master writes the eight-bit register number across the bus.
Following a second acknowledge, the master writes the eight-bit data value for the register across the bus. Upon
receiving a third acknowledge, the master issues a stop condition. This action concludes the register write.
ADDRESS
REGISTER NUMBER
DATA
0
Figure 28. Register Write Format
Register Read
Figure 29 shows the format of a register read. First, the master issues a start condition followed by a seven-bit
I2C™ address. Next, the master writes a zero to signify that it conducts a write operation. Upon receiving an
acknowledge from the slave, the master writes the eight-bit register number across the bus. Following a second
acknowledge, the master issues a repeat start condition. Then the master issues a seven-bit I2C™ address
followed by a one to signify that it conducts a read operation. Upon receiving a third acknowledge, the master
releases the bus to the TPS2459. The TPS2459 then writes the eight-bit data value from the register across the
bus. The master acknowledges receiving this byte and issues a stop condition. This action concludes the register
read.
I2CTM ADDRESS
REGISTER NUMBER
I2CTM ADDRESS
DATA
0
1
Figure 29. Register Read Format
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Using the TPS2459 to Control an AdvancedMC™ Slot
The TPS2459 has been designed for use in systems under I2C™ control. Figure 30 shows the TPS2459 in a
typical system implementing redundant power sources. A non-redundant application would omit the blocking FET
and leave the BLK pin unconnected.
BCS016N03 BCS057N03
R
SENSE
0.005 W
12 V
12 V
V
IN
R
SET
422 W
AdvancedMCTM
14
13
12
11
6
8
SENP SET
SENM
PASS
BLK
OUT12
0.01 mF
OUT3 17
3.3 V
15 IN12
PG12
4
7
3.3 V
16 IN3
{
0.01 mF
FLT12
To IMPC
22 VDD3
28 EN12
26 EN3
PG3 20
FLT3 19
TPS2459
From IMPC
6810 W
3320 W
{
SUM12
5
10 OREN
SUM3 21
2
3
SDA
SCL
0.1 mF
2
VINT
1
To I C
{
A0 A1 A2
30 18 25
AGND
27
GND GND GND GND GND
24 27 29 31
9
UDG-09037
Figure 30. TPS3459 Redundant System Schematic
36
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Product Folder Link(s): TPS2459
TPS2459
www.ti.com ............................................................................................................................................................................................ SLUS917–FEBRUARY 2009
Layout Considerations
TPS2459 applications require careful attention to layout to ensure proper performance and minimize
susceptibility to transients and noise. IImportant points to consider include:
•
•
•
•
•
•
•
•
Connect AGND and all GND pins to a ground plane.
Place a 0.01-µF or larger ceramic bypass capacitors on IN12 and VDD3.
Minimize the loop area created by the leads running to these devices.
Minimize the loop area between the SENM and SENP leads by running them side-by-side.
Use Kelvin connections at the points of contact with RSENSE Figure 31
Minimize the loop area between the SET and SENP leads.
Connect the SET leads to the same Kelvin points as the SENP leads, or as close to these points as possible.
Size the following runs to carry at least 20 A:
–
–
Runs on both sides of RSENSE
Runs from the drains and sources of the external FETs
•
•
•
Minimize the loop area between the OUT12 and SENP leads.
Size the runs to IN3 and OUT3 to carry at least 1 A.
Soldering the powerpad of the TPS2459 to the board will improve thermal performance.
Load Current Path
Load Current Path
Sense
Resistor
R
R
SET
SET
14 13 12
14 13 12
TPS2459
TPS2459
(a)
(b)
*Additional details ommoted for clarity.
Figure 31. Recommended RSENSE Layout
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TPS2459
SLUS917–FEBRUARY 2009............................................................................................................................................................................................ www.ti.com
Transient Protection
The need for transient protection in conjunction with hot-swap controllers should always be considered. When
the TPS2459 interrupts current flow, input inductance generates a positive voltage spike on the input and output
inductance generates a negative voltage spike on the output. Such transients can easily exceed twice the supply
voltage if steps are not taken to address the issue. Typical methods for addressing transients include :
•
•
•
•
minimizing lead length/inductance into and out of the device
transient voltage suppressors (TVS) on the input to absorb inductive spikes
Shottky diode and/or capacitors across the output to absorb negative spikes
a combination of ceramic and electrolytic capacitors on the input and output to absorb energy.
Equation 14 estimates the magnitude of these voltage spikes.
L
V
= V
+ I
´
SPIKE
NOM LOAD
C
(14)
where
•
•
•
•
VNOM is the nominal voltage at terminal being analyzed
L is the combined inductance of feed to RTN lines.
C is the capacitance at point of disconnect.
ILOAD is the current through terminal at TDISCONNECT
The inductance due to a straight length of wire is described in Equation 15.
æ
ö
æ
ç
è
ö
÷
ø
4´length
æ
ç
è
ö
÷
ø
LSTRAIGHTWIRE @ 0.2´length´ ln
- 0.75
ç
÷
ç
÷
diameter
è
ø
(15)
where
•
•
L is the length of the wire
D is the diameter
If sufficient capacitance to prevent transients from exceeding the absolute ratings of the TPS2459 cannot be
included the application requires the addition of transient protectors.
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Product Folder Link(s): TPS2459
PACKAGE MATERIALS INFORMATION
www.ti.com
28-Feb-2009
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0 (mm)
B0 (mm)
K0 (mm)
P1
W
Pin1
Diameter Width
(mm) W1 (mm)
(mm) (mm) Quadrant
TPS2459RHBR
TPS2459RHBT
QFN
QFN
RHB
RHB
32
32
3000
250
330.0
180.0
12.4
12.4
5.3
5.3
5.3
5.3
1.5
1.5
8.0
8.0
12.0
12.0
Q2
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
28-Feb-2009
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPS2459RHBR
TPS2459RHBT
QFN
QFN
RHB
RHB
32
32
3000
250
346.0
190.5
346.0
212.7
29.0
31.8
Pack Materials-Page 2
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