TPS24712DGSR [TI]
具有功率限制功能的 2.5V 至 18V 热插拔控制器，支持软启动 | DGS | 10 | -40 to 85;
| 型号： | TPS24712DGSR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有功率限制功能的 2.5V 至 18V 热插拔控制器，支持软启动 | DGS | 10 | -40 to 85 控制器 软启动 |
| 文件： | 总34页 (文件大小：2152K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPS24710, TPS24711
TPS24712, TPS24713
www.ti.com
SLVSAL2C –JANUARY 2011–REVISED MAY 2011
2.5-V to 18-V High-Efficiency Power-Limiting Hot-Swap Controller
Check for Samples: TPS24710, TPS24711, TPS24712, TPS24713
1
FEATURES
APPLICATIONS
•
•
•
•
•
•
•
•
•
2.5-V to 18-V Operation
•
•
•
•
•
Server Backplanes
Storage Area Networks (SAN)
Medical Systems
Plug-In Modules
Base Stations
Accurate Current Limiting for Startup
Programmable FET SOA Protection
Accurate 25-mV Current-Sense Threshold
Power-Good Output
Fast Breaker for Short-Circuit Protection
Programmable Fault Timer
Programmable UV Threshold
Drop-In Upgrade for LTC4211 – No Layout
Changes
•
•
PG, FLT Active-High and Active-Low Versions
MSOP-10 Package
DESCRIPTION
The TPS24710/11/12/13 is an easy-to-use, 2.5 V to 18 V, hot-swap controller that safely drives an external
N-channel MOSFET. The programmable current limit and fault time protect the supply and load from excessive
current at startup. After startup, currents above the user-selected limit will be allowed to flow until programmed
timeout – except in extreme overload events when the load is immediately disconnected from source. The low,
25mV current sense threshold is highly accurate and allows use of smaller, more efficient sense resistors
yielding lower power loss and smaller footprint.
Programmable power limiting ensures the external MOSFET operates inside its safe operating area (SOA) at all
times. This allows the use of smaller MOSFETS while improving system reliability. Power good and fault outputs
are provided for status monitoring and downstream load control.
TYPICAL APPLICATION (12 V at 10 A)
PINOUT
RSENSE
M1
DGS Package
(Top View)
VOUT
COUT
2 mΩ
CSD16403Q5
VIN
C1
470 μF
PGb (PG)
EN
FLTb (FLT)
VCC
1
2
3
4
5
10
0.1 μF
9
8
7
6
RGATE
3 V
PROG
TIMER
GND
SENSE
GATE
10 Ω
OUT
R1
R4
R5
130 kΩ
VCC
EN
SENSE
GATE
OUT
3.01 kΩ
3.01 kΩ
PGb (PG)
R2
TPS2471x
18.7 kΩ
TIMER
FLTb (FLT)
GND
TPS24710 TPS24711 TPS24712 TPS24713
PROG
Latch Off
Retry
PG
X
X
CT
56 nF
RPROG
53.6 kΩ
VUVLO = 10.8 V
ILMT = 12 A
X
L
L
X
H
H
L
L
H
H
tFAULT = 7.56 ms
FLT
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2011, Texas Instruments Incorporated
TPS24710, TPS24711
TPS24712, TPS24713
SLVSAL2C –JANUARY 2011–REVISED MAY 2011
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
DEVICE INFORMATION
TA
PACKAGE
PART NUMBER(1)
FUNCTION
Latched
Retry
FLT, PG POLARITY
MARKING
24710
TPS24710
Active Low
TPS24711
24711
–40ºC to 85ºC
MSOP-10
TPS24712
Latched
Retry
24712
Active High
TPS24713
24713
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range, all voltages referred to GND (unless otherwise noted)
VALUE
–0.3 to 30
–0.3 to 0.3
–0.3 to 0.3
–0.3 to 5
5
UNIT
EN, FLT(1)(2), FLTb(1)(3), GATE, OUT, PG(1)(2), PGb(1)(3), SENSE, VCC
PROG(1)
Input voltage range
V
SENSE to VCC
TIMER
Sink current
FLT, PG, FLTb, PGb
PROG
mA
Source current
Internally limited
2
All pins except PG and PGb
Human-body model
PG, PGb
ESD rating
0.5
kV
Charged-device model
Maximum junction, TJ
0.5
Temperature
Internally limited
°C
(1) Do not apply voltages directly to these pins.
(2) for TPS24712/13
(3) for TPS24710/11
THERMAL INFORMATION
TPS24710/11/12/13
THERMAL METRIC(1)
UNIT
MSOP (10) PINS
θJA
Junction-to-ambient thermal resistance
166.5
41.8
86.1
1.5
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
θJCtop
θJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
ψJB
84.7
n/a
θJCbot
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
2
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TPS24710, TPS24711
TPS24712, TPS24713
www.ti.com
SLVSAL2C –JANUARY 2011–REVISED MAY 2011
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
MIN NOM
MAX UNIT
SENSE, VCC
Input voltage range
2.5
0
18
V
EN, FLT, FLTb, PG, PGb, OUT
18
Sink current
Resistance
FLT, FLTb, PG, PGb
PROG
0
2
mA
kΩ
nF
µF
°C
4.99
1
500
TIMER
GATE(1)
External capacitance
1
Operating junction temperature range, TJ
–40
125
(1) External capacitance tied to GATE should be in series with a resistor no less than 1 kΩ.
ELECTRICAL CHARACTERISTICS
–40°C ≤ TJ ≤ 125°C, VCC = 12 V, VEN = 3 V, and RPROG = 50 kΩ to GND.
All voltages referenced to GND, unless otherwise noted.
PARAMETER
CONDITIONS
MIN NOM
MAX UNIT
VCC
UVLO threshold, rising
UVLO threshold, falling
UVLO hysteresis(1)
2.2
2.1
2.32
2.22
0.1
2.45
2.35
V
V
V
Enabled ― IOUT + IVCC + ISENSE
1
1.4
1.4
mA
mA
Supply current
Disabled ― EN = 0 V, IOUT + IVCC + ISENSE
0.45
EN
Threshold voltage, falling
Hysteresis(1)
1.2
1.3
50
0
V
mV
µA
µs
µs
µs
Input leakage current
Turnoff time
0 V ≤ VEN ≤ 30 V
–1
20
8
1
150
18
EN ↓ to VGATE < 1 V, CGATE = 33 nF
EN ↑
60
14
0.4
Deglitch time
Disable delay
FLT, FLTb
EN ↓ to GATE ↓, CGATE = 0, tpff50–90, See Figure 1
0.1
1
Output low voltage
Sinking 2 mA
0.11
0
0.25
1
V
VFLT = 0 V, 30 V
VFLTb = 0 V, 30 V
Input leakage current
PG, PGb
–1
µA
V(SENSE – OUT) rising, PG going low
V(SENSE – OUT) rising, PGb going high
Measured V(SENSE – OUT) falling, PG going high
Measured V(SENSE – OUT) falling, PGb going low
Sinking 2 mA
Threshold
140
240
340
mV
Hysteresis(1)
70
0.11
0
mV
V
Output low voltage
Input leakage current
0.25
1
VPG = 0 V, 30 V
–1
µA
ms
VPGb = 0 V, 30 V
Delay (deglitch) time
PROG
Rising or falling edge
2
3.4
6
Bias voltage
Sourcing 10 µA
0.65 0.678
0.7
0.2
V
Input leakage current
TIMER
VPROG = 1.5 V
–0.2
0
µA
Sourcing current
VTIMER = 0 V
8
10
12
µA
(1) These parameters are provided for reference only and do not constitute part of TI’s published device specifications for purposes of TI’s
product warranty.
Copyright © 2011, Texas Instruments Incorporated
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TPS24710, TPS24711
TPS24712, TPS24713
SLVSAL2C –JANUARY 2011–REVISED MAY 2011
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ELECTRICAL CHARACTERISTICS (continued)
–40°C ≤ TJ ≤ 125°C, VCC = 12 V, VEN = 3 V, and RPROG = 50 kΩ to GND.
All voltages referenced to GND, unless otherwise noted.
PARAMETER
CONDITIONS
MIN NOM
MAX UNIT
VTIMER = 2 V
8
2
10
4.5
12
7
µA
mA
V
Sinking current
VEN = 0 V, VTIMER = 2 V
Upper threshold voltage
Lower threshold voltage
Timer activation voltage
Bleed-down resistance
OUT
1.30
0.33
5
1.35
0.35
5.9
1.40
0.37
7
V
Raise GATE until ITIMER sinking, measure V(GATE – VCC), VCC = 12 V
VENSD = 0 V, VTIMER = 2 V
V
70
104
130
kΩ
Input bias current
GATE
VOUT = 12 V
16
30
µA
Output voltage
VOUT = 12 V
23.5
12
20
0.5
6
25.8
13.9
30
28
15.5
40
V
V
Clamp voltage
Inject 10 µA into GATE, measure V(GATE – VCC)
VGATE = 12 V
Sourcing current
µA
A
Fast turnoff, VGATE = 14 V
Sustained, VGATE = 4 V to 23 V
In inrush current limit, VGATE = 4 V to 23 V
Thermal shutdown
1
1.4
20
Sinking current
11
mA
µA
kΩ
µs
µs
20
14
8
30
40
Pulldown resistance
Fast-turnoff duration
Turn on delay
20
26
13.5
100
18
VCC rising to GATE sourcing, tprr50-50, See Figure 2
250
SENSE
Input bias current
Current limit threshold
VSENSE = 12 V, sinking current
VOUT = 12 V
30
25
40
27.5
15
µA
22.5
10
10
52
8
mV
VOUT = 7 V, RPROG = 50 kΩ
VOUT = 2 V, RPROG = 25 kΩ
12.5
12.5
60
Power limit threshold
mV
15
Fast-trip threshold
Fast-turnoff duration
Fast-turnoff delay
OTSD
68
mV
µs
13.5
200
18
V(VCC – SENSE) = 80 mV, CGATE = 0 pF, tprf50–50, See Figure 3
ns
Threshold, rising
Hysteresis(2)
130
140
10
°C
°C
(2) These parameters are provided for reference only and do not constitute part of TI’s published device specifications for purposes of TI’s
product warranty.
IGATE
VGATE
90%
50%
VVCC
VEN
50%
50%
0
0
Time
Time
t(prr50-50)
t(pff50-90)
T0494-01
T0492-01
Figure 1. tpff50–90 Timing Definition
Figure 2. tprr50–50 Timing Definition
4
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TPS24710, TPS24711
TPS24712, TPS24713
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SLVSAL2C –JANUARY 2011–REVISED MAY 2011
VGATE
50%
VVCC – VSENSE
50%
0
Time
t(prf50-50)
T0495-01
Figure 3. tprf50–50 Timing Definition
Copyright © 2011, Texas Instruments Incorporated
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TPS24710, TPS24711
TPS24712, TPS24713
SLVSAL2C –JANUARY 2011–REVISED MAY 2011
www.ti.com
FUNCTIONAL BLOCK DIAGRAM
M1
GATE
30 µA
VIN
RSENSE
RGATE
SENSE
8
OUT
7
6
60 mV
DC
Charge
Pump
RSET
Inrush
Latch
VCC
+
–
9
Servo
Amplifier
Gate
Comparator
Fast
Comparator
S
R
Q
RIMON
= 27
RSET
+
–
VCC
6 V
11 mA
Q
1-shot
0~60 µA
RIMON
+
–
A
æ
Min ç
è
ö
KpA
B
, 675 mV÷
ø
Main Opamp in Inrush
Becomes Comparator
After Inrush Limit
Complete
20 kΩ
B
+
PROG
–
3
2
1
PGb (PG)
2 ms
OUT
RPROG
+
–
UVLO
DC
+
–
PG
Comparator
2.32 V
2.22 V
240 mV
170 mV
+
–
EN
1.35 V
1.3 V
14 µs
10 µA
10 FLTb (FLT)
Fault Logic
+
–
+
POR
TSD
1.35 V
0.35 V
1.5 V
10 µA
5
GND
4
TIMER
CT
B0438-02
NOTE: Pins 1 and 10 are PG and FLT, respectively, for TPS24712/13
Figure 4. Block Diagram of the TPS24710/11
PIN FUNCTIONS
PINS
NAME
EN
I/O
I
DESCRIPTION
Active-high enable input. Logic input. Connects to resistor divider.
TPS24710/11 TPS24712/13
2
-
2
10
-
FLT
Active-high, open-drain output indicates overload fault timer has turned MOSFET off.
Active-low, open-drain output indicates overload fault timer has turned MOSFET off.
Gate driver output for external MOSFET
O
FLTb
GATE
GND
OUT
10
7
7
O
–
I
5
5
Ground
6
6
Output voltage sensor for monitoring MOSFET power.
6
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TPS24712, TPS24713
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NAME
SLVSAL2C –JANUARY 2011–REVISED MAY 2011
PIN FUNCTIONS (continued)
PINS
TPS24710/11 TPS24712/13
I/O
DESCRIPTION
Active-high, open-drain power good indicator. Status is determined by the voltage
across the MOSFET.
PG
-
1
-
O
I
Active-low, open-drain power good indicator. Status is determined by the voltage
across the MOSFET.
PGb
PROG
1
3
Power-limiting programming pin. A resistor from this pin to GND sets the maximum
power dissipation for the FET.
3
SENSE
TIMER
VCC
8
4
9
8
4
9
I
I/O
I
Current sensing input for resistor shunt from VCC to SENSE.
A capacitor connected from this pin to GND provides a fault timing function.
Input-voltage sense and power supply
DETAILED PIN DESCRIPTIONS
The following description relies on the typical application diagram on the front page of this data sheet, as well as
the functional block diagram in Figure 4.
EN: Applying a voltage of 1.35 V or more to this pin enables the gate driver. The addition of an external resistor
divider allows the EN pin to serve as an undervoltage monitor. Cycling EN low and then back high resets the
TPS24710/11/12/13 that has latched off due to a fault condition. This pin should not be left floating.
FLT: FLT is assigned for TPS24712/13. This active-high open-drain output assumes high-impedance when
TPS24712/13 has remained in current limit long enough for the fault timer to expire. The behavior of the FLT pin
depends on the version of the IC. The TPS24712 operates in latch mode and the TPS24713 operates in retry
mode. In latch mode, a fault timeout disables the external MOSFET and holds FLT in open drain condition. The
latched mode of operation is reset by cycling EN or VCC. In retry mode, a fault timeout first disables the external
MOSFET, next waits sixteen cycles of TIMER charging and discharging, and finally attempts a restart. This
process repeats as long as the fault persists. In retry mode, the FLT pin goes open-drain whenever the external
MOSFET is disabled by the fault timer. In a sustained fault, the FLT waveform becomes a train of pulses. The
FLT pin does not assert if the external MOSFET is disabled by EN, overtemperature shutdown, or UVLO. This
pin can be left floating when not used.
FLTb: FLTb is assigned for TPS24710/11. This active-low open-drain output pulls low when TPS24710/11/12/13
has remained in current limit long enough for the fault timer to expire. The behavior of the FLTb pin depends on
the version of the IC. The TPS24710 operates in latch mode and the TPS24711 operates in retry mode. In latch
mode, a fault timeout disables the external MOSFET and holds FLTb low. The latched mode of operation is reset
by cycling EN or VCC. In retry mode, a fault timeout first disables the external MOSFET, next waits sixteen
cycles of TIMER charging and discharging, and finally attempts a restart. This process repeats as long as the
fault persists. In retry mode, the FLTb pin is pulled low whenever the external MOSFET is disabled by the fault
timer. In a sustained fault, the FLTb waveform becomes a train of pulses. The FLTb pin does not assert if the
external MOSFET is disabled by EN, overtemperature shutdown, or UVLO. This pin can be left floating when not
used.
GATE: This pin provides gate drive to the external MOSFET. A charge pump sources 30 µA to enhance the
external MOSFET. A 13.9-V clamp between GATE and VCC limits the gate-to-source voltage, because VVCC is
very close to VOUT in normal operation. During start-up, a transconductance amplifier regulates the gate voltage
of M1 to provide inrush current limiting. The TIMER pin charges timer capacitor CT during the inrush. Inrush
current limiting continues until the V(GATE – VCC) exceeds the Timer Activation Voltage (6 V for VVCC = 12 V). Then
the TPS24710/11/12/13 enters into circuit-breaker mode. The Timer Activation Voltage is defined as a threshold
voltage. When V(GATE-VCC) exceeds this threshold voltage, the inrush operation is finished and the TIMER stops
sourcing current and begins sinking current. In the circuit-breaker mode, the current flowing in RSENSE is
compared with the current-limit threshold derived from the MOSFET power-limit scheme (see PROG). If the
current flowing in RSENSE exceeds the current limit threshold, then MOSFET M1 is turned off. The GATE pin is
disabled by the following three conditions:
1. GATE is pulled down by an 11-mA current source when
–
–
The fault timer expires during an overload current fault (VSENSE > 25 mV)
VEN is below its falling threshold
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–
VVCC drops below the UVLO threshold
2. GATE is pulled down by a 1 A current source for 13.5 µs when a hard output short circuit occurs and
V(VCC is greater than 60 mV, i.e., the fast-trip shutdown threshold. After fast-trip shutdown is
–
SENSE)
complete, an 11-mA sustaining current ensures that the external MOSFET remains off.
3. GATE is discharged by a 20 kΩ resistor to GND if the chip die temperature exceeds the OTSD rising
threshold.
GATE remains low in latch mode (TPS24710/12) and attempts a restart periodically in retry mode
(TPS24711/13).
If used, any capacitor connecting GATE and GND should not exceed 1 μF and it should be connected in series
with a resistor of no less than 1 kΩ. No external resistor should be directly connected from GATE to GND or from
GATE to OUT.
GND: This pin is connected to system ground.
OUT: This pin allows the controller to measure the drain-to-source voltage across the external MOSFET M1. The
power-good indicator (PG/PGb) relies on this information, as does the power limiting engine. The OUT pin should
be protected from negative voltage transients by a clamping diode or sufficient capacitors. A Schottky diode of
3 A / 40 V in a SMC package is recommended as a clamping diode for high-power applications. The OUT pin
should be bypassed to GND with a low-impedance ceramic capacitor in the range of 10 nF to 1 μF.
PG: PG is assigned for TPS24712/13. This active-high, open-drain output is intended to interface to downstream
dc/dc converters or monitoring circuits. PG assumes high-impedance after the drain-to-source voltage of the FET
has fallen below 170 mV and a 3.4-ms deglitch delay has elapsed. It pulls low when VDS exceeds 240 mV. PG
assumes low-impedance status after a 3.4-ms deglitch delay once VDS of M1 rises up, resulting from GATE being
pulled to GND at any of the following conditions:
•
•
An overload current fault occurs (VSENSE > 25 mV).
A hard output short circuit occurs, leading to V(VCC – SENSE) greater than 60 mV, i.e., the fast-trip shutdown
threshold has been exceeded.
•
•
•
VEN is below its falling threshold.
VVCC drops below the UVLO threshold.
Die temperature exceeds the OTSD threshold.
This pin can be left floating when not used.
PGb: PGb is assigned for TPS24710/11. This active-low, open-drain output is intended to interface to
downstream dc/dc converters or monitoring circuits. PGb pulls low after the drain-to-source voltage of the FET
has fallen below 170 mV and a 3.4-ms deglitch delay has elapsed. It goes open-drain when VDS exceeds 240
mV. PGb assumes high-impedance status after a 3.4-ms deglitch delay once VDS of M1 rises up, resulting from
GATE being pulled to GND at any of the following conditions:
•
•
An overload current fault occurs (VSENSE > 25 mV).
A hard output short circuit occurs, leading to V(VCC – SENSE) greater than 60 mV, i.e., the fast-trip shutdown
threshold has been exceeded.
•
•
•
VEN is below its falling threshold.
VVCC drops below the UVLO threshold.
Die temperature exceeds the OTSD threshold.
This pin can be left floating when not used.
PROG: A resistor from this pin to GND sets the maximum power permitted in the external MOSFET M1 during
inrush. Do not apply a voltage to this pin. If the constant power limit is not desired, use a PROG resistor of
4.99 kΩ. To set the maximum power, use Equation 1,
3125
P
=
LIM
RPROG ´ RSENSE
(1)
where PLIM is the allowed power limit of MOSFET M1. RSENSE is the load-current-monitoring resistor connected
between the VCC pin and the SENSE pin. RPROG is the resistor connected from the PROG pin to GND. Both
RPROG and RSENSE are in ohms and PLIM is in watts. PLIM is determined by the maximum allowed thermal stress of
MOSFET M1, given by Equation 2,
8
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SLVSAL2C –JANUARY 2011–REVISED MAY 2011
TJ(MAX) - TC(MAX)
P
<
LIM
RθJC(MAX)
(2)
where TJ(MAX) is the maximum desired transient junction temperature and TC(MAX) is the maximum case
temperature prior to a start or restart. RӨJC(MAX) is the junction-to-case thermal impedance of the pass MOSFET
M1 in units of °C/W. Both TJ(MAX) and TC(MAX) are in °C.
SENSE: This pin connects to the negative terminal of RSENSE. It provides a means of sensing the voltage across
this resistor, as well as a way to monitor the drain-to-source voltage across the external FET. The current limit
ILIM is set by Equation 3.
25 mV
ILIM
=
RSENSE
(3)
A fast trip shutdown occurs when V(VCC – VSENSE) exceeds 60 mV.
TIMER: A capacitor CT connected from the TIMER pin to GND determines the overload fault timing. TIMER
sources 10 µA when an overload is present, and discharges CT at 10 µA otherwise. M1 is turned off when VTIMER
reaches 1.35 V. In an application implementing auto-retry after a fault, this capacitor also determines the period
before the external MOSFET is re-enabled. A minimum timing capacitance of 1 nF is recommended to ensure
proper operation of the fault timer. The value of CT can be calculated from the desired fault time tFLT, using
Equation 4.
10 μA
CT
=
´ tFLT
1.35 V
(4)
The latch mode (TPS24710/12) or the retry mode (TPS24711/13) occurs if the load current exceeds the current
limit threshold or the fast-trip shutdown threshold, While in latch mode, the TIMER pin continues to charge and
discharge the attached capacitor periodically. In retry mode, the external MOSFET is disabled for sixteen cycles
of TIMER charging and discharging. The TIMER pin is pulled to GND by a 2-mA current source at the end of the
16th cycle of charging and discharging. The external MOSFET is then re-enabled. The TIMER pin capacitor, CT,
can also be discharged to GND during latch mode or retry mode by a 2-mA current source whenever any of the
following occurs:
•
•
VEN is below its falling threshold.
VVCC drops below the UVLO threshold.
VCC: This pin performs three functions. First, it provides biasing power to the integrated circuit. Second, it serves
as an input to the power-on reset (POR) and undervoltage lockout (UVLO) functions. The VCC trace from the
integrated circuit should connect directly to the positive terminal of RSENSE to minimize the voltage sensing error.
Bypass capacitor C1, shown in the typical application diagram on the front page, should be connected to the
positive terminal of RSENSE. A capacitance of at least 10 nF is recommended.
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TYPICAL CHARACTERISTICS
1200
5
T = 125°C
4
3
2
1
0
1000
800
600
400
T = 25°C
T = 25°C
T = 125°C
T = –40°C
T = –40°C
0
2
4
6
8
10
12
14
16
18
20
0
2
4
6
8
10
12
14
16
18
20
Input Voltage, VVCC (V)
Input Voltage, VVCC (V)
Figure 5. Supply Current vs Input Voltage at Normal
Operation (EN = High)
Figure 6. Supply Current vs Input Voltage at Shutdown
(EN = 0 V)
32
26.5
VCC Voltage = 12 V
VVCC = 12 V
28
26
25.5
25
VVCC = 2.5 V
24
T = 125°C
T = 25°C
20
16
T = –40°C
24.5
24
VVCC = 18 V
12
8
4
23.5
0
2
4
6
8
10
12
14
–50
–20
10
40
Temperature (°C)
70
100
130
Voltage, V(SENSE – OUT) (V)
Figure 7. Voltage Across RSENSE in Inrush Current
Limiting vs Temperature
Figure 8. Voltage Across RSENSE in Inrush Power Limiting
vs VDS of Pass MOSFET
1.8
1.6
1.4
1.2
0.25
0.2
40
VVCC = 12 V
Gate Current at Current Limiting
VVCC Voltage = 12 V
32
24
T = –40°C
T = 25°C
0.15
0.1
16
1
0.05
0
T = 25°C
8
0.8
0.6
0.4
0.2
0
V(VCC – SENSE)
0
T = 125°C
–0.05
–0.1
–0.15
–0.2
–0.25
T = 125°C
–8
–16
–24
–32
–40
T = –40°C
–0.2
–10
0
10
20
30
40
Time (µs)
0
5
10 15 20 25 30 35 40 45 50 55
Voltage, V(VCC – SENSE) (mV)
Figure 9. MOSFET Gate Current vs Voltage Across RSENSE
During Inrush Power Limiting
Figure 10. Gate Current During Fast Trip,
VVCC = VGATE = 12 V
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TYPICAL CHARACTERISTICS (continued)
0.9
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
0.25
32
28
24
20
16
12
8
0.2
T = 25°C
T = –40°C
0.15
0.1
T = 25°C
T = 125°C
0.05
0
V(VCC – SENSE)
T = 125°C
–0.05
–0.1
–0.15
–0.2
–0.25
T = –40°C
–0.1
VVCC = 3.3 V
–0.2
–10
0
10
20
30
40
Time (µs)
0
4
8
12
16
20
Input Voltage, VVCC (V)
Figure 11. Gate Current During Fast Trip,
VVCC = VGATE = 3.3 V
Figure 12. Gate Voltage With Zero Gate Current vs Input
Voltage
7
2
T = 125°C
T = 25°C
VVCC = 12 V
CT = 10 nF
1.6
6
5
4
3
1.2
T = –40°C
CT = 4.7 nF
0.8
CT = 1 nF
0.4
0
–50
–20
10
40
70
100
130
0
4
8
12
16
20
Temperature (°C)
Input Voltage, VVCC (V)
Figure 13. TIMER Activation Voltage Threshold vs Input
Voltage at Various Temperatures
Figure 14. Fault-Timer Period vs Temperature With
Various TIMER Capacitors
2
2.36
VVCC = 12 V
VVCC = 12 V
UVLO Upper Threshold
EN Upper Threshold
1.6
2.32
2.28
2.24
2.20
1.2
0.8
0.4
0
UVLO Lower Threshold
–50 –20 –10
10
30
50
70
90
110 130
–50
–20
10
40
70
100
130
Temperature (°C)
Temperature (°C)
Figure 15. EN Threshold Voltage vs Temperature
Figure 16. UVLO Threshold Voltage vs Temperature
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TYPICAL CHARACTERISTICS (continued)
240
220
200
180
160
140
64
63.5
63
PG Falling and PGb Rising
VVCC = 12 V
VVCC = 2.5 V
62.5
62
PG Rising and PGb Falling
61.5
61
VVCC = 18 V
60.5
60
–50
–20
10
40
Temperature (°C)
70
100
130
–50
–20
10
40
Temperature (°C)
70
100
130
Figure 17. Threshold Voltage of VDS vs Temperature, PGb
and PG Rising and Falling
Figure 18. Fast-Trip Threshold Voltage vs Temperature
160
140
120
160
140
120
VVCC = 18 V
VVCC = 2.5 V
VVCC = 2.5 V
VVCC = 18 V
100
80
100
80
VVCC = 12 V
VVCC = 12 V
60
60
–50
–20
10
40
Temperature (°C)
70
100
130
–50
–20
10
40
70
100
130
Temperature (°C)
Figure 19. PG and PGb Open-Drain Output Voltage in Low
State
Figure 20. FLT and FLTb Open-Drain Output Voltage in
Low State
1.344
0.7
VEN = 0 V
T = 125°C
1.342
1.34
0.6
VVCC = 18 V
VVCC = 12 V
T = 25°C
0.5
1.338
1.336
1.334
0.4
T = –40°C
VVCC = 2.5 V
0.3
0.2
–50
–20
10
40
Temperature (°C)
70
100
130
0
4
8
12
16
20
Input Voltage, VVCC (V)
Figure 21. Supply Current vs Input Voltage at Various
Temperatures When EN Pulled Low
Figure 22. Timer Upper Threshold Voltage vs Temperature
at Various Input Voltages
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TYPICAL CHARACTERISTICS (continued)
0.365
10.2
10.1
10
VVCC = 18 V
VVCC = 18 V
VVCC = 12 V
0.362
0.36
9.9
9.8
9.7
9.6
9.5
VVCC = 12 V
VVCC = 2.5 V
VVCC = 2.5 V
0.357
–50
–20
10
40
Temperature (°C)
70
100
130
–50
–20
10
40
70
100
130
Temperature (°C)
Figure 23. Timer Lower Threshold Voltage vs Temperature
at Various Input Voltages
Figure 24. Timer Sourcing Current vs Temperature at
Various Input Voltages
10.4
10.3
VVCC = 18 V
VVCC = 12 V
10.2
10.1
10
VVCC = 2.5 V
9.9
9.8
9.7
–50
–20
10
40
Temperature (°C)
70
100
130
Figure 25. Timer Sinking Current vs Temperature at Various Input Voltages
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SYSTEM OPERATION
INTRODUCTION
The TPS24710/11/12/13 provides all the features needed for a positive hot-swap controller. These features
include:
•
•
•
•
•
•
•
•
Undervoltage lockout
Adjustable (system-level) enable
turn-on inrush limiting
High-side gate drive for an external N-channel MOSFET
MOSFET protection by power limiting
Adjustable overload timeout — also called an electronic circuit breaker
Charge-complete indicator for downstream converter coordination
A choice of latch (TPS24710/12) or automatic restart mode (TPS24711/13)
The typical application diagram on the front page of this data sheet, and oscilloscope plots shown in Figure 26
through Figure 28 and Figure 30 through Figure 33, demonstrate many of the functions described previously.
BOARD PLUG IN
Figure 26 and Figure 27 illustrate the inrush current that flows when a hot swap board under the control of the
TPS24710/11/12/13 is plugged into a system bus. Only the bypass capacitor charge current and small bias
currents are evident when a board is first plugged in. The TPS24710/11/12/13 is held inactive, for a short period
while internal voltages stabilize. During this period GATE, PROG, TIMER are held low and PG, FLT, PGb, and
FLTb are held open drain. When the voltage on the internal VCC rail exceeds approximately 1.5 V, the power-on
reset (POR) circuit initializes the TPS24710/11/12/13 and a start-up cycle is ready to take place.
GATE, PROG, TIMER, PG, FLT, PGb, and FLTb are released after the internal voltages have stabilized and the
external EN (enable) thresholds have been exceeded. The part begins sourcing current from the GATE pin to
turn on MOSFET M1. The TPS24710/11/12/13 monitors both the drain-to-source voltage across MOSFET M1
and the drain current passing through it. Based on these measurements, the TPS24710/11/12/13 limits the drain
current by controlling the gate voltage so that the power dissipation within the MOSFET does not exceed the
power limit programmed by the user. The current increases as the voltage across the MOSFET decreases until
finally the current reaches the current limit ILIM
.
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Figure 26. Inrush Mode at Hot-Swap Circuit Insertion
INRUSH OPERATION
When the TPS24710/11/12/13 activates the pass MOSFET, M1, a current flows into the downstream bulk storage
capacitors. When this current exceeds the limit set by the power limit engine, the gate of the MOSFET is
regulated by a feedback loop to make the MOSFET current rise in a controlled manner. This not only limits the
inrush current charging capacitance but it also limits the power dissipation of the MOSFET to safe levels. A more
complete explanation of the power limiting scheme is given in the section entitled Action of the Constant Power
Engine. At the instant when the current in RSENSE reaches the programmed limit, the TIMER pin begins to charge
the timing capacitor CT with a current of approximately 10 μA. The TIMER pin continues to charge CT until
V(GATE – VCC) reaches the timer activation voltage (6 V for VVCC = 12 V). The TIMER then begins to discharge CT
with a current of approximately 10 μA. This indicates that the inrush mode is finished. If the TIMER exceeds its
upper threshold of 1.35 V before V(GATE – VCC) reaches the timer activation voltage, the GATE pin is pulled to
GND and the hot-swap circuit enters either latch mode (TPS24710/12) or auto-retry mode (TPS24711/13).
The power limit feature is disabled once the inrush operation is finished and the hotswap circuit becomes a
circuit breaker. The TPS24710/11/12/13 will turn off the MOSFET, M1, after a fault timer period once the load
exceeds the current limit threshold.
ACTION OF THE CONSTANT-POWER ENGINE
Figure 27 illustrates the operation of the constant-power engine during start-up. The circuit used to generate the
waveforms of Figure 27 was programmed to a power limit of 29.3 W by means of the resistor connected between
PROG and GND. At the moment current begins to flow through the MOSFET, a voltage of 12 V appears across
it (input voltage VVCC = 12 V), and the constant-power engine therefore allows a current of 2.44 A (equal to 29.3
W divided by 12 V) to flow. This current increases in inverse ratio as the drain-to-source voltage diminishes, so
as to maintain a constant dissipation of 29.3 W. The constant-power engine adjusts the current by altering the
reference signal fed to the current limit amplifier. The lower part of Figure 28 shows the measured power
dissipated within the MOSFET, labeled FET PWR, remaining substantially constant during this period of
operation, which ends when the current through the MOSFET reaches the current limit ILIM. This behavior can be
considered a form of foldback limiting, but unlike the standard linear form of foldback limiting, it allows the power
device to operate near its maximum capability, thus reducing the start-up time and minimizing the size of the
required MOSFET.
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I_IN: Input Current, 2 A/div
GAT: Voltage on GATE Pin, 5 V/div
V_DS: Drain-to-Source Voltage of M1, 5 V/div
TIMER: Voltage on TIMER Pin, 500 mV/div
FET_PWR: Power on M1 (product of V_DS and I_IN), 19 W/div
Time: 10 ms/div
C002
Figure 27. Computation of M1 Power Stress During Start-Up
CIRCUIT BREAKER AND FAST TRIP
The TPS24710/11/12/13 monitors load current by sensing the voltage across RSENSE. The TPS24710/11/12/13
incorporates two distinct thresholds: a current-limit threshold and a fast-trip threshold.
The functions of circuit breaker and fast-trip turn off are shown in Figure 28 through Figure 31.
Figure 28 shows the behavior of the TPS24710/11 when a fault in the output load causes the current passing
through RSENSE to increase to a value above the current limit but less than the fast-trip threshold. When the
current exceeds the current-limit threshold, a current of approximately 10 μA begins to charge timing capacitor
CT. If the voltage on CT reaches 1.35 V, then the external MOSFET is turned off. The TPS24710 latches off and
the TPS24711 commences a restart cycle. In either event, fault pin FLTb pulls low to signal a fault condition.
Overload between the current limit and the fast trip threshold is permitted for this period. This shutdown scheme
is sometimes called an electronic circuit breaker.
The fast-trip threshold protects the system against a severe overload or a dead short circuit. When the voltage
across the sense resistor RSENSE exceeds the 60 mV fast-trip threshold, the GATE pin immediately pulls the
external MOSFET gate to ground with approximately 1 A of current. This extremely rapid shutdown may
generate disruptive transients in the system, in which case a low-value resistor inserted between the GATE pin
and the MOSFET gate can be used to moderate the turn off current. The fast-trip circuit holds the MOSFET off
for only a few microseconds, after which the TPS24710/11/12/13 turns back on slowly, allowing the current-limit
feedback loop to take over the gate control of M1. Then the hot-swap circuit goes into either latch mode
(TPS24710/12) or auto-retry mode (TPS24711/13). Figure 30 and Figure 31 illustrate the behavior of the system
implementing TPS24710/11 when the current exceeds the fast-trip threshold.
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Figure 28. Circuit Breaker Mode During Over Load Condition
ILIMIT
M1
RSENSE
RGATE
VCC
SENSE
GATE
OUT
9
8
7
6
RSET
+
60 mV
–
Fast Trip
Comparator
60 μA
30 μA
Server
Amplifier
A1
+
A2
VCP
–
675 mV
Current
Limit Amp
PROG
3
RIMON
RPROG
+
B0439-02
Figure 29. Partial Diagram of the TPS24710/11/12/13 With Selected External Components
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Figure 30. Current Limit During Output Load Short Circuit Condition (Overview)
Figure 31. Current Limit During Output-Load Short-Circuit Condition (Onset)
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AUTOMATIC RESTART
The TPS24711/13 automatically initiates a restart after a fault has caused it to turn off the external MOSFET M1.
Internal control circuits use CT to count 16 cycles before re-enabling M1 as shown in Figure 32 (TPS24711). This
sequence repeats if the fault persists. The timer has a 1 : 1 charge-to-discharge current ratio. For the very first
cycle, the TIMER pin starts from 0 V and rises to the upper threshold of 1.35 V and subsequently falls to 0.35 V
before restarting. For the following 16 cycles, 0.35 V is used as the lower threshold. This small duty cycle often
reduces the average short-circuit power dissipation to levels associated with normal operation and eliminates
special thermal considerations for surviving a prolonged output short.
Figure 32. Auto-Restart Cycle Timing
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Figure 33. Latch After Overload Fault
PG, FLT, PGb, FLTb, AND TIMER OPERATIONS
The open-drain PG/PGb (PG is for TPS24712/13 and PGb is for TPS24710/11) output provides a deglitched
end-of-inrush indication based on the voltage across M1. PG/PGb is useful for preventing a downstream dc/dc
converter from starting while its input capacitor COUT is still charging. PG goes active-high and PGb goes
active-low about 3.4 ms after COUT is charged. This delay allows M1 to fully turn on and any transients in the
power circuits to end before the converter starts up. This type of sequencing prevents the downstream converter
from demanding full current before the power-limiting engine allows the MOSFET to conduct the full current set
by the current limit ILIM. Failure to observe this precaution may prevent the system from starting. The pullup
resistor shown on the PG/PGb pin in the typical application diagram on the front page is illustrative only; the
actual connection to the converter depends on the application. The PG/PGb pin may indicate that inrush has
ended before the MOSFET is fully enhanced, but the downstream capacitor will have been charged to
substantially its full operating voltage. Care should be taken to ensure that the MOSFET on-resistance is
sufficiently small to ensure that the voltage drop across this transistor is less than the minimum power-good
threshold of 140 mV. After the hot-swap circuit successfully starts up, the PG pin can return to a low-impedance
status and PGb to high-impedance status whenever the drain-to-source voltage of MOSFET M1 exceeds its
upper threshold of 340 mV, which presents the downstream converters a warning flag. This flag may occur as a
result of overload fault, output short fault, input overvoltage, higher die temperature, or the GATE shutdown by
UVLO and EN.
FLT/FLTb (FLT is for TPS24712/13 and FLTb is for TPS24710/11) is an indicator that the allowed fault-timer
period during which the load current can exceed the programmed current limit (but not the fast-trip threshold) has
expired. The fault timer starts when a current of approximately 10 μA begins to flow into the external capacitor,
CT, and ends when the voltage of CT reaches TIMER upper threshold, i.e., 1.35 V. FLT goes high and FLTb pulls
low at the end of the fault timer. Otherwise, FLT assumes a low-impedance state and FLTb a high-impedance
state.
The fault-timer state requires an external capacitor CT connected between the TIMER pin and GND pin. The
length of the fault timer is the charging time of CT from 0 V to its upper threshold of 1.35 V. The fault timer begins
to count under any of the following three conditions:
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1. In the inrush mode, TIMER begins to source current to the timer capacitor, CT, when MOSFET M1 is
enabled. TIMER begins to sink current from the timer capacitor, CT when V(GATE – VCC) exceeds the timer
activation voltage (see the Inrush Operation section). If V(GATE
does not reach the timer activation
–
VCC)
voltage before TIMER reaches 1.35 V, then the TPS24710/11/12/13 disables the external MOSFET M1. After
the MOSFET turns off, the timer goes into either latch mode (TPS24710/12) or retry mode (TPS24711/13).
2. In an overload fault, TIMER begins to source current to the timer capacitor, CT, when the load current
exceeds the programmed current limits. When the timer capacitor voltage reaches its upper threshold of
1.35 V, TIMER begins to sink current from the timer capacitor, CT, and the GATE pin is pulled to ground.
After the fault timer period, TIMER may go into latch mode (TPS24710/12) or retry mode (TPS24711/13).
3. In output short-circuit fault, TIMER begins to source current to the timer capacitor, CT, when the load current
exceeds the programmed current limits following a fast-trip shutdown of M1. When the timer capacitor voltage
reaches its upper threshold of 1.35 V, TIMER begins to sink current from the timer capacitor, CT, and the
GATE pin is pulled to ground. After the fault timer period, TIMER may go into latch mode (TPS24710/12) or
retry mode (TPS24711/13).
If the fault current drops below the programmed current limit within the fault timer period, VTIMER decreases and
the pass MOSFET remains enabled.
The behaviors of TIMER are different in the latch mode (TPS24710/12) and retry mode (TPS24711/13). If the
timer capacitor reaches the upper threshold of 1.35 V, then:
•
In latch mode, the GATE remains low and the TIMER pin continues to charge and discharge the attached
capacitor periodically until TPS24710/12 is disabled by UVLO or EN as shown in Figure 33.
•
In retry mode, TIMER charges and discharges CT between the lower threshold of 0.35 V and the upper
threshold of 1.35 V for sixteen cycles before the TPS24711/13 attempts to re-start. The TIMER pin is pulled
to GND at the end of the 16th cycle of charging and discharging and then ramps from 0 V to 1.35 V for the
initial half-cycle in which the GATE pin sources current. This periodic pattern is stopped once the overload
fault is removed or the TPS24711/13 is disabled by UVLO or EN.
OVERTEMPERATURE SHUTDOWN
The TPS24710/11/12/13 includes a built-in overtemperature shutdown circuit designed to disable the gate driver
if the die temperature exceeds approximately 140°C. An overtemperature condition also causes the FLT, PG,
FLTb and PGb pins to go to high-impedance states. Normal operation resumes once the die temperature has
fallen approximately 10°C.
START-UP OF HOT-SWAP CIRCUIT BY VCC OR EN
The connection and disconnection between a load and the system bus are controlled by turning on and turning
off the MOSFET, M1.
The TPS24710/11/12/13 has two ways to turn on MOSFET M1:
1. Increasing VVCC above UVLO upper threshold while EN is already higher than its upper threshold sources
current to the GATE pin. After an inrush period, TPS24710/11/12/13 fully turns on MOSFET M1.
2. Increasing EN above its upper threshold while VVCC is already higher than UVLO upper threshold sources
current to the GATE pin. After an inrush period, TPS24710/11/12/13 fully turns on MOSFET M1.
The EN pin can be used to start up the TPS24710/11/12/13 at a selected input voltage VVCC
.
To isolate the load from the system bus, the GATE pin sinks current and pulls the gate of MOSFET M1 low. The
MOSFET can be disabled by any of the following conditions: UVLO, EN, load current above current limit
threshold, hard short at load, or OTSD. Three separate conditions pull down the GATE pin:
1. GATE is pulled down by an 11-mA current source when any of the following occurs.
–
–
–
The fault timer expires during an overload current fault (VSENSE > 25 mV).
VEN is below its falling threshold.
VVCC drops below the UVLO threshold.
2. GATE is pulled down by a 1-A current source for 13.5 µs when a hard output short circuit occurs and V(VCC –
is greater than 60 mV, i.e., the fast-trip shutdown threshold. After fast-trip shutdown is complete, an
SENSE)
11-mA sustaining current ensures that the external MOSFET remains off.
3. GATE is discharged by a 20-kΩ resistor to GND if the chip die temperature exceeds the OTSD rising
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threshold.
DESIGN EXAMPLE: POWER-LIMITED START-UP
This design example assumes a 12-V system voltage with an operating tolerance of ±2 V. The rated load current
is 10 A, corresponding to a dc load of 1.2 Ω. If the current exceeds 12 A, then the controller should shut down
and then attempt to restart. Ambient temperatures may range from 20°C to 50°C. The load has a minimum input
capacitance of 470 μF. Figure 34 shows a simplified system block diagram of the proposed application.
This design procedure seeks to control the junction temperature of MOSFET M1 under both static and transient
conditions by proper selection of package, cooling, rDS(on), current limit, fault timeout, and power limit. The design
procedure further assumes that a unit running at full load and maximum ambient temperature experiences a brief
input-power interruption sufficient to discharge COUT, but short enough to keep M1 from cooling. A full COUT
recharge then takes place. Adjust this procedure to fit your application and design criteria.
PROTECTION
LOAD
RSENSE
M1
RGATE
RLOAD
1.2 W
0.1 μF
0.1 μF
12-V Main Bus Supply
COUT
470 μF
Specifications (at Output):
Peak Current Limit = 12 A
Nominal Current = 10 A
TPS2471x
TIMER
CT
B0440-02
Figure 34. Simplified Block Diagram of the System Constructed in the Design Example
STEP 1. Choose RSENSE
From the TPS24710/11/12/13 electrical specifications, the current-limit threshold voltage, V(VCC – SENSE), is around
25 mV. A resistance of 2 mΩ is selected for the peak current limit of 12 A, while dissipating only 200 mW at the
rated 10-A current (see Equation 5). This represents a 0.17% power loss.
V VCC - SENSE
(
)
RSENSE
=
,
ILIM
therefore,
25 mV
12 A
RSENSE
=
» 2 mW
(5)
STEP 2. Choose MOSFET M1
The next design step is to select M1. The TPS24710/11/12/13 is designed to use an N-channel MOSFET with a
gate-to-source voltage rating of 20 V.
Devices with lower gate-to-source voltage ratings can be used if a Zener diode is connected so as to limit the
maximum gate-to-source voltage across the transistor.
22
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The next factor to consider is the drain-to-source voltage rating, VDS(MAX), of the MOSFET. Although the
MOSFET only sees 12 V DC, it may experience much higher transient voltages during extreme conditions, such
as the abrupt shutoff that occurs during a fast trip. A TVS may be required to limit inductive transients under such
conditions. A transistor with a VDS(MAX) rating of at least twice the nominal input power-supply voltage is
recommended regardless of whether a TVS is used or not.
Next select the on resistance of the transistor, rDS(on). The maximum on-resistance must not generate a voltage
greater then the minimum power-good threshold voltage of 140 mV. Assuming a current limit of 12 A, a
maximum rDS(on) of 11.67 mΩ is required. Also consider the effect of rDS(on) upon the maximum operating
temperature TJ(MAX) of the MOSFET. Equation 6 computes the value of rDS(on)(MAX) at a junction temperature of
TJ(MAX). Most manufacturers list rDS(on)(MAX) at 25°C and provide a derating curve from which values at other
temperatures can be derived. Compute the maximum allowable on-resistance, rDS(on)(MAX), using Equation 6.
TJ(MAX) - TA(MAX)
rDS(on)(MAX)
=
,
2
IMAX ´ RqJA
therefore,
150°C - 50°C
rDS(on)(MAX)
=
= 13.6 mW
12 A 2 ´51°C/ W
(
)
(6)
Taking these factors into consideration, the TI CSD16403Q5 was selected for this example. This transistor has a
VGS(MAX) rating of 16 V, a VDS(MAX) rating of 25 V, and a maximum rDS(on) of 2.8 mΩ at room temperature. During
normal circuit operation, the MOSFET can have up to 10 A flowing through it. The power dissipation of the
MOSFET equates to 0.24 W and a 9.6°C rise in junction temperature. This is well within the data sheet limits for
the MOSFET. The power dissipated during a fault (e.g., output short) is far larger than the steady-state power.
The power handling capability of the MOSFET must be checked during fault conditions.
STEP 3. Choose Power-Limit Value, PLIM, and RPROG
MOSFET M1 dissipates large amounts of power during inrush. The power limit PLIM of the TPS24710/11/12/13
should be set to prevent the die temperature from exceeding a short-term maximum temperature, TJ(MAX)2. The
short-term TJ(MAX)2 could be set as high as 130°C while still leaving ample margin to the usual manufacturer’s
rating of 150°C. Equation 7 is an expression for calculating PLIM
,
2 ´rDS(on) ´RqCA + T
é
I
MAX
ù
TJ(MAX)2
-
(
)
ë
A(MAX) û
P
£ 0.8´
,
LIM
RqJC
therefore,
12 A 2 ´0.002 W ´ 51°C/ W -1.8°C/ W + 50°C
é
ë
ù
û
130°C -
(
(
)
(
)
)
ê
ú
P
£ 0.8´
= 29.3 W
LIM
1.8°C/ W
(7)
where RθJC is the junction-to-case thermal resistance of the MOSFET, rDS(on) is the resistance at the maximum
operating temperature, and the factor of 0.8 represents the tolerance of the constant-power engine. For an
ambient temperature of 50°C, the calculated maximum PLIM is 29.3 W. From Equation 1, a 53.6-kΩ, 1% resistor
is selected for RPROG (see Equation 8).
3125
RPROG
=
,
P
LIM ´R SENSE
therefore,
3125
RPROG
=
= 53.15 kW
29.3 W ´0.002 W
(8)
23
STEP 4. Choose Output Voltage Rising Time, tON, CT
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The maximum output voltage rise time, tON, set by the timer capacitor CT must suffice to fully charge the load
capacitance COUT without triggering the fault circuitry. Equation 9 defines tON for two possible inrush cases.
Assuming that only the load capacitance draws current during start-up,
2
COUT ´ VVCC(MAX)
COUT ´ VVCC(MAX)
COUT ´P
LIM
+
-
if
P
< ILIM ´ VVCC(MAX)
LIM
2
2´P
ILIM
2´ILIM
LIM
tON
=
COUT ´ VVCC(MAX)
if
P
> ILIM ´ VVCC(MAX)
LIM
ILIM
therefore,
2
)
470 μF´ 12 V
(
470 μF´ 29.3 W
470 μF´12 V
tON
=
+
-
= 0.614 ms
2
2´ 29.3 W
12 A
2´ 12 A
(
)
(9)
The next step is to determine the minimum fault-timer period. In Equation 9, the output rise time is tON. This is the
amount of time it takes to charge the output capacitor up to the final output voltage. However, the fault timer uses
the difference between the input voltage and the gate voltage to determine if the TPS24710/11/12/13 is still in
inrush limit. The fault timer continues to run until VGS rises 6 V (for VVCC = 12 V) above the input voltage. Some
additional time must be added to the charge time to account for this additional gate voltage rise. The minimum
fault time can be calculated using Equation 10,
6 V ´ CISS
tFLT = tON
+
,
IGATE
therefore,
6 V ´ 2040 pF
tFLT = 0.614 ms +
= 1.23 ms
20 μA
(10)
where CISS is the MOSFET input capacitance and IGATE is the minimum gate sourcing current of
TPS24710/11/12/13, or 20 μA. Using the example parameters in Equation 10 and the CSD16403Q5 data sheet
leads to a minimum fault time of 1.23 ms. This time is derived considering the tolerances of COUT, CISS, ILIM, PLIM
,
IGATE, and VVCC(MAX). The fault timer must be set to a value higher than 1.23 ms to avoid turning off during
start-up, but lower than any maximum fault time limit determined by the SOA curve of the device.
There is a maximum time limit set by the SOA curve of the MOSFET. Referring to Figure 35, which shows the
CSD16403Q5 SOA curve at TJ = 25°C, the MOSFET can tolerate 12 A with 12 V across it for approximately
20 ms. If the junction temperature TJ is other than 25°C, then the pulse time should be scaled by a factor of
(150°C – TJ) / (150°C – 25°C). Therefore, the fault timer should be set between 1.23 ms and 20 ms. For this
example, we will select 7 ms to allow for variation of system parameters such as temperature, load, component
tolerance, and input voltage. The timing capacitor is calculated in Equation 4 as 52 nF. Selecting the next-highest
standard value, 56 nF, yields a 7.56-ms fault time (see Equation 11).
10 μA
CT =
´ tFLT,
1.35 V
therefore,
10 μA
CT =
1.35 V
´7 ms = 52 nF
(11)
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1k
100
10
1ms
10ms
100ms
Area Limited
by RDS(on)
1
1s
0.1
Single Pulse
DC
RθJA = 94ºC/W (min Cu)
0.01
0.01
0.1
1
10
100
VDS – Drain-to-Source Voltage – V
G009
Figure 35. CSD16403Q5 SOA Curve
STEP 5. Calculate the Retry-Mode Duty Ratio
In retry mode, the TPS24711/13 is on for one charging cycle and off for 16 charge/discharge cycles, as can be
seen in Figure 32. The first CT charging cycle is from 0 V to 1.35 V, which gives 7.56 ms. The first CT discharging
cycle is from 1.35 V to 0.35 V, which gives 5.6 ms. Therefore, the total time is 7.56 ms + 33 × 5.6 ms = 192.36
ms. As a result, the retry mode duty ratio is 7.56 ms/192.36 ms = 3.93%.
STEP 6. Select R1 and R2 for UV
Next, select the values of the UV resistors, R1 and R2, as shown in the typical application diagram on the front
page. From the TPS24710/11/12/13 electrical specifications, VENTHRESH = 1.35 V. The VUV is the undervoltage
trip voltage, which for this example equals 10.7 V.
R
2
V
=
´ V
ENTHRESH
VCC
R + R
1
2
(12)
Assume R1 is 130 kΩ and use Equation 12 to solve for the R2 value of 18.7 kΩ.
STEP 7. Choose RGATE, R4, R5 and C1
In the typical application diagram on the front page, the gate resistor, RGATE, is intended to suppress
high-frequency oscillations. A resistor of 10 Ω will serve for most applications, but if M1 has a CISS below 200 pF,
then 33 Ω is recommended. Applications with larger MOSFETs and very short wiring may not require RGATE. R4
and R5 are required only if PGb and FLTb are used; these resistors serve as pullups for the open-drain output
drivers. The current sunk by each of these pins should not exceed 2 mA (see the RECOMMENDED
OPERATING CONDITIONS table). C1 is a bypass capacitor to help control transient voltages, unit emissions,
and local supply noise while in the disabled state. Where acceptable, a value in the range of 0.001 μF to 0.1 μF
is recommended.
ALTERNATIVE DESIGN EXAMPLE: GATE CAPACITOR (dV/dt) CONTROL IN INRUSH MODE
The TPS24710/11/12/13 can be used in applications that expect a constant inrush current. This current is
controlled by a capacitor connected from the GATE terminal to GND. A resistor of 1 kΩ placed in series with this
capacitor will prevent it from slowing a fast-turnoff event. In this mode of operation, M1 operates as a source
follower, and the slew rate of the output voltage approximately equals the slew rate of the gate voltage (see
Figure 36).
To implement a constant-inrush-current circuit, choose the time to charge, ∆t, using Equation 13,
COUT ´ VVCC
Dt =
ICHG
(13)
where COUT is the output capacitance, VVCC is the input voltage, and ICHG is the desired charge current. Set PLIM
to a value greater than VVCC × ICHG to prevent power limiting from affecting the desired current.
To select the gate capacitance, use Equation 14.
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æ
ö
Dt
CGATE = I
ç GATE
´
- C
÷
ISS
VVCC ø
è
(14)
M1
From Source
To Load
RGATE
Part of
TPS2471x
CGATE
GATE
1 kΩ
IGATE
30 μA
GND
S0509-02
Figure 36. Gate Capacitor (dV/dt) Control Inrush Mode.
ADDITIONAL DESIGN CONSIDERATIONS
Use of PG/PGb
Use the PG/PGb pin to control and coordinate a downstream dc/dc converter. If this is not done, then a long time
delay is needed to allow COUT to fully charge before the converter starts. An undesirable latch-up condition can
be created between the TPS24710/11/12/13 output characteristic and the dc/dc converter input characteristic if
the converter starts while COUT is still charging; the PG/PGb pin is one way to avoid this
Output Clamp Diode
Inductive loads on the output may drive the OUT pin below GND when the circuit is unplugged or during a
current-limit event. The OUT pin ratings can be satisfied by connecting a diode from OUT to GND. The diode
should be selected to control the negative voltage at the full short-circuit current. Schottky diodes are generally
recommended for this application.
Gate Clamp Diode
The TPS24710/11/12/13 has a relatively well-regulated gate voltage of 12 V to 15.5 V with a supply voltage VVCC
higher than 4 V. A small clamp Zener from gate to source of M1 is recommended if VGS of M1 is rated below 12
V. A series resistance of several hundred ohms or a series silicon diode is recommended to prevent the output
capacitance from discharging through the gate driver to ground.
High-Gate-Capacitance Applications
Gate voltage overstress and abnormally large fault current spikes can be caused by large gate capacitance. An
external gate clamp Zener diode is recommended to assist the internal Zener if the total gate capacitance of M1
exceeds about 4000 pF. When gate capacitor dV/dt control is used, a 1-kΩ resistor in series with CGATE is
recommended (see Figure 36). If the series R-C combination is used for MOSFETs with CISS less than 3000 pF,
then a Zener diode is not necessary.
26
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Bypass Capacitors
It is a good practice to provide low-impedance ceramic capacitor bypassing of the VCC and OUT pins. Values in
the range of 10 nF to 1 µF are recommended. Some system topologies are insensitive to the values of these
capacitors; however, some are not and require minimization of the value of the bypass capacitor. Input
capacitance on a plug-in board may cause a large inrush current as the capacitor charges through the
low-impedance power bus when inserted. This stresses the connector contacts and causes a short voltage sag
on the input bus. Small amounts of capacitance (e.g., 10 nF to 0.1 µF) are often tolerable in these systems.
Output Short-Circuit Measurements
Repeatable short-circuit testing results are difficult to obtain. The many details of source bypassing, input leads,
circuit layout and component selection, output shorting method, relative location of the short, and instrumentation
all contribute to variation in results. The actual short itself exhibits a certain degree of randomness as it
microscopically bounces and arcs. Care in configuration and methods must be used to obtain realistic results. Do
not expect to see waveforms exactly like those in this data sheet; every setup differs.
Layout Considerations
TPS24710/11/12/13 applications require careful attention to layout to ensure proper performance and to minimize
susceptibility to transients and noise. In general, all traces should be as short as possible, but the following list
deserves first consideration:
•
•
Decoupling capacitors on VCC pin should have minimal trace lengths to the pin and to GND.
Traces to VCC and SENSE must be short and run side-by-side to maximize common-mode rejection. Kelvin
connections should be used at the points of contact with RSENSE. (see Figure 37).
•
•
•
Power path connections should be as short as possible and sized to carry at least twice the full load current,
more if possible.
The device dissipates low power, so soldering the thermal pad to the board is not a requirement. However,
doing so improves thermal performance and reduces susceptibility to noise.
Protection devices such as snubbers, TVS, capacitors, or diodes should be placed physically close to the
device they are intended to protect, and routed with short traces to reduce inductance. For example, the
protection Schottky diode shown in the typical application diagram on the front page of this data sheet should
be physically close to the OUT pin.
LOAD CURRENT
PATH
LOAD CURRENT
PATH
RSENSE
TPS2471x
Method 1
TPS2471x
Method 2
M0217-02
Figure 37. Recommended RSENSE Layout
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www.ti.com
REVISION HISTORY
Changes from Revision A (March 2011) to Revision B
Page
•
Corrected voltage values shown in block diagram ............................................................................................................... 6
Changes from Revision B (April 2011) to Revision C
Page
•
•
Changed in PGb: from: 140V/340mV, to:170mV / 240mV ................................................................................................... 8
Changed in Equation 8: rDS(on) to RSENSE ............................................................................................................................ 23
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PACKAGE OPTION ADDENDUM
www.ti.com
14-May-2011
PACKAGING INFORMATION
Status (1)
Eco Plan (2)
MSL Peak Temp (3)
Samples
Orderable Device
Package Type Package
Drawing
Pins
Package Qty
Lead/
Ball Finish
(Requires Login)
TPS24710DGS
TPS24710DGSR
TPS24711DGS
TPS24711DGSR
TPS24712DGS
TPS24712DGSR
TPS24713DGS
TPS24713DGSR
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
MSOP
MSOP
MSOP
MSOP
MSOP
MSOP
MSOP
MSOP
DGS
DGS
DGS
DGS
DGS
DGS
DGS
DGS
10
10
10
10
10
10
10
10
80
2500
80
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
Green (RoHS
& no Sb/Br)
2500
80
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
2500
80
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
2500
Green (RoHS
& no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
14-May-2011
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
13-May-2011
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS24710DGSR
TPS24711DGSR
TPS24712DGSR
TPS24713DGSR
MSOP
MSOP
MSOP
MSOP
DGS
DGS
DGS
DGS
10
10
10
10
2500
2500
2500
2500
330.0
330.0
330.0
330.0
12.4
12.4
12.4
12.4
5.3
5.3
5.3
5.3
3.4
3.4
3.4
3.4
1.4
1.4
1.4
1.4
8.0
8.0
8.0
8.0
12.0
12.0
12.0
12.0
Q1
Q1
Q1
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
13-May-2011
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPS24710DGSR
TPS24711DGSR
TPS24712DGSR
TPS24713DGSR
MSOP
MSOP
MSOP
MSOP
DGS
DGS
DGS
DGS
10
10
10
10
2500
2500
2500
2500
358.0
358.0
358.0
358.0
335.0
335.0
335.0
335.0
35.0
35.0
35.0
35.0
Pack Materials-Page 2
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