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TPS24772

TPS24771

TPS24770

ZHCSDK8 –MARCH 2015

TPS2477x 2.5 至 18V 高性能热插拔

1 特性

3 说明

1

•

2.5V 至 18V 总线操作（30V 绝对最大值）

可编程保护设置：

TPS2477x 是一款针对 2.5V 至 18V 系统的高性能模

拟热插拔控制器。 TPS2477x 精确且具有高度可编程

保护设置，对设计故障隔离要求较高的高功率、高可用

性系统很有帮助。

–

电流限制：10mV 时为 ±5%

快速跳变：20mV 时为 ±10%

•

可编程场效应管 (FET) 安全运行区域 (SOA) 保护

可编程快速跳变的响应时间

该控制器还具有可编程电流限制、快速关断和故障定时

器功能，可在热短路等故障期间保护负载和电源。可

调整快速关断阈值和响应时间，以确保快速响应实际故

障，同时避免误跳变。该器件具有可编程的安全工作

区域 (SOA) 保护和浪涌定时器，可在所有条件下对金

属氧化物半导体场效应晶体管 (MOSFET) 加以保护。

TPS2477x 将电源正常状态标志置为有效后，会在过流

事件期间作为断路器工作并运行故障定时器，但不会限

制电流。当故障定时器到期后，控制器会关断。该控

制器具有两个独立定时器（浪涌/故障），用户可根据

系统需求定制保护功能。

双定时器（浪涌/故障）

模拟电流监视器（25mV 时为 1%）

可编程欠压 (UV) 与过压 (OV)

故障和电源正常状态标志

4mm × 4mm 24 引脚四方扁平无引线 (QFN) 封装

70 = 锁存，71 = 重试，72 = 快速锁存关闭

2 应用

•

企业级存储

企业级服务器

网络卡

最后，TPS2477x 非常灵活，可帮助热插拔设计满足

240VA 要求，本数据表中给出了一个设计示例。

240VA 应用

器件信息⁽¹⁾

器件型号

TPS24770

封装

封装尺寸（标称值）

TPS24771

TPS24772

RGE (24)

4.00mm x 4.00mm

(1) 要了解所有可用封装，请见数据表末尾的可订购产品附录。

4 简化电路原理图

HS FET

R_SNS

V_IN

V_OUT

将输出功率限制在 240VA，

20A I_LIM与 TPS2477x 实现的对比

C_OUT

C1

0.1 ꢀF

C_FST

R_HG

300

VA Limiting with TPS2477x

Regular 20 A ILIM

VDD SET FSTP

SENM HGATE OUTH

280

PGHS

FLTb

260

240

220

200

180

ENHS

OV

TPS2477x

IMONBUF

TFLT

TINR

PLIM

GND

IMON

C_INR

C_FLT

10

11

12

13

14

Output Voltage (V)

C022

1

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

English Data Sheet: SLVSCZ3

TPS24772

TPS24771

TPS24770

ZHCSDK8 –MARCH 2015

www.ti.com.cn

9.1 Overview ................................................................. 10

9.2 Functional Block Diagram ....................................... 10

9.3 Feature Description................................................. 11

9.4 Device Functional Modes........................................ 16

10 Application and Implementation........................ 17

10.1 Application Information.......................................... 17

10.2 Typical Application ............................................... 17

11 Power Supply Recommendations ..................... 40

12 Layout................................................................... 40

12.1 Layout Guidelines ................................................. 40

12.2 Layout Example .................................................... 42

13 器件和文档支持 ..................................................... 43

13.1 相关链接................................................................ 43

13.2 商标....................................................................... 43

13.3 静电放电警告......................................................... 43

13.4 术语表 ................................................................... 43

14 机械、封装和可订购信息....................................... 43

1

2

3

4

5

6

7

8

特性.......................................................................... 1

应用.......................................................................... 1

说明.......................................................................... 1

简化电路原理图........................................................ 1

修订历史记录 ........................................................... 2

Device Comparison Table..................................... 3

Pin Configuration and Functions......................... 3

Specifications......................................................... 4

8.1 Absolute Maximum Ratings ...................................... 4

8.2 ESD Ratings ............................................................ 4

8.3 Recommended Operating Conditions....................... 5

8.4 Thermal Information ................................................. 5

8.5 Electrical Characteristics........................................... 5

8.6 Timing Requirements ............................................... 7

8.7 Typical Characteristics.............................................. 8

Detailed Description ............................................ 10

9

5 修订历史记录

日期

修订版本

注释

2015 年 3 月

*

最初发布。

2

TPS24772

TPS24771

TPS24770

www.ti.com.cn

ZHCSDK8 –MARCH 2015

6 Device Comparison Table

PART NUMBER⁽¹⁾

TPS24770

LATCH / RETRY OPTION

Latch

TPS24771

Auto – Retry

TPS24772

Fast Latch Off

(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI

web site at www.ti.com.

7 Pin Configuration and Functions

QFN 24-Pin with Thermal Pad

RGE Package

Top View

19

24

23

22

21

20

NC

ENHS

NC

HGATE

SENM

FSTP

SET

TPS2477x

FLTb

PGHS

NC

VDD

IMONBUF

7

9

11

8

10

12

Pin Functions

TYPE⁽¹⁾

DESCRIPTION

NAME

ENHS

FLTb

NO.

2

I

O

I

Active-high enable input of Hot Swap. Logic input. Connects to resistor divider.

Active-low, open-drain output indicating various faults.

4

FSTP

16

Fast trip programming set pin for Hot Swap. A resistor is connected from positive terminal of R_SNSto

FSTP.

GND

10

18

12

13

–

O

Ground.

HGATE

IMON

Gate driver output for external Hot Swap MOSFET.

Analog monitor and current limit program point. Connect R_IMONto ground.

Voltage output proportional to the load current (0V–3.0V).

No connect. Tie to ground or leave floating.

I/O

O

IMONBUF

NC

1,3, 6,

20–24

NC

(1) I = Input; O = Output ; P = Power, NC = No Connect

3

TPS24772

TPS24771

TPS24770

ZHCSDK8 –MARCH 2015

www.ti.com.cn

Pin Functions (continued)

TYPE⁽¹⁾

DESCRIPTION

NAME

NO.

OUTH

19

I

Output voltage sensor for monitoring Hot Swap MOSFET's power. Connects to the source terminal of

the Hot Swap N channel MOSFET.

OV

9

Overvoltage comparator input. Connects to resistor divider. HGATE is pulled low when OV exceeds the

threshold. Connect to ground when not used.

PGHS

PLIM

5

O

I

Active-high, open-drain power-good indicator.

11

Power limit programming pin. A resistor from this pin to GND sets the maximum power dissipation for

the Hot Swap FET. Connect a 4.99 kΩ resistor to disable power limit.

SENM

SET

17

15

I

Current-sensing input for the sense resistor. Directly connects to the negative terminal of the sense

resistor.

Current-limit programming set pin for Hot Swap. A resistor is connected from positive terminal of the

sensing resistor.

TFLT

TINR

VDD

8

7

I/O

P

Fault timer, which runs when the device is in regular operation and there is an overcurrent condition.

Inrush timer, which runs during the inrush operation (start-up) if the part is in current limit or power limit.

Power Supply

14

8 Specifications

8.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)

(1)

MIN

–0.3

–0.6

–0.3

MAX

30

15

0.3

3.6

7

UNIT

V

VDD,SET, FSTP,SENM, OUTH, ENHS, FLTb, PGHS, OV

HGATE to OUTH

V

SET to VDD

Input Voltage

V

SENM, FSTP to VDD

V

TINR, TFLT, PLIM, IMON

IMONBUF

V

Sink Current

FLTb, PGHS

5

mA

°C

Source Current IMON, IMONBUF

Storage temperature, T_stg

5

–65

150

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

8.2 ESD Ratings

VALUE

±1500

±500

UNIT

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽²⁾

Charged-device model (CDM), per JEDEC specification JESD22-C101⁽³⁾

Electrostatic

discharge

(1)

V_(ESD)

V

(1) Electrostatic discharge (ESD) measures device sensitivity and immunity to damage caused by assembly line electrostatic discharges

into the device.

(2) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(3) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

4

TPS24772

TPS24771

TPS24770

www.ti.com.cn

ZHCSDK8 –MARCH 2015

8.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

2.5

0

MAX

18

UNIT

VDD, SENM, SET, FSTP

Input voltage

V

ENHS, FLTb, PGHS, OUTH

18

Sink current

FLTb, PGHS

IMON

0

2

mA

kΩ

Ω

Source current

0

1

PLIM

4.99

1

500

6

IMON

External resistance

FSTP

10

3

4000

400

70

SET

Ω

w/o R_STBL

(1)

R_IMON/ R_SET

With appropriate R_STBL

10

(2)

with C_HGATE> 47nF

10

1

200

TINR, TFLT

nF

µF

pF

°C

(2)

HGATE,

0

1

30

External capacitor

IMON

IMONBUF

100

125

Operating junction temperature, T_J

–40

(1) Refer to R_STBLRequirment for R_IMON/ R_SET< 10 as described in section Select R_SNSand V_SNS,CLSetting.

(2) External capacitance tied to HGATE, should be in series with a resistor no less than 1kΩ.

8.4 Thermal Information

RGE

THERMAL METRIC⁽¹⁾

UNIT

24 PINS

34.6

38.4

12.9

0.5

R_θJA

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

R_θJC(top)

R_θJB

°C/W

ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

ψ_JB

12.9

3.2

R_θJC(bot)

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

8.5 Electrical Characteristics

Unless otherwise noted these limits apply to the following: -40°C < T_J<125°C; 2.5V < V_VDD, V_OUT< 18V; V_ENHS= 2 V; V_OV= 0

V; V_HGATE, V_PGHS, V_FLTB, and V_IMONBUFare floating; C_INR= 1nF; C_FLT= 1nF; R_SET= 44.2 Ω; R_IMON= 2.98k Ω; R_FSTP= 200 Ω;

R_PLIM= 52 kΩ.

PARAMETER

TEST CONDITION

MIN

TYP

MAX

2.45

4

UNIT

INPUT SUPPLY (VDD)

V_UVR

V_UVhyst

I_QON

UVLO threshold, rising

UVLO hysteresis

2.2

2.32

0.10

2.95

V

Supply current: I_VDD+ I_OUTH

Device on, V_ENHS= 2V

mA

Hot Swap FET ENABLE (ENHS)

V_ENHS

Threshold voltage, rising

1.3

–1

1.35

50

1.4

1

V

V_ENHShyst

I_ENHS

Hysteresis

mV

µA

Input Leakage Current

0 ≤ V_ENHS≤ 30V

OVER VOLTAGE (OV)

V_OVR

V_OVhyst

I_OV

Threshold voltage, rising

1.3

–1

1.35

50

1.4

1

mV

µA

Hysteresis

Input leakage current

0 ≤ V_OV≤ 30V

5

TPS24772

TPS24771

TPS24770

ZHCSDK8 –MARCH 2015

www.ti.com.cn

Electrical Characteristics (continued)

Unless otherwise noted these limits apply to the following: -40°C < T_J<125°C; 2.5V < V_VDD, V_OUT< 18V; V_ENHS= 2 V; V_OV= 0

V; V_HGATE, V_PGHS, V_FLTB, and V_IMONBUFare floating; C_INR= 1nF; C_FLT= 1nF; R_SET= 44.2 Ω; R_IMON= 2.98k Ω; R_FSTP= 200 Ω;

R_PLIM= 52 kΩ.

PARAMETER

TEST CONDITION

MIN

TYP

MAX

UNIT

POWER LIMIT PROGRAMING (PLIM)

V_PLIM,BIAS

Bias voltage

Sourcing 10μA

0.65

114.75

56.95

18.9

0.675

0.7

V

R_PLIM= 52 kΩ; V_SENM-OUTH=12V

R_PLIM= 105 kΩ; V_SENM-OUTH=12V

R_PLIM= 261 kΩ; V_SENM-OUTH=12V

R_PLIM= 105 kΩ; V_SENM-OUTH=2V

R_PLIM= 105 kΩ; V_SENM-OUTH=18V

135 155.25

67

27

77.05

35.1

V_IMON,PL

Regulated IMON voltage during power limit

mV

µV

341.7

38.25

402

45

462.3

51.75

SLOW TRIP THRESHOLD (SET)

V_{OS_SET}Input referred offset (V_SNSto V_IMONscaling)

V_{GE_SET}

Gain error (V_SNSto V_IMONscaling)⁽¹⁾

FAST TRIP THRESHOLD PROGRAMMING (FSTP)

–150

150

R_SET= 44.2Ω; R_IMON=3kΩ to 1.2kΩ (V_SNS,CL=10mV

to 25mV)

–0.4%

0.4%

I_FSTP

FSTP input bias current

V_FSTP=12V

95

18

100

20

105

22

µA

R_FSTP= 200 Ω, V_SNSwhen V_HGATE

↓

V_FASTRIP

Fast trip threshold

R_FSTP= 1 kΩ, V_SNSwhen V_HGATE

R_FSTP= 4 kΩ, V_SNSwhen V_HGATE

↓

95

100

400

105

420

mV

↓

380

CURRENT SUMMING NODE (IMON)

V_IMON,CLSlow trip threshold at summing node

I_IMON-LKGIMON leakage current

CURRENT MONITOR (IMONBUF)

V

_IMON↑, when I_TFLTstarts sourcing

660

675

690

200

mV

nA

V_ENHS=0V, V_IMON= 1.5V

–200

V_{OS_IMONBUF}

GAIN_IMONBUF

BW_IMONBUF

Buffer offset

V_IMON= 50mV to 675mV, Input referred

ΔV_IMONBUF/ ΔV_IMON

–3

0

2.99

1

3

mV

V

Buffer voltage gain

Buffer closed loop bandwidth

2.97

3.01

C_IMONBUF= 75pF

MHz

Hot Swap GATE DRIVER (HGATE)

5 ≤ V_VDD≤ 16V; measure V_HGATE-OUTH

12

7

13.6

7.95

15.5

15

V

V_HGATE

HGATE output voltage

2.5V <V_VDD< 5V;

16V <V_VDD< 20V measure V_HGATE-OUTH

V_HGATEmax

I_HGATEsrc

I_{HGATEfastSink}

I_{HGATEsustSink}

Clamp voltage

Inject 10μA into HGATE, measure V_{(HGATE – OUTH)}

V_HGAT-OUTH= 2V-10V

12

44

13.9

55

1

15.5

66

V

µA

A

Sourcing current

Sinking current for fast trip

Sustained sinking current

V_HGATE-OUTH= 2V–15V; V_{(FSTP – SENM)}= 20mV

Sustained, V_HGATE-OUTH= 2V – 15V; V_ENHS= 0

0.45

30

1.6

60

44

mA

INRUSH TIMER (TINR)

I_TINRsrc

I_TINRsink

V_TINRup

Sourcing current

V_TINR= 0V, In power limit or current limit

V_TINR= 2V, In regular operation

8

1.5

1.3

10.25

2

12.5

2.5

µA

V

Sinking current

Upper threshold voltage

Raise V_TINRuntil HGATE starts sinking

1.35

1.4

Raise V_TINRto 2V. Reduce V_TINRuntil I_TINRis

sourcing.

V_TINRlr

Lower threshold voltage

0.33

0.35

0.37

v

R_TINR

Bleed down resistance

Pulldown current

Cycle number

V_VDD= 0V, V_TINR= 2V

70

2

104

4.2

130

7

kΩ

I_TINR-PD

V_TINR= 2V, when V_ENHS= 0V

mA

RETRY_CYCLE

# of timer cycles before retry (TPS24771 only)

TFLT and TINR connected (TPS24771 only)

TFLT and TINR not connected (TPS24771 only)

64

0.70%

0.35%

RETRY_DUTY

Retry duty cycle

R_PLIM= 52kΩ, V_SENM= 12V, V_OUTH= 0 V. Raise

IMON voltage and record IMON when TINR starts

sourcing current.

See Using Soft Start - I_HGATEand TINR

Considerations

V_IMON,TINR

47.75

90 132.25

mV

R_PLIM= 52kΩ, V_SENM-OUTH= 12V, Raise IMON

voltage and record IMON when I_HGATEstarts sinking

current.

See Using Soft Start - I_HGATEand TINR

Considerations

V_IMON,PL

114.75

23

135 155.25

mV

See Using Soft Start - I_HGATEand TINR

Considerations

ΔV_IMON,TINR

ΔV_IMON,TINR= V_IMON,PL- V_IMON,TINR

45

67

(1) Specified by characterization.

6

TPS24772

TPS24771

TPS24770

www.ti.com.cn

ZHCSDK8 –MARCH 2015

Electrical Characteristics (continued)

Unless otherwise noted these limits apply to the following: -40°C < T_J<125°C; 2.5V < V_VDD, V_OUT< 18V; V_ENHS= 2 V; V_OV= 0

V; V_HGATE, V_PGHS, V_FLTB, and V_IMONBUFare floating; C_INR= 1nF; C_FLT= 1nF; R_SET= 44.2 Ω; R_IMON= 2.98k Ω; R_FSTP= 200 Ω;

R_PLIM= 52 kΩ.

PARAMETER

TEST CONDITION

MIN

TYP

MAX

UNIT

FAULT TIMER (TFLT)

I_TFLTsrc

I_TFLTsink

V_TFLTup

R_TFLT

Sourcing current

Sinking current

V_TFLT= 0V, PGHS is high and in overcurrent

V_TFLT= 2V, Not in overcurrent

8

1.5

1.3

70

2

10.25

2

12.5

2.5

1.4

130

7

µA

V

Upper threshold voltage

Bleed down resistance

Pulldown current

Raise V_TFLTuntil HGATE starts sinking

V_ENHS= 0V, V_TFLT= 2V

1.35

104

5.6

kΩ

mA

I_TFLT-PD

V_TFLT= 2V, when V_ENHS= 0V

HOT SWAP OUTPUT (OUTH)

I_{OUTH, BIAS}

Input bias current

V_OUTH= 12V

30

70

µA

FAULT INDICATOR (FLTb)

V_{OL_FLTb}

I_FLTb

V_{HSFLT_IMON}

V_{HSFL_hyst}

Output low voltage

Input leakage current

Sinking 2 mA

0.11

0

0.25

1

V

V_FLTb= 0V, 30V

–1

88

µA

mV

V_IMONthreshold to detect Hot Swap FET short V_ENHS= 0V, Measured V_IMON↑ to GND when FLTb ↓

101

25

115

Hysteresis

HOT SWAP POWER GOOD OUTPUT (PGHS)

V_PGHSth

V_PGHShyst

V_{OL_PGHS}

I_PGHS

PGHS Threshold

Measure V_SENM-OUTH↓ when PGHS↑

V_SENM-OUTH

170

–1

270

80

375

mV

V

PGHS hysteresis

↑

PGHS Output low voltage

PHGS Input leakage current

Sinking 2mA

0.11

0

0.25

1

V_PGHS=0V to 30V

µA

THERMAL SHUTDOWN (OTSD)

T_OTSD

Thermal shutdown threshold

Hysteresis

Temperature rising

140

10

°C

T_OTSD,HYST

8.6 Timing Requirements

PARAMETER

TEST CONDITION

MIN

TYP

14

MAX

UNIT

µs

INPUT SUPPLY (VDD)

DEGL_UVLO

HOT SWAP FET ENABLE (ENHS)

DEGL_ENHSDeglitch time

OVER VOLTAGE (OV)

UVLO deglitch

Both rising and falling

2.2

3.8

3.9

5.5

5.7

µs

DEGL_OV

Deglitch time

µs

FAST TRIP (FSTP)

V_{(FSTP – SENM)}: –5mV to 5mV, C_HGATE= 0 pF

V_{(FSTP – SENM)}: -20mV to 20mV C_HGATE= 0 pF

600

300

63

t_FastOffDly

Fast turn-off delay

ns

µs

t_FastOffDur

Strong pull down current duration

53

73

INRUSH TIMER (TINR)

N_RETRY

Number of TINR cycles before retry

Retry duty cycle

TPS24741 only

64

0.35%

0.7%

T_INRnot connected to T_FLT

T_INRconnected to T_FLT

RETRY_DUTY

FAULT INDICATOR (FLTb)

t_{FLT_degl}Fault deglitch

HOT SWAP POWER GOOD OUTPUT (PGHS)

Both rising and falling

2.2

3.9

5.3

ms

Rising

Falling

0.7

7

1

8

1.3

9

t_PGHSdegl

PGHS deglitch time

7

TPS24772

TPS24771

TPS24770

ZHCSDK8 –MARCH 2015

www.ti.com.cn

8.7 Typical Characteristics

Unless otherwise noted these cureves apply to the following: -40°C < T_J<125°C; 2.5V < V_VDD, V_OUT< 18V; V_ENHS= 2 V; V_OV

0 v; V_HGATE, V_PGHS, V_FLTB, and V_IMONBUFare floating; C_INR= 1nF; C_FLT= 1nF; R_SET= 44.2 Ω; R_IMON= 2.98k Ω; R_FSTP= 200 Ω;

R_PLIM= 52 kΩ.

=

10

8

20

15

10

5

T = ±40C

T = 25°C

T = 125°C

T = ±40C

T = 25°C

T = 125°C

6

4

2

0

5

0

10

15

20

0

±50

0

5

0

3

10

15

20

Input Voltage (V)

Iq = I_VDD+I_OUTH

VDD (V)

C001

C002

Figure 1.

Figure 2.

0.50

0.40

0.30

0.20

0.10

0.00

1.40

1.38

1.36

1.34

1.32

1.30

1.28

1.26

1.24

1.22

1.20

Rising

Falling

Vpghs

50

100

150

±50

50

100

150

Temperature (C)

I_PGHS=2mA

Temperature (C)

C005

C006

Figure 3.

Figure 4.

1.40

1.38

1.36

1.34

1.32

1.30

1.28

1.26

1.24

1.22

1.20

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0.0

Rising

Falling

RPLIM = 51.1 k

RPLIM = 105 k

RPLIM = 261 k

50

100

150

±50

1

2

4

5

6

7

8

9

10 11 12

Temperature (C)

V_IN- V_OUTH(V)

C008

C009

V_IMONduring Power Limiting

Figure 5.

Figure 6.

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Typical Characteristics (continued)

Unless otherwise noted these cureves apply to the following: -40°C < T_J<125°C; 2.5V < V_VDD, V_OUT< 18V; V_ENHS= 2 V; V_OV

=

0 v; V_HGATE, V_PGHS, V_FLTB, and V_IMONBUFare floating; C_INR= 1nF; C_FLT= 1nF; R_SET= 44.2 Ω; R_IMON= 2.98k Ω; R_FSTP= 200 Ω;

R_PLIM= 52 kΩ.

2.0

1.5

0.5

0.4

0.3

0.2

0.1

0.0

±0.1

1.0

0.5

0.10

0.08

0.06

0.04

0.02

0.00

±0.02

T = ±40C

T = 25°C

T = 125°C

Vsns

1.0

0.5

0.0

±0.5

±1.0

±1.5

T = ±40C

T = 25°C

T = 125°C

Vsns

±0.5

±1.0

0

20

40

60

80

100

±20

0

50

100

±50

Time (µs)

C010

C011

V_HGATE-V_OUTH=10V

V_HGATE-V_OUTH=2V

Figure 7.

Figure 8.

50

40

30

20

10

0

30

25

20

15

10

5

0.20

0.15

0.10

0.05

0.00

±0.05

T = ±40C

T = 25°C

T = 125°C

Vsns

T = 125°C

0

1

2

3

4

5

6

7

8

9

10 11 12 13 14

0.0

0.2

0.4

0.6

±0.6

±0.4

±0.2

V_HGATE- V_OUTH(V)

Time (µs)

C014

C016

Sustained sink current

Figure 9.

Figure 10.

60

Ihgate

Itinr

40

20

0

±20

±40

±60

0

50

100

150

200

250

300

V_IMON

C018

V_HGATE-OUTH=4V

R_PLIM=52kΩ

T_J=25°C

Figure 11.

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9 Detailed Description

9.1 Overview

The TPS2477x Hot Swap features a programmable current limit, power limit, and fast trip threshold. It also has

dual timers: one for inrush and one during over current faults. Finally it features an analog current monitor that

can be used to provide current information to a microcontroller.

9.2 Functional Block Diagram

HS FET

V_OUT

+ V_SNS

-

V_IN

R_SNS

VDD

SET

FSTP

SENM

HGATE

OUTH

15

16

17

18

19

14

Fast

+ Comp

100ꢀA

HS

Charge

Pump

270mV

55ꢀA

dis_HS

44mA

FET_ON

HS_ON

PGH

HS_ON

5

HS

Control

EN_AMP

OUTH

AMP

+

ENHS

2

9

ON/

OFF

Control

Power

Limit

Engine

HS_SHORT

+

OV

101mV

LMT/OC

2.32V

Timer

1.35V

3x

7

4

10

12

11

8

13

IMONBUF

FLTB

PLIM

GND

IMON

R_IMON

TFLT

TINR

R_PLIM

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9.3 Feature Description

9.3.1 Enable and Over-voltage Protection

The part is enabled when the ENHS pin voltage exceeds 1.35V and is disabled when the pin voltage falls under

1.3V providing 50mV of hysteresis. A resistor divider can be connected to these pins to turn on the TPS2477x at

a certain bus voltage. The part will turn off if the OV pin exceeds 1.35V.

9.3.2 Current Limit and Power Limit during Start-up

The current limit and power limit of the TPS2477x are programmable to protect the load, power supply, and the

Hot Swap MOSFET. During start-up the active control loop will regulate the gate to ensure that the current

through the MOSFET and the power dissipation of the MOSFET is below their respective pre-programmed

thresholds. The maximum current allowed through the MOSFET (I_LIM) is determined with the equation below.

I_LIM,CLis the programmed current limit, P_LIMis the programmed power limit, and V_DSis the drain to source voltage

across the Hot Swap MOSFET.

æ

_LIMö

P

I_LIM= MIN I

ç _LIM,CL

,

÷

V_DS

è

ø

(1)

This results in an IV curve shown in Figure 12. I_LIM,PLdenotes the maximum allowed MOSFET current (I_DS) when

the part is in power limit. As V_DSincreases, I_LIM,PLdecreases and I_LIM,PL,MINdenotes the lowest I_LIM,PL, which

occurs at the largest V_DS(V_DS,MAX). The TPS2477x enforce this by regulating the voltage across R_SNS(V_SNS).

V_SNS,PLdenotes V_SNSwhen power limiting is active. Similarly to I_LIM,PL, V_SNS,PLdecreases as V_DSincreases and

V_SNS,PL,MINcorresponds to the lowest V_SNS,PL, which occurs at V_DS,MAX. V_SNS,CLis a current limiting sense voltage,

which is programmable in the TPS2477x.

V_SNS,CL

I_LIM,CL

V_SNS,PL

I_LIM,CL

I_LIM,PL,MIN

V_SNS,PL,MIN

V_DS

V_DS,MAX

V_DS

V_DS,MAX

Figure 12. Current vs V_DSand V_SNSvs V_DSProgrammed by Power Limit Engine.

The current and power limit can be programmed using the equations below.

sp

0.675´R_SET

=

V_SNS,CL

R_IMON

(2)

(3)

sp

V_SNS,CL

0.675´R_SET

=

I_LIM,CL

=

R_SNS

84375´R_SET

_PLIM´R_SNS´R_IMON

P

=

LIM

R

(4)

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Feature Description (continued)

Note, that the error is largest at V_SNS,PL,MINdue to offset of the internal amplifier. Also the operation at V_DS,MAXis

most critical because it corresponds to the short circuit condition and has the biggest impact on start time. Thus it

is critical to consider V_SNS,PL,MINduring design. Equation 5 shows the relationship of V_SNS,PL,MINas a function of

P_LIM, I_LIM,CL, V_SNS,CL, and V_DS,MAX. Note that I_LIM,CLand V_DS,MAXare usually determined by the system

requirements. The designer will have control over P_LIMand V_SNS,CL. In general, there will be a desire to reduce

the power limit to allow for smaller MOSFETs and to reduce the V_SNS,CLto improve efficiency (lower R_SNS).

However, this will also reduce V_SNS,PL,MINand the designer should ensure that it’s above the minimum

recommended value of 1.5mV.

sp

P

_LIM´ V_SNS,CL

V_SNS,PL,MIN

=

V_DS,MAX´I_LIM,CL

(5)

9.3.3 Two Level Protection During Regular Operation

After the TPS2477x has gone through start-up it will no longer actively control the gate. Instead it will run the

timer when the current is between the current limit and the fast trip threshold. Once the timer has expired the

gate will be pulled down. If the current ever exceeds the fast trip threshold, the gate will be pulled down

immediately.

9.3.4 Dual Timer (TFLT and TINR)

TPS2477x has two timer pins to allow the user to customize the protection. The TINR pin will source 10.25 µA

when the device is in start-up mode and is actively regulating the gate to limit the MOSFET power or current. It

will sink 2 µA otherwise. The TFLT pin will source 10.25 µA when the device is in regular operation and the FET

current exceeds the current limit. It will sink 2 µA otherwise. If either of the timer pins exceeds 1.35, the

TPS2477x will time out. The TPS24770 and TPS24772 will latch off. The TPS24771 will go through 64 cycles of

TINR and attempt to start-up again.

Since the TINR usually runs when the MOSFET is being stressed, TINR should be sized to maintain the FET

within its SOA. In general TFLT runs when the load is drawing more current than expected, which can stress the

load and the power supply. Thus TFLT should be programmed to have the right protection settings for the power

supply and the load. In some systems the load is allowed to draw current above the current limit for 250ms or 1s.

In that case a large TFLT is required, but a short TINR may still be desired to minimize the worst case FET

stress. In other applications a long TINR may be required to due to large downstream capacitances, but drawing

excessive current from the power supply for more than 5ms is not desired. In that case a short TFLT and a long

TINR should be used. Finally, many applications can use the same TINR and TFLT setting, in which case the

pins can be tied together and a single capacitor can be used. The two different options are shown in Figure 13.

TINR

TFLT

TINR

TFLT

C_FLT

C_INR

C_TMR

Figure 13. Timer Configurations

If two separate timer capacitors are used their values can be computed with the equations below:

sp

C_INR= 7.59 mF / s´ T

INR

(6)

(7)

sp

C_FLT= 7.59 mF / s´ T_FLT

sp

If a single capacitor is used C_TMRcan be computed with Equation 8.

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Feature Description (continued)

C_TMR= 6.11 mF / s´ T_TMR

(8)

9.3.5 3 Options for Response to a Fast Trip

The TPS24770, TPS24771, and TPS24772 have difference responses to a fast trip event to accommodate

different design requirements. When the current exceeds the fast trip threshold, the gate is quickly pulled down to

minimize damage that can be caused due to a short circuit. Figure 14 shows the response of the variout devices

options to a hot short on the output. The TPS24770 (latch) will attempt to re-start once after the hot-short is

observed and then stay off, the TPS24771 will continuously retry with a duty cycle of ~0.5% (0.7% if T_FLTand

T_INRare connected, 0.35% if T_FLTand T_INRare not connected), and the TPS24772 (fast latch off) will shut off and

never retry again. In general the TPS24772 will place the least amount of stress on the MOSFET, but is the least

likely to recover from a nuissance trip.

Hotshort Occurs

HGATE

TPS24770 - Latch

Retry once

VIN

Retries

Continuously. ~

0.5% duty cycle

HGATE

VIN

TPS24771 - retry

TPS24772 ±

Fast Latch Off

HGATE

VIN

Shuts Off and no

Retry

Figure 14. TPS24770/1/2 Response to a Short Circuit

9.3.6 Using Soft Start - I_HGATEand TINR Considerations

During start-up the TPS2477x regulates the HGATE to keep the FET power dissipation within P_LIM. This is

accomplished by an amplifier that monitors the IMON voltage and an internal reference voltage. The TPS2477x

will source current into HGATE if VIMON is lower than the reference voltage and will sink current into HGATE if

VIMON is above the reference voltage. In steady state, the V_IMONwill be regulated to the V_IMON,PLpoint, where

I_HGATEequals zero. Note that V_IMON,PLis a determined by R_PLIMand V_SENM– V_OUTH

.

The same amplifier feeds into the inrush timer circuitry to run the timer when the part is in power limit. The V_IMON

threshold at which the timer starts to source current is denoted as V_IMON, T_INR. Note that V_IMON,TINRis lower than

V_IMON,PLto account for tolerances and ensure that the timer is always active when the device is in power limit.

The difference between the two thresholds is defined as ΔV_{IMON, TINR}. Refer to Figure 11 for a typical I_HGATEand

I_TINRvs V_IMONcurve.

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Feature Description (continued)

Figure 15. I_TINRand I_HGATEvs V_IMON(V_DS= 12V, R_PLIM= 52kΩ)

It is critical to consider ΔV_IMON,

and Figure 15 if a soft start circuit is used. Typically, the soft start is

TINR

implemented by limiting the gate dv/dt with a capacitor, which in turn limits the inrush current to the output

capacitor. Often times, the inrush current is kept below I_LIM,PLto keep the timer from running. Note that the I_LIM,PL

is based on the V_IMON,PLthreshold and thus T_INRcan be activated even if the inrush current is below I_LIM,PL. To

prevent the timer from running unintentionally, the P_LIMshould be chosen above P_LIM,MIN,SS, which can be

computed as shown below. As an example consider the usage case where the maximum inrush current (I_INR,MAX

)

is 2A, the maximum input voltage (V_IN,MAX) is 13V and R_SET, R_IMON, and R_SNSare 100Ω, 2.7kΩ, and 1mΩ

respectively. For that case the power limit should be set to at least 58.3 W + P_LIMtolerance to ensure that the

inrush timer doesn’t run.

æ

ö

÷

ø

R_SET

P

= I

ç _INR,MAX

+ DV

´

´ V

IN,MAX

LIM,MIN,SS

IMON,TINR,MAX

R_IMON´R_SNS

è

100W

2.7kW´1mW

æ

ö

= 2A + 67mV ´

´13V = 58.3W

ç

÷

è

ø

(9)

9.3.7 Analog Current Monitor

The TPS2477x also features two analog current monitoring outputs: IMON and IMONBUF. Each has their own

advantages and disadvantages. The IMON is more accurate, because it doesn’t have the error added from the

second stage. However it is a high impedance output and leakage current on that node would result in

monitoring error. In addition it can only support 30pF of capacitance and its full scale range is 675mV (this is

where current limit kicks in). The IMONBUF takes the IMON signal and buffers it 3x. This introduces more error,

but the output is low impedance, has a larger full scale range, and can drive up to 100pF of capacitance.

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Feature Description (continued)

HS FET

+ V_SNS

R_SNS

–

V_IN

SET

SENM

HGATE

OUTH

15

17

18

19

x

3x

TPS2477x

12

13

IMON

R_IMON

IMONBUF

Figure 16. Current Monitoring Circuitry

9.3.8 Power Good Flag

The TPS2477x has a power good flag, which should be used to turn on downstream DC/DC converters. This

reduces the stress on the Hot Swap MOSFET during start-up. The PGHS pin of the TPS2477x is asserted (with

1 ms deglitch) when both:

•

Hot Swap is enabled and

V_DSof Hot Swap MOSFET is below 240 mV.

PGHS is de-asserted (with 8 ms deglitch) when either:

•

Hot Swap is disabled.

VDS of Hot Swap MOSFET is above 310 mV

In an overcurrent condition that causes the timer to time out and latch off.

9.3.9 Fault Reporting

TPS2477x will assert a fault by pulling down on the FLTb pin if any of the following occur:

•

Hot Swap MOSFET Shorted Fault ( ENHS = LO, but VIMON > 101 mV)

Hot Swap timer times out.

Over Temperature Shut Down (OTSD)

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9.4 Device Functional Modes

9.4.1 Hot Swap Functional Modes

The state machine for the Hot Swap section is shown in Figure 17. After a POR / UVLO event the Hot Swap

enters the Inrush up. Once operational the Hot Swap has the following functional modes:

•

Inrush Mode (INR): In this state the Hot Swap controller is actively regulating the HGATE to meet the current

limit and power limit settings. The inrush timer is running if the controller is in power or current limiting. If the

inrush timer times out the gate will be pulled down. The TPS24770 and TPS24772 will go to latched mode

and TPS24771 will go into retry mode.

•

Regular Operation Mode (REG): In this mode everything is operating properly so both the timers are

discharged and the HGATE is high. If there is an overcurrent condition (V_SNS> V_SNS,CL), the device will go

into fault mode. If there is a fast trip condition (V_SNS> V_FSTP), the gate will be pulled down with a 1A / 63 µs

pulse. The TPS24772 will go to the latched state and the TPS24770 and TPS24771 will go back to inrush for

a retry.

•

Fault Mode (FLT): In this mode the TPS2477x runs the fault timer. Once the timer expires the TPS24770

and TPS24772 will go to latch mode while TPS24771 will go to retry mode. If the overcurrent condition is

removed the controller will go back to the regular operation mode.

Latched Mode (Latched): In the latched mode the HGATE is low, the timer is being discharged, and the

FLTb is asserted. If there is a rising edge on ENHS the part will discharge the timers and go to the inrush

mode.

Retry Mode (Retry): Here the part will charge and discharge the inrush timer 64 times before attempting

another retry.

TPS24770/1

TPS24772

FSTRP=1

REG:

Latched

I_TINR= -2uA

I_TFLT= -2uA

HGATE: Low

RST

Discharge

Timers

EN_RE

TPS24770/2

INR:

EN_RE

I_TFLT= -2uA

I_TINR= -2uA

EN_AMP=0

HGATE: High

LMT =1: I_TINR= 10uA

LMT=0: I_TINR= 0

I_TFLT= -2uA

PGHS=1

UVLO

EN_AMP=1

HGATE: regulating

Count=63

Count<63

Retry Mode

Auto_Chg

I_TINR= 10uA

I_TFLT= -2uA

HGATE: Low

OC=1

OC=0

V_TINR>1.35

Legend:

LMT: In power or current limit

OC: Over Current (V_IMON>675mV)

EN_RE: Rising edge on ENHS

TO: Timer Timed Out

FLT:

I_TFLT= +10uA

I_TINR= -2uA

EN_AMP=0

HGATE: High

V_TINR>1.35

V_TFLT>1.35

Auto_Disch

V_TINR<0.35

Count +1

HGATE: Low

EN_AMP: Enable current limit and

power limit amplifier, which actively

regulates the sense voltage.

I_TINR= -2uA

I_TFLT= -2uA

HGATE: Low

TPS24771

FSTRP: Fast trip comparator is tripped

ILO: Immediate Latch Off. OTP setting

for no re-start after Fast Trip

Figure 17. Hot Swap State Machine

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10 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

10.1 Application Information

The TPS2477x is a highly configurable Hot Swap controller that can be fine-tuned for the application

requirement. When designing a Hot Swap 3 key scenarios should be considered:

•

Start-up.

Output of a Hot Swap is shorted to ground when the Hot Swap is on. This is often referred to as a “Hot-

Short”.

•

Powering up a board when the output and ground are shorted. This is usually called a “start into short”.

All of these scenarios place a lot of stress on the Hot Swap MOSFET and special care must be taken when

designing the Hot Swap circuit to keep the MOSFET within its Safe Operating Area (SOA). Note that the

component selection can often be iteratively and it’s recommended to use the publically available excel

calculators to crunch the numbers. See the TPS24770 Design Calculator in the Tools & Software link on the

Product folder.

10.2 Typical Application

Three application examples are provided. The first one is for a 100A Hot Swap with 5,500 µF of output

capacitance that uses standard power limited based start-up. Then there are two examples of designing for the

240 VA design requirment. One uses the CSD16415Q5B, which is an older generation MOFSET with great SOA.

The second one uses the CSD17573Q5B, which has lower SOA, but is more cost effective (price vs R_DSON).

10.2.1 12 V, 100 A, 5,500 µF Analog Hot Swap Design

The diagram below shows the application schematic for this design example.

0.5 Pꢀ[ꢀ3

CSD16415 x 4

R_SNS

V_OUT

V_IN

C_FST

2nF

D1

C_OUT

D2

MBRS330T3G

C1

R_SET

R_HG

R_FSTP

249ꢀ

SMDJ14

0.1ꢀF

1 ꢀF

73.2ꢀ

10ꢀ

VDD SET

ENHS

FSTP

SENM HGATE OUTH

R_DIV1

PGHS

FLTb

49.9Nꢀ

TPS2477x

R_DIV2

2.21Nꢀ

IMONBUF

TFLT

OV

TINR

PLIM

GND

R_DIV3

IMON

C_ENHS

33nF

R_PLIM

118Nꢀ

C_INR

47nF

C_FLT

5.62Nꢀ

R_IMON

2.67Nꢀ

2.2µF

Figure 18. Application Schematic for 100 A Hot Swap

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Typical Application (continued)

10.2.2 Design Requirements

Table 1 summarizes the design parameters that must be known before designing a Hot Swap circuit. When

charging the output capacitor through the Hot Swap MOSFET, the FET’s total energy dissipation equals the total

energy stored in the output capacitor (1/2CV²). Thus both the input voltage and output capacitance will determine

the stress experienced by the MOSFET. The maximum load current will drive the current limit and sense resistor

selection. In addition, the maximum load current, maximum ambient temperature, and the thermal properties of

the PCB (R_θCA) will drive the selection of the MOSFET R_DSONand the number of MOSFETs used. R_θCAis a

strong function of the layout and the amount of copper that is connected to the drain of the MOSFET. Air cooling

will also reduce R_θCA. It’s also important to know if there are any transient load requirements. Finally, whether

current monitoring is needed and its accuracy requirement will drive the selection of R_SNS, R_IMON, and R_SET

.

Table 1. Design Requirements for a 12V, 100A, 5500µF Hot Swap Design

DESIGN PARAMETER

EXAMPLE VALUE

Input voltage range

11 V – 13 V

100A

Maximum DC load current

Maximum Output Capacitance of the Hot Swap

Maximum Ambient Temperature

MOSFET R_θCA(function of layout)

Transient load requirement

5500 µF

55°C

50°C/W

130A for 250 ms

Yes

Pass “Hot-Short” on Output?

Pass a “Start into short”?

Yes

Is the load off until PG asserted?

Can a Hot Board be plugged in or Power Cycled?

IC used

Yes

No

TPS24772

No

Analog Current Monitor Used

10.2.3 Detailed Design Procedure

10.2.3.1 Select R_SNSand V_SNS,CLSetting

TPS2477x has a programmable V_SNS,CLwith a recommended range of 10 mV to 67.5 mV. It can be used with a

V_SNS,CLup to 200 mV, but that requires a resistor between SET and SENM to ensure stability of an internal loop.

This is shown in Figure 19. R_STBLcan be computed using the equation below.

R_IMON´R_SET

R_STBL

=

10´R_SET- R_IMON

(10)

For high power applications a lower V_SNS,CLleads to better efficiency so 20 mV is targeted for this design.

Targeting a current limit of 110A to allow margin for the load, the sense resistor can be calculated as follows:

V_SNS,TGT

20 mV

110 A

R_SNS,CLC

=

= 0.18 mW

I_LIM

(11)

Since 0.18 mΩ resistors aren’t available, the closest standard resistor should be chosen. To have better

efficiency, three 0.5mΩ resistors are used in parallel. Next the V_SNS,CLshould be computed based on the actual

R_SNSand then used to compute R_SETand R_IMON. R_SETis chosen to target 250 µA of current through SET and

IMON pins during current limit.

V_SNS,CL= I_LIM´R_SNS= 110 A ´0.1667 mW = 18.37 mV

(12)

V_SNS,CL

R_SET,CLC

=

= 73.3 W

250 mA

(13)

Chose R_SETto equal 73.2 Ω, which is the closest available standard resistor. Next obtain the calculated R_IMON

(R_IMON,CLC) as follows:

R

_SET´675 mV

73.2 W ´675 mV

R_IMON,CLC

=

= 2.69 kW

V_SNS,CL

18.37 mV

(14)

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Choose 2.67kΩ resistor for R_IMON, which is the closest available standard resistor. Since accurate current

monitoring is not needed a 2512 2 terminal sense resistor can be used.

Finally, compute the actual current limit (I_LIM,CL) and the analog current monitoring scaling factor V_IMON,GAIN(V_IMON

vs I_LOAD

)

0.675 V ´R_SET

0.675 V ´73.2 W

I_LIM,CL

=

_IMON´R_SENSE2.67 kW ´0.1667 mW

= 111 A

R

(15)

(16)

sp

R

_IMON´R_SNS

0.1667 mW ´ 2.67 kW

73.2W

V

=

= 6.08 mV / A

IMON,GAIN

R_SET

HS FET

V_IN

R_SNS

C1

0.1 μF

C_FST

R_HG

R_STBL

VDD SET FSTP

SENM

HGATE

ENHS

ENOR

OV

TPS2477x

IMON

PLIM

GND

Figure 19. Adding R_STBLfor V_SNS,CL> 67.5mV

10.2.3.2 Selecting the Fast Trip Threshold and Filtering

The TPS2477x allows the user to program the fast trip threshold. When this threshold is exceeded the gate is

quickly pulled down (<1µs). In addition C_FSTPcan be added to include some filtering into the comparator. The

selection of the fast trip threshold and filtering is influenced by the systems environment and requirements. In

general, picking a larger threshold and larger filtering time will result in more immunity to nuisance trips, but also

a slower response (possibly inadequate) to real fault conditions. It’s best to fine tune these threshold after testing

the real system. As a starting point it is recommended to set the fast trip threshold at least 1.25x larger than then

current limit. For this design example a 150A fast trip threshold along with a 500ns filtering time constant were

targeted to ensure that the transient requirement will be passed. The value for R_FSTPand C_FSTPcan be computed

as shown below:

I

_FSTP´R_SNS

150 A ´0.1667 mW

R_FSTP

=

= 250 W

100 µA

(17)

sp

t_FSTP

500 ns

C_FSTP

=

= 2 nF

R_FSTP

250 W

(18)

The next closest standard resistor and capacitor values should be chosen. In this case R_FSTP= 249Ω and

C_FSTP=2nF

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10.2.3.3 Selecting the Hot Swap FET(s)

It is critical to select the correct MOSFET for a Hot Swap design. The device must meet the following

requirements:

•

The V_DSrating should be sufficient to handle the maximum system voltage along with any ringing caused by

transients. For most 12V systems a 25 V or 30V FET is a good choice.

•

The SOA of the FET should be sufficient to handle all usage cases: start-up, hot-short, start into short.

R_DSONshould be sufficiently low to maintain the junction and case temperature below the maximum rating of

the FET. In fact, it is recommended to keep the steady state FET temperature below 125°C to allow margin to

handle transients.

•

Maximum continuous current rating should be above the maximum load current and the pulsed drain current

must be greater than the current threshold of the circuit breaker. Most MOSFETs that pass the first three

requirements will also pass these two.

A V_GSrating of +16 V is required, because the TPS2477x can pull up the gate as high as 15.5 V above

source.

For this design the CSD16415Q5B was selected for its low R_DSONand superior SOA. After selecting the

MOSFET, the maximum steady state case temperature can be computed as follows:

R_DSON

T

( )

J

T_C,MAX= T_A,MAX+ R_qCA´I_L²_OAD,MAX

´

n²

(19)

In the equation above n is the number of FETs used in parallel. For this example 4 FETS are used in parallel to

prevent over- heating and improve efficiency. Note that the R_DSONis a strong function of junction temperature,

which for most MOSFETS will be very close to the case temperature. A few iterations of the above equations

may be necessary to converge on the final R_DSONand T_C,MAXvalue. According to the CSD16415Q5B datasheet,

its R_DSONis about 1.3x greater at 100°C compared to room temperature . The equation below uses this R_DSON

value to compute the T_C,MAX. Note that the computed T_C,MAXis close to the junction temperature assumed for

R_DSON. Thus no further iterations are necessary. For this example an R_θCAof 50°C/W was used since there are 4

FETs close together and it’s expected that they will heat each other up. It’s highly recommended to test the

board at full load and double check the thermals with the calculations.

1.3´1 mW

(

2

)

C

T_C,MAX= 55°C + 50°

´ 100A

(

´

= 95.6°C

4²

(20)

W

10.2.3.4 Select Power Limit

In general, a lower power limit setting is preferred to reduce the stress on the MOSFET. However, at low power

limit levels both the V_SNSand V_IMONbecome very low, which results in more error caused by offsets. It is

recommended to keep V_SNSabove 1.5mV and V_IMONabove 27mV to ensure reasonable accuracy of the power

limit engine. Based on these requirements the minimum power limit can be computed as shown below.

V

V_IMON,MIN´R_SET

æ

ö

÷

ø

IN,MAX

P

=

´MIN V

,

ç

LIM,MIN

SNS,MIN

R_SNS

13 V

0.1667 mW

R_IMON

è

27 mV ´73.2 W

2.67 kW

æ

ö

=

´MIN 1.5 mV,

= 117 W

ç

÷

è

ø

(21)

In most applications the power limit can be set to P_LIM,MINusing the equation below. Here R_SNSand R_PWRare in

Ωs and P_LIMis in Watts.

sp

84375´R_SET

84375´73.2 W

R_PLIM

=

= 118.6 kW

R

_SNS´R_IMON´P

0.1.667 mW ´ 2.67 kW ´117 W

LIM

(22)

The closest available resistor should be selected. In this case it is a 118 kΩ.

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10.2.3.5 Set Fault Timer

The inrush timer runs when the Hot Swap is in power limit or current limit, which is the case during start-up. Thus

the timer has to be sized large enough to prevent a time-out during start-up. If the part starts directly into current

limit (I_LIMx V_DS< P_LIM) the maximum start time can be computed with the equation below:

C

_OUT´ V

IN,MAX

t_start,max

=

I_LIM,CL

(23)

For most designs (including this example) I_LIM,CLx V_DS> P_LIMso the Hot Swap will start in power limit and

transition into current limit. In that case the maximum start time can be computed as follows:

2

IN,MAX

2

é

ê

ë

ù

ú

û

é

ù

ú

V

C_OUT

2

P

LIM

2

I_LIM,CL

5500 mF (13 V)

117 W

t_start,max

=

´

+

=

´

+

= 4.0 ms

ê

ë

²ú

û

P

2

117 W

ê

ú

(110 A)

LIM

(24)

Note that the above start-time is based on typical current limit and power limit values. To ensure that the timer

never times out during start-up it is recommended to set the fault time (TINR) to be 1.5x t_start,maxor 6 ms. This will

account for the variation in power limit, timer current, and timer capacitance.

Next the designer should decide if having equal TINR and TFLT is acceptable. Note that to pass the load

transient the fault timer needs to be longer than 200 ms. If the inrush time is this long, it will place too much

stress on the MOSFET during a start into short. For this reason, it’s ideal to have two separate timers. To ensure

proper start up and to pass the load transient a target inrush time (T_INR,TGT) of 6 ms and a target fault time

(T_FLT,TGT) of 250ms is used. C_INR,CLCand C_FLT,CLCis computed as follows:

C_INR,CLC= 7.59 mF / s´ T

= 7.59 mF / s´ 6 ms = 45.6 nF

INR,TGT

(25)

sp

C_FLT,CLC= 7.59 mF / s´ T_FLT,TGT= 7.59 mF / s´ 250 ms = 1898 nF

(26)

The next largest available C_INRis chosen as 47 nF and the next largest available C_FLTis chosen as 2.2µF

Next, the actual T_INRand T_FLTcan be computed as shown below: Once the C_TMRis chosen the actual

programmed time out can be computed as follows.

C_INR

47 nF

T_TMR

=

7.59 mF / s 7.59 mF / s

= 6.2 ms

(27)

sp

C_FLT

7.59 mF / s 7.59 mF / s

2.2 mF

T_FLT

=

= 290 ms

(28)

10.2.3.6 Check MOSFET SOA

Once the power limit and fault timer are chosen, it’s critical to check that the FET will stay within its SOA during

all test conditions. For this design example the TPS24772 is used, which does not retry during a hot-short. Thus

the worst condition is a start-up into a short circuit. In this case the TPS24772 will start into a power limit and

regulate at that point for 6.2 ms (T_INR). Based on the SOA of the CSD16415Q5B, it can handle 13 V, 15 A for 10

ms and it can handle 13 V, 100 A for 1 ms. The SOA for 6.2 ms can be extrapolated by approximating SOA vs

time as a power function as shown below:

I_SOAt = a´ t^m

( )

100 A

15 A

æ

ö

ln

ç

÷

ln I

(

t

/ I

t

_SOA( ₁)

( )

)

SOA 2

è

ø

m =

=

= -0.82

ln t / t

(

1 ms

æ

ö

)

1

2

ç

è

÷

ø

10 ms

I_SOA

t

( ₁) ₌

100 A

0.82

( )

a =

= 100 A ´ ms

-0.82

t₁^m

1 ms

(

)

I_SOA6.2 ms = 100 A ´(ms)^0.82´(6.2 ms)^-0.82= 22.4 A

(

)

(29)

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Note that the SOA of a MOSFET is specified at a case temperature of 25°C, while the case temperature can be

hotter during a start into a short. It is important to understand the hottest temperature that a MOSFET can be

during a start-up (T_{C, MAX, START}). If a board has been off for a while and then it’s turned on T_{A, MAX}is a good

estimate for T_{C,MAX, START}. However, if a board is on and then gets power cycled or a hot board is unplugged and

plugged back in T_C,MAXshould be used for T_C,MAX,START. This will depend on system requirements. For this

design example it’s assumed that the board can only be plugged in cold and T_A,MAXis used to estimate

T_C,MAX,START

.

T_J,ABSMAX- T_A,MAX

T_J,ABSMAX- 25°C

150°C - 55°C

150°C - 25°C

I_SOA6.2 ms,T

(

= I

6.2 ms,25°C ´

( )

= 22.4 A ´

= 17 A

)

C,MAX,START

SOA

(30)

Based on this calculation the MOSFET can handle 17 A, 13 V for 6.2 ms at 55°C elevated case temperature, but

is only required to handle 9A during a start into short. Thus there is good margin and this will be a robust design.

In general, it is recommended that the MOSFET can handle 1.3x more than what is required during a hot-short.

This provides margin to cover the variance of the power limit and fault time.

10.2.3.7 Choose Under Voltage and Over Voltage Settings

The TPS2477x has comparators with 1.35V threshold on the ENHS, ENOR, and OV pins. A resistor divider can

be used to set Undervoltage and Overvoltage thresholds for the bus. For this design example 10V and 14V were

chosen as the limits to allow some margin for the 11V to 13V input bus. Once these limits are known, R_DIV2and

R_DIV3can be computed using the equations below. R_DIV1was set to 49.9 kΩ, which keeps the power

consumption reasonable low without being too susceptible to leakage currents.

R

_DIV1´1.35 V

49.9 kW ´1.35 V

R_DIV2,3= R_DIV2+ R_DIV3

=

= 7.79 kW

V_UV-1.35 V

10 V -1.35 V

(31)

sp

R

_DIV1+ R_DIV2,3´1.35 V

)

49.9 kW + 7.79 kW ´1.35 V

)

(

R_DIV3

=

= 5.56 kW

V_OV

14 V

(32)

(33)

R_DIV2= R_DIV2,3- R_DIV1= 7.79 kW - 5.56 kW = 2.23 kW

Choose closest available resistors standard 1% resistors: R_DIV2= 2.21 kΩ and R_DIV3= 5.62 kΩ. The actual Under

Voltage and Over Voltage settings can be computed for the chosen resistors as follows:

R

_DIV1+ R_DIV2+ R_DIV3

2.21 kW + 5.62 kW + 49.9 kW

2.21 kW + 5.62 kW

V_{UV _ act}= 1.35V ´

= 1.35 V ´

= 9.95 V

R_DIV2+ R_DIV3

(34)

(35)

sp

R

_DIV1+ R_DIV2+ R_DIV3

2.21 kW + 5.62 kW + 49.9 kW

5.62 kW

V_{OV _ act}= 1.35 V ´

= 1.35 V ´

= 13.87 V

R_DIV3

10.2.3.8 Selecting C₁and C_OUT

It is recommended to add ceramic bypass capacitors to help stabilize the voltages on the input and output. Since

C_INwill be charged directly on hot-plug, its value should be kept small. 0.1µF is a good target. Since C_OUT

doesn’t get charged during hot-plug, a larger value such as 1 µF could be used.

10.2.3.9 Adding C_ENHS

When the ENHS pin is pulled below its threshold and raised back up the IC will reset. Note that during a hot

short the input voltage can easily droop below the UV threshold and cycle the ENHS pin. For the TPS24770 and

TPS24771 ICs this will not change the behavior. However, when using the TPS24772 the cycling of the ENHS

will result in the IC attempting to restart, which is undesired (this is the main reason why someone would use the

TPS24772). To avoid this behavior a capacitor should be added to the ENHS to provide filtering. 33 nF was

chosen for this example.

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10.2.3.10 Selecting D1 and D2

During hot plug and hot short events there could be significant transients on the input and output of the Hot

Swap that could cause operation outside of the IC specifications. To ensure reliable operation a TVS on the input

and a Schottkey diode on the output are recommended. In this example a SMDJ14A and MBRS330T3G are

used.

10.2.3.11 Checking Stability

For most applications, the TPS2477x is stable without any additional components. However in some cases

additional C_GS,EXTis required as shown in the following figure to help stabilize the current and power limit loop.

Typically this is for low current limits and low sense voltages. It is easy to check whether these extra components

are needed using the equations below. Note that the transconductance (also referred to as gm and gfs) of the

FET will vary based on the current and thus gm' is used in the equations as a normalizing parameter. The

CSD16415Q5B has a gm of 168 siemens at 40A of I_DS, resulting in gm' of 26.56. For this example, C_GS,MIN(per

FET) was computed to be 0.25nF, while the C_ISSof the CSD16415Q5B is 3.15nF providing plenty of margin for

the design. In general it is recommended to have a 2x margin from the typical C_ISSand C_GS,MINto account for

any variation that the FET would have. If the C_ISSof the MOSFET isn't large enough an external RC should be

added as shown in the figure below.

ö^1.5

÷

ø

R_SNS

æ

ç

è

R_IMON

R_SET

C_GS,MIN= 6.54´10^-12´ gm'´

´

n

(36)

g_m

I

(_DS)

168

40

g_m^'

=

= 26.56

I_DS

(37)

(38)

1.5

2.67k

0.1667m

æ

ö

C_GS,MIN= 6.54´10^-12´ 26.56´

´

= 0.25nF

ç

÷

73.2

4

è

ø

C_GS,EXT

R_HG

1 kꢀ

HGATE

Figure 20. Adding C_GS,EXTto Ensure Stability

10.2.3.12 Compute Tolerances

After finishing a design it is often desired to know the variations of each setting. Often times there are multiple

error sources and there are two common ways to analyze the circuit. One is worst case, which adds all of the

error sources and the other one is root sum square (RSS), which is less conservative. When error sources are

independent, using the RSS method provides a more statistically accurate view of the tolerances. This method is

used in this section. Note that the error calculations are quite long and tedious and it’s recommended to use TI’s

excel tools, which support both worst case and RSS analysis. For this example the below tolerances are

assumed. The following table lists the assumptions for the component tolerances. Note that the sense resistor

itself is 1% accurate, but multiple two terminal 2512 resistors are used so additional error is introduced from

solder resistance and layout limitations of paralleling resistors. For this example 3% is assumed as the total error

of the sensing network.

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Table 2. Component Tolerances

COMPONENTS

TOLERANCE

R_IMONand R_SET

R_SNS(Including Layout + Soldering)

R_DIV1, R_DIV2, R_DIV3, R_PLIM, R_FST

C_INR, C_FLT

1%

3%

1%

10%

First, the tolerance of the current monitoring and current limit is computed.

There are 5 error sourcing contributing to the current monitoring accuracy on the IMON pin: tolerance of R_SET

(ER_SET), tolerance of R_IMON(ER_IMON), tolerance of R_SNS(E_RSNS), the IC gain error (ER_GAIN), and the IC offset

error (ER_OS). All of these errors are in % with the exception of the offset error. To get a percent error due to the

offset error (ER_OS%) simply divide the offset by the sense voltage. For the TPS2477x, ER_GAINis 0.4%, and ER_OS

is 150 µV.

Based on these values the full scale (I_FS,ERR,IMON) current monitoring accuracy at the Imon pin can be computed

with the following equations.

æ

ç

è

ö²

÷

ø

ER_OS

2

)

I_FS,ERR,IMON

=

ER

(

+ ER

+

_SET) ( _SNS) ( _IMON) (

GAIN

R_SNS´I_LIM

2

)

= 1%²+ 3%²+1%²+ 0.4%²+ 150 µV / 18.34 mV = 3.4%

(

(39)

Note that the TPS2477x detects the current limit when the IMON pin exceeds 675 mV. Thus the current limit

error I_LIM,ERis a combination of the I_FS,ERR,IMONand the current limit error at the I_MONpin (I_LIM,ERR,IMON). The 675

mV threshold varies up to 15 mV so I_LIM,ERR,IMONis 2.3% and the current limit error can be computed as follows:

2

_FS,ERR,IMON) (_LIM,ERR,IMON)

2

I_LIM,ERR

=

I

(

+ I

=

3.4%²+ 2.3%²= 4.1%

(40)

Next the power limit error is computed. This error is made up of three sources: the error from external

components (ER_COMP), the error when translating the sense voltage to IMON (I_{PL,ERR, IMON}), and the error of the

power limit engine at IMON (ER_IMON,PL). Both ER_SNSand ER_{IMON, PL}are a function of the operating point of the

power limit engine. Note that this error is greatest at largest V_DS, since V_SNS,PLis smallest (refer to Figure 12).

For this example V_DSis largest when V_IN= 13 V (maximum V_IN) and V_OUT= 0 V and the error is computed at this

operating point. The sense voltage (V_SNS) and the voltage at the IMON pin (V_IMON) should be computed for this

operating point using the equations below:

P

_LIM´R_SNS

117 W ´0.1667 mW

V_SNS

=

= 1.5 mV

V_DS

13 V

(41)

sp

V

_SNS´R_IMON

1.5 mV ´ 2670 W

V

=

= 54.7 mV

IMON

R_SET

73.2 W

(42)

The I_PL,ERR,IMONcan be computed similarly to I_FS,ERR,IMONusing the equation below.

sp

æ

ç

è

ö²

÷

ø

2

ER_OS

V_SNS

150 µV

1.5 mV

2

)

2

)

æ

ö

I_PL,ERR,IMON

=

ER

(

+

=

0.4%

(

+

= 10%

GAIN

ç

÷

è

ø

(43)

The tolerance of the power limit engine is specified at three V_IMONpoints in the datasheet: 135 mV (±20.3 mV),

67.5 mV (±10.1 mV), and 27 mV (±8.1 mV). To get the % error at the real operating point, the absolute error

should be extrapolated and divided by V_IMONas shown in the equation below. This is graphically depicted in

Figure 23.

10.1 mV-8.1 mV

8.1 mV + (54.7 mV - 27 mV)´ _{67.5 mV-27 mV}

ERR_IMON,PL

=

= 17.3%

54.7 mV

(44)

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20.3

10.1

9.5

8.1

27

67.5

54.7

135

V_IMON,PL(mV)

Figure 21. Extrapolating Power Limit Error

Once ER_IMON,PLand I_PL,ERR,IMONare known the total power limit error (PL_ERR,TOT) can be computed using the

equation below. The component error (3.5%) comes from R_SNS(3%), R_PLIM(1%), R_SET(1%), and R_IMON(1%).

2

)

PL_ERR,TOT

=

ERR

+ I

+ ERR

COMP

(

_IMON,PL) (_PL,ERR,IMON)

(

2

)

17.3% + 10% + 3.5% = 20.3%

(

) ( ) (

(45)

After computing the fast trip voltage threshold to be 24.9 mV (100 µA × 249 Ω), the fast trip threshold error

resulting from the IC (FST_{ERR, IC}) can be computed using a similar extrapolation method as used for power limit.

The component error of R_SNSand R_FSTshould be added to obtain the total fast trip error (FST_ERR,TOT). Both

equations are shown below.

5 mV-2 mV

2 mV + 24.9 mV - 20 mV ´

)

(

100 mV-20 mV

FST_ERR,IC

=

= 8.8%

24.9 mV

(46)

sp

2

FST_ERR,TOT

=

8.8% + 1% + 3% = 9.4%

(

) ( ) ( )

(47)

The IC error of the UV / OV threshold is always 3.7% (0.05 V / 1.35 V). Assuming that all resistors have a 1%

error the component error is 1.41% (2 resistors). When using the RSS method the total error is 4%. For the timer

error, the IC contributes 22% and 10% comes from the component. When using the RSS method the total error

becomes 24.2%.

The table below summarizes the final tolerances of the design:

Table 3. Design Tolerances

SETTINGS

Current Limit

Fast Trip

ACCURACY

4.1%

9.4%

Power Limit

TFLT, TINR

UV/OV

20.3%

24.2%

4.0%

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10.2.4 Application Curves

Figure 22. Start up (C_OUT=5500µF)

Figure 23. Undervoltage and Overvoltage

Figure 24. Start Up with Output Shorted to GND

Figure 25. Load Step 100A to 120A

Figure 26. Hot Short on Output with Full Load

(zoomed out)

Figure 27. Hot Short on Output with Full Load

(zoomed in)

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Figure 28. Hot Short on Output with No Load (zoomed out)

Figure 29. Hot Short on Output with No Load (zoomed in)

10.2.5 240 VA Application Using CSD16415Q5B

The diagram below shows the application schematic for this design example. See the TPS24770 Design

Calculator to help with these calculations.

0.5 P

R_SNS

CSD16415

V_OUT

V_IN

C_OUT

C_FST

2.4nF

D1

SMDJ14

D2

C1

R_SET

R_HG

R_FSTP

200ꢀ

1 ꢀF

0.1ꢀF

MBRS330T3G

100ꢀ

10ꢀ

VDD SET

ENHS

FSTP

SENM HGATE

OUTH

PGHS

FLTb

R_DIV1

49.9Nꢀ

R_POW

121Nꢀ

TPS2477x

R_DIV2

1k

2.21Nꢀ

IMONBUF

TFLT

OV

TINR

PLIM

GND

R_DIV3

IMON

C_ENHS

33nF

C_DVDT

R_PLIM

4.99Nꢀ

C_INR

1nF

C_FLT

R_IMON

3.48Nꢀ

100nF

5.62Nꢀ

2.2µF

Figure 30. Application Schematic for 240VA Design with CSD16415Q5B

10.2.5.1 Design Requirements

The following table summarizes the requirements for this design. Note that the output power cannot exceed

240W for more than 250 ms.

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Table 4. Design Requirements for a 240 VA Design using CSD16415Q5B

DESIGN PARAMETER

EXAMPLE VALUE

10.8 V – 13.2V

240 W

Input voltage range

Output Power Limit (VA limiting)

Maximum Output Capacitance of the Hot Swap

Maximum Ambient Temperature

MOSFET R_θCA(function of layout)

Transient load requirement?

Pass “Hot-Short” on Output?

Pass a “Start into short”?

2500 uF

55°C

35°C/W

POUT is allowed to surpass 240W for <250 ms

Yes

Is the load off until PG asserted?

IC used

Yes

TPS24772

No

Analog Current Monitor Used

MOSFET

CSD16415Q5B

Yes

Can a Hot Board be plugged in or Power Cycled?

10.2.5.2 Theory of Operations

Before going into the details of the design it’s important to understand the impact that R_POWhas on the circuit.

Refer to Figure 31 for this discussion.

R_SNS

i_SET

SENM

SET

15

17

i_POW

IMON

12

i_IMON

Figure 31. Impact of R_POWResistor

Note that the TPS2477x detects overcurrent conditions when V_IMONreaches 675mV, which occurs when there is

sufficient current (i_IMON) flowing through R_IMON. Also note that i_IMONis a sum of i_SETand i_POW. If i_IMON,CL, i_SET,CL

,

and i_POW,CLcorrespond to these same current when V_IMONreaches 675mV and TPS2477x detects current limit,

the following equations can be written.

675 mV

i_IMON,CL

=

;i_IMON,CL= i_SET,CL+ i_POW,CL

R_IMON

(48)

V_IN- 675 mV

-

675 mV

R_IMON

i_SET,CL

=

R_POW

(49)

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Also note that the amplifier ensures that SET and SENM are equal and thus I_LIMcan be derived as follows:

675 mV

i_IMON,CL

=

;i_IMON,CL= i_SET,CL+ i_POW,CL

R_IMON

(50)

(51)

æ

ç

è

ö

÷

ø

R_SETR_SET

=

R_SNSR_SNS

V ´R_SET

675mV 675mV

+

IN

I_LIM= i_SET,CL

´

-

R_IMON

R_POW

R_SNS´R_POW

Examining the equation above, it can be seen that I_LIMreduces as V_INbecomes larger. Note that the ultimate

goal is to limit output power. However, when the FET is on, V_INis very close to V_OUTand they can be assumed to

be equal.

The figure below compares the ideal I_LIMvs V_OUT(I_LIM=240 W / V_OUT) profile to that of the R_POWimplementation

shown here. The error is large when the output voltage is far from 12V, but the performance is quite good near

12V. The next figure shows the effective output power limit for output voltages from 10 V to 14 V. It can be seen

that the results are quite good and much better than using a simple 20A current limit, without the R_POWresistor to

compensate for V_INvariation.

50

40

30

20

10

0

300

280

260

240

220

200

180

Ideal

Linear VA Limiting

VA Limiting with TPS2477x

Regular 20 A ILIM

0

5

10

15

20

25

10

11

12

Output Voltage (V)

13

14

Output Voltage (V)

C021

C022

Figure 32. Current Limit (with R_POW) vs Output Voltage

Figure 33. Output Power Limiting using R_POWvs Standard

ILIM

10.2.5.3 Design Procedure

10.2.5.3.1 Select V_SNS,CL, R_SNS, and R_SETSetting

For this example, V_SNS,CLof 10 mV was selected to optimize efficiency. Then R_SNScan be computed to 0.5mΩ.

There is some flexibility in picking the R_SETvalue. In this case targeting 100 µA for I_SET,CL, R_SETis computed to

be 100 Ω as shown in the following equation.

V_SNS,CL

10 mV

100 µA

R_SET

=

= 100 W

i_SET,CL

(52)

10.2.5.3.1.1 Select R_POWand R_IMON

R_POWcontrols the slope of the I_LIMvs V_INcurve and thus the ideal slope should be found first before selecting

R_POW. This can be done by taking the derivative of the ideal current limit (I_{LIM, IDEAL}) vs V_INcurve and evaluating it

at 12V. This is found to be –1.667 A/V as shown in the equations below. Next the derivative of equation 51 is

taken to isolate the terms that influence the slope of I_LIMvs V_INcurve. Since R_SETand R_SNShave already been

selected, R_POWremains the only parameter that can be varied. Thus, R_POWis computed using the last equation

below.

dI_LIM,IDEAL

-240 W

2

A

= -1.667

V

= 12 V =

)

(

IN

V

dV

IN

12 V

(

)

(53)

dI_LIM

-R_SET

=

dV

R

_SNS´R_POW

IN

(54)

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-R_SET

-100 W

R_SNS

0.5m W

-1.667^A

R_POW,CLC

=

= 120 kW

dI_LIM,IDEAL

V

(

= 12 V

)

IN

dV

IN

(55)

The closest available standard resistor is chosen for R_POW, which is 121kΩ.

Next R_IMONshould be chosen to ensure that the output power limit is 240 W at 12 V, which is the typical

operating point. R_IMONis computed to be 3.49kΩ and the closest available standard resistor of 3.48 kΩ is chosen.

12 V - 0.675 V

i_IMON,CL= i_SET,CL+ i_POW,CL= 100 µA +

= 193.6 µA

121 kW

(56)

(57)

sp

V

675 mV

IMON,CL

R_IMON

=

= 3.49 kW

i_IMON,CL

193.6 µA

10.2.5.3.1.2 Selecting the Hot Swap FET(s)

It is critical to select the correct MOSFET for a Hot Swap design. The device must meet the following

requirements:

•

The V_DSrating should be sufficient to handle the maximum system voltage along with any ringing caused by

transients. For most 12V systems a 25 V or 30V FET is a good choice.

•

The SOA of the FET should be sufficient to handle all usage cases: start-up, hot-short, start into short.

R_DSONshould be sufficiently low to maintain the junction and case temperature below the maximum rating of

the FET. In fact, it is recommended to keep the steady state FET temperature below 125°C to allow margin to

handle transients.

•

Maximum continuous current rating should be above the maximum load current and the pulsed drain current

must be greater than the current threshold of the circuit breaker. Most MOSFETs that pass the first three

requirements will also pass these two.

A V_GSrating of +16 V is required, because the TPS2477x can pull up the gate as high as 15.5 V above

source.

For this design the CSD16415Q5B was selected for its low R_DSONand superior SOA. After selecting the

MOSFET, the maximum steady state case temperature can be computed as follows:

R_DSON

T

( )

J

T_C,MAX= T_A,MAX+ R_qCA´I_L²_OAD,MAX

´

n²

(58)

In the equation above n is the number of FETs used in parallel. Note that the R_DSONis a strong function of

junction temperature, which for most MOSFETS will be very close to the case temperature. A few iterations of

the above equations may be necessary to converge on the final R_DSONand T_C,MAXvalue. According to the

CSD16415Q5B datasheet, its R_DSONis about 1.2 x greater at 75°C compared to room temperature. . The

equation below uses this R_DSONvalue to compute the T_C,MAX. Note that the computed T_C,MAXis close to the

junction temperature assumed for R_DSON. Thus no further iterations are necessary.

C

T_C,MAX= 55°C + 35°

´ 20A ²´ 1.2´1 mW = 72°C

(

) (

)

W

(59)

10.2.5.3.1.3 Keeping MOSFET within SOA During Normal Start-up

Next, the designer must ensure that the MOSFET will stay within SOA during start-up and a start-up into short.

Note that the TPS24772 (fast latch off) is used for this design so the MOSFET stress during a hot short is

minimal.

Since R_POWbiases the I_MONpin, it interferes with FET power limiting and it’s recommended to disable FET power

limiting it by selecting a 4.99kΩ resistor for R_POW

.

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The inrush current can be limited by adding a capacitor from HGATE to GND (C_DVDT) as shown in the application

diagram. This capacitor limits the slew rate of HGATE at start-up, which will in turn limit the slew rate of V_OUT

Assuming that the load is off until PGHS is asserted, all of the inrush current would be going into C_OUTand be

inversely proportional to the slew rate of V_OUT. Refer to the application plots for a start-up waveform. In addition,

a 1kΩ resistor is placed in series with C_DVDTto ensure that C_DVDTdoesn’t slow down the short circuit response of

the Hot Swap.

.

For this example, a 100 nF capacitor was used for C_DVDT. This results in an inrush current (I_INR) of 1.375A, total

inrush time (t_INR) of 24.5, and peak FET power dissipation (P_FET,PEAK) of 18.7W as shown in equations below.

This assumes maximum input voltage of 13.2 V

I

_HGATE´ C_OUT

55 µA ´ 2500 µF

I

=

= 1.375 A

INR

C_DVDT

100 nF

(60)

sp

V

_IN,MAX´ C_DVDT

13.2 V ´100 nF

t_INR

=

= 24.5 ms

I_HGATE

55 µA

(61)

(62)

P

= V_IN,MAX´I

= 13.2 V ´1.375 A = 18.2 W

INR,MAX

INR

Next, it’s importation to check that the MOSFET can handle this stress level. Note that the power dissipation of

the MOSFET will start at P_INR,MAXand will reduce to zero as the V_DSdrop across the MOSFET reduces. The

effective stress on the MOSFET can be approximated to be P_INR,MAXfor t_INR/2, which is the equivalent amount of

energy. For this example, the FET stress is 18.7W for 12.3 ms. Looking at the SOA curve of the CSD16415Q5B,

at V_DSof 13.2 V it can handle ~15A for 10ms or ~4A for 100ms. Using the same method as the previous design

example, it can be computed that the MOSFET can handle 13.4A for 12.3 ms when V_DS=13.2 V.

The SOA of a MOSFET is specified at a case temperature of 25°C, while the real case temperature can be

hotter during a start into a short. It is important to understand the hottest temperature that a MOSFET can be

during a start-up (T_{C, MAX, START}). If a board has been off for a while and then it’s turned on, T_{A, MAX}is a good

estimate for T_{C,MAX, START}. However, if a board is on and then gets power cycled or gets unplugged and plugged

back in, T_C,MAXshould be used for T_C,MAX,START. This will depend on system requirements. For this design

example, it is assumed that a hot board can be power cycled or hot plugged and thus T_C,MAXis used to estimate

T_C,MAX,START

.

T_J,ABSMAX- T_C,MAX,START

I_SOA12.3 ms,T

(

= I

12.3 ms, 25°C ´

( )

)

C,MAX,START

SOA

T_J,ABSMAX- 25°C

150°C - 72°C

150°C - 25°C

= 13.4 A ´

= 8.4 A

(63)

Based on this calculation the MOSFET can handle 8.4 A, 13.2 V for 12.3 ms at 72°C elevated case temperature,

but is only required to handle 1.375 A. Thus there is good margin and this will be a robust design. In general a

1.3x margin is recommended to cover for variations.

Next, the start into short case is considered. Since the MOSFET power limit is disabled, the current through the

MOSFET will reach 20A before the part starts to regulate and runs the inrush timer. In order to minimize FET

stress, a short inrush timer is chosen (1nF of C_INR). Unfortunately, when a very short timer is used and there is a

dv/dt capacitor, the FET stress cannot be simply estimated by T_INR. In the following figure, it is clear that the FET

has both voltage and significant current across it for longer than just T_INR. This occurs because TINR is only

activated when IIN reaches the current limit threshold, which doesn’t happen immediately due to the slow dv/dt

on the gate and the limited transconductance of the FET.

The current is not a square pulse, which makes it hard to compare the FET stress to the SOA curves. Thus the

stress shown in the following figure needs to be converted to an equivalent square pulse. For this example, the

equivalent pulse was assumed to be 20 A for 1ms. The MOSFET can handle 100A, 13.2 V for 1ms, which can

be derated to 62 A when accounting for elevated case temperature. This provides plenty of margin and ensures

a robust design.

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T_J,ABSMAX- T_C,MAX,START

I_SOA1 ms,T

(

= I

1 ms, 72°C ´

( )

)

C,MAX,START

SOA

T_J,ABSMAX- 25°C

150°C - 72°C

150

°

C

-

25

°

C

= 100 A ´

= 62 A

(64)

Figure 34. Start-up Into Short

10.2.5.3.1.4 Choose Fault Timer

To pass the load transient, a target fault time (T_FLT,TGT) of 250ms is used. C_FLT,CLCis computed as follows:

sp

C_FLT,CLC= 7.59 mF / s´ T_FLT,TGT= 7.59 mF / s´ 250 ms = 1898 nF

(65)

(66)

The next largest available C_FLTis chosen as 2.2µF, which results in a TFLT of 290ms as shown below.

C_FLT

2.2 mF

T_FLT

=

7.59 mF / s 7.59 mF / s

= 290 ms

10.2.5.3.1.5 Choose Under Voltage and Over Voltage Settings

For this design example 10V and 14V were chosen as the limits to allow some margin for the 10.8V to 13.2V

input bus. These are identical to the previous design example. See Choose Under Voltage and Over Voltage

Settings section for programming these thresholds.

10.2.5.3.1.6 Selecting C_INand C_OUT

It is recommended to add ceramic bypass capacitors to help stabilize the voltages on the input and output. Since

C_INwill be charged directly on hot-plug, it’s value should be kept small. 0.1µF is a good target. Since C_OUT

doesn’t get charged during hot-plug, a larger value such as 1 µF could be used.

10.2.5.3.1.7 Selecting D1 and D2

During hot plug and hot short events there could be significant transients on the input and output of the Hot

Swap that could cause operation outside of the IC specifications. To ensure reliable operation a TVS on the input

and a Schottkey diode on the output are recommended. In this example a SMDJ14A and MBRS330T3G are

used.

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10.2.5.3.1.8 Adding C_ENHS

When the ENHS pulled below its threshold and raised back up the IC will reset. Note that during a hot short the

input voltage can easily droop below the UV threshold and cycle the ENHS pin. For the TPS24770 and

TPS24771 ICs this will not change the behavior. However, when using the TPS24772 the cycling of the ENHS

will result in the IC attempting to restart, which is undesired (this is the main reason why someone would use the

TPS24772). To avoid this behavior a capacitor should be added to the ENHS to provide filtering. 33 nF was

chosen for this example.

10.2.5.3.1.9 Stability Considerations

Since there is a 100nF C_DVDTattached to HGATE, this significantly increases the effective capacitance of

HGATE and guarantees stability for this application.

10.2.5.4 Application Curves

Figure 35. No Load then Hot Short (Zoomed Out)

Figure 36. Full Load then Hot Short (Zoomed In)

Figure 37. Overcurrent

Figure 38. Start Up into Short

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Figure 39. Start up (C_OUT= 2500 µF)

Figure 40. Start up showing PGHS and FLTb (C_OUT= 2500

µF)

Figure 41. Under Voltage and Over Voltage with V_INRising

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10.2.6 240 VA Application Using CSD17573Q5B

This design example has identical requirements to the previous one, but the CSD17573Q5B is used instead of

the CSD16415Q5B. The CSD17573Q5B is cheaper and offers better R_DSON, but its SOA is not as good. Thus it

was necessary to add Q₂and R_SET2to reduce the stress during a start up into a short circuit. Given that Q₂is a

small signal PFET that is cheap, the overall BOM cost of this solution should be cheaper than the previous one.

See the TPS24770 Design Calculator to help with these calculations.

100 N

0.5 P

CSD17573

Q₁

R_SNS

V_OUT

V_IN

Q₂

R_SET

100ꢀ

C_OUT

D1

SMDJ14

D2

C1

C_FST

2.4nF

0.1ꢀF

1 ꢀF

MBRS330T3G

R_HG

R_SET2

R_FSTP

10ꢀ

200ꢀ

25ꢀ

SET

FSTP

SENM HGATE

OUTH

PGHS

FLTb

R_DIV1

VDD

49.9Nꢀ

R_POW

121Nꢀ

ENHS

TPS2477x

R_DIV2

1k

2.21Nꢀ

IMONBUF

TFLT

OV

C_ENHS

33 nF

TINR

PLIM

GND

R_DIV3

IMON

C_DVDT

C_INR

1nF

R_PLIM

C_FLT

5.62Nꢀ

100nF

R_IMON

3.48Nꢀ

4.99Nꢀ

2.2µF

Figure 42. 240 VA Design Using CSD17573Q5B

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10.2.6.1 Design Requirements

The following table summarizes the requirements for this design.

Table 5. Design Requirements for the 240 VA Design Using CSD17573Q5B

DESIGN PARAMETER

Input voltage range

EXAMPLE VALUE

10.8 V – 13.2 V

240 W

Output Power Limit (VA limiting)

Maximum Output Capacitance of the Hot Swap

Maximum Ambient Temperature

MOSFET R_θCA(function of layout)

Transient load requirement?

Pass “Hot-Short” on Output?

Pass a “Start into short”?

2500 µF

55°C

35°C/W

POUT is allowed to surpass 240W for <250 ms

Yes

Is the load off until PG is asserted?

IC used

Yes

TPS24772

No

Analog Current Monitor Used

MOSFET

CSD17573Q5B

Yes

Can a Hot Board be plugged in or Power Cycled?

10.2.6.1.1 Choosing C₁, C_OUT, C_FLT, C_ENHS, D₁, D₂, R_SET, R_POW, R_IMON, R_SNS, C_DVDT, R_PLIM, and UV/OV Thresholds

These components and settings are chosen in the same fashion as the previous design example. See 240 VA

Application Using CSD16415Q5B.

10.2.6.1.2 Selecting the Hot Swap FET(s)

It is critical to select the correct MOSFET for a Hot Swap design. The device must meet the following

requirements:

•

The V_DSrating should be sufficient to handle the maximum system voltage along with any ringing caused by

transients. For most 12V systems a 25 V or 30V FET is a good choice.

•

The SOA of the FET should be sufficient to handle all usage cases: start-up, hot-short, start into short.

R_DSONshould be sufficiently low to maintain the junction and case temperature below the maximum rating of

the FET. In fact, it is recommended to keep the steady state FET temperature below 125°C to allow margin to

handle transients.

•

Maximum continuous current rating should be above the maximum load current and the pulsed drain current

must be greater than the current threshold of the circuit breaker. Most MOSFETs that pass the first three

requirements will also pass these two.

A V_GSrating of +16 V is required, because the TPS2477x can pull up the gate as high as 15.5 V above

source.

For this design the CSD17573Q5B was selected for its low R_DSONand great cost point. After selecting the

MOSFET, the maximum steady state case temperature can be computed as follows:

R_DSON

T

( )

J

T_C,MAX= T_A,MAX+ R_qCA´I_L²_OAD,MAX

´

n²

(67)

In the equation above n is the number of FETs used in parallel. Note that the R_DSONis a strong function of

junction temperature, which for most MOSFETS will be very close to the case temperature. A few iterations of

the above equations may be necessary to converge on the final R_DSONand T_C,MAXvalue. According to the

CSD17573Q5B datasheet, its R_DSONis about 1.2 x greater at 65°C compared to room temperature. The equation

below uses this R_DSONvalue to compute the T_C,MAX. Note that the computed T_C,MAXis close to the junction

temperature assumed for R_DSON. Thus no further iterations are necessary.

C

T_C,MAX= 55°C + 35°

´ 20 A ²´ 1.2´0.84 mW = 69°C

(

) (

)

W

(68)

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10.2.6.1.3 Keeping the MOSFET within SOA

As in the previous example, it is important to ensure that the MOSFET stays within its SOA during both regular

start-up and start-up into short.

First consider the regular start-up. The same C_DVDTis used as the last example so the FET is required to handle

18.2W (or 1.38A and 13.2V) for 12.3 ms. Based on the SOA curve of the CSD17573Q55B, at V_DSof 13.2 V it

can handle 4.5 A for 10 ms or 2 A for 100 ms. Using the same method as the previous design example, it can be

inferred that the MOSFET can handle 4.2 A for 12.3 ms when V_DS=13.2 V.

The SOA of a MOSFET is specified at a case temperature of 25°C, while the case temperature can be hotter

during a start into a short. It is important to understand the hottest temperature that a MOSFET can be during a

start-up (T_{C, MAX, START}). If a board has been off for a while and then it’s turned on T_{A, MAX}is a good estimate for

T_{C,MAX, START}. However, if a board is on and then gets power cycled T_C,MAXshould be used for T_C,MAX,START. This

will depend on system requirements. For this design example, it’s assumed that a hot board can be power cycled

or hot plugged and T_C,MAXis used to estimate T_C,MAX,START

.

T_J,ABSMAX- T_C,MAX,START

I_SOA12.3 ms,T

(

= I

12.3 ms ,25°C ´

( )

)

C,MAX,START

SOA

T_J,ABSMAX- 25°C

150°C - 69°C

150°C - 25°C

= 4.2 A ´

= 2.7 A

(69)

Based on this calculation the MOSFET can handle 2.7 A, 13.2 V for 12.3 ms at 69°C elevated case temperature,

but is only required to handle 1.38 A. Thus there is sufficient margin to make this a robust design. Again a 1.3x

margin is recommended to cover for variations.

Next, consider the start into short condition. Similar to the previous design the MOSFET would need to handle

20A and 13.2 V for ~1ms. Checking the SOA curve of the CSD17573Q5B, it can only handle 10A and 13.2 V for

1ms, so it’s SOA is clearly not sufficient.

This is where Q₂and R_SET2come in. They serve to reduce the current limit during starting up (I_LIM,START) while

the V_DSof the Hot Swap MOSFET is above V_Tof Q₂(1V to 2V). The ratio of I_LIMto I_LIM,START, denoted as I_RATIO

,

is a function of R_SETand R_SET2as shown below. For this example a ratio of 0.2 (I_LIM,START=4A) was targeted to

reduce MOSFET stress, keep the current limit above I_INR, and ensure sufficient signal on V_SNSto keep the error

reasonable. Once _IRATIOis chosen, R_SET2is computed to be 25 Ω as shown below.

I_LIM,START

R_SET/ /R_SET2

=

I_RATIO

=

I_LIM

R_SET

(70)

I_RATIO

0.2

R_SET2= R_SET

´

= 100 W ´

= 25 W

1-I_RATIO

1- 0.2

(71)

The start-up into short (with R_SET2and Q₂) is shown in Figure 43 below. The equivalent power pulse is now 4A

for ~0.5ms. The MOSFET can handle 10A, 13.2 V for 1ms, which can be derated to 6.5 A when accounting for

elevated case temperature. Since the MOSFET is only required to handle 4A for 0.5ms there is plenty of margin

in the design.

T_J,ABSMAX- T_C,MAX,START

I_SOA1 ms,T

(

= I

1 ms ,25°C ´

( )

)

C,MAX,START

SOA

T_J,ABSMAX- 25°C

150°C - 69°C

150°C - 25°C

= 10 A ´

= 6.5 A

(72)

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Figure 43. Start-up Into Short (with R_SETand Q₂)

10.2.6.2 Q2 Selection

There is a lot of flexibility when selecting Q₂. Any PMOS with a ±20V V_GSrating and 20V of V_DSrating is

sufficient. For this example IRLML5203PbF was used. Note that the 100k series resistor along with the C_ISSof

Q2 (~500pF) for a filter with a 50 µs time constant. This protects Q₂in case there is high frequency ringing on V_IN

that causes V_IN– V_OUTto exceed 20V. This will usually happened during hot-plug or hot-short.

10.2.6.3 Application Curves

Figure 44. Full Load then Hot Short (Zoomed Out)

Figure 45. Full Load then Hot Short (Zoomed In)

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Figure 46. Over Current

Figure 47. Start Up Into Short

Figure 48. Start up (C_OUT= 2500 µF)

Figure 49. Start up showing PGHS and FLTb (C_OUT= 2500

µF)

Figure 50.

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11 Power Supply Recommendations

In general, operation is best when the input supply isn’t noisy and doesn’t have significant transients. For noisier

environments filtering on input, output, and fast trip should be adjusted to avoid nuisance trips.

12 Layout

12.1 Layout Guidelines

When doing the layout of the TPS2477x the following are considered best practice.

•

Ensure proper Kelvin Sense of R_SNS.

Keep the filtering capacitor C_FSTPas close to the IC as possible.

Place a Shottky diode and a ceramic bypass capacitor close to the source of the Hot Swap MOSFET

Do not connect VDD to the Kelvin Sense trace for SET and FSTP

Note that special care must be taken when placing the bypass capacitor for the VDD pin. During Hot Shorts,

there is a very large dv/dt on input voltage during the MOSFET turn off. If the bypass capacitor is placed right

next to the pin and the trace from R_SNSto the pin is long, an LC filter is formed. As a result a large differential

voltage can develop between VDD and SENM if there is a large transient on Vin. This could result in a

violation of the abs max rating from VDD to SENM. To avoid this, place the bypass capacitor close to RSNS

instead of the VDD pin.

SENM

Vdd

Trace

inductance

Figure 51. Layout Don't

•

When using parallel resistors the layout becomes even more critical. Due to PCB parasitics, the current

through each R_SNSmay be different, which results in different sense voltages across the two resistors. It’s

important to average these in order to get a proper current measurement. This can be accomplished by

forming a resistor divider with the traces. As long as Dis1 = Dis2, the final V_SNSwill be an average of the drop

across the two resistors.

40

TPS24772

TPS24771

TPS24770

www.ti.com.cn

ZHCSDK8 –MARCH 2015

Layout Guidelines (continued)

Power Flow

R_SNS1

V_IN

R_SNS2

+ V_SNS

-

Figure 52. Sense Layout with 2 R_SNS

41

TPS24772

TPS24771

TPS24770

ZHCSDK8 –MARCH 2015

www.ti.com.cn

12.2 Layout Example

Power Flow

G

S

V_IN

HS FET

R_SNS

D

V_OUT

OUTH

19

24

23

22

21

20

NC

HGATE

C_FSTP

ENHS

NC

SENM

FSTP

TPS2477X

FLTb

SET

VDD

PGHS

NC

IMONBUF

11

12

7

8

9

10

layer1

layer2

via

Power_GND

42

TPS24772

TPS24771

TPS24770

www.ti.com.cn

ZHCSDK8 –MARCH 2015

13 器件和文档支持

13.1 相关链接

以下表格列出了快速访问链接。范围包括技术文档、支持与社区资源、工具和软件，并且可以快速访问样片或购买

链接。

表 6. 相关链接

器件

产品文件夹

请单击此处

样片与购买

请单击此处

技术文档

请单击此处

工具与软件

请单击此处

支持与社区

请单击此处

TPS24770

TPS24771

TPS24772

13.2 商标

All trademarks are the property of their respective owners.

13.3 静电放电警告

这些装置包含有限的内置 ESD 保护。存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损

伤。

13.4 术语表

SLYZ022 — TI 术语表。

这份术语表列出并解释术语、首字母缩略词和定义。

14 机械、封装和可订购信息

以下页中包括机械、封装和可订购信息。这些信息是针对指定器件可提供的最新数据。这些数据会在无通知且不

对本文档进行修订的情况下发生改变。欲获得该数据表的浏览器版本，请查阅左侧的导航栏。

43

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TI 保证其所销售的组件的性能符合产品销售时 TI 半导体产品销售条件与条款的适用规范。仅在 TI 保证的范围内，且 TI 认为有必要时才会使

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IMPORTANT NOTICE

邮寄地址：上海市浦东新区世纪大道1568 号，中建大厦32 楼邮政编码： 200122

GENERIC PACKAGE VIEW

RGE 24

VQFN - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

Images above are just a representation of the package family, actual package may vary.

Refer to the product data sheet for package details.

4204104/H

PACKAGE OUTLINE

RGE0024B

VQFN - 1 mm max height

S

C

A

L

E

3

.

0

PLASTIC QUAD FLATPACK - NO LEAD

4.1

3.9

B

A

0.5

0.3

PIN 1 INDEX AREA

4.1

3.9

0.3

0.2

DETAIL

OPTIONAL TERMINAL

TYPICAL

C

1 MAX

SEATING PLANE

0.08 C

0.05

0.00

2X 2.5

(0.2) TYP

2.45 0.1

7

12

EXPOSED

SEE TERMINAL

DETAIL

THERMAL PAD

13

6

2X

SYMM

25

2.5

18

1

0.3

24X

20X 0.5

0.2

19

24

0.1

C A B

SYMM

24X

PIN 1 ID

(OPTIONAL)

0.05

0.5

0.3

4219013/A 05/2017

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

www.ti.com

EXAMPLE BOARD LAYOUT

RGE0024B

VQFN - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

(

2.45)

SYMM

24

19

24X (0.6)

1

18

24X (0.25)

(R0.05)

TYP

25

SYMM

(3.8)

20X (0.5)

13

6

(

0.2) TYP

VIA

7

12

(0.975) TYP

(3.8)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:15X

0.07 MIN

ALL AROUND

0.07 MAX

ALL AROUND

SOLDER MASK

OPENING

METAL

EXPOSED

METAL

EXPOSED

METAL

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

NON SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

4219013/A 05/2017

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown

on this view. It is recommended that vias under paste be filled, plugged or tented.

www.ti.com

EXAMPLE STENCIL DESIGN

RGE0024B

VQFN - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

4X ( 1.08)

(0.64) TYP

19

24

24X (0.6)

1

25

18

24X (0.25)

(R0.05) TYP

SYMM

(0.64)

TYP

(3.8)

20X (0.5)

13

6

METAL

TYP

7

12

SYMM

(3.8)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD 25

78% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE

SCALE:20X

4219013/A 05/2017

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

www.ti.com

重要声明和免责声明

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型号：	TPS24770RGET
厂家：	TEXAS INSTRUMENTS
描述：	具有电流监控功能的 2.5V 至 18V 高性能热插拔控制器 \| RGE \| 24 \| -40 to 125 控制器监控
文件：	总51页 (文件大小：2932K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TPS24770RGET [TI]

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