TPS2491DGSRG4 [TI]
POSITIVE HIGH-VOLTAGE POWER-LIMITING HOTSWAP CONTROLLER; 正高电压功率限制热插拔控制器
| 型号： | TPS2491DGSRG4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | POSITIVE HIGH-VOLTAGE POWER-LIMITING HOTSWAP CONTROLLER |
| 文件： | 总22页 (文件大小：567K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPS2490
Actual Size
3,0 mm X 4,88 mm
TPS2491
www.ti.com
SLVS503–NOVEMBER 2003
POSITIVE HIGH-VOLTAGE POWER-LIMITING HOTSWAP CONTROLLER
FEATURES APPLICATIONS
•
•
•
•
•
Server Backplanes
Storage Area Networks (SAN)
Medical Systems
Plug-in Modules
Base Stations
•
Programmable Power Limiting and Current
Limiting for Complete SOA Protection
•
•
Wide Operating Range: +9 V to +80 V
Latched Operation (TPS2490) and Automatic
Retry (TPS2491)
•
•
•
•
•
High-side Drive for Low-RDS(on) External
N-channel MOSFET
DGS Package
(Top View)
Programmable Fault Timer to Protect the
MOSFET and Eliminate Nuisance Shutdowns
VCC
EN
VREF
PROG
TIMER
GND
1
2
3
4
5
10
9
SENSE
GATE
OUT
Power Good Open-Drain Output for Down-
stream DC/DC Coordination
8
7
Enable can be used as a Programmable
Undervoltage Lockout or Logic Control
PG
6
Small, Space-saving 10-pin MSOP Package
DESCRIPTION
The TPS2490 and TPS2491 are easy-to-use, positive high voltage, 10-pin Hot Swap Power Manager™ devices
that safely drive an external N-channel MOSFET switch. The power limit and current limit (both are adjustable
and independent of each other) ensure that the external MOSFET operates inside a selected safe operating area
(SOA) under the harshest operating conditions. Applications include inrush current limiting, electronic circuit
breaker protection, controlled load turn-on, interfacing to down-stream dc-to-dc converters, and power feed
protection. These devices are available in a small, space-saving 10-pin MSOP package and significantly reduce
the number of external devices, saving precious board space. The TPS2490/91 is supported by application
notes, an evaluation module, and a design tool.
Typical Application and Corresponding SOA
M1
IRF540NS
R
S
V
at 4 A
O
V
= 48 Vdc
I
C1
0.01 Ω
0.1 µF
D1
SMAJ60A
R6
470 kΩ
R5
10 Ω
R1
324 kΩ
10
9
8
7
VCC
SENSE
GATE
OUT
1
2
Power Good
EN
6
PG
TPS2490/91
R2
13.3 kΩ
VREF
PROG
R3
41.2 kΩ
GND
TIMER
4
Programmed
SOA, 16mS
3
5
C
O
I
V
P
= 5 A,
LIM
220 µF
C
T
R4
8.25 kΩ
/V
= 34.2 V/31.7 V,
= 34 W,
ON OFF
0.1 µF
LIM
Timeout = 16 mS
Hot Swap Power Manager is a trademark of Texas Instruments.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2002–2003, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
TPS2490
TPS2491
www.ti.com
SLVS503–NOVEMBER 2003
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION
TA
FUNCTION
Latched
Retry
PACKAGE
VSSOP-10
(MSOP)
PART NUMBER(1)
TPS2490DGS
SYMBOL
BIY
-40°C to 85°C
TPS2491DGS
BIX
(1) Add an R suffix to the device type for tape and reel packaging.
ABSOLUTE MAXIMUM RATINGS(1)
over operating free-air temperature range (unless otherwise noted)
UNIT
V
Input voltage range, VCC, SENSE, EN, OUT
Output voltage range, GATE, PG
Input voltage range, PROG
-0.3 to 100
-0.3 to 100
-0.3 to 6
-0.3 to 6
10
V
V
Output voltage range, TIMER, VREF
Sink current, PG
V
mA
mA
mA
kV
V
Source current, VREF
0 to 2
2
Sink Current, PROG
ESD - human body model
2
ESD - charged device model
Maximum junction temperature, TJ
Storage temperature, TST
500
150
°C
°C
°C
–65 to 150
260
Lead temperature 1.6 mm (1/16 inch) from case for 10 seconds
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability
RECOMMENDED OPERATING CONDITIONS
MIN
9
NOM
MAX
80
4
UNIT
V
VVCC
VPROG
IVREF
TJ
Input voltage range
Input voltage range
0
V
Operating current range (sourcing), VREF
Operating junction temperature
Operating free-air temperature
0
1
mA
°C
-40
-40
125
85
TA
°C
DISSIPATION RATING TABLE
PACKAGE
TA <25°C
POWER RATING
mW
DERATING FACTOR
ABOVE TA= 25°C
(mW/°C)
TA = 70°C
POWER RATING
(mW)
TA = 85°C
POWER RATING
(mW)
VSSOP-10 (MSOP)
376
3.76
207
150
2
TPS2490
TPS2491
www.ti.com
SLVS503–NOVEMBER 2003
ELECTRICAL CHARACTERISTICS
unless otherwise noted, minimum and maximum limits apply across the recommended operating junction temperature and
voltage range, VTIMER = 0 V, and all outputs unloaded; typical specifications are at TJ = 25°C, VVCC = 48 V, VTIMER = 0 V, and
all outputs unloaded; positive currents are into pins.
PARAMETER
SUPPLY CURRENT (VCC)
TEST CONDITIONS
MIN
TYP
MAX UNIT
Enabled
Disabled
VEN = Hi, VSENSE = VOUT = VVCC
450
90
1000
250
µA
µA
VEN = Lo, VSENSE = VVCC = VOUT = 0
CURRENT SENSE INPUT (SENSE)
ISENSE
REFERENCE VOLTAGE OUTPUT (VREF)
VREF Reference voltage
POWER LIMITING INPUT (PROG)
Input bias current
VSENSE = VVCC, VOUT = VVCC
7.5
4
20
µA
V
0 < IVREF < 1 mA
3.9
4.1
Input bias current, device enabled, sourcing or
sinking
IPROG
0 < VPROG < 4 V, VEN = 48 V
IPROG = 200 µA, VEN = 0 V
5
µA
RPROG
Pulldown resistance, device disabled
375
600
Ω
POWER LIMITING AND CURRENT LIMITING (SENSE)
Current sense threshold V(VCC-SENSE) with
power limiting trip
VPROG = 2.4 V, VOUT = 0 V or
VPROG = 0.9 V, VOUT = 30 V, VVCC = 48 V
VCL
17
45
25
50
33
55
mV
mV
VSENSE
Current sense threshold V(VCC-sense) without
power limiting trip
VPROG = 4 V, VSENSE = VOUT
VPROG = 4 V, VOUT = VSENSE
V(VCC-SENSE): 0 → 200 mV,
C(GATE-OUT) = 2 nF, V(GATE-OUT) = 1 V
,
tF_TRIP
Large overload response time to GATE low(1)
1.2
µS
TIMER OPERATION (TIMER)
Charge current (sourcing)
VTIMER = 0 V
15.0
20.0
1.50
2.10
3.9
25.0
25.0
2.5
2.5
4
34.0
30.0
3.70
3.10
4.1
µA
µA
µA
µA
V
VTIMER = 0 V, TJ = 25°C
VTIMER = 5 V
Discharge current (sinking)
VTIMER = 5 V, TJ = 25°C
TIMER upper threshold voltage
TIMER lower reset threshold voltage
Fault retry duty cycle
TPS2491 only
TPS2491 only
0.96
1.0
1.04
1.0%
V
DRETRY
0.5% 0.75%
GATE DRIVE OUTPUT (GATE)
VSENSE = VVCC, V(GATE-OUT) = 7 V,
VEN = Hi
IGATE
GATE sourcing current
15
22
35
µA
VEN = Lo, VGATE = VVCC
1.8
75
2.4
2.8
mA
mA
GATE sinking current
VEN = Hi, VGATE = VVCC
,
125
250
V(VCC-SENSE)≥ 200 mV
GATE output voltage, V(GATE-OUT)
12
16
40
V
Propagation delay: EN going true to GATE
output high(1)
VEN = 0 → 2.5 V, 50% of VEN to 50% of
VGATE, VOUT = VVCC, R(GATE-OUT)= 1 MΩ
tD_ON
25
µS
VEN = 2.5 V → 0, 50% of VEN to 50% of
Propagation delay: EN going false (0 V) to
GATE output low(1)
tD_OFF
VGATE, VOUT = VVCC
,
0.5
1
1
µS
µS
R(GATE-OUT)= 1 MΩ, tFALL < 0.1 µS
VTIMER: 0 → 5 V, tRISE < 0.1 µS, 50% of
Propagation delay: TIMER expires to GATE
output low(1)
VTIMER to 50% of VGATE, VOUT = VVCC
,
0.8
R(GATE-OUT) = 1 MΩ,
POWER GOOD OUTPUT (PG)
IPG = 2 mA
IPG = 4 mA
0.1
0.25
0.5
V
V
VPG_L
VPGTL
Low voltage (sinking)
0.25
PG threshold voltage, VOUT rising, PG goes
open drain
VSENSE = VVCC, measure V(VCC-OUT)
0.8
1.25
1.7
V
(1) Not tested in production.
3
TPS2490
TPS2491
www.ti.com
SLVS503–NOVEMBER 2003
ELECTRICAL CHARACTERISTICS (continued)
unless otherwise noted, minimum and maximum limits apply across the recommended operating junction temperature and
voltage range, VTIMER = 0 V, and all outputs unloaded; typical specifications are at TJ = 25°C, VVCC = 48 V, VTIMER = 0 V, and
all outputs unloaded; positive currents are into pins.
PARAMETER
TEST CONDITIONS
VSENSE = VVCC, measure V(VCC-OUT)
VSENSE = VVCC
MIN
TYP
2.7
1.4
9
MAX UNIT
PG threshold voltage, VOUT falling, PG goes
low
VPGTH
∆VPGT
tDPG
2.2
3.2
V
V
PG threshold hysteresis voltage, V(SENSE-OUT)
PG deglitch delay, detection to output, rising
VSENSE = VVCC
5
15
10
ms
µA
(2)
and falling edges
Leakage current, PG false, open drain
OUTPUT VOLTAGE FEEDBACK INPUT (OUT)
IOUT Bias current
ENABLE INPUT (EN)
VOUT = VVCC, VEN = Hi, sinking
VOUT = GND, VEN = Lo, sourcing
8
20
40
µA
µA
18
VEN_H
VEN_L
Threshold, VEN going high
1.32
1.22
1.35
1.25
100
1.38
1.28
V
V
Threshold, VEN going low
VEN hysteresis(2)
mV
µA
Leakage current
VEN = 48 V
1
INPUT SUPPLY UVLO (VCC)
VVCC turn on
Rising
Falling
8.4
8.3
75
8.8
V
V
VVCC turn off
Hysteresis(2)
7.5
mV
(2) Not tested in production.
4
TPS2490
TPS2491
www.ti.com
SLVS503–NOVEMBER 2003
TYPICAL CHARACTERISTICS
SUPPLY CURRENT
vs
SUPPLY VOLTAGE
CURRENT LIMIT TRIP
vs
SUPPLY VOLTAGE
600
550
500
450
400
350
55
54
53
52
51
T = 1255C
J
T = 255C
J
T = −405C
J
50
49
T = 255C
J
T = −405C
J
48
47
T = 1255C
J
300
250
46
45
200
9
19
29
39
49
59
69
79
9
19
29
CC
39
49
59
69
79
V
CC
− Supply Voltage − V
V
− Supply Voltage − V
Figure 1.
Figure 2.
GATE PULLUP CURRENT
vs
GATE PULLDOWN CURRENT(EN = 0 V)
vs
SUPPLY VOLTAGE
SUPPLY VOLTAGE
2.6
2.5
2.4
2.3
2.2
35
33
31
29
27
25
23
T = 1255C
J
T = 255C
J
T = 1255C
J
T = −405C
J
T = 255C
J
21
19
17
2.1
2
T = −405C
J
15
9
9
19
29
39
49
59
69
79
19
29
39
49
59
69
79
V
CC
− Supply Voltage − V
V
CC
− Supply Voltage − V
Figure 3.
Figure 4.
5
TPS2490
TPS2491
www.ti.com
SLVS503–NOVEMBER 2003
TYPICAL CHARACTERISTICS (continued)
GATE PULLDOWN CURRENT
vs
CURRENT LIMIT RESPONSE TIME
vs
SUPPLY VOLTAGE
SUPPLY VOLTAGE
(EN = 4 V, V(vcc – sense) = 200 mV)
(EN = 4 V, V(vcc – sense) = 200 mV)
215
195
1200
1000
800
T = 1255C
J
T = −405C
J
175
T = 255C
J
T = 255C
J
155
135
600
T = −405C
J
400
T = 1255C
J
115
95
200
0
75
9
19
29
39
49
59
69
79
9
14
19
V
24
29
34
39
44
49
− Supply Voltage − V
V
CC
− Supply Voltage − V
CC
Figure 5.
Figure 6.
GATE OUTPUT VOLTAGE
vs
TIMER PULLUP CURRENT
vs
SUPPLY VOLTAGE
SUPPLY VOLTAGE
14.50
14.25
32
30
28
26
24
22
T = 1255C
J
T = 1255C
J
T = 255C
J
T = 255C
J
14
13.75
13.50
T = −405C
J
T = −405C
J
20
18
29
V
9
19
39
49
59
69
79
9
19
29
39
49
59
69
79
− Supply Voltage − V
V
CC
− Supply Voltage − V
CC
Figure 7.
Figure 8.
6
TPS2490
TPS2491
www.ti.com
SLVS503–NOVEMBER 2003
TYPICAL CHARACTERISTICS (continued)
TIMER CHARGE/DISCHARGE RATIO
vs
SUPPLY VOLTAGE AND TEMPERATURE
EN THRESHOLD VOLTAGE (FALLING)
vs
SUPPLY VOLTAGE
9.80
9.75
1.255
1.254
1.253
1.252
1.251
1.250
1.249
1.248
1.247
1.246
1.245
T = 255C
J
T = 1255C
J
T = −405C
J
9.70
T = 255C
J
T = −405C
J
T = 1255C
J
9.65
9.60
9
19
29
39
49
59
69
79
9
19
29
39
49
59
69
79
V
CC
− Supply Voltage − V
V
CC
− Supply Voltage − V
Figure 9.
Figure 10.
EN THRESHOLD VOLTAGE (RISING)
vs
SUPPLY VOLTAGE
1.351
1.350
1.349
1.348
1.347
1.346
T = 1255C
J
T = 255C
J
T = −405C
J
1.345
9
19
29
39
49
59
69
79
V
CC
− Supply Voltage − V
Figure 11.
7
TPS2490
TPS2491
www.ti.com
SLVS503–NOVEMBER 2003
FUNCTIONAL BLOCK DIAGRAM
4 V
Reference
10
VCC
2
Charge
Pump
VREF
Constant
Power
Engine
Enable
22 mA
A
3
Gate Control
Amplifier
50 mV max
A
V (DS)
Detector
+
PROG
+
_
2B
8
B
S
GATE
14 V
−
2 mA
I (D)
Detector
Power/Current
Amplifier
+
7
OUT
S
−
Inrush
Complete
6
PG
+
_
9 mS
Deglitch
9
SENSE
2.25 V and
1.25 V
25 mA
+
Enable
Fault
Logic
8.4 V and
8.3 V
_
UVLO
+
_
4 V
and
1 V
+
1
EN
_
1.35 V and
1.25 V
Timer
Enable
2.5 mA
POR
For Autoretry Opion with
Duty Cycle of 0.75%
5
GND
4
TIMER
TERMINAL FUNCTIONS
TERMINAL
I/O
DESCRIPTION
NAME
EN
NO.
1
I
O
I
Device enable
VREF
PROG
TIMER
GND
2
Reference voltage output, used to set power threshold on PROG pin
3
Power-limit setting input
Fault timing capacitor
Ground
4
I/O
5
PG
6
O
I
Power good reporting output, open-drain
Output voltage feedback
Gate output
OUT
7
GATE
SENSE
VCC
8
O
I
9
Current-limit sense input
Supply input
10
I
8
TPS2490
TPS2491
www.ti.com
SLVS503–NOVEMBER 2003
DETAILED PIN DESCRIPTION
The following description relies on the typical application diagram shown on page 1, and the functional block
diagram.
VCC: This pin is associated with three functions: 1) biasing power to the integrated circuit, 2) input to power on
reset (POR) and under voltage lockout (UVLO) functions, and 3) voltage sense at one terminal of RS for M1
current measurement. The voltage must exceed the POR (about 6 V for roughly 400µ S) and the internal UVLO
(about 8 V) before normal operation (driving the GATE) may begin. Connections to VCC should be designed to
minimize RS voltage sensing errors and to maximize the effect of C1 and D1; place C1 at RS rather than at the IC
pin to eliminate transient sensing errors. GATE, PROG, PG, and TIMER are held low when either UVLO or POR
are active.
SENSE: Monitors the voltage at the drain of M1, and the downstream side of RS providing the constant power
limit engine with feedback of both M1 current (ID) and voltage (VDS). Voltage is determined by the difference
between SENSE and OUT, while the current analog is the difference between VCC and SENSE. The constant
power engine uses VDS to compute the allowed ID and is clamped to 50 mV, acting like a traditional current limit
at low VDS. The current limit is set by the following equation:
50 mV
I
+
LIM
R
S
Design the connections to SENSE to minimize RS voltage sensing errors. Don’t drive SENSE to a large voltage
difference from VCC because it is internally clamped to VCC. The current limit function can be disabled by
connecting SENSE to VCC.
GATE: Provides the high side (above VCC) gate drive for M1. It is controlled by the internal gate drive amplifier,
which provides a pull-up of 22 µA from an internal charge pump and a strong pull-down to ground of 75 mA
(min). The pull-down current is a non-linear function of the amplifier overdrive; it provides small drive for small
overloads, but large overdrive for fast reaction to an output short. There is a separate pull-down of 2 mA to shut
M1 off when EN or the UVLO cause this to happen. An internal clamp protects the gate of M1 (to OUT) and
generally eliminates the need for an external clamp in almost all cases for devices with 20 V VGS(MAX) ratings; an
external Zener may be required to protect the gate of devices with VGS(MAX) < 16 V. A small series resistance
(R5) of 10 Ω should be inserted in the gate lead if the CISSof M1 > 200 pF, otherwise use 33 Ω for small
MOSFETs.
A capacitor can be connected from GATE to ground to create a slower inrush with a constant current profile
without affecting the amplifier stability. Add a series resistor of about 1 kΩ to the gate capacitor to maintain the
gate clamping and current limit response time.
OUT: This input pin is used by the constant power engine and the PG comparator to measure VDS of M1 as
V(VCC–SENSE). Internal protection circuits leak a small current from this pin when it is low. If the load circuit can
drive OUT below ground, connect a clamp (or freewheel) diode such as an S1B from OUT (cathode) to GND
(anode).
EN: The GATE driver is enabled if the positive threshold is exceeded and the internal POR and UVLO thresholds
have been satisfied. EN can be used as a logic control input, an analog input voltage monitor as illustrated by
R1/R2 in the typical application circuit on page 1, or it can be tied to VCC to always enable the TPS2490/91. The
hysteresis associated with the internal comparator makes this a stable method of detecting a low input condition
and shutting the downstream circuits off. A TPS2490 that has latched off can be reset by cycling EN below its
negative threshold and back high.
VREF: Provides a 4.0-V reference voltage for use in conjunction with R3/R4 of the typical application circuit to
set the voltage on the PROG pin. The reference voltage is available once the internal POR and UVLO thresholds
have been met. It is not designed as a supply voltage for other circuitry, therefore ensure that no more than 1 mA
is drawn. Bypass capacitance is not required, but if a special application requires one, less than 1000 pF can be
placed on this pin.
PROG: The voltage applied to this pin (0–4 V) programs the power limit used by the constant power engine.
Normally, a resistor divider R3/R4 is connected from VREF to PROG to set the power limit according to the
following equation:
9
TPS2490
TPS2491
www.ti.com
SLVS503–NOVEMBER 2003
P
LIM
V
+
PROG
10 I
LIM
where PLIM is the desired power limit of M1 and ILIM is the current limit setpoint (see SENSE). PLIM is determined
by the desired thermal stress on M1:
T
T
J(MAX)
S(MAX)
P
t
LIM
R
qJC(MAX)
where TJ(MAX) is the maximum desired transient junction temperature of M1 and TS(MAX) is the maximum case
temperature prior to a start or restart.
VPROG is used in conjunction with VDS to compute the (scaled) current, ID_ALLOWED, by the constant power engine.
ID_ALLOWED is compared by the gate amplifier to the actual ID, and used to generate a gate drive. If ID
<
ID_ALLOWED, the amplifier turns the gate of M1 full on because there is no overload condition; otherwise GATE is
regulated to maintain the ID = ID_ALLOWED relationship.
A capacitor may be tied from PROG to ground to alter the natural constant power inrush current shape. If
properly designed, the effect is to cause the leading step of current in Figure 12 to look like a ramp.
PROG is internally pulled to ground whenever EN, POR, or UVLO are not satisfied or the TPS2490 is latched off.
This feature serves to discharge any capacitance connected to the pin. Do not apply voltages greater than 4 V to
PROG. If the constant power limit is not used, PROG should be tied to VREF through a 47-kΩ resistor.
TIMER: An integrating capacitor, CT, connected to the TIMER pin provides a timing function that controls the
fault-time for both versions and the restart interval for the TPS2491. The timer charges at 25 µA whenever the
TPS2490/91 is in power limit or current limit and discharges at 2.5 µA otherwise. The charge-to-discharge current
ratio is constant with temperature even though there is a positive temperature coefficient to both. If TIMER
reaches 4 V, the TPS2490 pulls GATE to ground, latch off, and discharge CT. The TPS2491 pulls GATE to
ground and attempt a restart (re-enable GATE) after a timing sequence consisting of discharging CT down to 1 V
followed by 15 more charge and discharge cycles. The TPS2490 can be reset by either cycling the EN pin or the
UVLO (e.g. power cycling). TIMER discharges when EN is low or UVLO or POR are active. The TIMER pin
should be tied to ground if this feature is not used.
PG: This open-drain output is intended to interface to downstream dc/dc converters or monitoring circuits. PG
goes open-drain (high voltage with a pull-up) after VDS of M1 has fallen to about 1.25 V and a 9 ms deglitch time
period has elapsed. PG is false (low or low resistance to ground) whenever EN is false, VDS of M1 is above
2.5 V, or UVLO is active. PG can also be viewed as having an input and output voltage monitor function. The
9-ms deglitch circuit operates to filter short events that could cause PG to go inactive (low) such as a momentary
overload or input voltage step. VPG voltage can be greater than VVCC because it s ESD protection is only with
respect to ground.
GND: This pin is connected to system ground.
10
TPS2490
TPS2491
www.ti.com
SLVS503–NOVEMBER 2003
APPLICATION INFORMATION
BASIC OPERATION
The TPS2490/91 provides all the features needed for a positive hotswap controller. These features include: 1)
under-voltage lockout; 2) adjustable (system-level) enable; 3) turn-on inrush limit; 4) high-side gate drive for an
external N-channel MOSFET; 5) MOSFET protection (power limit and current limit); 6) adjustable overload
timeout—also called an electronic circuit breaker; 7) charge-complete indicator for downstream converter
coordination; and 8) an optional automatic restart mode. The TPS2490/91 features superior power-limiting
MOSFET protection that allows independent control of current limit (to set maximum full-load current), power limit
(to control junction temperature rise), and overload time (to control case temperature rise).
The typical application circuit, and oscilloscope plots of Figures 12–16 demonstrate many of the functions
described above.
Board Plug-In (Figure 12)
Only the bypass capacitor charge current and small bias currents are evident when a board is first plugged in.
The TPS2490/91 is held inactive, and GATE, PROG, TIMER, and PG are held low for less than 1 ms while
internal voltages stabilize. A startup cycle is ready to take place after the stabilization.
GATE, PROG, TIMER, and PG are released after stabilization in this example because both the internal UVLO
threshold and the external EN (enable) thresholds have been exceeded. The part begins sourcing current from
the GATE pin and M1 begins to turn on while the voltage across it, V(SENSE–OUT), and current through it,
V(VCC–SENSE), are monitored. Current initially rises to the value which satisfies the power limit engine (PLIM÷ VVCC
)
since the output capacitor was discharged.
TIMER and PG Operation (Figure 12)
The TIMER pin charges CT as long as limiting action continues, and discharges at a 1/10 charge rate when
limiting stops. If the voltage on CT reaches 4 V before the output is charged, M1 is turned off and either a
latch-off or restart cycle commences, depending on the part type. The open-drain PG output provides a
deglitched end-of-charge indication which is based on the voltage across M1. PG is useful for preventing a
downstream dc/dc converter from starting while CO is still charging. PG goes active (open drain) about 9 ms after
CO is charged. This delay allows M1 to fully turn on and any transients in the power circuits to end before the
converter starts up. The resistor pull-up shown on pin PG in the typical application diagram only demonstrates
operation; the actual connection to the converter depends on the application. Timing can appear to terminate
early in some designs if operation transitions out of the power limit mode into a gate charge limited mode at low
VDS values.
VCC10 V/div
PG
10 V/div
I
1 A/div
OUT
IN
Timer 1 V/div
10 V/div
Figure 12. Basic Board Insertion
11
TPS2490
TPS2491
www.ti.com
SLVS503–NOVEMBER 2003
APPLICATION INFORMATION (continued)
Action of the Constant Power Engine (Figure 13)
The calculated power dissipated in M1, VDS × ID, is computed under the same startup conditions as Figure 12.
The current of M1, labeled IIN, initially rises to the value that satisfies the constant power engine; in this case it is
34 W ÷ 48 V = 0.7 A. The 34 W value is programmed into the engine by setting the PROG voltage using the
equation given in the PROG pin description. VDSof M1, which is calculated as V(VCC–OUT) , falls as CO charges,
thus allowing the M1 drain current to increase. This is the result of the internal constant power engine adjusting
the current limit reference to the GATE amplifier as CO charges and VDS falls. The calculated device power in
Figure 13, labeled FET PWR, is seen to be flat-topped and constant within the limitations of circuit tolerance and
acquisition noise. A fixed current limit is implemented by clamping the constant power engine s output to 50 mV
when VDS is low. This protection technique can be viewed as a specialized form of foldback limiting; the benefit
over linear foldback is that it yields the maximum output current from a device over the full range of VDS and still
protects the device.
VCC − OUT
10 V/div
FET PWR 10 W/div
VOUT 10 V/div
I
IN
1 A/div
M1 Power Measured 29.6 W,
Calculated 34.4 W
Figure 13. Computation of M1 Stress During Startup
Response to a Hard Output Short (Figure 14 and Figure 15)
Figure 14 shows the short circuit response over the full time-out period that begins when the output voltage falls
and ends when M1 is turned off. M1 current is actively controlled by the power limiting engine and gate amplifier
circuit while the TIMER pin charges CT to the 4 V threshold that causes M1 to be turned off. The TPS2490
latches off after the threshold is reached until either the input voltage drops below the UVLO threshold or EN
cycles through the false (low) state. The TPS2491 goes through a timing sequence before attempting a restart.
12
TPS2490
TPS2491
www.ti.com
SLVS503–NOVEMBER 2003
APPLICATION INFORMATION (continued)
TIMER
1 V/div
I
IN
5 A/div
GATE 10 V/div
OUT 10 V/div
Figure 14. Current Limit Overview
The TPS2490/91 responds rapidly to the short circuit as seen in Figure 15. The falling OUT voltage is the result
of M1 and CO currents through the short s impedance at this time scale. The internal GATE clamp causes the
GATE voltage to follow the output voltage down and subsequently limits the negative VDS to 1–2 V. The rapidly
rising fault current overdrives the GATE amplifier causing it to overshoot and rapidly turn M1 off by sinking
current to ground. M1 slowly turns back on as the GATE amplifier recovers; M1 then settles to an equilibrium
operating point determined by the power limiting circuit.
GATE 10 V/div
VCC 10 V/div
OUT 10 V/div
I
IN
5A/div
Figure 15. Current Limit Onset
Minimal input voltage overshoot appears in Figure 15 because a local 100-µF bypass capacitor and very short
input leads were used. The input voltage would overshoot as the input current abruptly drops in a typical
application due to the stored energy in the input distribution s inductance. The exact waveforms seen in an
application depend upon many factors including parasitics of the voltage distribution, circuit layout, and the short
itself.
13
TPS2490
TPS2491
www.ti.com
SLVS503–NOVEMBER 2003
APPLICATION INFORMATION (continued)
Automatic Restart (Figure 16)
The TPS2491 automatically initiates a restart after a fault has caused it to turn off M1. Internal control circuits use
CT to count 16 cycles before re-enabling M1. This sequence continues to repeat if the fault persists. The TIMER
has a 1:10 charge-to-discharge current ratio, and uses a 1-V lower threshold. The fault-retry duty cycle
specification quantifies this behavior. This small duty cycle often reduces the average short-circuit power
dissipation to levels associated with normal operation and eliminates special thermal considerations for surviving
a prolonged output short.
GATE 10 V/div
OUT 10 V/div
TIMER 1 V/div
I
IN
.5 A/div
Figure 16. TPS2491 Restart Cycle Timing
DESIGN PROCEDURE
This design procedure seeks to control the junction temperature of M1 under both static and transient conditions
by selecting the device s package, cooling, RDSON, current limit, fault timeout, and power limit. The following
procedure assumes that a unit running at full load and maximum ambient temperature experiences a brief input
power interruption sufficient to discharge CO, but short enough to keep M1 from cooling. A full CO recharge then
takes place. Adjust this procedure to fit your application and design criteria.
This procedure assumes that CO is the only load during inrush. Only simple first-order thermal models, natural
convection and a large PCB pad for M1 are assumed. The assumptions build generous safety margins into the
design to allow for the inherent inaccuracies of the models and variations of real-world conditions.
Other tools and applications information are available on the TI website that supplement the following procedure.
STEP 1. Choose RS
Given the maximum operating current, IMAX, compute the current sense resistance, RS.
0.05
R +
S
1.2 I
MAX
This equation allows for minimum current limit, a sense resistor tolerance of 5%, and 5% margin. Round the
result down to the nearest available standard value.
STEP 2. Choose M1
First select a VDS rating that allows for the maximum input voltage and transients. Next select an operating
RDSON, package, and cooling to control operating temperature. The following equation computes the value of
RDSON(MAX)at a junction temperature of TJ(MAX). Most manufacturers list RDSON(MAX) at 25°C and provide a derating
curve from which values at other temperatures can be derived. Compute the maximum allowable on-resistance,
RDSon(MAX), using the equation:
14
TPS2490
TPS2491
www.ti.com
SLVS503–NOVEMBER 2003
APPLICATION INFORMATION (continued)
T
T
A(MAX)
J(MAX)
R
v
DSON(MAX)
2
R
I
qJA
MAX
where TJ(MAX) is the desired maximum steady-state junction temperature (typically 125°C), and TA(MAX) is the
maximum ambient temperature. RθJA, the junction-to-ambient thermal resistance, depends upon the package
style chosen and the details of heat-sinking and cooling. Note the RθJC and RθJA for use below.
STEP 3. Choose PLIM, R3, R4
M1 dissipates large amounts of power during power-up or output short circuit. The power limit PLIM of the
TPS2940/91 should be set to prevent the die temperature from exceeding a short term maximum temperature,
TJ(MAX)2. The short-term TJ(MAX)2 could be set as high as 150°C while still leaving ample margin to the usual
manufacturer s rating of 175°C. An expression for calculating PLIM is:
2
MAX
ǒ
Ǔ) T
A(MAX)ƫ
* ƪ I
T
R
R
qCA
DSON
J(MAX)2
P
v 0.7
LIM
R
qJC
where RθJC is M1 junction-to-case thermal resistance, RDSON is the channel resistance at the maximum operating
temperature, and the factor of 0.7 represents the tolerance of the constant power engine. Next calculate VPROG
and the divider resistors R3 and R4. R3 must be greater than 4 kΩ, but it is recommended that 10 kΩ or greater
be used.
P
0.05
+
LIM
V
+
where I
PROG
LIM
10 I
R
LIM
S
V
PROG
R4
R3 ) R4
+
V
REF
STEP 4. Choose tON, CT
The on-time, tON, set by capacitor CT must suffice to fully charge the load capacitance CO without triggering the
fault circuitry. Assuming that only the load capacitance draws current during startup:
2
C
V
C
P
O
VCC(MAX)
O
LIM
)
if P
t I
V
LIM VCC(MAX)
LIM
2
LIM
2 P
2 I
LIM
t
+
ON
C
O
V
VCC(MAX)
if P
w I
V
LIM
LIM VCC(MAX)
I
LIM
Using this value of tON, CTis computed as:
*6
ǒ1 ) C
T_TOLǓ
C + 8.5 10 t
) C
OUT_TOL
T
ON
where CT_TOL and COUT_TOL are the tolerances associated with each capacitor. Assuming CO is a 20% tolerance
part, COUT_TOL has a value of 0.2. This expression assures the worst case set of parts will always start.
STEP 5. Choose The Turn On Voltage, R1 & R2
Assuming that EN is used as an analog input, the turn-on voltage, VON and turn-off voltage, VOFF are defined as:
+ ǒ 1.35 V Ǔ
+ ǒ 1.25 V Ǔ
V
V
OFF
ON
R2
R2
R1R2
R1R2
Use caution in selecting very large values of R1 and R2 because the leakage current causes errors in the
threshold voltages.
15
TPS2490
TPS2491
www.ti.com
SLVS503–NOVEMBER 2003
APPLICATION INFORMATION (continued)
STEP 6. Choose R5, R6, & C1
R5 is intended to suppress high-frequency oscillations; a resistor of 10Ω will serve for most applications but if M1
has a CISS below 200 pF, then use 33 Ω. Applications with larger MOSFETs and very short wiring may not
require R5. R6 is required only if the PG output drives a circuit that requires it. It is recommended that the sink
current be less than 2 mA. C1 is a bypass capacitor to help with control of transient voltages, unit emissions, and
local supply noise while in the disabled state. Where acceptable, a value in the range of 0.001 µF to 0.1 µF is
recommended.
STEP 7. Choose D1
Transient voltage suppressor D1 is required in applications where there will be enough energy in the distribution
inductance to cause a voltage surge above the TPS2490/91 rated maximum. Such transients can be caused by
card insertions or shorts on the input or output of the TPS2490/91.
ALTERNATIVE INRUSH DESIGNS
Gate Capacitor (dV/dt) Control
The TPS2490/91 can be used with applications that require constant turn-on currents. The current is controlled
by a single capacitor from the GATE terminal to ground with a series resistor. M1 appears to operate as a source
follower (following the gate voltage) in this implementation. Choose a time to charge, ∆t, based on the output
capacitor, input voltage VI, and desired charge current, ICHARGE. Select ICHARGE to be less than PLIM ÷ VVCC if the
power limit feature is kept.
C
V
O
VCC
Dt +
I
CHARGE
To select the gate capacitance:
Dt
+ ǒI
Ǔ* C
C
G
GATE
ISS
V
VCC
where CISS is the gate capacitance of M1, and IGATE is the nominal gate charge current. The TIMER capacitor
can then be selected to be much smaller as the current and power limit is not active during initial power on. A
series resistor of about 1 kΩ should be used in conjunction with CG.
PROG Inrush Control
A capacitor can be connected from the PROG pin to ground to reduce the initial current step seen in Figure 12
based on the typical application circuit on page 1. This method maintains a relatively fast turn-on time without the
drawbacks of a gate-to-ground capacitor that include increased short circuit response time and less predictable
gate clamping.
ADDITIONAL DESIGN CONSIDERATIONS
Use of PG
Use the PG pin to control and coordinate a downstream dc/dc converter. A long time delay is needed to allow CO
to fully charge before the converter starts if this is not done. An undesirable latchup condition can be created
between the TPS2490 output characteristic and the dc/dc converter input characteristic if the converter starts
while CO is still charging; the PG pin is one way to avoid this.
Faults and Backplane Voltage Droop
A hard short at the output of the TPS2490/91 during normal operation could result in activation of the enable or
UVLO circuit instead of the current limit if the input voltage droops sufficiently. The lower GATE drive in this
condition will cause a prolonged, larger over-current spike. This can be eliminated by filtering EN, or distributing
capacitance on the bus itself. Capacitance from adjacent plugged-in units may help with this as well.
16
TPS2490
TPS2491
www.ti.com
SLVS503–NOVEMBER 2003
APPLICATION INFORMATION (continued)
Output Clamp Diode
Inductive loads on the output may drive the OUT pin below GND when the circuit is unplugged or during a
current limit. The OUT pin ratings can be maintained with a small diode, such as an S1B, across TPS2490/91
OUT to GND.
Gate Clamp Diode
The TPS2490/91 has a relatively well-regulated gate voltage of 12–16 V, even with low supply voltages. A small
clamp Zener from gate to source of M1, such as a BZX84C7V5, is recommended if VGS of M1 is rated below this.
High Gate Capacitance Applications
Gate voltage overstress and abnormally large fault current spikes can be caused by large gate capacitance. An
external gate clamp Zener diode is recommended if the total gate capacitance of M1 exceeds about 4000 pF.
When gate capacitor inrush control is used, a 1-kΩ resistor in series with CG is recommended. If the series R-C
combination is used for MOSFETs with CISS less than 3000 pF, then a Zener is not necessary.
Output Short Circuit Measurements
Repeatable short-circuit testing results are difficult to obtain. The many details of source bypassing, input leads,
circuit layout and component selection, output shorting method, relative location of the short, and instrumentation
all contribute to obtaining different results. The actual short itself exhibits a certain degree of randomness as it
microscopically bounces and arcs. Care in configuration and methods must be used to obtain realistic results. Do
not expect to see waveforms exactly like those in the data sheet—every setup differs.
Layout Considerations
Good layout practice places the power devices D1, RS, M1, and CO so power flows in a sequential fashion, and
preferably in a straight line. A ground plane under the power and the TPS2490/91 is desirable. The TPS2490/91
should be placed close to the sense resistor and the MOSFET; a Kelvin connection is recommended to achieve
accurate current sensing across RS. A low-impedance GND connection is required because the TPS2490/91 can
momentarily sink upwards of 100 mA from the gate of M1. The GATE amplifier has high bandwidth while active,
so keep the gate trace length short. The PROG, TIMER, and EN pins have high input impedances, therefore
keep their input leads short. Oversize power traces and power device connections to assure low voltage drop
and good thermal performance.
17
PACKAGE OPTION ADDENDUM
www.ti.com
6-Dec-2006
PACKAGING INFORMATION
Orderable Device
TPS2490DGS
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
MSOP
DGS
10
10
10
10
10
10
10
10
80 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
TPS2490DGSG4
TPS2490DGSR
TPS2490DGSRG4
TPS2491DGS
MSOP
MSOP
MSOP
MSOP
MSOP
MSOP
MSOP
DGS
DGS
DGS
DGS
DGS
DGS
DGS
80 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
80 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
TPS2491DGSG4
TPS2491DGSR
TPS2491DGSRG4
80 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
30-Jun-2007
TAPE AND REEL INFORMATION
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
30-Jun-2007
Device
Package Pins
Site
Reel
Reel
A0 (mm)
B0 (mm)
K0 (mm)
P1
W
Pin1
Diameter Width
(mm) (mm) Quadrant
(mm)
330
(mm)
12
TPS2490DGSR
TPS2491DGSR
DGS
DGS
10
10
NSE
NSE
5.3
5.3
3.3
3.3
1.3
1.3
8
8
12
12
Q1
Q1
330
12
TAPE AND REEL BOX INFORMATION
Device
Package
Pins
Site
Length (mm) Width (mm) Height (mm)
TPS2490DGSR
TPS2491DGSR
DGS
DGS
10
10
NSE
NSE
370.0
370.0
355.0
355.0
75.0
75.0
Pack Materials-Page 2
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