TPS25200QDRVRQ1 [TI]
关断时可实现反向电流阻断的 2.5V 至 6.5V、67mΩ、2.1A 至 2.7A 汽车电子保险丝 | DRV | 6 | -40 to 125;
| 型号： | TPS25200QDRVRQ1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 关断时可实现反向电流阻断的 2.5V 至 6.5V、67mΩ、2.1A 至 2.7A 汽车电子保险丝 | DRV | 6 | -40 to 125 电子 光电二极管 |
| 文件： | 总28页 (文件大小：2835K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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TPS25200-Q1
ZHCSDG1 –MARCH 2015
TPS25200-Q1 具有精度可调节的电流限制和过压钳位的 5V 电子熔丝
1 特性
3 说明
1
•
符合汽车应用要求
TPS25200-Q1 器件是一款具有精确电流限制和过压钳
位的 5V 电子熔丝。 此器件在过压和过压事件发生时
为负载和电源提供强健保护。
•
具有符合 AEC-Q100 的下列结果：
–
–
器件人体模型 (HBM) 分类等级 2
器件充电器件模型 (CDM) 分类等级 C5
TPS25200-Q1 是一款智能保护型负载开关，可耐受
20V 的 VIN 电压。当 IN 引脚上施加错误电压时，输出
会钳位在 5.4V 电压，从而保护负载。 当 IN 引脚上的
电压超过 7.6V 时，器件会与负载断开连接，从而避免
损坏器件和/或负载。
•
•
•
•
•
•
•
2.5V 至 6.5V 工作电压
20V 持续 VIN（绝对最大值）
7.6V 输入过压关断
5.25V 至 5.55V 固定过压钳位
0.6μs 过压锁定响应
TPS25200-Q1 具有一个内部 67mΩ 电源开关，并且用
于在多种异常情况下保护电源、器件和负载。 此器件
提供高达 2.4A 的持续负载电流。 通过一个接地电阻，
可在 85mA 至 2.7A 范围内对限流值进行设置。 当发
生过载时，输出电流会被限制在由 RILIM 电阻设置的电
流值上。 如果出现持续过载，此器件最终将进入热关
断模式，以防止对 TPS25200-Q1 器件造成损坏。
3.5μs 短路响应
67mΩ 高侧金属氧化物半导体场效应晶体管
(MOSFET)
•
精确的电流限制设置（包含电阻）：2.5A（最小
值）与 2.9A（最大值）；2.1A（最小值）与
2.5A（最大值）
•
•
•
•
2.7A 电流下的电流限制精度为 ±6.3%
禁用时，反向电流阻断
器件信息(1)
内置软启动
器件型号
封装
WSON (6)
封装尺寸（标称值）
与 TPS2553 引脚到引脚兼容
TPS25200-Q1
2.00mm x 2.00mm
(1) 要了解所有可用封装，请见数据表末尾的可订购产品附录。
2 应用范围
•
•
•
汽车 USB 端口保护
USB 电源开关
USB 受控设备
4 简化电路原理图
V
IO
VOUT 与 VIN 之间的关系
300kΩ
Fault signal
VOUT (V)
Over Voltage Clamp
(OVC)
TPS25200-Q1
V
IN
V
OUT
6
IN
OUT
ILIM
1
2
3
C
IN
5.4 V
300 kΩ
5 GND
4 EN
C
OUT
FAULT
Turn Off
MOSFET
Thermal Pad
R
ILIM
UVLO (2.35 V)
OVLO (7.6 V)
VIN (V)
20 V
1
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
English Data Sheet: SLVSCU5
TPS25200-Q1
ZHCSDG1 –MARCH 2015
www.ti.com.cn
目录
9.1 Overview ................................................................... 9
9.2 Functional Block Diagram ......................................... 9
9.3 Feature Description................................................. 10
9.4 Device Functional Modes........................................ 11
10 Application and Implementation........................ 12
10.1 Application Information.......................................... 12
10.2 Typical Application ................................................ 12
11 Power Supply Recommendations ..................... 19
12 Layout................................................................... 19
12.1 Layout Guidelines ................................................. 19
12.2 Layout Example .................................................... 19
13 器件和文档支持 ..................................................... 20
13.1 文档支持................................................................ 20
13.2 商标....................................................................... 20
13.3 静电放电警告......................................................... 20
13.4 术语表 ................................................................... 20
14 机械封装和可订购信息 .......................................... 20
1
2
3
4
5
6
7
特性.......................................................................... 1
应用范围................................................................... 1
说明.......................................................................... 1
简化电路原理图........................................................ 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 3
7.1 Absolute Maximum Ratings ...................................... 3
7.2 ESD Ratings.............................................................. 4
7.3 Recommended Operating Conditions....................... 4
7.4 Thermal Information.................................................. 4
7.5 Electrical Characteristics........................................... 5
7.6 Switching Characteristics.......................................... 6
7.7 Typical Characteristics.............................................. 6
Parameter Measurement Information .................. 8
Detailed Description .............................................. 9
8
9
5 修订历史记录
日期
修订版本
注释
2015 年 3 月
*
最初发布。
2
Copyright © 2015, Texas Instruments Incorporated
TPS25200-Q1
www.ti.com.cn
ZHCSDG1 –MARCH 2015
6 Pin Configuration and Functions
DRV Package
6-Pin WSON With Exposed Thermal Pad
Top View
OUT
1
6
5
4
IN
Thermal
Pad
ILIM 2
GND
EN
3
FAULT
Pin Functions
PIN
I/O
DESCRIPTION
NAME
NO.
Logic-level control input. When this pin is driven high, the power switch is enabled. When this pin
is driven low, the power switch turns off. This pin cannot be left floating and it must be limited
below the absolute maximum rating if tied to the IN pin.
EN
4
I
Active-low open-drain output. This pin is asserted during an overcurrent, overvoltage, or
overtemperature event. Connect a pullup resistor to the logic I/O voltage.
FAULT
GND
ILIM
3
5
2
O
—
O
Ground connection. Connect this pin externally to the exposed thermal pad.
External resistor. The ILIM pin is used to set the current-limit threshold. The recommended value
for this pin is: 36 kΩ ≤ RILIM ≤ 1100 kΩ.
Input voltage. Connect a ceramic capacitor with a value of 0.1 μF or greater from the IN pin to the
GND pin as close to the IC as possible.
IN
6
1
I
OUT
O
—
Protected power switch, VOUT.
The exposed thermal pad is internally connected to the GND pin. Use the thermal pad to heat-sink
the device to the circuit board traces. Connect the thermal pad to the GND pin externally.
Thermal pad
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range, voltage are referenced to GND (unless otherwise noted)(1)
MIN
MAX
20
UNIT
IN
–0.3
–0.3
–7
V
V
V
Voltage
OUT, EN, ILIM, FAULT
From IN to OUT
7
20
Continuous output current, IO
Thermally Limited
Continuous FAULT output sink current
Continuous ILIM output source current
Operating junction temperature, TJ
Storage temperature, Tstg
25
150
mA
µA
Internally limited
–65
150
°C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under recommended
operating conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Copyright © 2015, Texas Instruments Incorporated
3
TPS25200-Q1
ZHCSDG1 –MARCH 2015
www.ti.com.cn
7.2 ESD Ratings
VALUE
±2000
±750
UNIT
Human body model (HBM), per AEC Q100-002(1)
Charged device model (CDM), per AEC Q100-011
V(ESD)
Electrostatic discharge
V
(1) AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
6.5
UNIT
V
VIN
Input voltage of IN
2.5
0
VEN
IFAULT
IOUT
RILIM
TJ
Enable pin voltage
6.5
V
Continuous FAULT sink current
Continuous output current of OUT
Current-limit set resistors
Operating junction temperature
0
10
mA
A
2.4
36
1100
125
kΩ
°C
–40
7.4 Thermal Information
DRV (WSON)
THERMAL METRIC(1)
UNIT
6 PINS
66.5
83.4
36.1
1.6
RθJA
Junction-to-ambient thermal resistance
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
ψJB
36.5
7.6
RθJC(bot)
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
4
Copyright © 2015, Texas Instruments Incorporated
TPS25200-Q1
www.ti.com.cn
ZHCSDG1 –MARCH 2015
7.5 Electrical Characteristics
Conditions are –40°C ≤ TJ ≤ 125°C and 2.5 V ≤ VIN ≤ 6.5 V. VEN = VIN, RILIM = 36 kΩ. Positive current into pins. Typical value
is at 25°C. All voltages are with respect to ground (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
POWER SWITCH
TJ = 25°C
67
67
67
75
95
2.5 V ≤ VIN ≤ 5 V,
IOUT = 2.4 A
rDS(on)
IN–OUT resistance(1)
–40°C ≤ TJ ≤ 85°C
–40°C ≤ TJ ≤ 125°C
mΩ
105
ENABLE INPUT EN
EN pin turn on threshold
Input rising
Input falling
1.9
V
V
EN pin turn off threshold
Hysteresis
0.6
–2
330(2)
500
mV
µA
IEN
Leakage current
VEN = 0 V or 5.5 V
2
DISCHARGE
RDCHG
OUT Discharge Resistance
VOUT = 5 V, VEN = 0 V
625
Ω
CURRENT LIMIT
RILIM = 36 kΩ
RILIM = 42.2 kΩ
RILIM = 56 kΩ
RILIM = 80.6 kΩ
RILIM = 150 kΩ
RILIM = 1100 kΩ
2530
2140
1620
1110
590
2700
2300
1740
1206
647
2870
2460
1860
1300
710
IOS
Current-limit, see Figure 12
mA
40
83
130
OVERVOLTAGE LOCKOUT, IN
V(OVLO) IN rising OVLO threshold voltage
Hysteresis
IN rising
6.8
7.6
70(2)
8.45
5.55
V
mV
VOLTAGE CLAMP, OUT
V(OVC)
OUT clamp voltage threshold
CL = 1 µF, RL = 100 Ω, VIN = 6.5 V
5.25
5.4
V
SUPPLY CURRENT
VEN = 0 V, VIN = 5 V
1
1040
147
5
1700
200
IIN(off)
Supply current, low-level output
µA
VEN = 0 or 5 V, VIN = 20 V
RILIM = 36 kΩ
RILIM = 150 kΩ
VIN = 5 V,
No load on OUT
IIN(on)
IREV
Supply current, high-level output
Reverse leakage current
µA
µA
120
190
VOUT = 6.5V, VIN = VEN = 0 V, TJ = 25°C,
Measure IOUT
3.2
5
UNDERVOLTAGE LOCKOUT, IN
VUVLO IN rising UVLO threshold voltage
Hysteresis
FAULT FLAG
VOL Output low voltage, FAULT
Off-state leakage
THERMAL SHUTDOWN
Thermal shutdown threshold, OTSD2(3)
IN rising
2.35
30(2)
2.45
V
mV
IFAULT = 1 mA
VFAULT = 6.5 V
50
180
1
mV
µA
155
135
Thermal shutdown threshold only in
current-limit, OTSD1(3)
°C
Hysteresis
20(2)
(1) Pulse-testing techniques maintain junction temperature close to ambient temperature. Thermal effects must be taken into account
separately.
(2) These parameters are provided for reference only and does not constitute part of TI's published device specifications for purposes of
TI's product warranty.
(3) For more information on the thermal sensors, OTSD1 and OTSD2, see the Thermal Sense section.
Copyright © 2015, Texas Instruments Incorporated
5
TPS25200-Q1
ZHCSDG1 –MARCH 2015
www.ti.com.cn
7.6 Switching Characteristics
Conditions are –40°C ≤ TJ ≤ 125°C and 2.5 V ≤ VIN ≤ 6.5 V. VEN = VIN, RILIM = 36 kΩ. Positive current are into pins. Typical
value is at 25°C. All voltages are with respect to GND (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
POWER SWITCH
tr
tf
OUT voltage rise time
OUT voltage fall time
CL = 1 µF, RL = 100 Ω, (see Figure 10)
CL = 1 µF, RL = 100 Ω, (see Figure 10)
2.05
0.18
3.2
ms
0.2
ENABLE INPUT EN
ton Turn-on time
toff
2.5 V ≤ VIN ≤ 5 V, CL = 1 µF, RL = 100 Ω,
(see Figure 10)
5.12
0.22
7.3
0.3
ms
ms
2.5 V ≤ VIN ≤ 5 V, CL = 1 µF, RL = 100 Ω,
(see Figure 10)
Turn-off time
CURRENT LIMIT
t(IOS)
Short-circuit response time
VIN = 5 V (see Figure 12)
3.5(1)
0.6(1)
µs
µs
OVERVOLTAGE LOCKOUT, IN
t(OVLO_off_delay) Turn-off Delay for OVLO
FAULT FLAG
VIN = 5 V to 10 V with 1 V/µs ramp-up rate,
VOUT with 100-Ω load
FAULT assertion or deassertion because of
overcurrent condition
FAULT deglitch
5
8
12
ms
(1) This parameter is provided for reference only and does not constitute part of TI's published device specifications for purposes of TI's
product warranty.
7.7 Typical Characteristics
200
180
160
140
120
100
80
2.5
2
VIN = 2.5 V
VIN = 5 V
VIN = 2.5 V
VIN = 5 V
1.5
1
60
40
0.5
0
20
0
-50
0
50
100
150
-50
0
50
100
150
Junction Temperature (qC)
Junction Temperature (qC)
D001
D002
RILIM = 36 KΩ
RILIM = 36 KΩ
Figure 1. IIN(on) vs Junction Temperature
Figure 2. IIN(off) vs Junction Temperature
6
Copyright © 2015, Texas Instruments Incorporated
TPS25200-Q1
www.ti.com.cn
ZHCSDG1 –MARCH 2015
Typical Characteristics (continued)
100
90
80
70
60
50
40
30
20
10
0
5
4.5
4
3.5
3
2.5
2
1.5
1
0.5
0
-50
0
50
100
150
-50
0
50
100
150
Junction Temperature (qC)
Junction Temperature (qC)
D003
D004
VEN = VIN = 0 V
VOUT = 6.5 V
Figure 3. IREV vs Junction Temperature
Figure 4. rDS(ON) vs Junction Temperature
7.8
7.75
7.7
5.5
5.45
5.4
7.65
7.6
7.55
7.5
5.35
7.45
7.4
5.3
-50
0
50
100
150
-50
0
50
100
150
Junction Temperature (qC)
Junction Temperature (qC)
D005
D006
CL = 1 µF
RL = 100 Ω
VIN = 6.5 V
Figure 5. V(OVLO) vs Junction Temperature
Figure 6. VO(VC) vs Junction Temperature
3000
2500
2000
1500
1000
500
560
550
540
530
520
510
500
490
480
RILIM = 36 K:
RILIM = 42.2 K:
RILIM = 80.6 K:
RILIM = 150 K:
0
-50
0
50
100
150
2
3
4
5
6
7
Junction Temperature (qC)
Input Voltage (V)
D007
D0098
Figure 7. IOS vs Junction Temperature
Figure 8. Discharge Resistance vs VIN
Copyright © 2015, Texas Instruments Incorporated
7
TPS25200-Q1
ZHCSDG1 –MARCH 2015
www.ti.com.cn
8 Parameter Measurement Information
OUT
90%
10%
tr
tf
VOUT
RL
CL
Figure 9. Output Rise and Fall Test Load
Figure 10. Power-On and Off Timing
IOS
50%
ton
50%
VEN
IOUT
toff
90%
VOUT
tIOS
10%
Figure 11. Enable Timing, Active High Enable
Figure 12. Output Short Circuit Parameters
8
Copyright © 2015, Texas Instruments Incorporated
TPS25200-Q1
www.ti.com.cn
ZHCSDG1 –MARCH 2015
9 Detailed Description
9.1 Overview
The TPS25200-Q1 device is an intelligent low-voltage switch or e-Fuse with robust overcurrent and overvoltage
protection which are suitable for a variety of applications.
The TPS25200-Q1 current-limited power switch uses N-channel MOSFETs in applications requiring up to 2.4 A
of continuous load current. The device allows the user to program the current-limit threshold between 85 mA and
2.7 A (typical) through an external resistor. The device enters constant-current mode when the load exceeds the
current-limit threshold.
The TPS25200-Q1 input can withstand 20-V DC voltage, but clamps VOUT to a precision regulated 5.4 V and
shuts down in the event that the VIN value exceeds 7.6 V. The device also integrates overcurrent and short-circuit
protection. The precision overcurrent limit helps minimize over designing of the input power supply while the fast
response short-circuit protection isolates the load when a short circuit is detected.
The additional features of the device include the following:
•
Overtemperature protection to safely shutdown in the event of an overcurrent event or a slight overvoltage
event where the VOUT clamp is engaged over an extended period of time.
•
Deglitched fault reporting to filter the FAULT signal to ensure that the TPS25200-Q1 device does not provide
false-fault alerts.
•
•
Output discharge pulldown to ensue a load is off and not in an undefined operational state.
Reverse blocking when disabled to prevent back-drive from an active load which inadvertently causes
undetermined behavior in the application.
9.2 Functional Block Diagram
Current
Sense
CS
IN
OUT
UVLO
Charge
Pump
Current
Limit
Driver
OVLO
See Note A
EN
GND
Zener Diode
OTSD
Thermal
Sense
OVC
8-ms
Deglitch
FAULT
ILIM
A. 6.4-V typical clamp voltage
Copyright © 2015, Texas Instruments Incorporated
9
TPS25200-Q1
ZHCSDG1 –MARCH 2015
www.ti.com.cn
9.3 Feature Description
9.3.1 Enable
This logic enable input controls the power switch and device supply current. A logic-high input on the EN pin
enables the driver, control circuits, and powers the switch. The enable input is compatible with both TTL and
CMOS logic levels.
The EN pin can be tied to VIN with a pullup resistor, and is protected with an integrated Zener diode. Use a
sufficiently large (300 kΩ) pullup resistor to ensure that V(EN) is limited below the absolute maximum rating.
9.3.2 Thermal Sense
The TPS25200-Q1 device uses two independent thermal sensing circuits for self protection that monitor the
operating temperature of the power switch and disable operation if the temperature exceeds the values listed in
the Recommended Operating Conditions table. The TPS25200-Q1 device operates in constant-current mode
during an overcurrent condition, which increases the voltage drop across the power switch. The power
dissipation in the package is proportional to the voltage drop across the power switch, which increases the
junction temperature during an overcurrent condition. The first thermal sensor (OTSD1) turns off the power
switch when the die temperature exceeds 135°C (minimum) and the device is in current-limit protection.
Hysteresis is built into the thermal sensor, and the switch turns on after the device has cooled by approximately
20°C.
The TPS25200-Q1 device also has a second ambient thermal sensor (OTSD2). The thermal sensor turns off the
power switch when the die temperature exceeds 155°C (minimum) regardless of whether the power switch is in
current-limit protection and turns on the power switch after the device has cooled by approximately 20°C. The
TPS25200-Q1 device continues to cycle off and on until the fault is removed.
9.3.3 Overcurrent Protection
The TPS25200-Q1 device initiates thermal protection by thermal cycling during an extended overcurrent
condition. The device turns off when the junction temperature exceeds 135°C (typical) while in current limit. The
device remains off until the junction temperature cools by 20°C (typical) and then restarts. The TPS25200-Q1
device cycles on and off until the overload is removed (see Figure 26 and Figure 29).
The TPS25200-Q1 device responds to an overcurrent condition by limiting the output current to the IOS levels
shown in Figure 12. When an overcurrent condition is detected, the device maintains a constant output current
and the output voltage is reduced accordingly. During an overcurrent event, two possible overload conditions can
occur.
The first condition is when a short circuit or partial short circuit is present when the device is powered up or
enabled. The output voltage is held near zero potential with respect to ground and the TPS25200-Q1 device
ramps the output current to the IOS level. The TPS25200-Q1 device limits the current to the IOS level until the
overload condition is removed or the device begins a thermal cycle.
The second condition is when a short circuit, partial short circuit, or transient overload occurs while the device is
enabled and powered on. The device responds to the overcurrent condition within the time, tIOS (see Figure 12).
The current-sense amplifier is overdriven during this time and momentarily disables the internal current-limit
MOSFET. The current-sense amplifier recovers and limits the output current to the IOS level. Similar to the
previous case, the TPS25200-Q1 device limits the current to the IOS level until the overload condition is removed
or the device begins a thermal cycle.
9.3.4 FAULT Response
The FAULT open-drain output is asserted (active low) during an overcurrent, overtemperature, or overvoltage
condition. The TPS25200-Q1 device asserts the FAULT signal until the fault condition is removed and the device
resumes normal operation. The TPS25200-Q1 device is designed to eliminate false FAULT reporting by using an
internal delay deglitch circuit for overcurrent (8-ms typical) conditions without the requirement for external
circuitry. This design ensures that the FAULT signal is not accidentally asserted because of normal operation
such as starting into a heavy capacitive load. The deglitch circuitry delays entering and leaving current-limit
induced fault conditions.
10
Copyright © 2015, Texas Instruments Incorporated
TPS25200-Q1
www.ti.com.cn
ZHCSDG1 –MARCH 2015
Feature Description (continued)
The FAULT signal is not deglitched when the MOSFET is disabled because of an overtemperature condition but
is deglitched after the device has cooled and begins to turn on. This unidirectional deglitch prevents FAULT
oscillation during an overtemperature event.
The FAULT signal is not deglitched when the MOSFET is disabled into overvoltage-lockout (OVLO) or out of
OVLO. The TPS25200-Q1 device does not assert the FAULT during output-voltage clamp mode.
Connect the FAULT pin with a pullup resistor to a low-voltage I/O rail.
9.3.5 Output Discharge
A 480-Ω (typical) output discharge dissipates the stored charge and leakage current on the OUT pin when the
TPS25200-Q1 device is in undervoltage-lockout (UVLO) or OVLO or is disabled. The pulldown capability
decreases as VIN decreases (see Figure 8).
9.4 Device Functional Modes
The input voltage of the TPS25200-Q1 device can withstand up to 20 V. The input voltage, within a range of 0 V
to 20 V, can be divided to four modes which are described in the following sections.
VOUT (V)
Over Voltage Clamp
(OVC)
5.4 V
Turn Off
MOSFET
VIN (V)
UVLO (2.35 V)
OVLO (7.6 V)
20 V
Figure 13. Output vs Input Voltage
9.4.1 Undervoltage Lockout (UVLO)
The undervoltage lockout (UVLO) circuit disables the power switch until the input voltage reaches the UVLO turn-
on threshold. Built-in hysteresis prevents unwanted on and off cycling because of input voltage droop during turn
on.
9.4.2 Overcurrent Protection (OCP)
When 2.35 V < VIN < 5.4 V, the TPS25200-Q1 device is a traditional power switch that provides overcurrent
protection.
9.4.3 Overvoltage Clamp (OVC)
When 5.4 V < VIN < 7.6 V, the overvoltage-clamp (OVC) circuit clamps the output voltage to 5.4 V. Within this VIN
range, the overcurrent protection remains active. Fast transients can exceed the bandwidth of the internal gate-
control amplifier but such events will not risk damage to the load. In the unlikely event that a transient is fast
enough to exceed the amplifier bandwidth but not severe enough to exceed 7.6 V, it may cause momentary
droops in VOUT while the amplifier catches up and settles on VOUT = 5.4 V. For example, a 5-V to 7-V transient
with 0.5-V/ms slew rate and with 2 × 47 µF // 100-Ω load, some drooping occurs at VOUT
.
9.4.4 Overvoltage Lockout (OVLO)
When VIN exceeds 7.6 V, the overvoltage lockout (OVLO) circuit turns off the protected power switch.
Copyright © 2015, Texas Instruments Incorporated
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10 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information
The TPS25200-Q1 device is a 5-V eFuse with precision current-limit and overvoltage clamp. When a slave
device such as a mobile data-card device is hot plugged into a USB port as shown in Figure 14, an input
transient voltage could damage the slave device because of the cable inductance. Placing the TPS25200-Q1
device at the input of a mobile device as an overvoltage and overcurrent protector can help safeguard the slave
device. Input transients also occur when the current through the cable parasitic inductance changes abruptly
which can occur when the TPS25200-Q1 device turns off the internal MOSFET in response to an overvoltage or
overcurrent event. The TPS25200-Q1 device can withstand the transient without a bypass bulk capacitor, or
other external overvoltage protection components at the input side. The TPS25200-Q1 device also can be used
at the host side as a traditional power switch that is pin-to-pin compatible with the TPS2553 device.
Mobile Device
Rcable
Lcable
OUT
IN
TPS25200-Q1
GND
5-V
USB Port
Load
Figure 14. Hot Plug into 5-V USB Port With Parasitic Cable Resistance and Inductance
10.2 Typical Application
10.2.1 Overvoltage and Overcurrent Protector
VIO
300 kΩ
FAULT signal
TPS25200-Q1
0.1 µF
VIN
VOUT
6
1
IN
OUT
300 kΩ
ILIM
GND
5
2
3
4
EN
FAULT
22 µF
Thermal Pad
RILIM
Figure 15. Typical Application Schematic
Use the IOS level listed in the Electrical Characteristics table or the IOS value in the Equation 1 to select the value
of RILIM
.
12
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Typical Application (continued)
10.2.1.1 Design Requirements
For this design example, use the values listed in Table 1 as the input parameters.
Table 1. Design Parameters
DESIGN PARAMETERS
Normal input operation voltage
Output transient voltage
Minimum current limit
EXAMPLE VALUE
5 V
6.5 V
2.1 A
2.9 A
Maximum current limit
10.2.1.2 Detailed Design Procedure
10.2.1.2.1 Step by Step Design Produce
To begin the design process a few parameters must be decided upon. The designer needs to know the following:
•
•
•
•
Normal Input Operation Voltage
Output transient voltage
Minimum Current Limit
Maximum Current Limit
10.2.1.2.2 Input and Output Capacitance
Input and output capacitance improves the performance of the device; the actual capacitance should be
optimized for the particular application. For all applications, a ceramic bypass capacitor with a value of 0.1 µF or
greater is recommended between the IN and GND pins. This capacitor should be placed as close to the device
as possible for local noise decoupling.
When VIN ramp up exceeds 7.6 V, VOUT follows VIN until the TPS25200-Q1 device turns off the internal MOSFET
after t(OVLO_off_delay). Because t(OVLO_off_delay) largely depends on the VIN ramp rate, VOUT receives some peak
voltage. Increasing the output capacitance can lower the output peak voltage as shown in Figure 16.
10
8
6
4
2
0
0
10
20
30
40
50
Output Capacitor (µF)
C008
Figure 16. VOUT Peak Voltage vs COUT
(VIN Step From 5 V to 15 V With 1-V/us Ramp-Up Rate)
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10.2.1.2.3 Programming the Current-Limit Threshold
The overcurrent threshold is user programmable through an external resistor. The TPS25200-Q1 device uses an
internal regulation loop to provide a regulated voltage on the ILIM pin. The current-limit threshold is proportional
to the current sourced out of the ILIM pin. The recommended 1% resistor range for RILIM is 36 kΩ ≤ RILIM ≤ 1100
kΩ to ensure stability of the internal regulation loop. Many applications require that the minimum current limit is
above a certain current level or that the maximum current limit is below a certain current level. Therefore,
considering the tolerance of the overcurrent threshold is important when selecting a value for RILIM. The following
equations approximate the resulting overcurrent threshold for a given external resistor value, RILIM. See the
Electrical Characteristics table for specific current-limit settings. The traces routing the RILIM resistor to the
TPS25200-Q1 device should be as short as possible to reduce parasitic effects on the current-limit accuracy.
RILIM can be selected to provide a current-limit threshold that occurs either above a minimum load current or
below a maximum load current.
To design above a minimum current-limit threshold, find the intersection of RILIM and the minimum desired load
current on the IOS(min) curve. Select a value of RILIM below this value. Programming the current limit above a
minimum threshold is important to ensure start up into full load or heavy capacitive loads.
To design below a maximum current-limit threshold, find the intersection of RILIM and the maximum desired load
current on the IOS(max) curve. Select a value of RILIM above this value. Programming the current limit below a
maximum threshold is important to avoid current limiting the upstream power supplies which causes the input
voltage bus to droop.
Use Equation 1, Equation 2, and Equation 3, to calculate the minimum, nominal, and maximum current-limit
thresholds for IOS (respectively). For each equation, 36 kΩ ≤ RILIM ≤ 1100 kΩ.
97399 (V)
IOSmin (mA) =
IOSnom (mA) =
IOSmax (mA) =
- 30
1.015
RILIM
(kW)
(1)
(2)
(3)
98322 (V)
1.003
RILIM
(kW)
96754 (V)
0.985
+ 30
RILIM
(kW)
3500
3000
2500
2000
1500
1000
500
800
700
600
500
400
300
200
100
0
IOS(min)
IOS(typ)
IOS(max)
IOS(min)
IOS(typ)
IOS(max)
0
30 40 50 60 70 80 90 100 110 120 130 140 150
150 250 350 450 550 650 750 850 950 1050 1150
Current-Limit Resistor (k:)
Current-Limit Resistor (k:)
D016
D017
36 kΩ ≤ RILIM ≤ 150 KΩ
150 kΩ ≤ RILIM ≤ 1100 KΩ
Figure 17. Current-Limit Threshold vs RILIM
I
Figure 18. Current-Limit Threshold vs RILIM II
14
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ZHCSDG1 –MARCH 2015
10.2.1.2.4 Design Above a Minimum Current Limit
Some applications require that current limiting does not occur below a certain threshold. For this example,
assume that 2.1 A must be delivered to the load so that the minimum desired current-limit threshold is 2100 mA.
Use Equation 1 and Figure 17 to select a value for RILIM, with IOSmin = 2100 mA, as shown in Equation 4.
1
1
1.015
1.015
æ
ö
÷
÷
ø
97399
97399
æ
ö
RILIM (kW) = ç
=
= 43.22 kW
ç
÷
ç
è
IOS(min) + 30
2100 + 30
è
ø
(4)
Select the closest 1% resistor less than the calculated value: RILIM = 42.2 kΩ. This value sets the minimum
current-limit threshold at 2130 mA as shown in Equation 5.
97399 (V)
1.015
97399
42.2 ´ 1.01 1.015
IOSmin (mA) =
- 30 =
- 30 = 2130 mA
RILIM
(kW)
(
)
(5)
Use Equation 3, Figure 17, and the previously calculated value for RILIM to calculate the maximum resulting
current-limit threshold as shown in Equation 6.
96754
IOSmax (mA) =
+ 30 = 2479 mA
(42.2 ´ 0.99)0.985
(6)
The resulting current-limit threshold minimum is 2130 mA and maximum is 2479 mA with RILIM = 42.2kΩ ± 1%.
10.2.1.2.5 Design Below a Maximum Current Limit
Some applications require that current limiting must occur below a certain threshold. For this example, assume
that 2.9 A must be delivered to the load so that the minimum desired current-limit threshold is 2900 mA. Use
Equation 3 and Figure 18 to select RILIM
.
1
1
0.985
æ
ö
÷
÷
ø
96754
96754
0.985
æ
ö
IR
ILIM
(kW) = ç
=
= 35.57 kW
ç
÷
ç
è
IOS(max) - 30
2900 - 30
è
ø
(7)
Select the closest 1% resistor greater than the calculated value: RILIM = 36 kΩ. This value sets the maximum
current-limit threshold at 2894 mA as shown in Equation 8.
96754 (V)
0.985
96754
IOSmax (mA) =
+ 30 =
+ 30 = 2894 mA
0.985
RILIM
(kW)
36 ´ 0.99
(
)
(8)
Use Equation 1, Figure 18, and the previously calculated value for RILIM to calculate the minimum resulting
current-limit threshold as shown in Equation 9.
97399
IOSmin (mA) =
- 30 = 2508 mA
36 ´ 1.01 1.015
(
)
(9)
The resulting minimum current-limit threshold minimum is 2592 mA and maximum is 2894 mA with RILIM = 36 kΩ
± 1%.
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10.2.1.2.6 Power Dissipation and Junction Temperature
The low on-resistance of the internal N-channel MOSFET allows small surface-mount packages to pass large
currents. Estimating the power dissipation and junction temperature is good design practice. The following
analysis provides an approximation for calculating the junction temperature based on the power dissipation of the
package.
NOTE
Thermal analysis is strongly dependent on additional system-level factors. Such factors
include air flow, board layout, copper thickness and surface area, and proximity to other
devices dissipating power. Good thermal design practice must include all system-level
factors in addition to individual component analysis.
Begin by determining the rDS(on) value of the N-channel MOSFET relative to the input voltage (VIN) and operating
temperature. As an initial estimate, use the highest operating ambient temperature of interest and read rDS(on)
from Figure 4 in the Typical Characteristics section. When VIN is lower than V(OVC), the TPS25200-Q1 device is
an traditional power switch. Using this value, calculate the power dissipation with Equation 10.
2
PD = rDS(on) × IOUT
where
•
•
•
PD = Total power dissipation (W)
rDS(on) = Power switch on-resistance (Ω)
IOUT = Maximum current-limit threshold (A)
(10)
When VIN exceeds V(OVC), but is lower than V(OVLO), the TPS25200-Q1 clamp output is fixed to V(OVC). Use
Equation 11 to calculate the power dissipation.
PD = (VIN – V(OVC)) × IOUT
where
•
V(OVC) = Overvoltage clamp voltage (V)
(11)
This step calculates the total power dissipation of the N-channel MOSFET.
Finally, calculate the junction temperature using Equation 12.
TJ = PD × RθJA + TA
where
•
•
R
θJA = Thermal resistance (°C/W)
TA = Ambient temperature (°C)
(12)
Compare the calculated junction temperature with the initial estimate. If these two values are not within a few
degrees, repeat the calculation using the refined rDS(on) value from the previous calculation as the new estimate.
Two or three iterations are generally sufficient to achieve the desired result. The final junction temperature is
highly dependent on thermal resistance RθJA, and the thermal resistance is highly dependent on the individual
package and board layout.
16
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ZHCSDG1 –MARCH 2015
10.2.1.3 Application Curves
9
8
0.36
0.32
0.28
0.24
0.2
12
11
10
9
VOUT
V
IN
V IN
V OUT
FAULT
IOUT
7
8
6
7
5
6
5
4
0.16
0.12
0.08
0.04
0
4
3
3
2
2
1
1
0
±1
0
±2.0 ±1.5 ±1.0 ±0.5
0.0
Time (s)
0.5
1.0
1.5
2.0
-1
-0.04
C001
-80
-40
0
40
80
120
160
Time (s)
D019
Figure 19. VOUT vs VIN (0 V to 10 V)
Figure 20. VIN Step, 5 V to 8 V With 4.7 μF || 100 Ω
13
12
11
10
9
11
V
V
V IN
IN
10
9
V OUT
FAULT
OUT
8
7
8
6
7
5
6
4
5
3
4
2
3
2
1
1
0
0
-1
-1
-6
-4
-2
0
2
4
-2
0
2
4
6
8
Time (us)
C012
Time (s)
D018
Figure 22. 5-V to 10-V OVLO Response Time
Figure 21. Pulse Overvoltage With 100 Ω
5
4
3
2
1
0
5
5
5
EN
V
IN
4
3
2
1
0
-1
4
3
4
3
2
1
0
-1
V
OUT
2
1
EN
0
V
IN
V
OUT
±1
±1
±4
1
6
11
16
-1.2
-0.2
0.8
1.8
2.8
Time (ms)
Time (ms)
C013
C013
Figure 23. Turn On Delay and Rise Time, 150 µF || 2.5 Ω
Figure 24. Turn Off Delay and Fall Time, 150 µF || 2.5 Ω
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7
3.5
3
7
6
3.5
3
EN
FAULT
IOUT
EN
FAULT
IOUT
6
5
4
2.5
2
5
2.5
2
4
3
1.5
1
3
1.5
1
2
2
1
0.5
0
1
0.5
0
0
0
-1
-2
-0.5
18
-1
-20
-0.5
80
2
6
10
Time (ms)
14
0
20
40
60
Time (ms)
D009
D010
Figure 25. Enable into Output Short
Figure 26. 2.5-Ω to Output Short Transient Response
7
6
3.5
3
7
6
3.5
VOUT
FAULT
IOUT
3
5
2.5
2
5
2.5
2
4
4
3
1.5
1
3
1.5
1
2
2
1
0.5
0
1
0.5
0
VOUT
FAULT
IOUT
0
0
-1
-0.5
-1
-0.5
-70
-50
-30
-10
10
30
-20
0
20
40
60
80
Time (ms)
Time (ms)
D011
D012
Figure 27. Output Short to 2.5-Ω Load Recovery Response
Figure 28. No Load to Output Short-Transient Response
6
6
7
3.5
3
VOUT
FAULT
IOUT
VOUT
IOUT
6
5
5
4
5
2.5
2
4
3
2
1
0
-1
4
3
3
1.5
1
2
2
1
1
0.5
0
0
0
-1
-0.5
-1
-70
-50
-30
-10
10
30
-0.8
0
0.8
1.6
2.4
3.2
Time (ms)
Time (ms)
D013
D014
Figure 29. Output Short to No-Load Recovery Response
Figure 30. Hot-Short With 50 mΩ
18
Copyright © 2015, Texas Instruments Incorporated
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ZHCSDG1 –MARCH 2015
6
5
60
50
40
30
20
10
0
VOUT
IOUT
4
3
2
1
0
-1
-2
-10
-20
-4
-2
0
2
4
6
Time (Ps)
D015
Figure 31. 50-mΩ Hot-Short Response Time
11 Power Supply Recommendations
The TPS25200-Q1 device is designed for 2.7 V < VIN < 5 V (typical) voltage rails. Although a VOUT clamp is
provided, it is not intended to regulate VOUT at approximately 5.4 V with 6 V < VIN < 7 V. This clamp is a
protection feature only.
12 Layout
12.1 Layout Guidelines
•
For all applications, a 0.1-µF or greater ceramic bypass capacitor between the IN and GND pins is
recommended as close to the device as possible for local noise decoupling.
•
•
For output capacitance, see Figure 16. A low-ESR ceramic capacitor is recommended.
The traces routing the RILIM resistor to the device should be as short as possible to reduce parasitic effects on
the current-limit accuracy.
•
The thermal pad should be directly connected to PCB ground plane using wide and short copper trace.
12.2 Layout Example
VIA to Power Ground Plane
FAULT
3
4
5
6
EN
ILIM
2
1
IN
High Frequency
Bypass Capacitor
OUT
Power Ground
VI/O
Figure 32. TPS25200-Q1 Board Layout
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www.ti.com.cn
13 器件和文档支持
13.1 文档支持
13.1.1 相关文档ꢀ
相关文档如下：
TPS2553，《精度可调节限流配电开关》，SLVS841
13.2 商标
All trademarks are the property of their respective owners.
13.3 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
13.4 术语表
SLYZ022 — TI 术语表。
这份术语表列出并解释术语、首字母缩略词和定义。
14 机械封装和可订购信息
以下页中包括机械封装和可订购信息。 这些信息是针对指定器件可提供的最新数据。 这些数据会在无通知且不对
本文档进行修订的情况下发生改变。 欲获得该数据表的浏览器版本，请查阅左侧的导航栏。
20
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Copyright © 2015, 德州仪器半导体技术（上海）有限公司
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS25200QDRVRQ1
TPS25200QDRVTQ1
ACTIVE
ACTIVE
WSON
WSON
DRV
DRV
6
6
3000 RoHS & Green
250 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 125
-40 to 125
SIL
SIL
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Addendum-Page 2
GENERIC PACKAGE VIEW
DRV 6
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4206925/F
PACKAGE OUTLINE
DRV0006A
WSON - 0.8 mm max height
SCALE 5.500
PLASTIC SMALL OUTLINE - NO LEAD
2.1
1.9
A
B
PIN 1 INDEX AREA
2.1
1.9
0.8
0.7
C
SEATING PLANE
0.08 C
(0.2) TYP
0.05
0.00
1
0.1
EXPOSED
THERMAL PAD
3
4
6
2X
7
1.3
1.6 0.1
1
4X 0.65
0.35
0.25
6X
PIN 1 ID
(OPTIONAL)
0.3
0.2
6X
0.1
C A
C
B
0.05
4222173/B 04/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
DRV0006A
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
6X (0.45)
6X (0.3)
(1)
1
7
6
SYMM
(1.6)
(1.1)
4X (0.65)
4
3
SYMM
(1.95)
(R0.05) TYP
(
0.2) VIA
TYP
LAND PATTERN EXAMPLE
SCALE:25X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4222173/B 04/2018
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If some or all are implemented, recommended via locations are shown.
www.ti.com
EXAMPLE STENCIL DESIGN
DRV0006A
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
SYMM
7
6X (0.45)
METAL
1
6
6X (0.3)
(0.45)
SYMM
4X (0.65)
(0.7)
4
3
(R0.05) TYP
(1)
(1.95)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD #7
88% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:30X
4222173/B 04/2018
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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邮寄地址：上海市浦东新区世纪大道 1568 号中建大厦 32 楼，邮政编码：200122
Copyright © 2020 德州仪器半导体技术（上海）有限公司
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