TPS2550DBV [TI]
ADJUSTABLE CURRENT-LIMITED POWER-DISTRIBUTION SWITCHES; 可调电流限制的配电开关
| 型号： | TPS2550DBV |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | ADJUSTABLE CURRENT-LIMITED POWER-DISTRIBUTION SWITCHES |
| 文件： | 总28页 (文件大小：1948K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPS2550
TPS2551
www.ti.com
SLVS736–FEBRUARY 2008
ADJUSTABLE CURRENT-LIMITED POWER-DISTRIBUTION SWITCHES
1
FEATURES
DESCRIPTION
•
•
•
•
•
•
•
•
•
•
Adjustable Current-Limit, 100 mA–1100 mA
Fast Overcurrent Response - 2 µS Typical
85-mΩ High-Side MOSFET (DBV Package)
Reverse Input-Output Voltage Protection
Operating Range: 2.5 V to 6.5 V
The TPS2550/51 power-distribution switch is
intended for applications where heavy capacitive
loads and short-circuits are likely to be encountered,
incorporating a 100-mΩ, N-channel MOSFET in a
single package. The current-limit threshold is user
adjustable between 100 mA and 1.1 A via an external
resistor. The power-switch rise and fall times are
controlled to minimize current surges during
switching.
Deglitched Fault Report
1-µA Maximum Standby Supply Current
Ambient Temperature Range: –40°C to 85°C
Built-in Soft-Start
The device limits the output current to a desired level
by switching into a constant-current mode when the
output load exceeds the current-limit threshold or a
short is present. An internal reverse-voltage detection
comparator disables the power-switch in the event
that the output voltage is driven higher than the input
to protect devices on the input side of the switch. The
FAULT logic output asserts low during both
overcurrent and reverse-voltage conditions.
15 kV ESD Protection (with external
capacitance)
APPLICATIONS
•
•
•
•
•
USB Ports/Hubs
Cell phones
Laptops
Heavy Capacitive Loads
Reverse-Voltage Protection
TPS2550/51
USB Data
0.1 mF
5 V USB
INPUT
USB
Port
IN
OUT
TPS2550/TPS2551
DRV PACKAGE
(TOP VIEW)
TPS2550/TPS2551
DBV PACKAGE
(TOP VIEW)
RFAULT
100 kW
120 mF *
1
2
3
6
5
4
IN
OUT
ILIM
IN
OUT
1
2
3
6
5
4
ILIM
GND
EN
GND
EN
FAULT
EN
ILIM
FAULT Signal
FAULT
FAULT
RILIM
15 kW
EN = Active Low for the TPS2550
EN = Active High for the TPS2551
Control Signal
GND
Power Pad
* USB Requirement that downstream-facing ports
are bypassed with at least 120 mF per hub
Figure 1. Typical Application as USB Power Switch
GENERAL SWITCH CATALOG
33 mW, Single
80 mW, Single
80 mW, Triple
80 mW, Dual
80 mW, Dual
80 mW, Quad
80 mW, Quad
TPS201xA 0.2 A to 2 A
0.2 A to 2 A
0.2 A to 2 A
TPS2014
TPS2015
TPS2041B 500 mA
TPS2051B 500 mA
TPS2045A 250 mA
TPS2049 100 mA
TPS2055A 250 mA
TPS2061
TPS2065
TPS2068
TPS2069
600 mA
1 A
TPS202x
TPS203x
TPS2042B 500 mA
TPS2052B 500 mA
TPS2046B 250 mA
TPS2080 500 mA
TPS2081 500 mA
TPS2082 500 mA
TPS2090 250 mA
TPS2091 250 mA
TPS2092 250 mA
TPS2043B 500 mA
TPS2053B 500 mA
TPS2047B 250 mA
TPS2057A 250 mA
TPS2056
TPS2062
TPS2066
TPS2060
TPS2064
250 mA
1 A
1 A
1.5 A
1.5 A
TPS2044B 500 mA
TPS2054B 500 mA
TPS2048A 250 mA
TPS2085 500 mA
TPS2086 500 mA
TPS2087 500 mA
TPS2095 250 mA
TPS2096 250 mA
TPS2097 250 mA
1 A
1 A
1.5 A
1.5 A
TPS2063
TPS2067
1 A
1 A
TPS2058
250 mA
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2008, Texas Instruments Incorporated
TPS2550
TPS2551
www.ti.com
SLVS736–FEBRUARY 2008
This device contains circuits to protect its inputs and outputs against damage due to high static voltages or electrostatic fields.
These circuits have been qualified to protect this device against electrostatic discharges (ESD) of up to 2 kV according to
MIL-STD-883C, Method 3015; however, it is advised that precautions be taken to avoid application of any voltage higher than
maximum-rated voltages to these high-impedance circuits. During storage or handling the device leads should be shorted together
or the device should be placed in conductive foam. In a circuit, unused inputs should always be connected to an appropriate logic
voltage level, preferably either VCC or ground. Specific guidelines for handling devices of this type are contained in the publication
Guidelines for Handling Electrostatic-Discharge-Sensitive (ESDS) Devices and Assemblies available from Texas Instruments.
AVAILABLE OPTIONS AND ORDERING INFORMATION
(1)
DEVICE
AMBIENT
TEMPERATURE
ENABLE
SON
SOT23(1)
(DBV)
RECOMMENDED MAXIMUM
CONTINUOUS LOAD CURRENT
(DRV)
TPS2550
TPS2551
Active low
Active high
TPS2550DRV
TPS2551DRV
TPS2550DBV
TPS2551DBV
1.1 A
1.1 A
–40°C to 85°C
(1) Add an R suffix to the device type for tape and reel.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted(1)
(2)
VALUE
–0.3 to 7
UNIT
V
Voltage range on IN, OUT, EN or EN, ILIM, FAULT
Voltage range from IN to OUT
–7 to 7
V
IOUT Continuous output current
Internally limited
See "Dissipation Rating
Table"
Continuous total power dissipation
FAULT sink current
ILIM source current
25
mA
mA
kV
V
1
2
HBM
ESD
CDM
500
TJ
TSgt Storage temperature
Lead temperature 1,6 mm (1/16-inch) from case for 10 seconds
Maximum junction temperature
–40 to 150
–65 to 150
300
°C
°C
°C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Voltages are referenced to GND unless otherwise noted.
DISSIPATION RATING TABLE
BOARD PACKAGE
THERMAL
RESISTANCE
θJA
THERMAL
RESISTANCE
θJC
T
A ≤ 25°C
DERATING
FACTOR ABOVE
TA = 25°C
TA = 70°C
POWER
RATING
TA = 85°C
POWER
RATING
POWER
RATING
Low-K(1)
High-K(2)
Low-K(1)
High-K(2)
DBV
DBV
DRV
DRV
350°C/W
160°C/W
140°C/W
75°C/W
55°C/W
55°C/W
20°C/W
20°C/W
285 mW
625 mW
715 mW
1330 mW
2.85 mW/°C
6.25 mW/°C
7.1 mW/°C
13.3 mW/°C
155 mW
340 mW
395 mW
730 mW
114 mW
250 mW
285 mW
530 mW
(1) The JEDEC low-K (1s) board used to derive this data was a 3in × 3in, two-layer board with 2-ounce copper traces on top of the board.
(2) The JEDEC high-K (2s2p) board used to derive this data was a 3in × 3in, multilayer board with 1-ounce internal power and ground
planes and 2-ounce copper traces on top and bottom of the board.
2
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SLVS736–FEBRUARY 2008
RECOMMENDED OPERATING CONDITIONS
MIN
2.5
0
MAX
6.5
UNIT
VIN
Input voltage, IN
V
VEN
TPS2550
TPS2551
6.5
Enable voltage
V
V/EN
IOUT
RILIM
I/FAULT
0
6.5
Continuous output current, OUT
0
1.1
A
Current-limit set resistor from ILIM to GND
FAULT sink current
14.3
0
80.6
10
kΩ
mA
DRV
DBV
–40
–40
105
125
Operating virtual junction
temperature
TJ
°C
ELECTRICAL CHARACTERISTICS
over recommended operating junction temperature range, 2.5 V ≤ VIN ≤ 6.5 V, RILIM = 14.3 kΩ, V/EN = 0 V, or VEN = 5.0 V
(unless otherwise noted)
PARAMETER
TEST CONDITIONS(1)
MIN
TYP
85
MAX
UNIT
POWER SWITCH
DBV package, TJ = 25 °C
95
135
115
145
1.5
DBV package, –40 °C ≤TJ ≤125 °C
DRV package, TJ = 25 °C
DRV package, –40 °C ≤TJ ≤105 °C
VIN = 6.5 V
rDS(on)
Static drain-source on-state resistance
mΩ
100
1.0
tr
tf
Rise time, output
Fall time, output
VIN = 2.5 V
VIN = 6.5 V
VIN = 2.5 V
0.65
1.0
CL = 1 µF, RL = 100 Ω,
(see Figure 2)
ms
0.2
0.2
0.5
0.5
ENABLE INPUT EN OR EN
VIH
VIL
IEN
ton
High-level input voltage
1.1
V
Low-level input voltage
Input current
0.66
0.5
3
VEN = 0 V or 6.5 V, V/EN = 0 V or 6.5 V
–0.5
µA
ms
ms
Turnon time
CL = 1 µF, RL = 100 Ω, (see Figure 2)
toff
Turnoff time
3
CURRENT LIMIT
RILIM = 80.6 kΩ
RILIM = 38.3 kΩ
RILIM = 15 kΩ
RILIM = 80.6 kΩ
RILIM = 38.3 kΩ
RILIM = 15 kΩ
110
300
215
500
300
650
IOS
Short-circuit current, OUT connected to GND
1050 1400
1650
340
mA
290
620
315
665
IOC
Current-limit threshold (Maximum DC output current IOUT delivered to load)
705
1550 1650
2
1750
tIOS
Response time to short circuit
VIN = 5.0 V (see Figure 3)
µs
REVERSE-VOLTAGE PROTECTION
Reverse-voltage comparator trip point
(VOUT – VIN
95
3
135
5
190
7
mV
ms
)
Time from reverse-voltage condition to
MOSFET turn off
VIN = 5.0 V
SUPPLY CURRENT
VIN = 6.5 V, No load on OUT, VEN = 6.5 V or VEN = 0 V, 14.3 kΩ
≤ RILIM ≤ 80.6 kΩ
IIN_off
Supply current, low-level output
0.1
1
µA
RILIM = 15 kΩ
150
130
1
µA
µA
µA
VIN = 6.5 V, No load on OUT, VEN = 0 V or
VEN = 6.5 V
IIN_on
IREV
Supply current, high-level output
Reverse leakage current
RILIM = 80.6 kΩ
VOUT = 6.5 V, VIN = 0 V
TJ = 25 °C
0.01
(1) Pulse-testing techniques maintain junction temperature close to ambient temperature; thermal effects must be taken into account
separately.
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ELECTRICAL CHARACTERISTICS (continued)
over recommended operating junction temperature range, 2.5 V ≤ VIN ≤ 6.5 V, RILIM = 14.3 kΩ, V/EN = 0 V, or VEN = 5.0 V
(unless otherwise noted)
PARAMETER
UNDERVOLTAGE LOCKOUT
TEST CONDITIONS(1)
MIN
TYP
MAX
UNIT
VUVLO
Low-level input voltage, IN
Hysteresis, IN
VIN rising
2.35
25
2.45
V
TJ = 25 °C
mV
FAULT FLAG
VOL Output low voltage, FAULT
I/FAULT = 1 mA
V/FAULT = 6.5 V
180
1
mV
µA
ms
Off-state leakage
FAULT assertion or de-assertion due to overcurrent condition
5
2
7.5
4
10
FAULT deglitch
FAULT assertion or de-assertion due to reverse-voltage
condition
6
ms
THERMAL SHUTDOWN
Thermal shutdown threshold
155
135
°C
°C
°C
Thermal shutdown threshold in current-limit
Hysteresis
15
4
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SLVS736–FEBRUARY 2008
DEVICE INFORMATION
Terminal Functions
I/O
TERMINAL
DESCRIPTION
NAME
TPS2550DBV TPS2551DBV TPS2550DRV TPS2551DRV
EN
EN
3
–
2
–
3
2
4
–
5
–
4
5
I
I
Enable input, logic low turns on power switch
Enable input, logic high turns on power switch
GND
Ground connection; should be connected
externally to POWER PAD
IN
1
4
1
4
6
3
6
3
I
Input voltage; connect a 0.1 µF or greater
ceramic capacitor from IN to GND as close to the
IC as possible.
FAULT
O
Active-low open-drain output, asserted during
overcurrent, overtemperature, or reverse-voltage
conditions.
OUT
ILIM
6
5
6
5
1
2
1
2
O
I
Power-switch output
External resistor used to set current-limit
threshold; recommended 14.3 kΩ ≤ RILIM ≤ 80.6
kΩ.
POWER
PAD
–
–
PAD
PAD
Internally connected to GND; used to heat-sink
the part to the circuit board traces. Should be
connected to GND pin.
FUNCTIONAL BLOCK DIAGRAM
-
Reverse
Voltage
Comparator
+
IN
CS
OUT
Current
Sense
Charge
Pump
Current
Limit
Driver
EN
FAULT
UVLO
GND
ILIM
Thermal
Sense
8-ms Deglitch
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SLVS736–FEBRUARY 2008
PARAMETER MEASUREMENT INFORMATION
OUT
t
f
t
r
R
L
C
L
90%
10%
90%
10%
V
OUT
TEST CIRCUIT
V
EN
50%
90%
50%
50%
50%
V
EN
t
off
t
off
t
on
t
on
90%
V
V
OUT
OUT
10%
10%
VOLTAGE WAVEFORMS
Figure 2. Test Circuit and Voltage Waveforms
I
OS
I
OUT
t
IOS
Figure 3. Response Time to Short-Circuit Waveform
DECREASING
LOAD
RESISTANCE
VOUT
DECREASING
LOAD
RESISTANCE
IOUT
IOS
IOC
Figure 4. Output Voltage vs. Current-Limit Threshold
6
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SLVS736–FEBRUARY 2008
TYPICAL CHARACTERISTICS
Figure 5. Turnon Delay and Rise Time
Figure 6. Turnoff Delay and Fall Time
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SLVS736–FEBRUARY 2008
TYPICAL CHARACTERISTICS (continued)
Figure 7. Device Enabled into Short-Circuit
Figure 8. Full-Load to Short-Circuit Transient Response
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SLVS736–FEBRUARY 2008
TYPICAL CHARACTERISTICS (continued)
Figure 9. Short-Circuit to Full-Load Recovery Response
Figure 10. No-Load to Short-Circuit Transient Response
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TYPICAL CHARACTERISTICS (continued)
Figure 11. Short-Circuit to No-Load Recovery Response
Figure 12. No Load to 1Ω Transient Response
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TYPICAL CHARACTERISTICS (continued)
Figure 13. 1Ω to No Load Transient Response
Figure 14. Reverse-Voltage Protection Response
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SLVS736–FEBRUARY 2008
TYPICAL CHARACTERISTICS (continued)
Figure 15. Reverse-Voltage Protection Recovery
2.40
2.39
2.38
2.37
2.36
UVLO Rising
2.35
2.34
UVLO Falling
2.33
2.32
2.31
2.30
-50
0
50
100
150
T
- Junction Temperature - °C
J
Figure 16. UVLO – Undervoltage Lockout – V
12
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SLVS736–FEBRUARY 2008
TYPICAL CHARACTERISTICS (continued)
0.50
0.45
V
= 6.5 V
IN
V
= 5 V
0.40
0.35
0.30
IN
V
= 3.3 V
IN
0.25
0.20
0.15
0.10
V
= 2.5 V
IN
0.05
0
-50
0
50
- Junction Temperature - °C
100
150
T
J
Figure 17. IIN – Supply Current, Output Disabled – µA
150
135
120
R
= 20 kW
ILIM
V
= 6.5 V
IN
V
= 5 V
IN
105
90
V
V
= 3.3 V
= 2.5 V
IN
75
IN
60
45
30
15
0
-50
0
50
100
150
T
- Junction Temperature - °C
J
Figure 18. IIN – Supply Current, Output Enabled – µA
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TYPICAL CHARACTERISTICS (continued)
20
18
V
T
= 5 V,
IN
= 25°C
A
16
14
12
10
8
6
4
2
0
0
1.5
3
4.5
6
Peak Current - A
Figure 19. Current Limit Response – µs
150
125
100
75
DRV Package
DBV Package
50
25
0
-50
0
50
100
150
T
- Junction Temperature - °C
J
Figure 20. MOSFET rDS(on) Vs. Junction Temperature
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SLVS736–FEBRUARY 2008
DETAILED DESCRIPTION
OVERVIEW
The TPS2550/51 are current-limited, power distribution switches using N-channel MOSFETs for applications
where short-circuits or heavy capacitive loads will be encountered. These devices allow the user to program the
current-limit threshold between 100 mA and 1.1 A via an external resistor. Additional device shutdown features
include overtemperature protection and reverse-voltage protection. The device incorporates an internal charge
pump and gate drive circuitry necessary to drive the N-channel MOSFET. The charge pump supplies power to
the driver circuit and provides the necessary voltage to pull the gate of the MOSFET above the source. The
charge pump operates from input voltages as low as 2.5 V and requires little supply current. The driver controls
the gate voltage of the power switch. The driver incorporates circuitry that controls the rise and fall times of the
output voltage to limit large current and voltage surges and provide built-in soft-start functionality.
OVERCURRENT
The TPS2550/51 responds to an overcurrent condition by limiting its output current to the IOC and IOS levels
shown in Figure 21. Three response profiles are possible depending on the loading conditions and are
summarized in Figure 4.
One response profile occurs if the TPS2550/51 is enabled into a short-circuit. The output voltage is held near
zero potential with respect to ground and the TPS2550/51 ramps the output current to IOS (see Figure 7).
A second response profile occurs if a short is applied to the output after the TPS2550/51 is enabled. The device
responds to the overcurrent condition within time tIOS (see Figure 3). The current-sense amplifier is over-driven
during this time and momentarily disables the internal current-limit MOSFET. The current-sense amplifier
gradually recovers and limits the output current to IOS
.
A third response profile occurs if the load current gradually increases. The device first limits the load current to
IOC. If the load demands a current greater than IOC, the TPS2550/51 folds back the current to IOS and the output
voltage decreases to IOS x RLOAD for a resistive load, which is shown in Figure 4.
The TPS2550/51 thermal cycles if an overload condition is present long enough to activate thermal limiting in any
of the above cases. The device turns off when the junction temperature exceeds 135°C (typ). The device
remains off until the junction temperature cools 15°C (typ) and then restarts. The TPS2550/51 cycles on/off until
the overload is removed (see Figure 9 and Figure 11) .
REVERSE-VOLTAGE PROTECTION
The reverse-voltage protection feature turns off the N-channel MOSFET whenever the output voltage exceeds
the input voltage by 135 mV (typical) for 4-ms. This prevents damage to devices on the input side of the
TPS2550/51 by preventing significant current from sinking into the input capacitance. The N-channel MOSFET is
allowed to turn-on once the output voltage goes below the input voltage for the same 4-ms deglitch time. The
reverse-voltage comparator also asserts the FAULT output (active-low) after 4-ms.
FAULT RESPONSE
The FAULT open-drain output is asserted (active low) during an overcurrent, overtemperature or reverse-voltage
condition. The output remains asserted until the fault condition is removed. The TPS2550/51 is designed to
eliminate false FAULT reporting by using an internal delay "deglitch" circuit for overcurrent (7.5-ms) and
reverse-voltage (4-ms) conditions without the need for external circuitry. This ensures that FAULT is not
accidentally asserted due to normal operation such as starting into a heavy capacitive load. The deglitch circuitry
delays entering and leaving fault conditions. Overtemperature conditions are not deglitched and assert the
FAULT signal immediately.
UNDERVOLTAGE LOCKOUT (UVLO)
The undervoltage lockout (UVLO) circuit disables the power switch until the input voltage reaches the UVLO
turn-on threshold. Built-in hysteresis prevents unwanted on/off cycling due to input voltage drop from large
current surges.
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SLVS736–FEBRUARY 2008
ENABLE (EN OR EN)
The logic enable controls the power switch, bias for the charge pump, driver, and other circuits to reduce the
supply current. The supply current is reduced to less than 1-µA when a logic high is present on EN or when a
logic low is present on EN. A logic low input on EN or a logic high input on EN enables the driver, control circuits,
and power switch. The enable input is compatible with both TTL and CMOS logic levels.
THERMAL SENSE
The TPS2550/51 protects itself with two independent thermal sensing circuits that monitor the operating
temperature of the power-switch and disables operation if the temperature exceeds recommended operating
conditions. The device operates in constant-current mode during an overcurrent conditions, which increases the
voltage drop across power-switch. The power dissipation in the package is proportional to the voltage drop
across the power-switch, so the junction temperature rises during an overcurrent condition. The first thermal
sensor turns off the power-switch when the die temperature exceeds 135°C and the part is in current limit. The
second thermal sensor turns off the power-switch when the die temperature exceeds 155°C regardless of
whether the power-switch is in current limit. Hysteresis is built into both thermal sensors, and the switch turns on
after the device has cooled approximately 15 °C. The switch continues to cycle off and on until the fault is
removed. The open-drain false reporting output FAULT is asserted (active low) immediately during an
overtemperature shutdown condition.
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SLVS736–FEBRUARY 2008
APPLICATION INFORMATION
INPUT AND OUTPUT CAPACITANCE
Input and output capacitance improve the performance of the device; the actual capacitance should be optimized
for the particular application. For all applications, a 0.01 µF to 0.1µF ceramic bypass capacitor between IN and
GND is recommended as close to the device as possible for local noise de-coupling. This precaution reduces
ringing on the input due to power-supply transients. Additional input capacitance may be needed on the input to
reduce voltage overshoot from exceeding the absolute maximum voltage of the device during heavy transients.
This is especially important during bench testing when long, inductive cables are used to connect the evaluation
board to the bench power-supply.
Placing a high-value electrolytic capacitor on the output pin is recommended when the large transient currents
are expected on the output. Additionally, bypassing the output with a 0.01 µF to 0.1 µF ceramic capacitor
improves the immunity of the device to short-circuit transients.
PROGRAMMING THE CURRENT-LIMIT THRESHOLD
The overcurrent threshold is user programmable via an external resistor. Many applications require that the
minimum current-limit is above a certain current level or that the maximum current-limit is below a certain current
level, so it is important to consider the tolerance of the overcurrent threshold when selecting a value for RILIM
.
The following equations and Figure 21 can be used to calculate the resulting overcurrent threshold for a given
external resistor value (RILIM). Figure 21 includes current-limit tolerance due to variations caused by temperature
and process. The traces routing the RILIM resistor to the TPS2550/51should be as short as possible to reduce
parasitic effects on the current-limit accuracy.
There are two important current-limit thresholds for the device and are related by Figure 4. The first threshold is
the short-circuit current threshold IOS. IOS is the current delivered to the load if the part is enabled into a
short-circuit or a short-circuit is applied during normal operation. The second threshold is the overcurrent
threshold IOC. IOC is the peak DC current that can be delivered to the load before the device begins to limit
current. IOC is important if ramped loads or slow transients are common to the application. It is important to
consider both IOS and IOC when choosing RILIM. RILIM can be selected to provide a current-limit threshold that
occurs 1) above a minimum load current or 2) below a maximum load current.
To design above a minimum current-limit threshold, find the intersection of RILIM and the maximum desired load
current on the IOS(min) curve and choose a value of RILIM below this value. Programming the current-limit above a
minimum threshold is important to ensure start-up into full-load or heavy capacative loads. The resulting
maximum DC load current is the intersection of the selected value of RILIM and the IOC(max) curve.
To design below a maximum DC current level, find the intersection of RILIM and the maximum desired load
current on the IOC(max) curve and choose a value of RILIM above this value. Programming the current-limit below a
maximum threshold is important to avoid current-limiting upstream power supplies causing the input voltage bus
to droop. The resulting minimum short-circuit current is the intersection of the selected value of RILIM and the
IOS(min) curve.
Overcurrent Threshold Equations (IOC):
•
•
•
IOC(max) (mA) = (24500 V) / (RILIM kΩ) 0.975
IOC(typ) (mA) = (23800 V) / (RILIM kΩ) 0.985
IOC(min) (mA) = (23100 V) / (RILIM kΩ) 0.996
Short-Circuit Current Equations (IOS):
•
•
•
IOS(max) (mA) = (25500 V) / (RILIM kΩ) 1.013
IOS(typ) (mA) = (28700 V) / (RILIM kΩ) 1.114
IOS(min) (mA) = (39700 V) / (RILIM kΩ) 1.342
where 14.3 kΩ ≤ RILIM ≤ 80.6 kΩ. IOS(typ) and IOS(max) are not plotted to improve graph clarity.
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1800
1700
1600
1500
1400
I
OC(max)
1300
1200
1100
1000
I
OC(typ)
I
900
800
700
OC(min)
600
500
400
300
200
I
OS(min)
100
0
15
20
25
30
35
40
45
50
- kW
55
60
65
70
75
80
R
ILIM
Figure 21. Current-Limit Threshold Vs.RILIM
APPLICATION 1: DESIGNING ABOVE A MINIMUM CURRENT-LIMIT
Some applications require that current-limiting cannot occur below a certain threshold. For this example, assume
that 1 A must be delivered to the load so that the minimum desired current-limit threshold is 1000 mA. Use the
IOS equations and Figure 21 to select RILIM
.
•
•
•
•
IOS(min) (mA) = 1000 mA
IOS(min) (mA) = (39700 V) / (RILIM (kΩ)) 1.342
RILIM (kΩ) = [(39700 V) / (IOS(min) (mA))] 1/1.342
RILIM = 15.54 kΩ
Select the closest 1% resistor less than the calculated value: RILIM = 15.4 kΩ. This sets the minimum current-limit
threshold at 1 A . Use the IOC equations, Figure 21, and the previously calculated value for RILIM to calculate the
maximum resulting current-limit threshold.
•
•
•
•
RILIM = 15.4 kΩ
IOC(max) (mA) = (24500 V) / (RILIM (kΩ)) 0.975
IOC(max) (mA) = (24500 V) / (15 (kΩ)) 0.975
IOC(max) = 1703 mA
The resulting maximum current-limit theshold is 1.7 A with a 15.4 kΩ resistor.
APPLICATION 2: DESIGNING BELOW A MAXIMUM CURRENT-LIMIT
Some applications require that current-limiting must occur below a certain threshold. For this example, assume
that the desired upper current-limit threshold must be below 1.25 A to protect an up-stream power supply. Use
the IOC equations and Figure 21 to select RILIM
.
•
•
•
•
IOC(max) (mA) = 1250 mA
IOC(max) (mA) = (24500 V) / (RILIM (kΩ)) 0.975
RILIM (kΩ) = [(24500 V) / (IOC(max) (mA))] 1/0.975
RILIM = 21.15 kΩ
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Select the closest 1% resistor greater than the calculated value: RILIM = 21.5 kΩ. This sets the maximum
current-limit threshold at 1.25 A . Use the IOS equations, Figure 21, and the previously calculated value for RILIM
to calculate the minimum resulting current-limit threshold.
•
•
•
•
RILIM = 21.5 kΩ
IOS(min) (mA) = (39700 V) / (RILIM (kΩ)) 1.342
IOS(min) (mA) = (39700 V) / (21.5 (kΩ)) 1.342
IOS(min) = 647 mA
The resulting minimum current-limit threshold is 647 mA with a 21.5 kΩ resistor.
POWER DISSIPATION AND JUNCTION TEMPERATURE
The low on-resistance of the N-channel MOSFET allows small surface-mount packages to pass large currents. It
is good design practice to estimate power dissipation and junction temperature. The below analysis gives an
approximation for calculating junction temperature based on the power dissipation in the package. However, it is
important to note that thermal analysis is strongly dependent on additional system level factors. Such factors
include air flow, board layout, copper thickness and surface area, and proximity to other devices dissipating
power. Good thermal design practice must include all system level factors in addition to individual component
analysis.
Begin by determining the rDS(on) of the N-channel MOSFET relative to the input voltage and operating
temperature. As an initial estimate, use the highest operating ambient temperature of interest and read rDS(on)
from the typical characteristics graph. Using this value, the power dissipation can be calculated by:
2
PD = rDS(on) × IOUT
Where:
PD = Total power dissipation (W)
rDS(on) = Power switch on-resistance (Ω)
IOUT = Maximum current-limit threshold (A)
This step calculates the total power dissipation of the N-channel MOSFET.
Finally, calculate the junction temperature:
TJ = PD × RΘJA + TA
Where:
TA = Ambient temperature (°C)
RΘJA = Thermal resistance (°C/W)
PD = Total power dissipation (W)
Compare the calculated junction temperature with the initial estimate. If they are not within a few degrees, repeat
the calculation using the "refined" rDS(on) from the previous calculation as the new estimate. Two or three
iterations are generally sufficient to achieve the desired result. The final junction temperature is highly dependent
on thermal resistance RθJA, and thermal resistance is highly dependent on the individual package and board
layout. The "Dissipating Rating Table" at the begginng of this document provides example thermal resistances for
specific packages and board layouts.
UNIVERSAL SERIAL BUS (USB) POWER-DISTRIBUTION REQUIREMENTS
One application for this device is for current-limiting in universal serial bus (USB) applications. The original USB
interface was a 12-Mb/s or 1.5-Mb/s, multiplexed serial bus designed for low-to-medium bandwidth PC
peripherals (e.g., keyboards, printers, scanners, and mice). As the demand for more bandwidth increased, the
USB 2.0 standard was introduced increasing the maximum data rate to 480-Mb/s. The four-wire USB interface is
conceived for dynamic attach-detach (hot plug-unplug) of peripherals. Two lines are provided for differential data,
and two lines are provided for 5-V power distribution.
USB data is a 3.3-V level signal, but power is distributed at 5 V to allow for voltage drops in cases where power
is distributed through more than one hub across long cables. Each function must provide its own regulated 3.3 V
from the 5-V input or its own internal power supply. The USB specification classifies two different classes of
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devices depending on its maximum current draw. A device classified as low-power can draw up to 100 mA as
defined by the standard. A device classified as high-power can draw up to 500 mA. It is important that the
minimum current-limit threshold of the current-limiting power-switch exceed the maximum current-limit draw of
the intended application. The latest USB standard should always be referenced when considering the
current-limit threshold
The USB specification defines two types of devices as hubs and functions. A USB hub is a device that contains
multiple ports for different USB devices to connect and can be self-powered (SPH) or bus-powered (BPH). A
function is a USB device that is able to transmit or receive data or control information over the bus. A USB
function can be embedded in a USB hub. A USB function can be one of three types included in the list below.
•
•
•
Low-power, bus-powered function
High-power, bus-powered function
Self-powered function
SPHs and BPHs distribute data and power to downstream functions. The TPS2550/51 has higher current
capability than required for a single USB port allowing it to power multiple downstream ports.
SELF-POWERED AND BUS-POWERED HUBS
A SPH has a local power supply that powers embedded functions and downstream ports. This power supply
must provide between 4.75 V to 5.25 V to downstream facing devices under full-load and no-load conditions.
SPHs are required to have current-limit protection and must report overcurrent conditions to the USB controller.
Typical SPHs are desktop PCs, monitors, printers, and stand-alone hubs.
A BPH obtains all power from an upstream port and often contains an embedded function. It must power up with
less than 100 mA. The BPH usually has one embedded function, and power is always available to the controller
of the hub. If the embedded function and hub require more than 100 mA on power up, the power to the
embedded function may need to be kept off until enumeration is completed. This is accomplished by removing
power or by shutting off the clock to the embedded function. Power switching the embedded function is not
necessary if the aggregate power draw for the function and controller is less than 100 mA. The total current
drawn by the bus-powered device is the sum of the current to the controller, the embedded function, and the
downstream ports, and it is limited to 500 mA from an upstream port.
LOW-POWER BUS-POWERED AND HIGH-POWER BUS-POWERED FUNCTIONS
Both low-power and high-power bus-powered functions obtain all power from upstream ports. Low-power
functions always draw less than 100 mA; high-power functions must draw less than 100 mA at power up and can
draw up to 500 mA after enumeration. If the load of the function is more than the parallel combination of 44 Ω
and 10 µF at power up, the device must implement inrush current limiting.
USB POWER-DISTRIBUTION REQUIREMENTS
USB can be implemented in several ways regardless of the type of USB device being developed. Several
power-distribution features must be implemented.
•
•
SPHs must:
–
–
Current-limit downstream ports
Report overcurrent conditions
BPHs must:
–
–
–
Enable/disable power to downstream ports
Power up at <100 mA
Limit inrush current (<44 Ω and 10 µF)
•
Functions must:
–
–
Limit inrush currents
Power up at <100 mA
The feature set of the TPS2550/51 meets each of these requirements. The integrated current-limiting and
overcurrent reporting is required by self-powered hubs. The logic-level enable and controlled rise times meet the
need of both input and output ports on bus-powered hubs and the input ports for bus-powered functions.
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AUTO-RETRY FUNCTIONALITY
Some applications require that an overcurrent condition disables the part momentarily during a fault condition
and re-enables after a pre-set time. This auto-retry functionality can be implemented with an external resistor and
capacitor. During a fault condition, FAULT pulls low disabling the part. The part is disabled when EN is pulled
low, and FAULT goes high impedance allowing CRETRY to begin charging. The part re-enables when the voltage
on EN reaches the turnon threshold, and the auto-retry time is determined by the resistor/capacitor time
constant. The part will continue to cycle in this manner until the fault condition is removed.
TPS2551
0.1 mF
Output
R
Input
R
IN
OUT
LOAD
FAULT
100 kW
C
LOAD
ILIM
FAULT
EN
R
ILIM
20 kW
1 kW
GND
C
RETRY
Power Pad
0.1 mF
Figure 22. Auto-Retry Functionality
Some applications require auto-retry functionality and the ability to enable/disable with an external logic signal.
The figure below shows how an external logic signal can drive EN through RFAULT and maintain auto-retry
functionality. The resistor/capacitor time constant determines the auto-retry time-out period.
TPS2551
Output
R
Input
IN
OUT
0.1 mF
LOAD
C
LOAD
External Logic
Signal & Driver
ILIM
R
FAULT
FAULT
EN
R
ILIM
100 kW
1kW
20 kW
GND
C
RETRY
Power Pad
0.1 mF
Figure 23. Auto-Retry Functionality With External EN Signal
LATCH-OFF FUNCTIONALITY
The circuit in Figure 24 uses an SN74HC00 quad-NAND gate to implement overcurrent latch-off. The SN74HC00
high-speed CMOS logic gate is selected because it operates over the 2.5V – 6.5V range of the TPS2550/51.
This circuit is designed to work with the active-high TPS2551. ENABLE must be logic low during start-up until VIN
is stable to ensure that the switch initializes in the OFF state. A logic high on ENABLE turns on the switch after
VIN is stable. FAULT momentarily pulls low during an overcurrent condition, which latches STAT logic low and
disables the switch. The host can monitor STAT for an overcurrent condition. Toggling ENABLE resets STAT and
re-enables the switch.
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TPS2551
0.1 mF
Input
Output
IN
OUT
0.1 mF
R
LOAD
10 kW
C
LOAD
External Logic
Enable Signal
ILIM
EN
15 kW
GND
FAULT
Power Pad
R
FAULT
10 kW
SN74HC00D
STAT
Figure 24. Overcurrent Latch-Off Using a Quad-NAND Gate
TWO-LEVEL CURRENT-LIMIT CIRCUIT
Some applications require different current-limit thresholds depending on external system conditions. Figure 25
shows an implementation for an externally controlled, two-level current-limit circuit. The current-limit threshold is
set by the total resistance from ILIM to GND (see previously discussed "Programming the Current-Limit
Threshold" section). A logic-level input enables/disables MOSFET Q1 and changes the current-limit threshold by
modifying the total resistance from ILIM to GND. Additional MOSFETs/resistor combinations can be used in
parallel to Q1/R2 to increase the number of additional current-limit levels.
NOTE:
ILIM should never be driven directly with an external signal.
TPS2550/51
0.1 mF
Input
Output
IN
OUT
R
R
LOAD
FAULT
C
LOAD
R1
80.6 kW
100 kW
ILIM
R2
20 kW
FAULT
EN
FAULT Signal
Control Signal
GND
Power Pad
Current Limit
Control Signal
Q1
2N7002
Figure 25. Two-Level Current-Limit Circuit
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PACKAGE OPTION ADDENDUM
www.ti.com
19-Feb-2008
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
SOT-23
SOT-23
SON
Drawing
TPS2550DBVR
TPS2550DBVT
TPS2550DRVR
TPS2550DRVT
TPS2551DBVR
TPS2551DBVT
TPS2551DRVR
TPS2551DRVT
PREVIEW
PREVIEW
PREVIEW
PREVIEW
PREVIEW
PREVIEW
PREVIEW
PREVIEW
DBV
6
6
6
6
6
6
6
6
3000
250
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
DBV
DRV
DRV
DBV
3000
250
SON
SOT-23
SOT-23
SON
3000
250
DBV
DRV
DRV
3000
250
SON
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
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Addendum-Page 1
IMPORTANT NOTICE
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