TPS2556-Q1 [TI]
低电平有效的汽车类 0.5-5A 可调节 ILIMIT 2.5-6.5V、22mΩ USB 电源开关;
| 型号： | TPS2556-Q1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 低电平有效的汽车类 0.5-5A 可调节 ILIMIT 2.5-6.5V、22mΩ USB 电源开关 开关 电源开关 |
| 文件： | 总29页 (文件大小：1925K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ZHCSC61B – MARCH 2014 – REVISED SEPTEMBER 2020
TPS2556-Q1, TPS2557-Q1
TPS255x-Q1 精密汽车用可调电流受限配电开关
1 特性
3 说明
•
符合 AEC-Q100
TPS2556-Q1 和 TPS2557-Q1 配电开关专门用于需要
精密电流限制，或者能够处理大电容负载和短路的汽车
应用。这些器件借助一个外部电阻器提供 500mA 至
5A（典型值）之间的可编程电流限制阈值。对电源开
关上升和下降时间的控制最大限度地减少了接通或关闭
期间的电流浪涌。
– 器件人体放电模式 (HBM) 静电放电 (ESD) 分类
等级 H2
– 器件组件充电模式 (CDM) ESD 分类等级 C5
提供功能安全
•
– 可帮助进行功能安全系统设计的文档
满足 USB 限流要求
当 输 出 负 载 超 过 限 流 阈 值 时 ， TPS2556-Q1
和
•
•
TPS2557-Q1 器件通过切换到恒定电流模式来将输出
电流限制在安全的水平上。在过流和过热情况下，
FAULT 逻辑输出为低电平有效。
可调电流限值：500mA 至 5A（典型值）
• 4.5A 电流下的限流精度为 ±6.5%
快速短路响应：3.5μs（典型值）
• 22mΩ 高侧 MOSFET
•
与 TPS2511-Q1 或 TPS2513A-Q1 一同使用，可实现
一款低功耗、符合汽车标准的 USB 充电端口解决方
案。此解决方案能够为目前普遍使用的手机和平板电脑
充电。
•
•
•
工作电压范围：2.5V 至 6.5V
最大待机电源电流 2μA
内置软启动
器件信息
封装(1)
• 15kV 和 8kV 系统级 ESD 能力
订货编号
封装尺寸
•
安全相关认证：
TPS2556QDRB
TPS2557QDRB
S-PVSON (8)
S-PVSON (8)
3mm x 3mm
3mm x 3mm
– 通过 UL 2367 的 UL 认证
– 通过 IEC 60950 的 CB 认证
– 通过 IEC 62368 的 CB 认证
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
2 应用
汽车 USB 充电端口
5 V OUT
0.1 μF
IN
IN
OUT
OUT
TPS2556-Q1
100 kΩ
USB
Connector
TPS2557-Q1
RILIM
ILIM
FAULT
VBUS
Control Signal
DC to DC
Converter
EN
GND
Thermal Pad
D–
D+
or Controller
(LM25117-Q1,
TPS54340-Q1,
TPS54240-Q1,
TPS40170-Q1)
GND
VIN
DM1
DP1
COUT
TPS2513A-Q1
DM2
CUSB
GND
DP2
Recommend TPS2561A-Q1
for the Dual Port Solution
作为单端口汽车 USB 充电端口电源开关的典型应用
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLVSC97
TPS2556-Q1, TPS2557-Q1
ZHCSC61B – MARCH 2014 – REVISED SEPTEMBER 2020
www.ti.com.cn
Table of Contents
9.2 Functional Block Diagram...........................................9
9.3 Feature Description.....................................................9
9.4 Device Functional Modes..........................................10
10 Applications and Implementation..............................12
10.1 Application Information........................................... 12
10.2 Typical Application, Design for Current Limit.......... 12
11 Power Supply Recommendations..............................17
12 Layout...........................................................................18
12.1 Layout Guidelines................................................... 18
12.2 Layout Example...................................................... 18
13 Device and Documentation Support..........................19
13.1 Related Links.......................................................... 19
13.2 Trademarks.............................................................19
13.3 Electrostatic Discharge Caution..............................19
13.4 Glossary..................................................................19
14 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Device Comparison Table...............................................3
6 Terminal Configuration and Functions..........................3
7 Specifications.................................................................. 3
7.1 Absolute Maximum Ratings........................................ 3
7.2 Handling Ratings.........................................................4
7.3 Recommended Operating Conditions.........................4
7.4 Thermal Information....................................................4
7.5 Electrical Characteristics.............................................5
7.6 Switching Characteristics............................................5
7.7 Typical Characteristics................................................6
8 Parameter Measurement Information............................7
9 Detailed Description........................................................8
9.1 Overview.....................................................................8
Information.................................................................... 20
4 Revision History
Changes from Revision A (March 2014) to Revision B (September 2020)
Page
向特性 部分添加了功能安全链接和安全相关认证项目符号.................................................................................1
更新了整个文档的表、图和交叉参考的编号格式................................................................................................ 1
•
•
Changes from Revision * (March 2014) to Revision A (March 2014)
Page
•
将“说明”中的器件型号从 TPS2511-Q 更改为 TPS2511-Q1........................................................................... 1
• Changed CURRENT LIMIT values in Electrical Characteristics table ...............................................................5
• Changed Equation 1 ........................................................................................................................................12
• Revised 图 10-2 graph......................................................................................................................................12
• Changed Equation 2 ........................................................................................................................................13
• Changed resistor value from 33.2 kΩ to 33.6 kΩ ...........................................................................................13
• Changed Equation 3 ........................................................................................................................................13
• Changed Equation 4 ........................................................................................................................................14
• Changed current-limit threshold from 4 316 mA to 4 406 mA ..........................................................................14
• Changed values in 表 10-2 .............................................................................................................................. 14
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5 Device Comparison Table
MAX. OPERATING
CURRENT (A)
DEVICE
OUTPUTS
ENABLES
TYPICAL rDS(on) (mΩ)
TPS2556-Q1
TPS2557-Q1
TPS2561A-Q1
5
5
1
1
2
Active-low
Active-high
Active-high
22
22
44
2.5
6 Terminal Configuration and Functions
1
2
3
4
8
7
6
5
GND
IN
FAULT
OUT
OUT
ILIM
Thermal
Pad
IN
EN
EN = Active-low for the TPS2556-Q1
EN = Active-high for the TPS2557-Q1
图 6-1. 8-Terminal S-PVSON With Thermal Pad DRB Package (Top View)
Terminal Functions
TERMINAL
TPS2556-Q1
4
I/O
DESCRIPTION
NAME
TPS2557-Q1
EN
I
I
Enable input, logic low turns on power switch.
Enable input, logic high turns on power switch.
Ground connection; connect externally to PowerPAD.
–
4
EN
–
GND
1
1
–
Input voltage; connect a 0.1 μF or greater ceramic capacitor from
IN to GND as close to the IC as possible.
IN
2, 3
2, 3
I
Active-low open-drain output, asserted during overcurrent or
overtemperature conditions.
FAULT
OUT
8
6, 7
5
8
6, 7
5
O
O
O
Power-switch output.
External resistor used to set current-limit threshold; recommended
20 kΩ ≤ R(ILIM) ≤ 187 kΩ.
ILIM
Internally connected to GND; used to heat-sink the part to the
circuit board traces. Connect therma pad to GND terminal
externally.
Thermal pad
–
–
–
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range unless otherwise noted(1) (2)
MIN
–0.3
–7
MAX(2)
UNIT
V
Voltage range on IN, OUT, EN or EN, ILIM, FAULT
Voltage range from IN to OUT
7
7
V
I
Continuous output current
Continuous FAULT sink current
ILIM source current
Internally limited
25
mA
mA
°C
Internally limited
Internally limited
TJ
Maximum junction temperature
–40
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
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Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2) Voltages are referenced to GND unless otherwise noted.
7.2 Handling Ratings
PARAMETER
MIN
–65
–2
MAX UNIT
Tstg
Storage temperature range
150
2
°C
kV
V
Human-body model (HBM) ESD stress voltage(2)
Charged-device model (CDM) ESD stress voltage(3)
750
8
–750
–8
(1)
V(ESD)
Contact discharge
Air discharge
System level(4)
kV
15
–15
(1) Electrostatic discharge (ESD) to measure device sensitivity or immunity to damage caused by assembly-line electrostatic discharges
into the device.
(2) The passing level per AEC-Q100 Classification H2.
(3) The passing level per AEC-Q100 Classification C5.
(4) Surges per EN61000-4-2, 1999 applied between USB connection for V(BUS) and ground of the TPS2556EVM (HPA423, replacing
TPS2556 with TPS2556-Q1) evaluation module (SLUU393). These were the test levels, not the failure threshold.
7.3 Recommended Operating Conditions
MIN
2.5
0
MAX UNIT
V(IN)
V( EN )
V(EN)
VIH
Input voltage, IN
Enable voltage
6.5
6.5
6.5
V
TPS2556-Q1
TPS2557-Q1
V
0
High-level input voltage on EN or EN
Low-level input voltage on EN or EN
Continuous output current, OUT
Continuous FAULT sink current
Operating junction temperature
Recommendedlimit-resistor range
1.1
V
VIL
0.66
5
I(OUT)
0
0
A
10
mA
°C
TJ
125
187
–40
20
R(ILIM)
kΩ
7.4 Thermal Information
TPS2556-Q1,
TPS2557-Q1
THERMAL METRIC(1)
UNIT
DRB
8 TERMINALS
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
41.5
56
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
Junction-to-board thermal resistance
16.4
0.7
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
ψJT
16.5
3.5
ψJB
RθJC(bot)
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report (SPRA953).
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7.5 Electrical Characteristics
over recommended operating conditions, VEN = 0 V, or VEN = VIN (unless otherwise noted)
PARAMETER
TEST CONDITIONS(1)
MIN
TYP MAX UNIT
POWER SWITCH
TJ = 25°C
22
25
35
Static drain-source on-state
resistance
rDS(on)
mΩ
–40 °C ≤ TJ ≤ 125°C
ENABLE INPUT EN OR EN
Enable terminal turnon or turnoff
0.66
1.1
0.5
V
threshold
Hysteresis
Input current
55(2)
mV
I(EN)
V(EN) = 0 V or 6.5 V, or V( EN) = 0 V or 6.5 V
–0.5
μA
CURRENT LIMIT
4180
1610
945
4500 4745
1805 1980
1110 1270
R(ILIM) = 24.9 kΩ
Current-limit threshold (maximum dc output current I(OUT) delivered to
load) and short-circuit current, OUT connected to GND
IOS
mA
R(ILIM) = 61.9 kΩ
R(ILIM) = 100 kΩ
SUPPLY CURRENT
I(IN_off)
I(IN_on)
I(REV)
Supply current, low-level output
V(IN) = 6.5 V, no load on OUT, V( EN) = 6.5 V or V(EN) = 0 V
0.1
95
2.5
120
110
1
μA
μA
μA
μA
R(ILIM) = 24.9 kΩ
V(IN) = 6.5 V, no load on OUT
R(ILIM) = 100 kΩ
Supply current, high-level output
85
Reverse leakage current
V(OUT) = 6.5 V, VIN = 0 V
TJ = 25 °C
0.01
UNDERVOLTAGE LOCKOUT
V(UVLO)
Low-level input voltage, IN
V(IN) rising
2.35 2.45
35(2)
V
Hysteresis, IN
mV
FAULT FLAG
VOL
Output low voltage, FAULT
Off-state leakage
I( FAULT) = 1 mA
V( FAULT) = 6.5 V
180
1
mV
μA
ms
FAULT deglitch
FAULT assertion or de-assertion due to overcurrent condition
6
9
13
THERMAL SHUTDOWN
T(OTSD2) Thermal shutdown threshold
155
135
°C
°C
°C
Thermal shutdown threshold in
current-limit
T(OTSD)
Hysteresis
20(2)
(1) Pulse-testing techniques maintain junction temperature close to ambient temperature; thermal effects must be taken into account
separately.
(2) These parameters are provided for reference only, and do no constitute part of TI's published specifications for purposes of TI's
product warranty.
7.6 Switching Characteristics
MIN TYP MAX UNIT
VIN = 6.5 V
VIN = 2.5 V
VIN = 6.5 V
VIN = 2.5 V
2
1
3
2
4
3
tr
tf
Rise time, output
Fall time, output
CL = 1 μF, RL = 100 Ω,
(see 图 8-1)
ms
0.6
0.4
0.8
0.6
1.0
0.8
9
ton
Turnon time
ms
ms
μs
CL = 1 μF, RL = 100 Ω, (see 图 8-1)
V(IN) = 5 V (see 图 8-2)
toff
Turnoff time
6
t(IOS)
Response time to short circuit
3.5(1)
(1) These parameters are provided for reference only, and do no constitute part of TI's published specifications for purposes of TI's
product warranty
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7.7 Typical Characteristics
2.335
2.330
2.325
2.320
700
600
500
400
300
200
100
0
V(IN) = 2.5 V
V(IN) = 6.5 V
UVLO Rising
UVLO Falling
2.315
2.310
2.305
2.300
2.295
2.290
œ100
0
50
100
150
0
50
100
150
œ50
œ50
Junction Temperature (°C)
Junction Temperature (°C)
C001
C002
图 7-1. UVLO – Undervoltage Lockout – V
图 7-2. IIN – Supply Current, Output Disabled – nA
120
1.20E-04
1.10E-04
1.00E-04
9.00E-05
8.00E-05
100
80
60
40
V(IN) = 2.5 V
V(IN) = 3.3 V
TJ = t40°C
7.00E-05
20
0
T=25°C
J
V
= 5 V
(IN)
TJ = 125°C
V(IN) = 6.5 V
6.00E-05
2
3
4
5
6
7
0
50
100
150
œ50
Input Voltage (V)
C004
Junction Temperature (°C)
C003
R(ILIM) = 24.9 kΩ
R(ILIM) = 24.9 kΩ
图 7-4. IIN – Supply Current, Output Enabled –
μA
图 7-3. IIN – Supply Current, Output Enabled –
μA
35
30
25
20
15
10
5
1.200
1.000
0.800
0.600
0.400
T = t40°C
J
0.200
0.000
T = 25°C
J
T = 125°C
J
0
0
50
100
150
0
50
100
150
200
œ50
Junction Temperature (°C)
V(IN) t V(OUT) (mV)
C005
C0067
图 7-5. MOSFET rDS(on) Versus Junction
R(ILIM) = 100 kΩ
Temperature
图 7-6. Switch Current Versus Drain-Source
Voltage Across Switch
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2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
5.000
4.500
4.000
3.500
3.000
2.500
2.000
1.500
1.000
0.500
0.000
TJ = t40°C
TJ = t40°C
T = 25°C
J
TJ = 25°C
TJ = 125°C
TJ = 125°C
0.0
0
50
100
150
200
0
50
100
150
200
V(IN) œ V(OUT) (mV)
V(IN) œ V(OUT) (mV)
C007
C010
R(ILIM) = 24.9 kΩ
R(ILIM) = 61.9 kΩ
图 7-8. Switch Current Versus Drain-Source
图 7-7. Switch Current Versus Drain-Source
Voltage Across Switch
Voltage Across Switch
8 Parameter Measurement Information
OUT
tr
V(OUT)
tf
RL
CL
90%
10%
90%
10%
TEST CIRCUIT
V(EN)
50%
50%
50%
ton
50%
V(EN)
toff
tonn
toff
90%
90%
V(OUT)
V(OUT)
10%
10%
VOLTAGE WAVEFORMS
图 8-1. Test Circuit and Voltage Waveforms
IOS
I(OUT)
t(IOS)
图 8-2. Response Time to Short-Circuit Waveform
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Decreasing
Load Resistance
V
(OUT)
Decreasing
Load Resistance
I
(OUT)
I
OS
图 8-3. Output Voltage Versus Current-Limit Threshold
9 Detailed Description
9.1 Overview
The TPS2556-Q1 and TPS2557-Q1 are current-limited, power-distribution switches using N-channel MOSFETs
for applications that might encounter short circuits or heavy capacitive loads . This device allows the user to
program the current-limit threshold between 500 mA and 5 A (typical) via an external resistor. This device
incorporates an internal charge pump and the gate-drive circuitry necessary to drive the N-channel MOSFET.
The charge pump supplies power to the driver circuit and provides the necessary voltage to pull the gate of the
MOSFET above the source. The charge pump operates from input voltages as low as 2.5 V and requires little
supply current. The driver controls the gate voltage of the power switch. The driver incorporates circuitry that
controls the rise and fall times of the output voltage to limit large current and voltage surges and provides built-in
soft-start functionality. The TPS2556-Q1 and TPS2557-Q1 family limits the output current to the programmed
current-limit threshold IOS during an overcurrent or short-circuit event by reducing the charge-pump voltage
driving the N-channel MOSFET and operating it in the linear range of operation. The result of limiting the output
current to IOS reduces the output voltage at OUT by no longer fully enhancing the N-channel MOSFET.
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9.2 Functional Block Diagram
CS
OUT
IN
Current
Sense
Charge
Pump
Current
Limit
Driver
EN
FAULT
UVLO
GND
Thermal
Sense
8-ms Deglitch
ILIM
9.3 Feature Description
9.3.1 Overcurrent Conditions
The TPS2556-Q1 and TPS2557-Q1 devices respond to overcurrent conditions by limiting their output current to
IOS. On detecting an overcurrent condition, the device maintains a constant output current, and the output
voltage reduces accordingly. Two possible overload conditions can occur.
The first condition is when a short circuit or partial short circuit is present on a powered-up and enabled device.
With the output voltage held near zero potential with respect to ground, the TPS2556-Q1 or TPS2557-Q1 device
ramps the output current to IOS. The TPS2556-Q1 and TPS2557-Q1 devices limit the current to IOS until removal
of the overload condition or until the device begins to cycle thermally.
The second condition is when a short circuit, partial short circuit, or transient overload occurs while the device is
enabled and powered on. The device responds to the overcurrent condition within time t(IOS) (see 图 8-2).
Overdriving the current-sense amplifier during this time and momentarily disables the internal N-channel
MOSFET. The current-sense amplifier recovers and ramps the output current to IOS. Similar to the previous
case, the TPS2556-Q1 and TPS2557-Q1 devices limit the current to IOS until removal of the overload condition
or until the device begins to cycle thermally.
The TPS2556-Q1 and TPS2557-Q1 cycle thermally if an overload condition is present long enough to activate
thermal limiting in any of the above cases. The device turns off when the junction temperature exceeds 135°C
(minimum) while in current limit. The device remains off until the junction temperature cools 20°C (typical) and
then restarts. The TPS2556-Q1 and TPS2557-Q1 cycle on and off until removal of the overload (see 图 10-7).
9.3.2 FAULT Response
Assertion (active-low) of the FAULT open-drain output occurs during an overcurrent or overtemperature
condition. The TPS2556-Q1 and TPS2557-Q1 devices assert the FAULT signal until removal of the fault
condition and the resumption of normal device operation. Design of the TPS2556-Q1 and TPS2557-Q1 devices
eliminates false FAULT reporting by using an internal delay (9-ms typical) deglitch circuit for overcurrent
conditions without the need for external circuitry. This avoids accidental FAULT assertion due to normal
operation, such as starting into a heavy capacitive load. The deglitch circuitry delays entering and leaving
current-limit-induced fault conditions. Deglitching of the FAULT signal does not occur when an overtemperature
condition disables the MOSFET, but does occur after the device has cooled and begins to turn on. This
unidirectional deglitch prevents FAULT oscillation during an overtemperature event.
9.3.3 Thermal Sense
The TPS2556-Q1 and TPS2557-Q1 devices self-protect by using two independent thermal sensing circuits that
monitor the operating temperature of the power switch and disable operation if the temperature exceeds
recommended operating conditions. The TPS2556-Q1 and TPS2557-Q1 devices operate in constant-current
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mode during an overcurrent condition, which increases the voltage drop across power switch. The power
dissipation in the package is proportional to the voltage drop across the power switch, which increases the
junction temperature during an overcurrent condition. The first thermal sensor (OTSD) turns off the power switch
when the die temperature exceeds 135°C (min) and the part is in current limit. Hysteresis is built into the thermal
sensor, and the switch turns on after the device has cooled approximately 20°C.
The TPS2556-Q1 and TPS2557-Q1 devices also have a second thermal sensor (OTSD2). This thermal sensor
turns off the power switch when the die temperature exceeds 155°C (minimum) regardless of whether the power
switch is in current limit, and turns on the power switch after the device has cooled approximately 20°C. The
TPS2556-Q1 and TPS2557-Q1 devices continue to cycle off and on until the fault is removed.
9.4 Device Functional Modes
9.4.1 Undervoltage Lockout (UVLO)
The undervoltage lockout (UVLO) circuit disables the power switch until the input voltage reaches the UVLO
turnon threshold. Built-in hysteresis prevents unwanted on-and-off cycling due to input voltage droop during
turnon.
9.4.2 Enable ( EN OR EN)
The logic enable controls the power switch and device supply current. The supply current is reduced to less than
2 μA when a logic high is present on EN or when a logic low is present on EN. A logic low input on EN or a logic
high input on EN enables the driver, control circuits, and power switch. The enable input is compatible with both
TTL and CMOS logic levels.
9.4.3 Auto-Retry Functionality
Some applications require that an overcurrent condition disable the device momentarily during a fault condition
and re-enables it after a preset time. This auto-retry functionality can be implemented with an external resistor
and capacitor. During a fault condition, FAULT pulls EN low. Pulling EN below the turnoff threshold disables the
part is disabled, and FAULT goes into the high-impedance state, allowing CRETRY to begin charging. The device
re-enables when the voltage on EN reaches the turnon threshold. The resistor-capacitor time constant
determines the auto-retry time. The device continues to cycle in this manner until removal of the fault condition.
TPS2557-Q1
Input
RFAULT
100 kW
Output
CLOAD
0.1 µF
IN
OUT
RLOAD
ILIM
RILIM
20 kW
FAULT
EN
1 kW
GND
CRETRY
0.22 µF
Thermal Pad
图 9-1. Auto-Retry Functionality
Some applications require auto-retry functionality and the ability to enable and disable with an external logic
signal. 图 9-2 shows how an external logic signal can drive EN through RFAULT and maintain auto-retry
functionality. The resistor-capacitor time constant determines the auto-retry time-out period.
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TPS2557-Q1
Input
Output
IN
OUT
0.1 µF
CLOAD
RLOAD
ILIM
External Logic
Signal and Driver
RILIM
20 kΩ
RFAULT
100 kΩ
FAULT
EN
GND
CRETRY
0.22 µF
Thermal Pad
图 9-2. Auto-Retry Functionality With External EN Signal
9.4.4 Two-Level Current-Limit Circuit
Some applications require different current-limit thresholds depending on external system conditions. 图 9-3
shows an implementation for an externally controlled, two-level current-limit circuit. The current-limit threshold is
set by the total resistance from ILIM to GND (see Programming the Current-Limit Threshold). A logic-level input
enables and disables MOSFET Q1 and changes the current-limit threshold by modifying the total resistance from
ILIM to GND. One can use additional MOSFET and resistor combinations in parallel with Q1 and R2 to increase
the number of additional current-limit levels.
CAUTION
Never drive ILIM directly with an external signal.
TPS2556-Q1, TPS2557-Q1
0.1 µF
Input
Output
IN
OUT
RFAULT
100 kΩ
CLOAD
RLOAD
R1
187 kΩ
ILIM
R2
22.1 kΩ
FAULT Signal
FAULT
EN
GND
Control Signal
Thermal Pad
Q1
Current-Limit
Control Signal
图 9-3. Two-Level Current-Limit Circuit
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10 Applications and Implementation
10.1 Application Information
The devices are current-limited, power-distribution switches. They limit the output current to IOS when
encountering short circuits or heavy capacitive loads.
10.2 Typical Application, Design for Current Limit
The use of theTPS2556-Q1 and TPS2557-Q1 devices is as a power switch to limit the output current. FAULT is
an open drain pulled high to V(IN) with a resistor, a host can use to monitor overcurrent or thermal shutdown.
TPS2556-Q1
V(OUT)
RLOAD
0.1 µF
V(IN) = 5 V
OUT
IN
RFAULT
100 kW
150 µF
ILIM
FAULT Signal
Enable Signal
FAULT
EN
24.9 kW
GND
Thermal Pad
图 10-1. Application Schematic for Current Limit, TPS2556-Q1
10.2.1 Design Requirements
For this design example, use the following as the input parameters.
表 10-1. Design Parameters
DESIGN PARAMETER
EXAMPLE VALUE
Input voltage
5 V
3 A
5 A
Minimum current limit
Maximum current limit
10.2.2 Detailed Design Procedure
10.2.2.1 Determine Design Parameters
Beginning the design process requires deciding on a few parameters. The designer must know the following:
• Input voltage
• Minimum current limit
• Maximum current limit
10.2.2.2 Programming the Current-Limit Threshold
The overcurrent threshold is user-programmable via an external resistor. The TPS2556-Q1 and TPS2557-Q1
devices use an internal regulation loop to provide a regulated voltage on the ILIM terminal. The current-limit
threshold is proportional to the current sourced out of ILIM. The recommended 1% resistor range for RILIM is
20 kΩ ≤ R(ILIM) ≤ 187 kΩ to ensure stability of the internal regulation loop. Many applications require that the
minimum current limit be above a certain current level or that the maximum current limit be below a certain
current level, so it is important to consider the tolerance of the overcurrent threshold when selecting a value for
RILIM. The following equations approximate the resulting overcurrent threshold for a given value of external
resistor RILIM. Consult the Electrical Characteristics table for specific current-limit settings. The traces routing the
RILIM resistor to the TPS2556-Q1 and TPS2557-Q1 devices should be as short as possible to reduce parasitic
effects on the current-limit accuracy.
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101 810 V
0.9538
IOS(max)(mA) =
R(ILIM)
kW
113 849 V
1.0049
IOS(nom)(mA) =
IOS(min)(mA) =
R(ILIM)
kW
125 477 V
1.058
R(ILIM)
kW
(1)
6000
5500
5000
4500
4000
3500
3000
2500
2000
1500
1000
500
I
OS(min)
IOS(typ)
I
OS(max)
0
20 30 40 50 60 70 80 90 100 110 120 130 140 150
RILIM (kꢀ)
C002
图 10-2. Current-Limit Threshold versus R(ILIM)
10.2.2.3 Selecting Current-Limit Resistor 1
Some applications require that current limiting not occur below a certain threshold. For this example, assume
that 3 A must be delivered to the load so that the minimum desired current-limit threshold is 3 000 mA. Use the
IOS equations and 图 10-2 to select R(ILIM)
.
IOS(min)(mA) = 3 000 mA
125 477 V
1.058
IOS(min)(mA) =
R(ILIM)
kW
1
æ
ç
ç
ç
ç
ö1.058
125 477 V
÷
÷
÷
÷
R
R
(ILIM)(kW) =
I
mA÷
ç
è OS(min)
ø
(ILIM)(kW) = 34 kW
(2)
Select the closest 1% resistor less than the calculated value: R(ILIM) = 33.6 kΩ. This sets the minimum current-
limit threshold at 3 000 mA . Use the IOS equations, 图 10-2, and the previously calculated value for R(ILIM) to
calculate the maximum resulting current-limit threshold.
RILIM(kW) = 33.6 kW
101810 V
0.9538
IOS(max)(mA) =
R(ILIM)
kW
101810 V
33.60.9538 kW
IOS(max)(mA) =
IOS(max)(mA) = 3 564 mA
(3)
The resulting maximum current-limit threshold is 3 564 mA with a 33.6-kΩ resistor.
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10.2.2.4 Selecting Current-Limit Resistor 2
Some applications require that current limiting must occur below a certain threshold. For this example, assume
that the desired upper current-limit threshold must be below 5,000 mA to protect an upstream power supply. Use
the IOS equations and 图 10-2 to select R(ILIM)
.
IOS(max)(mA) = 5 000 mA
101 810 V
0.9538
IOS(max)(mA) =
R(ILIM)
kW
1
æ
ç
ç
ç
ç
ö0.9538
101 810 V
÷
÷
÷
÷
R
R
(ILIM)(kW) =
I
mA÷
ç
è OS(max)
ø
(ILIM)(kW) = 23.6 kW
(4)
Select the closest 1% resistor greater than the calculated value: R(ILIM) = 23.7 kΩ. This sets the maximum
current-limit threshold at 5 000 mA . Use the IOS equations, 图 10-2, and the previously calculated value for RILIM
to calculate the minimum resulting current-limit threshold.
R(ILIM)(kW) = 23.7 kW
125 477 V
1.058
R(ILIM)
IOS(min)(mA) =
125 477 V
23.71.058
IOS(min)(mA) =
IOS(min)(mA) = 4 406 mA
(5)
The resulting minimum current-limit threshold is 4 406 mA with a 23.7-kΩ resistor.
10.2.2.5 Accounting for Resistor Tolerance
The previous sections described the selection of RILIM given certain application requirements and the importance
of understanding the current-limit threshold tolerance. The analysis focused only on the TPS2556-Q1 and
TPS2557-Q1 device performance and assumed an exact resistor value. However, resistors sold in quantity are
not exact and are bounded by an upper and lower tolerance centered around a nominal resistance. The
additional RILIM resistance tolerance directly affects the current-limit threshold accuracy at a system level. The
following table shows a process that accounts for worst-case resistor tolerance assuming 1% resistor values.
Step one follows the selection process outlined in the foregoing application examples. Step two determines the
upper and lower resistance bounds of the selected resistor. Step three uses the upper and lower resistor bounds
in the IOS equations to calculate the threshold limits. It is important to use tighter tolerance resistors, for example
0.5% or 0.1%, when precision current limiting is desirable.
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表 10-2. Common RILIM Resistor Selections
Resistor Tolerance
Actual Limits
Ideal Resistor Closest 1%
Desired Nominal
Current Limit (mA)
(kΩ)
Resistor (kΩ)
IOS MIN (mA) IOS NOM (mA) IOS MAX (mA)
1% low (kΩ) 1% high (kΩ)
750
148.1
111.3
89.1
74.3
63.7
55.8
49.6
44.7
40.7
37.3
34.4
32.0
29.9
28.0
26.4
24.9
23.6
22.4
21.4
20.4
147
110
145.5
108.9
87.8
74.3
62.8
55.6
49.4
43.8
39.8
37.0
34.5
31.3
29.8
27.7
25.8
24.7
23.5
22.4
21.3
20.3
148.5
111.1
89.6
75.8
64.0
56.8
50.4
44.6
40.6
37.8
35.1
31.9
30.4
28.3
26.4
25.1
23.9
22.8
21.7
20.7
632
756
881
1000
1250
1500
1750
2000
2250
2500
2750
3000
3250
3500
3750
4000
4250
4500
4750
5000
5250
5500
859
1011
1256
1486
1760
1986
2238
2528
2781
2991
3215
3542
3720
4000
4293
4501
4730
4961
5216
5472
1161
1426
1673
1964
2203
2468
2770
3033
3249
3480
3816
3997
4282
4579
4789
5020
5253
5509
5765
88.7
75
1079
1289
1540
1749
1983
2255
2493
2691
2904
3216
3386
3655
3937
4138
4360
4585
4834
5083
63.4
56.2
49.9
44.2
40.2
37.4
34.8
31.6
30.1
28
26.1
24.9
23.7
22.6
21.5
20.5
10.2.2.6 Power Dissipation and Junction Temperature
The low on-resistance of the N-channel MOSFET allows small surface-mount packages to pass large currents. It
is good design practice to estimate power dissipation and junction temperature. The following analysis gives an
approximation for calculating junction temperature based on the power dissipation in the package. However, it is
important to note that thermal analysis is strongly dependent on additional system-level factors. Such factors
include air flow, board layout, copper thickness and surface area, and proximity to other devices that dissipate
power. Good thermal design practice must include all system-level factors in addition to individual component
analysis.
Begin by determining the rDS(on) of the N-channel MOSFET relative to the input voltage and operating
temperature. As an initial estimate, use the highest operating ambient temperature of interest and read rDS(on)
from the typical characteristics graph. Using this value, calculate the power dissipation by:
2
PD = rDS(on) × IOUT
where:
PD = Total power dissipation (W)
rDS(on) = Power-switch on-resistance (Ω)
I(OUT) = Maximum current-limit threshold (A)
This step calculates the total power dissipation of the N-channel MOSFET.
Finally, calculate the junction temperature:
TJ = PD × RθJA + TA
where:
TA = Ambient temperature (°C)
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RθJA = Thermal resistance (°C/W)
PD = Total power dissipation (W)
Compare the calculated junction temperature with the initial estimate. If they are not within a few degrees, repeat
the calculation using the refined rDS(on) from the previous calculation as the new estimate. Two or three iterations
are generally sufficient to achieve the desired result. The final junction temperature is highly dependent on
thermal resistance RθJA, and thermal resistance is highly dependent on the individual package and board
layout. The Thermal Information table lists thermal resistances of the device that one can use to help calculate
the thermal performance of the board design.
10.2.3 Application Curves
V
V
OUT
2 V/div
OUT
2 V/div
V
V
EN_bar
5 V/div
EN_bar
5 V/div
I
I
IN
2 A/div
IN
2 A/div
t - Time - 2 ms/div
t - Time - 2 ms/div
图 10-3. Turnon Delay and Rise Time
图 10-4. Turnoff Delay and Fall Time
V
V
EN_bar
5 V/div
OUT
2 V/div
FAULT_bar
5 V/div
FAULT_bar
5 V/div
I
I
IN
2 A/div
IN
5 A/div
t - Time - 2 ms/div
t - Time - 5 ms/div
图 10-5. Device Enabled Into Short Circuit
图 10-6. Full-Load to Short-Circuit Transient
Response
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V
OUT
2 V/div
FAULT_bar
5 V/div
I
IN
5 A/div
t - Time - 5 ms/div
图 10-7. Short-Circuit to Full-Load Recovery Response
11 Power Supply Recommendations
Design of the devices is for operation from an input voltage supply range of 2.5 V to 6.5 V. The current capability
of the power supply should exceed the maximum current limit of the power switch.
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12 Layout
12.1 Layout Guidelines
• For all applications, TI recommends a 0.1-µF or greater ceramic bypass capacitor between IN and GND as
close to the device as possible for local noise decoupling. This precaution reduces ringing on the input due to
power-supply transients. The application may require additional input capacitance on the input to prevent
voltage overshoot from exceeding the absolute-maximum voltage of the device during heavy transient
conditions.
• Output capacitance is not required, but TI recommends placing a high-value electrolytic capacitor on the
output pin when there is an expectation of large transient currents on the output.
• The traces routing the RILIM resistor to the device should be as short as possible to reduce parasitic effects
on the current limit accuracy.
• Connect the thermal pad directly to PCB ground plane using wide and short copper trace.
12.2 Layout Example
VIA to Power Ground Plane
Power
Ground
FAULT
1
2
3
4
8
7
6
5
High Frequency
Bypass Capacitor
IN
OUT
ILIM
图 12-1. TPS2556-Q1 and TPS2557-Q1 Board Layout
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13 Device and Documentation Support
13.1 Related Links
The following table lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
表 13-1. Related Links
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TPS2556-Q1
TPS2557-Q1
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
13.2 Trademarks
所有商标均为其各自所有者的财产。
13.3 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
13.4 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
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14 Mechanical, Packaging, and Orderable Information
The following packaging information and addendum reflect the most-current data available for the designated
devices. This data is subject to change without notice and without revision of this document.
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PACKAGE OPTION ADDENDUM
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PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS2556QDRBRQ1
TPS2556QDRBTQ1
TPS2557QDRBRQ1
TPS2557QDRBTQ1
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SON
SON
SON
SON
DRB
DRB
DRB
DRB
8
8
8
8
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 125
-40 to 125
-40 to 125
-40 to 125
2556Q
NIPDAU
NIPDAU
NIPDAU
2556Q
2557Q
2557Q
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Apr-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS2556QDRBRQ1
TPS2556QDRBTQ1
TPS2557QDRBRQ1
TPS2557QDRBTQ1
SON
SON
SON
SON
DRB
DRB
DRB
DRB
8
8
8
8
3000
250
330.0
180.0
330.0
180.0
12.4
12.4
12.4
12.4
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
1.1
1.1
1.1
1.1
8.0
8.0
8.0
8.0
12.0
12.0
12.0
12.0
Q2
Q2
Q2
Q2
3000
250
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Apr-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPS2556QDRBRQ1
TPS2556QDRBTQ1
TPS2557QDRBRQ1
TPS2557QDRBTQ1
SON
SON
SON
SON
DRB
DRB
DRB
DRB
8
8
8
8
3000
250
346.0
210.0
346.0
210.0
346.0
185.0
346.0
185.0
33.0
35.0
33.0
35.0
3000
250
Pack Materials-Page 2
PACKAGE OUTLINE
DRB0008B
VSON - 1 mm max height
SCALE 4.000
PLASTIC SMALL OUTLINE - NO LEAD
3.1
2.9
B
A
PIN 1 INDEX AREA
3.1
2.9
C
1 MAX
SEATING PLANE
0.08 C
0.05
0.00
EXPOSED
THERMAL PAD
1.65 0.05
(0.2) TYP
4
5
2X
1.95
2.4 0.05
8
1
6X 0.65
0.35
0.25
8X
PIN 1 ID
0.1
C A B
C
0.5
0.3
8X
(OPTIONAL)
0.05
4218876/A 12/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
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EXAMPLE BOARD LAYOUT
DRB0008B
VSON - 1 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(1.65)
SYMM
8X (0.6)
1
8
8X (0.3)
(2.4)
(0.95)
6X (0.65)
4
5
(R0.05) TYP
(0.575)
(2.8)
(
0.2) VIA
TYP
LAND PATTERN EXAMPLE
SCALE:20X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4218876/A 12/2017
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
DRB0008B
VSON - 1 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
SYMM
METAL
TYP
8X (0.6)
8X (0.3)
1
8
(0.63)
SYMM
(1.06)
6X (0.65)
5
4
(R0.05) TYP
(1.47)
(2.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD
81% PRINTED SOLDER COVERAGE BY AREA
SCALE:25X
4218876/A 12/2017
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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