TPS2560ADRC [TI]
Dual Channel Precision Adjustable Current-Limited Power Switches; 双通道精密可调电流限制电源开关
| 型号： | TPS2560ADRC |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | Dual Channel Precision Adjustable Current-Limited Power Switches |
| 文件： | 总24页 (文件大小：1040K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPS2560A
TPS2561A
www.ti.com
SLVSB28 –DECEMBER 2011
Dual Channel Precision Adjustable Current-Limited Power Switches
Check for Samples: TPS2560A, TPS2561A
1
FEATURES
APPLICATIONS
2
•
•
•
•
Two separate current limiting channels
Meets USB Current-Limiting Requirements
Adjustable Current Limit, 250 mA–2.8 A (typ)
•
•
•
•
USB Ports/Hubs
Digital TV
Set-Top Boxes
VOIP Phones
Accurate 2.1A Min / 2.5A Max Setting
(Including Resistor)
DESCRIPTION
•
•
•
•
•
•
•
•
Fast Overcurrent Response - 3.5-μs (typ)
Two 44-mΩ High-Side MOSFETs
Operating Range: 2.5 V to 6.5 V
2-μA Maximum Standby Supply Current
Built-in Soft-Start
The TPS2560A and TPS2561A are dual-channel
power-distribution switches intended for applications
where precision current limiting is required or heavy
capacitive loads and short circuits are encountered.
These devices offer a programmable current-limit
threshold between 250 mA and 2.8 A (typ) per
channel via an external resistor. The power-switch
rise and fall times are controlled to minimize current
surges during turn on/off.
15 kV / 8 kV System-Level ESD Capable
UL Listed – File No. E169910
CB & Nemko Certified
Each channel of the TPS2560A/61A devices limits
the output current to a safe level by switching into a
constant-current mode when the output load exceeds
the current-limit threshold. The FAULTx logic output
for each channel independently asserts low during
overcurrent and over temperature conditions.
TPS2560A/61A
DRC PACKAGE
(TOP VIEW)
TPS2560A/61A
2.5V – 6.5V
0.1 μF
VOUT1
IN
IN
OUT1
OUT2
10
9
8
7
6
1
2
3
4
5
GND
IN
IN
EN1
EN2
FAULT1
OUT1
OUT2
ILIM
2x RFAULT
100 kΩ
VOUT2
PAD
RILIM
2x CLOAD
ILIM
Fault Signal
FAULT1
FAULT2
EN1
FAULT2
Fault Signal
Control Signal
Control Signal
GND
ENx = Active Low for the TPS2560A
ENx = Active High for the TPS2561A
EN2
Power Pad
Figure 1. Typical Application as USB Power Switch
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
PowerPAD is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2011, Texas Instruments Incorporated
TPS2560A
TPS2561A
SLVSB28 –DECEMBER 2011
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
AVAILABLE OPTIONS AND ORDERING INFORMATION
MARKING
RECOMMENDED MAXIMUM
CONTINUOUS LOAD CURRENT PER
CHANNEL
(3)
AMBIENT
TEMPERATURE
SON
DEVICE(1)
ENABLE
(2)
(DRC)
TPS2560A
TPS2561A
Active low
Active high
TPS2560ADRC
TPS2561ADRC
2560A
2561A
–40°C to 85°C
2.5 A
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
(2) Maximum ambient temperature is a function of device junction temperature and system level considerations, such as power dissipation
and board layout. See dissipation rating table and recommended operating conditions for specific information related to these devices.
(3) Add an R suffix to the device type for tape and reel.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted(1)
(2)
VALUE
UNIT
V
Voltage range on IN, OUTx, ENx or ENx, ILIM, FAULTx
Voltage range from IN to OUTx
Continuous output current
–0.3 to 7
–7 to 7
V
Internally Limited
Continuous total power dissipation
Continuous FAULTx sink current
ILIM source current
See the Dissipation Rating Table
25
mA
mA
kV
V
Internally Limited
HBM
ESD
2
500
CDM
ESD – system level (contact/air)(3)
8/15
–40 to OTSD2(4)
kV
°C
TJ
Maximum junction temperature
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Voltages are referenced to GND unless otherwise noted.
(3) Surges per EN61000-4-2, 1999 applied between USB and output ground of the TPS2560AEVM (HPA424) evaluation module
(documentation available on the Web.) These were the test level, no the failure threshold.
(4) Ambient over temperature shutdown threshold
DISSIPATION RATING TABLE
THERMAL
THERMAL
RESISTANCE
TA ≤ 25°C
POWER
RATING
RESISTANCE(1)
BOARD
PACKAGE
θJA
θJC
High-K(2)
DRC
41.6 °C/W
10.7 °C/W
2403 mW
(1) Mounting per the PowerPADTM Thermally Enhanced Package application report (SLMA002)
(2) The JEDEC high-K (2s2p) board used to derive this data was a 3in × 3in, multilayer board with 1-ounce internal power and ground
planes and 2-ounce copper traces on top and bottom of the board.
2
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SLVSB28 –DECEMBER 2011
RECOMMENDED OPERATING CONDITIONS
MIN
2.5
0
MAX
6.5
UNIT
VIN
Input voltage, IN
Enable voltage
V
VENx
VENx
VIH
TPS2560A
TPS2561A
6.5
V
V
0
6.5
High-level input voltage on ENx or ENx
Low-level input voltage on ENx or ENx
1.1
VIL
0.66
2.5
IOUTx
Continuous output current per channel, OUTx
Continuous FAULTx sink current
0
0
A
10
mA
°C
TJ
Operating virtual junction temperature
Recommended resistor limit range
–40
20
125
187
RILIM
kΩ
ELECTRICAL CHARACTERISTICS
over recommended operating conditions, V/ENx = 0 V, or VENx = VIN (unless otherwise noted)
PARAMETER
TEST CONDITIONS(1)
MIN
TYP MAX UNIT
POWER SWITCH
TJ = 25 °C
44
50
70
4
Static drain-source on-state
resistance per channel, IN to OUTx
rDS(on)
mΩ
–40 °C ≤TJ ≤125 °C
VIN = 6.5 V
2
1
3
2
tr
tf
Rise time, output
Fall time, output
VIN = 2.5 V
3
CLx = 1 μF, RLx = 100 Ω,
(see Figure 2)
ms
VIN = 6.5 V
0.6
0.4
0.8
0.6
1.0
0.8
VIN = 2.5 V
ENABLE INPUT EN OR EN
Enable pin turn on/off threshold
0.66
1.1
V
Hysteresis
55(2)
mV
μA
ms
ms
IEN
ton
toff
Input current
Turnon time
Turnoff time
VENx = 0 V or 6.5 V, V/ENx = 0 V or 6.5 V
–0.5
0.5
9
CLx = 1 μF, RLx = 100 Ω, (see Figure 2)
6
CURRENT LIMIT
OUTx connected to GND
RILIM = 24.3 kΩ±1%
RILIM = 47.5 kΩ±1%
2100 2300 2500
2100 2300 2500
3.5(2)
IOS
Current-limit (see Figure 4)
Response time to short circuit
mA
OUT1 and OUT2 connected to GND
VIN = 5.0 V (see Figure 3)
tIOS
μs
(1) Pulse-testing techniques maintain junction temperature close to ambient temperature; thermal effects must be taken into account
separately.
(2) These parameters are provided for reference only, and do not constitute part of TI's published specifications for purposes of TI's product
warranty.
Copyright © 2011, Texas Instruments Incorporated
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ELECTRICAL CHARACTERISTICS (continued)
over recommended operating conditions, V/ENx = 0 V, or VENx = VIN (unless otherwise noted)
PARAMETER
TEST CONDITIONS(1)
MIN
TYP MAX UNIT
SUPPLY CURRENT
IIN_off
IIN_on
IREV
Supply current, low-level output
Supply current, high-level output
Reverse leakage current
VIN = 6.5 V, No load on OUTx, V ENx = 6.5 V or VENx = 0 V
0.1
100
85
2.0
125
110
1.0
μA
μA
μA
μA
RILIM = 20 kΩ
VIN = 6.5 V, No load on OUT
RILIM = 100 kΩ
VOUTx = 6.5 V, VIN = 0 V
TJ = 25°C
0.01
UNDERVOLTAGE LOCKOUT
UVLO Low-level input voltage, IN
Hysteresis, IN
FAULTx FLAG
VOL Output low voltage, FAULTx
VIN rising
2.35
35
2.45
V
TJ = 25°C
mV
I FAULTx = 1 mA
V FAULTx = 6.5 V
180
1
mV
μA
ms
Off-state leakage
FAULTx deglitch
FAULTx assertion or de-assertion due to overcurrent condition
6
9
13
THERMAL SHUTDOWN
OTSD2
OTSD
Thermal shutdown threshold
155
135
°C
°C
°C
Thermal shutdown threshold in
current-limit
Hysteresis
20(3)
(3) These parameters are provided for reference only, and do not constitute part of TI's published specifications for purposes of TI's product
warranty.
4
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SLVSB28 –DECEMBER 2011
DEVICE INFORMATION
Pin Functions
PIN
TPS2560A
4
I/O
DESCRIPTION
NAME
EN1
TPS2561A
-
I
I
I
I
Enable input, logic low turns on channel one
power switch
EN1
-
5
4
Enable input, logic high turns on channel one
power switch
-
Enable input, logic low turns on channel two
power switch
EN2
EN2
-
5
Enable input, logic high turns on channel two
power switch
GND
IN
1
1
Ground connection; connect externally to
PowerPAD
2, 3
2, 3
I
Input voltage; connect a 0.1 μF or greater
ceramic capacitor from IN to GND as close to the
IC as possible.
FAULT1
FAULT2
10
6
10
6
O
O
Active-low open-drain output, asserted during
overcurrent or overtemperature condition on
channel one.
Active-low open-drain output, asserted during
overcurrent or overtemperature condition on
channel two
OUT1
OUT2
ILIM
9
8
7
9
8
7
O
O
O
Power-switch output for channel one
Power-switch output for channel two
External resistor used to set current-limit
threshold; recommended 20 kΩ ≤ RILIM ≤ 187 kΩ.
Internally connected to GND; used to heat-sink
the part to the circuit board traces. Connect
PowerPAD to GND pin externally.
PowerPAD
™
PAD
PAD
FUNCTIONAL BLOCK DIAGRAM
Current
Sense
CS
IN
OUT1
FAULT1
9-ms Deglitch
Thermal
Sense
Charge
Pump
Current
EN1
EN2
Driver
Limit
ILIM
FAULT2
UVLO
Thermal
Sense
9-ms Deglitch
GND
CS
OUT2
Current
Sense
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SLVSB28 –DECEMBER 2011
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PARAMETER MEASUREMENT INFORMATION
OUTx
tr
tf
RLx
CLx
90%
10%
VOUTx
90%
10%
TEST CIRCUIT
VENx
50%
50%
50%
ton
50%
VENx
toff
ton
toff
90%
90%
VOUTx
VOUTx
10%
10%
VOLTAGE WAVEFORMS
Figure 2. Test Circuit and Voltage Waveforms
IOS
IOUTx
tIOS
Figure 3. Response Time to Short Circuit Waveform
Decreasing
Load Resistance
V
OUTx
Decreasing
Load Resistance
I
OUTx
I
OS
Figure 4. Output Voltage vs. Current-Limit Threshold
6
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SLVSB28 –DECEMBER 2011
TYPICAL CHARACTERISTICS
TPS2560A/61A
VIN = 5V
0.1 uF
VOUT1
IN
IN
OUT1
OUT2
2x RFAULT
100 kΩ
VOUT2
24.9kΩ
2x 150 µF
ILIM
FAULT 1
FAULT 2
EN1
Faultx Signals
Control Signals
GND
EN2
Power Pad
Figure 5. Typical Characteristics Reference Schematic
V
OUT1
5 V/div
V
OUT1
5 V/div
V
OUT2
5 V/div
V
OUT2
5 V/div
VEN1_bar
VEN1_bar
5 V/div
VEN1_bar = VEN2_bar
VEN1_bar = VEN2_bar
5 V/div
I
I
IN
2 A/div
IN
2 A/div
t - Time - 2 ms/div
t - Time - 2 ms/div
Figure 6. Turn-on Delay and Rise Time
Figure 7. Turn-off Delay and Fall Time
V
V
OUT1
5 V/div
OUT1
5 V/div
V
OUT2
5 V/div
V
OUT2
5 V/div
FAULT2_bar
5 V/div
FAULT2_bar
5 V/div
I
I
IN
2 A/div
IN
2 A/div
t - Time - 20 ms/div
t - Time - 20 ms/div
Figure 8. Full-Load to Short-Circuit Transient Response
Figure 9. Short-Circuit to Full-Load Recovery Response
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TYPICAL CHARACTERISTICS (continued)
700
2.335
2.33
600
2.325
500
400
300
200
100
UVLO Rising
2.32
V
= 6.5 V
2.315
2.31
IN
2.305
V
= 2.5 V
IN
UVLO Falling
2.3
0
2.295
-100
-50
2.29
-50
0
50
- Junction Temperature - °C
100
150
0
50
100
150
T
J
T
- Junction Temperature - °C
J
Figure 10. UVLO – Undervoltage Lockout – V
Figure 11. IIN – Supply Current, Output Disabled – nA
120
120
110
100
V
= 6.5 V
V
= 5 V
IN
IN
RILIM = 20kΩ
TJ = 125°C
100
80
V
= 3.3 V
V
= 2.5 V
IN
IN
60
40
90
80
TJ = -40°C
R
= 20 kΩ
TJ = 25°C
ILIM
20
0
70
60
-50
0
50
- Junction Temperature - °C
100
150
2
3
4
5
6
7
T
J
Input Voltage - V
Figure 12. IIN – Supply Current, Output Enabled – µA
Figure 13. IIN – Supply Current, Output Enabled – µA
70
60
0.6
0.5
0.4
T
= -40°C
= 25°C
A
50
40
T
A
T
= 125°C
0.3
0.2
A
30
20
10
0
R
= 100 kW
ILIM
0.1
0
0
50
100
150
200
-50
0
50
100
150
V
- V
- mV/div
OUT
IN
T
- Junction Temperature - °C
J
Figure 14. MOSFET rDS(on) Vs. Junction Temperature
Figure 15. Switch Current Vs. Drain-Source Voltage
Across Switch
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SLVSB28 –DECEMBER 2011
TYPICAL CHARACTERISTICS (continued)
3.0
1.0
0.9
0.8
0.7
2.5
TJ = -40°C
T
= -40°C
= 25°C
2.0
A
0.6
0.5
0.4
0.3
0.2
TJ = 25°C
T
A
1.5
T
= 125°C
A
1.0
TJ = 125°C
RILIM = 20kΩ
R
= 61.9 kW
ILIM
0.5
0
0.1
0
0
20
40
60
80
100
- mV/div
120
140
160
0
50
100
150
200
V
- V
OUT
VIN-VOUT - mV
IN
Figure 16. Switch Current Vs. Drain-Source Voltage
Across Switch
Figure 17. Switch Current vs. Drain-Source Voltage
Across Switch
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DETAILED DESCRIPTION
OVERVIEW
The TPS2560A/61A is a dual-channel, current-limited power-distribution switch using N-channel MOSFETs for
applications where short circuits or heavy capacitive loads will be encountered. This device allows the user to
program the current-limit threshold between 250 mA and 2.8 A (typ) per channel via an external resistor. This
device incorporates an internal charge pump and gate drive circuitry necessary to drive the N-channel
MOSFETs. The charge pump supplies power to the driver circuit for each channel and provides the necessary
voltage to pull the gate of the MOSFET above the source. The charge pump operates from input voltages as low
as 2.5 V and requires little supply current. The driver controls the gate voltage of the power switch. The driver
incorporates circuitry that controls the rise and fall times of the output voltage to limit large current and voltage
surges and provides built-in soft-start functionality. Each channel of the TPS2560A/61A limits the output current
to the programmed current-limit threshold IOS during an overcurrent or short-circuit event by reducing the charge
pump voltage driving the N-channel MOSFET and operating it in the linear range of operation. The result of
limiting the output current to IOS reduces the output voltage at OUTx because the N-channel MOSFET is no
longer fully enhanced.
OVERCURRENT CONDITIONS
The TPS2560A/61A responds to overcurrent conditions by limiting the output current per channel to IOS. When
an overcurrent condition is detected, the device maintains a constant output current and reduces the output
voltage accordingly. Two possible overload conditions can occur.
The first condition is when a short circuit or partial short circuit is present when the device is powered-up or
enabled. The output voltage is held near zero potential with respect to ground and the TPS2560A/61A ramps the
output current to IOS. The TPS2560A/61A devices will limit the current to IOS until the overload condition is
removed or the device begins to thermal cycle.
The second condition is when a short circuit, partial short circuit, or transient overload occurs while the device is
enabled and powered on. The device responds to the overcurrent condition within time tIOS (see Figure 3). The
current-sense amplifier is overdriven during this time and momentarily disables the internal current-limit
MOSFET. The current-sense amplifier recovers and ramps the output current to IOS. Similar to the previous case,
the TPS2560A/61A will limit the current to IOS until the overload condition is removed or the device begins to
thermal cycle.
The TPS2560A/61A thermal cycles if an overload condition is present long enough to activate thermal limiting in
any of the above cases. The device turns off when the junction temperature exceeds 135°C (min) while in current
limit. The device remains off until the junction temperature cools 20°C (typ) and then restarts. The
TPS2560A/61A cycles on/off until the overload is removed (see Figure 9) .
10
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SLVSB28 –DECEMBER 2011
FAULTx RESPONSE
The FAULTx open-drain outputs are asserted (active low) on an individual channel during an overcurrent or
overtemperature condition. The TPS2560A/61A asserts the FAULTx signal until the fault condition is removed
and the device resumes normal operation on that channel. The TPS2560A/61A is designed to eliminate false
FAULTx reporting by using an internal delay "deglitch" circuit (9-ms typ) for overcurrent conditions without the
need for external circuitry. This ensures that FAULTx is not accidentally asserted due to normal operation such
as starting into a heavy capacitive load. The deglitch circuitry delays entering and leaving current-limited induced
fault conditions. The FAULTx signal is not deglitched when the MOSFET is disabled due to an overtemperature
condition but is deglitched after the device has cooled and begins to turn on. This unidrectional deglitch prevents
FAULTx oscillation during an overtemperature event.
UNDERVOLTAGE LOCKOUT (UVLO)
The undervoltage lockout (UVLO) circuit disables the power switch until the input voltage reaches the UVLO
turn-on threshold. Built-in hysteresis prevents unwanted on/off cycling due to input voltage droop during turn on.
ENABLE (ENx OR ENx)
The logic enables control the power switches and device supply current. The supply current is reduced to less
than 2-μA when a logic high is present on ENx or when a logic low is present on ENx. A logic low input on ENx
or a logic high input on ENx enables the driver, control circuits, and power switches. The enable inputs are
compatible with both TTL and CMOS logic levels.
THERMAL SENSE
The TPS2560A/61A self protects by using two independent thermal sensing circuits that monitor the operating
temperature of the power switch and disable operation if the temperature exceeds recommended operating
conditions. Each channel of the TPS2560A/61A operates in constant-current mode during an overcurrent
conditions, which increases the voltage drop across the power switch. The power dissipation in the package is
proportional to the voltage drop across the power switch, which increases the junction temperature during an
overcurrent condition. The first thermal sensor (OTSD) turns off the individual power switch channel when the die
temperature exceeds 135°C (min) and the channel is in current limit. Hysteresis is built into the thermal sensor,
and the switch turns on after the device has cooled approximately 20°C.
The TPS2560A/61A also has a second ambient thermal sensor (OTSD2). The ambient thermal sensor turns off
both power switch channels when the die temperature exceeds 155°C (min) regardless of whether the power
switch channels are in current limit and will turn on the power switches after the device has cooled approximately
20°C. The TPS2560A/61A continues to cycle off and on until the fault is removed.
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APPLICATION INFORMATION
INPUT AND OUTPUT CAPACITANCE
Input and output capacitance improves the performance of the device; the actual capacitance should be
optimized for the particular application. For all applications, a 0.1μF or greater ceramic bypass capacitor between
IN and GND is recommended as close to the device as possible for local noise decoupling. This precaution
reduces ringing on the input due to power-supply transients. Additional input capacitance may be needed on the
input to reduce voltage overshoot from exceeding the absolute maximum voltage of the device during heavy
transient conditions. This is especially important during bench testing when long, inductive cables are used to
connect the evaluation board to the bench power supply.
Output capacitance is not required, but placing a high-value electrolytic capacitor on the output pin is
recommended when large transient currents are expected on the output.
PROGRAMMING THE CURRENT-LIMIT THRESHOLD
The overcurrent threshold is user programmable via an external resistor, RILIM. RILIM sets the current-limit
threshold for both channels. The TPS2560A/61A use an internal regulation loop to provide a regulated voltage on
the ILIM pin. The current-limit threshold is proportional to the current sourced out of ILIM. The recommended 1%
resistor range for RILIM is 20 kΩ ≤ RILIM ≤ 187 kΩ to ensure stability of the internal regulation loop. Many
applications require that the minimum current limit is above a certain current level or that the maximum current
limit is below a certain current level, so it is important to consider the tolerance of the overcurrent threshold when
selecting a value for RILIM. The following equations calculates the resulting overcurrent threshold for a given
external resistor value (RILIM). The traces routing the RILIM resistor to the TPS2560A/61A should be as short as
possible to reduce parasitic effects on the current-limit accuracy.
52850V
RILIM0.957kW
IOSmax (mA) =
56000V
IOSnom(mA) =
RILIMkW
61200V
RILIM1.056kW
IOSmin(mA) =
(1)
3000
2750
2500
2250
2000
1750
1500
1250
1000
IOS(max)
750
500
250
0
IOS(typ)
IOS(min)
20
30
40
50
60
70
80
90
100
110
RILIM – Current Limit Resistor – kΩ
120
130
140
150
Figure 18. Current-Limit Threshold vs. RILIM
12
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SLVSB28 –DECEMBER 2011
APPLICATION 1: DESIGNING ABOVE A MINIMUM CURRENT LIMIT
Some applications require that current limiting cannot occur below a certain threshold. For this example, assume
that 2 A must be delivered to the load so that the minimum desired current-limit threshold is 2000 mA. Use the
IOS equations and Figure 18 to select RILIM
IOSmin(mA) = 2000mA
.
61200V
RILIM1.056kW
IOSmin(mA) =
1
æ
ç
ç
ö1.056
61200V
÷
÷
÷
÷
ø
RILIM(kW) =
ç
ç
I
mA
è OSmin
RILIM(kW) = 25.52kW
(2)
Select the closest 1% resistor less than the calculated value: RILIM = 25.5 kΩ. This sets the minimum current-limit
threshold at 2 A . Use the IOS equations, Figure 18, and the previously calculated value for RILIM to calculate the
maximum resulting current-limit threshold.
RILIM(kW) = 25.5kW
52850V
IOSmax (mA) =
RILIM0.957kW
52850V
IOSmax (mA) =
25.50.957kW
IOSmax (mA) = 2382mA
(3)
The resulting maximum current-limit threshold is 2382 mA with a 25.5 kΩ resistor.
APPLICATION 2: DESIGNING BELOW A MAXIMUM CURRENT LIMIT
Some applications require that current limiting must occur below a certain threshold. For this example, assume
that the desired upper current-limit threshold must be below 1000 mA to protect an up-stream power supply. Use
the IOS equations and Figure 18 to select RILIM
IOSmax (mA) = 1000mA
.
52850V
RILIM0.957kW
IOSmax (mA) =
1
æ
ç
ç
ö0.957
52850V
mA
÷
÷
÷
÷
ø
RILIM(kW) =
ç
ç
I
è OSmax
RILIM(kW) = 63.16kW
(4)
Select the closest 1% resistor greater than the calculated value: RILIM = 63.4 kΩ. This sets the maximum
current-limit threshold at 1000 mA . Use the IOS equations, Figure 18, and the previously calculated value for
RILIM to calculate the minimum resulting current-limit threshold.
RILIM(kW) = 63.4kW
61200V
IOSmin(mA) =
RILIM1.056kW
61200V
IOSmin(mA) =
63.41.056kW
IOSmin(mA) = 765mA
(5)
The resulting minimum current-limit threshold is 765 mA with a 63.4 kΩ resistor.
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ACCOUNTING FOR RESISTOR TOLERANCE
The previous sections described the selection of RILIM given certain application requirements and the importance
of understanding the current-limit threshold tolerance. The analysis focused only on the TPS2560A/61A
performance and assumed an exact resistor value. However, resistors sold in quantity are not exact and are
bounded by an upper and lower tolerance centered around a nominal resistance. The additional RILIM resistance
tolerance directly affects the current-limit threshold accuracy at a system level. The following table shows a
process that accounts for worst-case resistor tolerance assuming 1% resistor values. Step one follows the
selection process outlined in the application examples above. Step two determines the upper and lower
resistance bounds of the selected resistor. Step three uses the upper and lower resistor bounds in the IOS
equations to calculate the threshold limits. It is important to use tighter tolerance resistors, e.g. 0.5% or 0.1%,
when precision current limiting is desired.
Table 1. Common RILIM Resistor Selections
Resistor Tolerance
Actual Limits
Ideal
Resistor
(kΩ)
Closest 1%
Resistor
(kΩ)
Desired Nominal
Current Limit (mA)
IOS MIN
(mA)
IOS Nom
(mA)
IOS MAX
(mA)
1% low (kΩ) 1% high (kΩ)
300
400
186.7
140.0
93.3
70.0
56.0
46.7
40.0
35.0
31.1
28.0
25.5
23.3
21.5
20.0
187
140
93.1
69.8
56.2
46.4
40.2
34.8
30.9
28
185.1
138.6
92.2
69.1
55.6
45.9
39.8
34.5
30.6
27.7
25.2
23.0
21.3
19.8
188.9
141.4
94.0
70.5
56.8
46.9
40.6
35.1
31.2
28.3
25.8
23.4
21.7
20.2
241.6
328.0
299.5
400.0
357.3
471.4
600
504.6
601.5
696.5
800
684.0
802.3
917.6
1000
1200
1400
1600
1800
2000
2200
2400
2600
2800
859.9
996.4
1129.1
1356.3
1555.9
1786.2
2001.4
2199.3
2405.3
2633.0
2831.9
3034.8
1052.8
1225.0
1426.5
1617.3
1794.7
1981.0
2188.9
2372.1
2560.4
1206.9
1393.0
1609.2
1812.3
2000.0
2196.1
2413.8
2604.7
2800.0
25.5
23.2
21.5
20
14
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SLVSB28 –DECEMBER 2011
POWER DISSIPATION AND JUNCTION TEMPERATURE
The low on-resistance of the N-channel MOSFET allows small surface-mount packages to pass large currents. It
is good design practice to estimate power dissipation and junction temperature. The below analysis gives an
approximation for calculating junction temperature based on the power dissipation in the package. However, it is
important to note that thermal analysis is strongly dependent on additional system level factors. Such factors
include air flow, board layout, copper thickness and surface area, and proximity to other devices dissipating
power. Good thermal design practice must include all system level factors in addition to individual component
analysis.
Begin by determining the rDS(on) of the N-channel MOSFET relative to the input voltage and operating
temperature. As an initial estimate, use the highest operating ambient temperature of interest and read rDS(on)
from the typical characteristics graph. Using this value, the power dissipation can be calculated by:
2
PD = (RDS(on) × IOUT1 2) +(RDS(on) × IOUT2
)
Where:
PD = Total power dissipation (W)
rDS(on) = Power switch on-resistance of one channel (Ω)
IOUTx = Maximum current-limit threshold set by RILIM(A)
This step calculates the total power dissipation of the N-channel MOSFET.
Finally, calculate the junction temperature:
TJ = PD × θJA + TA
Where:
TA = Ambient temperature (°C)
θJA = Thermal resistance (°C/W)
PD = Total power dissipation (W)
Compare the calculated junction temperature with the initial estimate. If they are not within a few degrees, repeat
the calculation using the "refined" rDS(on) from the previous calculation as the new estimate. Two or three
iterations are generally sufficient to achieve the desired result. The final junction temperature is highly dependent
on thermal resistance θJA, and thermal resistance is highly dependent on the individual package and board
layout. The Dissipating Rating Table provides example thermal resistances for specific packages and board
layouts.
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SLVSB28 –DECEMBER 2011
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AUTO-RETRY FUNCTIONALITY
Some applications require that an overcurrent condition disables the part momentarily during a fault condition
and re-enables after a pre-set time. This auto-retry functionality can be implemented with an external resistor and
capacitor. During a fault condition, FAULTx pulls ENx low disabling the part. The part is disabled when ENx is
pulled below the turn-off threshold, and FAULTx goes high impedance allowing CRETRY to begin charging. The
part re-enables when the voltage on ENx reaches the turn-on threshold, and the auto-retry time is determined by
the resistor/capacitor time constant. The part will continue to cycle in this manner until the fault condition is
removed.
TPS2561A
Input
0.1 μF
VOUT1
VOUT2
OUT1
OUT2
IN
RFAULT
2x 100 kΩ
2x CLOAD
ILIM
RILIM
20 kΩ
FAULT1
EN1
GND
FAULT2
EN2
CRETRY
2x 0.22 µF
Power Pad
Figure 19. Auto-Retry Functionality
Some applications require auto-retry functionality and the ability to enable/disable with an external logic signal.
The figure below shows how an external logic signal can drive EN through RFAULT and maintain auto-retry
functionality. The resistor/capacitor time constant determines the auto-retry time-out period.
TPS2561A
Input
0.1 μF
OUT1
OUT2
VOUT1
VOUT2
IN
External Logic
Signal & Drivers
2x CLOAD
RFAULT
2x 100 kΩ
ILIM
RILIM
20 kΩ
FAULT1
EN1
GND
FAULT2
EN2
CRETRY
2x 0.22 µF
Power Pad
Figure 20. Auto-Retry Functionality With External EN Signal
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SLVSB28 –DECEMBER 2011
TWO-LEVEL CURRENT-LIMIT CIRCUIT
Some applications require different current-limit thresholds depending on external system conditions. Figure 21
shows an implementation for an externally controlled, two-level current-limit circuit. The current-limit threshold is
set by the total resistance from ILIM to GND (see previously discussed Programming the Current-Limit Threshold
section). A logic-level input enables/disables MOSFET Q1 and changes the current-limit threshold by modifying
the total resistance from ILIM to GND. Additional MOSFET/resistor combinations can be used in parallel to
Q1/R2 to increase the number of additional current-limit levels.
NOTE
ILIM should never be driven directly with an external signal.
TPS2560A/61A
0.1 μF
2.5V – 6.5V
VOUT1
IN
IN
OUT1
OUT2
2x RFAULT
100 kΩ
VOUT2
2x CLOAD
R1
187 kΩ
Fault Signal
FAULT1
FAULT2
EN1
ILIM
Fault Signal
Control Signal
Control Signal
R2
22.1 kΩ
GND
EN2
Power Pad
Q1
Current Limit
Control Signal
Figure 21. Two-Level Current-Limit Circuit
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PACKAGE OPTION ADDENDUM
www.ti.com
6-Apr-2012
PACKAGING INFORMATION
Status (1)
Eco Plan (2)
MSL Peak Temp (3)
Samples
Orderable Device
Package Type Package
Drawing
Pins
Package Qty
Lead/
Ball Finish
(Requires Login)
TPS2560ADRCR
TPS2560ADRCT
TPS2561ADRCR
TPS2561ADRCT
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SON
SON
SON
SON
DRC
DRC
DRC
DRC
10
10
10
10
3000
250
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
3000
250
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
23-Jun-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS2560ADRCR
TPS2561ADRCR
TPS2561ADRCT
SON
SON
SON
DRC
DRC
DRC
10
10
10
3000
3000
250
330.0
330.0
180.0
12.4
12.4
12.4
3.3
3.3
3.3
3.3
3.3
3.3
1.1
1.1
1.1
8.0
8.0
8.0
12.0
12.0
12.0
Q2
Q2
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
23-Jun-2012
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPS2560ADRCR
TPS2561ADRCR
TPS2561ADRCT
SON
SON
SON
DRC
DRC
DRC
10
10
10
3000
3000
250
346.0
346.0
210.0
346.0
346.0
185.0
29.0
29.0
35.0
Pack Materials-Page 2
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