TPS2586X-Q1_技术文档

TPS25860-Q1, TPS25862-Q1

SLVSFP0 – AUGUST 2021

TPS2586x-Q1 2.2-MHz, Low EMI Dual USB Type-A and Type-C^®Charging Ports

Controller With Sync DC/DC Converter and Programmable Current Limit

•

3-A capability advertisement on CC

V_BUSapplication and discharge

V_CONNsource: 200 mA

1 Features

•

AEC-Q100 qualified for automotive applications:

– Temperature grade 1: T_Arange –40°C to

+125°C

– HBM ESD classification level H2

– CDM ESD classification level C5

Optimized for ultra-low EMI requirements:

– Meets CISPR25 class 5 standard

– HotRod^™package minimizes switch node

ringing

– Automatic DCP modes (TPS25860-Q1):

•

Shorted mode per BC1.2 and YD/T 1591

2009

1.2-V mode

2.7-V Divider 3 mode

•

Load shedding versus programmable T_A

Device T_Jrange: –40°C to +150°C

FAULT flag reports (TPS25862-Q1): USB

overcurrent, thermal shutdown

– Spread spectrum reduces peak emissions

Synchronous buck regulator

•

USB ports ON and OFF control (TPS25862-Q1)

– High efficiency at 2.2 MHz: 93.6% at V_IN= 12 V,

I_{PA_BUS}= 3 A and I_{PB_BUS}= 2.4 A

– 18-mΩ/10-mΩ low R_DS(ON)buck regulator

MOSFETs

2 Applications

•

Automotive USB charging ports

Automotive USB media hubs

– Operating voltage range: 5.5 V to 26 V,

withstand 36-V input

– Adjustable frequency: 200 kHz to 3 MHz

– FPWM with spread-spectrum dithering

– Selectable output voltage: 5.1 V, 5.17 V, 5.3 V,

5.4 V

3 Description

The TPS2586x-Q1 is an integrated USB charging

port solution, which includes a synchronous, high

efficiency DC/DC converter and integrated detection

and control for implementing USB Battery Charging

1.2 and Type-C ports.

•

Internal power path:

Device Information⁽¹⁾

– 7-mΩ/7-mΩ low R_DS(ON)internal USB power

MOSFETs

– Programmable current limit for USB ports with

high accuracy: ±10% at 3.4 A

– OUT: 5.1-V, 200-mA supply for auxiliary loads

Line drop compensation: 90 mV at 2.4-A load

Compliant to USB-IF standards

– Type-C rev 1.3

PART NUMBER

TPS25860-Q1

TPS25862-Q1

PACKAGE

BODY SIZE (NOM)

VQFN-HR (25) 3.50 mm × 4.50 mm

•

(1) For detail part numbers for all available different options, see

the orderable addendum at the end of the data sheet.

100

95

90

85

80

75

70

VIN=6V

2.1MHz

65

60

VIN=13.5V 2.1MHz

VIN=18V 2.1MHz

0.1

1

2

3

4

5

6

Load Current(A)

Efficiency vs Output Current

Simplified Schematic: TPS2586x-Q1

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

TPS25860-Q1, TPS25862-Q1

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Table of Contents

1 Features............................................................................1

2 Applications.....................................................................1

3 Description.......................................................................1

4 Revision History.............................................................. 2

5 Description (continued).................................................. 3

6 Device Comparison Table...............................................4

7 Pin Configuration and Functions...................................4

8 Specifications.................................................................. 7

8.1 Absolute Maximum Ratings........................................ 7

8.2 ESD Ratings............................................................... 7

8.3 Recommended Operating Conditions.........................8

8.4 Thermal Information....................................................8

8.5 Electrical Characteristics.............................................9

8.6 Timing Requirements................................................12

8.7 Switching Characteristics..........................................13

8.8 Typical Characteristics..............................................14

9 Parameter Measurement Information..........................19

10 Detailed Description....................................................19

10.1 Overview.................................................................19

10.2 Functional Block Diagram.......................................20

10.3 Feature Description.................................................21

10.4 Device Functional Modes........................................36

11 Application and Implementation................................ 37

11.1 Application Information............................................37

11.2 Typical Applications.................................................37

12 Power Supply Recommendations..............................47

13 Layout...........................................................................48

13.1 Layout Guidelines................................................... 48

13.2 Layout Example...................................................... 49

13.3 Ground Plane and Thermal Considerations............49

14 Device and Documentation Support..........................51

14.1 Receiving Notification of Documentation Updates..51

14.2 Support Resources................................................. 51

14.3 Trademarks.............................................................51

14.4 Electrostatic Discharge Caution..............................51

14.5 Glossary..................................................................51

15 Mechanical, Packaging, and Orderable

Information.................................................................... 51

4 Revision History

DATE

REVISION

NOTES

August 2021

*

Initial release

2

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5 Description (continued)

The TPS2586x-Q1 is a family of highly-integrated USB charging controller for Type-C and Type-A dual ports

application.

The device integrates a monolithic, synchronous, rectified, step-down, switch-mode converter with internal power

MOSFETs and two USB current-limit switches with charging port auto-detection. The TPS2586x-Q1 offers a

compact solution with excellent load and line regulation over a wide input supply range. The synchronous

buck regulator operates with peak-current mode control and is internally compensated to simplify the design. A

resistor on the FREQ pin sets the switching frequency between 200 kHz and 3 MHz. Operating below 400 kHz

results in better system efficiency and operation above 2.1 MHz avoids the AM radio bands and allows for use of

a smaller inductor.

The TPS2586x-Q1 integrates standard USB Type-C^®port controller functionality including Configuration

Channel (CC) logic for 3-A and 1.5-A current advertisement. Battery Charging (Rev. 1.2) integration provides the

required electrical signatures necessary for non-Type-C, legacy USB devices which use USB data line signaling

to determine USB port current sourcing capabilities. The TPS2586x-Q1 also has integrated VCONN power that

can meet the USB3.1 power requirement. The part is especially suitable for dual-port application due to the high

system integration and small footprint.

Since the TPS2586x-Q1 supports intelligent thermal regulation, the output current and voltage can be regulated

according to the temperature sensing through the TS pin. The device needs to connect a NTC thermistor on the

TS pin to monitor the ambient temperature or PCB board temperature, depending on where the NTC thermistor

is put in the USB charging module or PCB board. Select a different NTC thermistor and bottom-side series

resistor can change the temperature for load shedding.

The TPS2586x-Q1 have four selectable USB output voltage settings: 5.1 V, 5.17 V, 5.3 V, and 5.4 V.

The TPS2586x-Q1 integrates a precision current sense amplifier for cable droop compensation and user-

programmable current limit tuning. The cable compensation is only available when the output voltage is set

to 5.17 V. The cable compensation voltage is 90 mV at 2.4-A output current. Cable compensation aids portable

devices in charging at optimum current and voltage under heavy loads by changing the buck regulator output

voltage linearly with load current to counteract the voltage drop due to wire resistance in automotive cabling.

The BUS voltage measured at a connected portable device remains approximately constant, regardless of load

current, allowing the battery charger of the portable device to work optimally.

The TPS2586x-Q1 provides various safety features for USB charging and system operations, including external

negative thermistor monitoring, cycle-by-cycle current limit, hiccup short-circuit protection, undervoltage lockout,

BUS overcurrent, OUT overcurrent, and die overtemperature protection.

The device family is available in 25-pin, 3.5-mm × 4.5-mm QFN package.

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6 Device Comparison Table

DEVICE NUMBER

TPS25860-Q1

TPS25862-Q1

USB ports Number

Dual

Support Type-C Protocol

NTC Thermistor Input (TS)

USB Load Switch ON/OFF Control

Fault Event Indication

Yes, only Port A

Yes

No

Yes

No

Support MFi new OCP

Yes

External Clock Synchronization

Yes, range 200 kHz to approximately 3 MHz Yes, range 200 kHz to approximately 3

MHz

BC1.2 DCP

Yes

No

Apple and Samsung charging scheme

Cable Compensation

Selectable Output Voltage

Adjustable Output Short Current Limit

FPWM/PFM

Yes

No

Yes⁽¹⁾

Yes

FPWM

DCDC always ON (EN pull High)

Spread Spectrum

Yes

Package

QFN-25 3.5 mm × 4.5 mm

(1) VSET short to GND to set 5.17-V output voltage. Compensation voltage is 90 mV when either USB port A or USB port B output 2.4-A

current.

7 Pin Configuration and Functions

Figure 7-1. TPS25860 RPQ Package 25-Pin (QFN)

Top View

Figure 7-2. TPS25862 RPQ Package 25-Pin (QFN)

Top View

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Table 7-1. Pin Functions for TPS25860 RPQ Package

NAME

NO.

TYPE ⁽¹⁾

DESCRIPTION

Output Voltage Setting. Short to GND to set the 5.17-V output voltage. Float or pull up to

V_SENSEto set 5.1-V output voltage. Tie to GND through a 40.2-KΩ resistor to set 5.3-V

output voltage. Tie to GND through a 80.6-KΩ resistor to set 5.4-V output voltage.

VSET

1

A

TS

2

3

A

P

Temperature Sense terminal. Connect the TS input to the NTC thermistor.

Input of internal bias supply. Must connect to the SENSE pin directly. Power the internal

circuit.

BIAS

PA_DP

PA_DM

AGND

4

5

6

7

8

A

P

A

D+ data line. Connect to USB Port A connector.

D- data line. Connect to USB Port A connector.

Analog ground terminal. Connect AGND to PGND.

Connect to Type-C Port A CC1 pin. Analog Input/Output

Connect to Type-C Port A CC2 pin. Analog Input/Output

PA_CC1

PA_CC2

Current Limit program. Connect a resistor to set the current limit threshold. Short to GND

to set the default 3.55-A current limit for Port A, and 2.84-A current limit for Port B.

ILIM

9

A

P

PA_BUS

SENSE

PB_BUS

OUT

10

11

12

13

Port A BUS output

Output Voltage Sensing. External load on this pin is strictly prohibited. Connect to the

other side of the external inductor.

Port B BUS output

Output pin. Provide 5.1-V voltage to power external load with max 200-mA capability. The

voltage follows the VSET setting.

NC

14

15

A

Makes no electrical connection.

CFG

Configuration pin. For internal circuit, must connect a 5.1-KΩ resistor to AGND.

Power Ground terminal. Connected to the source of LS FET internally. Connect to system

ground, AGND, and the ground side of the C_INand C_OUTcapacitors. The path to C_INmust

be as short as possible.

PGND

16, 24, 25

P

PB_DM

PB_DP

17

18

A

D- data line. Connect to USB port B connector.

D+ data line. Connect to USB port B connector.

Switching Frequency Program and External Clock Input. Connect a resistor from FREQ to

GND to set the switching frequency.

FREQ/ SYNC

EN/UV

BOOT

IN

19

20

21

22

23

A

P

Enable pin. Precision enable controls the regulator switching action and type-C. Do not

float. High = on, Low = off. Can be tied to SENSE directly. Precision enable input allows

adjustable UVLO by external resistor divider if tie to IN pin.

Bootstrap capacitor connection. Internally, the BOOT is connected to the cathode of the

boost-strap diode. Connect the 0.1-μF bootstrap capacitor from SW to BOOT

Input power. Connected to external DC supply. Expected range of bypass capacitors is 1

μF to 10 μF, connect from IN to PGND. Can withstand up to 36 V without damage but

operating is suspended if VIN is above the 26-V OVP threshold.

Switching output of the regulator. Internally connected to source of the HS FET and drain

of the LS FET. Connect to output inductor.

SW

(1) A = Analog, P = Power, G = Ground.

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Table 7-2. Pin Functions for TPS25862 RPQ Package

NAME

NO.

TYPE ⁽¹⁾

DESCRIPTION

Output Voltage Setting. Short to GND to set the 5.17-V output voltage. Float or pull up to

V_SENSEto set 5.1-V output voltage. Tie to GND through a 40.2-KΩ resistor to set 5.3-V

output voltage. Tie to GND through a 80.6-KΩ resistor to set 5.4-V output voltage.

VSET

1

A

TS

2

3

A

P

Temperature Sense terminal. Connect the TS input to the NTC thermistor.

Input of internal bias supply. Must connect to the SENSE pin directly. Power the internal

circuit.

BIAS

USB Port A Fault Indication. /PA_FAULT indicates overcurrent on PA_BUS or

overtemperature conditions. /PA_FAULT is an open drain in normal conditions. Pull /

PA_FAULT low during fault conditions.

PA_FAULT

PA_EN

4

5

A

USB Port A Enable pin. To control the USB port A channel load switch ON/OFF. When

pull-low, the pin turns off the port A USB power and CC1/2 current and voltage. When

pull-high, the pin turns on the port A USB power and CC1/2 current and voltage. Can be

tied to SENSE directly to automatically turn on USB port.

AGND

PA_CC1

PA_CC2

6

7

8

P

A

Analog ground terminal. Connect AGND to PGND.

Connect to Type-C Port A CC1 pin. Analog Input/Output.

Connect to Type-C Port A CC2 pin. Analog Input/Output.

Current Limit program. Connect a resistor to set the current limit threshold. Short to GND

to set the default 3.55-A current limit for Port A, and 2.84-A current limit for Port B.

ILIM

9

A

P

PA_BUS

SENSE

PB_BUS

OUT

10

11

12

13

Port A BUS output

Output Voltage Sensing, external load on this pin is strictly prohibited. Connect to the other

side of the external inductor.

Port B BUS output

Output pin. Provide 5.1-V voltage to power external load with max 200-mA capability. The

voltage follows the VSET setting.

NC

14

15

A

Makes no electrical connection.

CFG

Configuration pin. For internal circuit, must connect a 5.1-KΩ resistor to AGND.

Power Ground Terminal. Connected to the source of LS FET internally. Connect to system

ground, AGND, and the ground side of C_INand C_OUTcapacitors. Path to C_INmust be as

short as possible.

PGND

16, 24, 25

17

P

A

USB Port B Enable pin. To control the USB port B channel load switch ON/OFF. When

pull-low, the pin turns off the port B USB power. When pull-high, the pin turns on the port B

USB power. Can be tied to SENSE directly to automatically turn on USB port.

PB_EN

USB Port B Fault Indication. /PB_FAULT indicates overcurrent on PB_BUS or

overtemperature conditions. /PB_FAULT is an open drain in normal conditions. Pull /

PB_FAULT low during fault conditions.

PB_FAULT

FREQ/ SYNC

EN/UV

BOOT

18

19

20

21

22

23

A

P

Switching Frequency Program and External Clock Input. Connect a resistor from FREQ to

GND to set the switching frequency.

Enable pin. Precision enable controls the regulator switching action and type-C. Do not

float. High = on, Low = off. Can be tied to SENSE directly. Precision enable input allows

adjustable UVLO by external resistor divider if tie to IN pin.

Bootstrap capacitor connection. Internally, the BOOT is connected to the cathode of the

bootstrap diode. Connect the 0.1-μF bootstrap capacitor from SW to BOOT.

Input power. Connected to external DC supply. Expected range of bypass capacitors is

1 μF to 10 μF. Connect from IN to PGND. Withstand up to 36 V without damage but

operating is suspended if VIN is above the 26-V OVP threshold.

IN

Switching output of the regulator. Internally connected to source of the HS FET and drain

of the LS FET. Connect to output inductor.

SW

(1) A = Analog, P = Power, G = Ground.

6

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8 Specifications

8.1 Absolute Maximum Ratings

Over the recommended operating junction temperature range of -40°C to +150°C and AGND = PGND (unless otherwise

noted)⁽¹⁾

PARAMETER

MIN

–0.3

-0.3

MAX

40⁽²⁾

35

6

UNIT

IN to PGND

IN to SW

SENSE to PGND

EN to AGND

11

6

Input voltage

V

FREQ/SYNC to AGND

PA_EN, PB_EN to AGND

VSET, ILIM to AGND

AGND to PGND

6

–0.3

–3.5

–0.3

0.3

6

Input voltage

PA_FAULT, PB_FAULT, FAULT to AGND

SW to PGND

V

26

35

6

SW to PGND (less than 10 ns transients)

BOOT to SW

Output voltage

PA_BUS, PB_BUS to PGND

CC1, CC2, CFG to AGND

DP, DM to AGND

6

Voltage range

V

PA_FAULT, PB_FAULT to AGND

TS to AGND

6

Pin positive sink current, I_SNKCC1, CC2 (while applying VCONN)

1

A

I/O current

DP to DM in BC1.2 DCP Mode

Junction temperature

–35

–40

–65

35

150

mA

°C

T_J

T_stg

Storage temperature

(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply

functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions.

If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully

functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.

(2) VIN rising slew rate below 20 V/ms if in 0 V to 36 V or above transient.

8.2 ESD Ratings

VALUE

±2000⁽²⁾

±750⁽³⁾

UNIT

Human body model (HBM), per AEC Q100-002⁽¹⁾

V_(ESD)Electrostatic discharge

Corner pins

V

Charged device model (CDM), per

AEC Q100-011

Other pins

(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

(2) The passing level per AEC-Q100 Classification H2.

(3) The passing level per AEC-Q100 Classification C5.

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8.3 Recommended Operating Conditions

Over the recommended operating junction temperature range of -40°C to 150°C. Voltages are with respect to GND (unless

otherwise noted)

MIN

5.5

0

NOM

MAX UNIT

IN to PGND

26

EN

VSENSE

V_I

Input voltage

TS

0

VSENSE

3.3

PA_EN, PB_EN

0

V

FREQ/SYNC when driven by external clock

0

V_PU

V_O

Pull up voltage

Output voltage

PA_FAULT, PB_FAULT

0

VSENSE

5.5

PA_BUS, PB_BUS

5

PA_BUS

0

3

A

PB_BUS

0

2.84

I_O

Output current

OUT

0

0.2

DP to DM Continuous current in BC1.2 DCP Mode

–15

15

CC1 or CC2 source current when supplying

VCONN

I_SRC

I_SNK

Source current

Sink current

250 mA

10

PA_FAULT, PB_FAULT

R_VSET

0

100

kΩ

uF

°C

R_EXT

External resistnace

External capacitance

R_ILIM

R_FREQ

C_EXT

T_J

C_BOOT

0.1

Operating junction temperature

–40

150

8.4 Thermal Information

TPS2586x-Q1

THERMAL METRIC^{(1) (2)}

RPQ (VQFN)

UNIT

25 PINS

30

R_θJA

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

°C/W

R_θJC(top)

R_θJB

17.6

7.2

Ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

1

Ψ_JB

7.2

R_θJC(bot)

12

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

(2) Power rating at a specific ambient temperature T_Ashould be determined with a maximum junction temperature of 150 °C.

8

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8.5 Electrical Characteristics

Limits apply over the recommended operating junction temperature (T_J) range of -40°C to +150°C; V_IN= 13.5 V, f_SW

=2.1MHz, VSET short to GND unless otherwise stated. Minimum and maximum limits are specified through test, design or

statistical correlation. Typical values represent the most likely parametric norm at T_J= 25°C, and are provided for reference

purposes only.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

SUPPLY VOLTATE (IN PIN)

Shutdown quiescent current;

measured at IN pin.

I_SD

VEN/UV = 0, –40°C ≤ T_J≤ 85°C

21

50

uA

Voltage on VIN pin when buck

regulator stops switching

V_{OVLO_R}

26.6

1.26

27.5

0.5

28.4

V

V_{OVLO_HYS}

Hysteresis

ENABLE AND UVLO (EN/UVLO PIN)

Rising threshold for not in External

UVLO

V_{EN/UVLO_R}

V_EN/UVrising threshold

V_EN/UVLOfalling

1.3

1.34

1.98

V

V_{EN/UVLO_HYS}

Hysteresis

100

mV

PA_EN, PB_EN input level required to

turn on PA_BUS and PB_BUS Load

Switch

V_{PA/B_EN_H}

V_{PA_EN}or V_{PB_EN}rising threshold

1.6

V

PA_EN, PB_EN input level required to

turn off PA_BUS and PB_BUS Load

Switch

V_{PA/B_EN_L}

V_{PA_EN}or V_{PB_EN}falling threshold

0.97

1.5

V

V_{EN1/2_HYS}

Hysteresis

100

mV

BOOTSTRAP

V_{BTST_UVLO}

Bootstrap voltage UVLO threshold

Bootstrap pull-up resistence

2.2

7.7

V

VSENSE-BOOT = 0.1 V, Need a test

mode

R_BOOT

Ω

BUCK REGULATOR

I_L-SC-HS

I_L-SC-LS

I_L-NEG-LS

I_ZC

High-side current limit

BOOT-SW = 5 V

SENSE = 5 V

10.2

8.5

11.4

10

12.6

11.5

A

Low-side current limit

Low-side negative current limit

Zero current detector threshold

–5

0.01

CC1 or CC2 pulldown resistance = R_d,

VSET float or pull up to V_SENSE, T_J

=

-1%

5.1

+1%

V

25℃

CC1 or CC2 pulldown resistance = R_d,

VSET short to AGND, T_J= 25℃

-1%

–2

5.17

5.3

+1%

2

V

V_SENSE

BUCK Output voltage

CC1 or CC2 pulldown resistance = R_d,

R_VSET= 40.2 KΩ, T_J= 25℃

CC1 or CC2 pulldown resistance = R_d,

R_VSET= 80.6 KΩ, T_J= 25℃

5.4

V

CC1 or CC2 pulldown resistance = R_d,

-40℃ ≤ T_J≤150℃

V_SENSE

BUCK Output voltage accuracy

%

SENSE input level to enable DCDC

switching

V_SENSErising, CC1 or CC2 pull down

resistance = R_d

V_{DCDC_UVLO_R}

V_{DCDC_UVLO_HYS}

V_DROP

3.85

4

0.4

300

18

4.15

V

V_SENSEfalling, CC1 or CC2 pull down

resistance = R_d

Hysteresis

V

V_IN= V_SENSE+ V_DROP,V_SENS= 5.1 V,

I_{PA_BUS}= 3A, I_{PB_BUS}= 2.4 A

Dropout voltage ( V_IN-V_SENSE

)

mV

mΩ

I_{PA_BUS}= 3 A, I_{PB_BUS}= 2.4 A, BOOT-

SW = 5 V, –40℃≤ T_J≤ 150℃

R_DS-ON-HS

R_DS-ON-LS

High-side MOSFET ON-resistance

Low-side MOSFET ON-resistance

34

I_{PA_BUS}= 3 A, I_{PB_BUS}= 2.4 A, V_SENSE

= 5 V, –40℃ ≤ T_J≤ 150℃

9.5

18.5

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8.5 Electrical Characteristics (continued)

Limits apply over the recommended operating junction temperature (T_J) range of -40°C to +150°C; V_IN= 13.5 V, f_SW

=2.1MHz, VSET short to GND unless otherwise stated. Minimum and maximum limits are specified through test, design or

statistical correlation. Typical values represent the most likely parametric norm at T_J= 25°C, and are provided for reference

purposes only.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

POWER SWITCH AND CURRENT LIMIT

USB Load Switch MOSFET ON-

resistance

I_{PA_BUS}= 3 A, I_{PB_BUS}= 2.4 A; –40℃ ≤

T_J≤ 150℃

R_{DS-ON_USB}

R_{DS-ON_OUT}

6.8

11.73

mΩ

OUT Load Switch MOSFET ON-

resistance

I_OUT= 0.3 A

230

R_{DS-ON_VCONN}

On-state resistance

T_J= 25°C, I_CCn= 0.25 A

410

550

740

mΩ

–40°C ≤T_J≤ 150°C, I_CCn= 0.25 A

Voltage on SENSE pin that will enable

the USB Load Switch

V_{USBLS_UVLO_R}

3.95

4.1

200

500

4.25

V

mV

Ω

V_{USBLS_UVLO_HYS}Hysteresis

Discharge resistance for Port A or Port Apply 5V on PA_BUS or PB_BUS,

B BUS

R_{BUS_DCHG}

250

670

750

730

PA_EN or PB_EN pull low

Rising threshold voltage for BUS not

discharged

V_{TH_R_BUS_DCHGb}

700

100

150

mV

KΩ

V_{TH_HYS_BUS_DCHG}Hysteresis

V_{PA_BUS}= 4 V, No sink termination on

CC lines, Time>t_{W_BUS_DCHG}

V_{BUS_DCHG_BLEED}BUS bleed resistance

100

200

R_ILIM= 48.7 KΩ

679

1947

2415

2999

3233

3901

3862

3412

424

849

2163

2683

3332

3592

4334

4544

3592

530

1018

2379

2951

3665

3951

4767

5225

3771

636

mA

R_ILIM= 19.1 KΩ

R_ILIM= 15.4 KΩ

R_ILIM= 12.4 KΩ

I_{OS_HI}(USB Port

B)

Port B BUS output short-circuit

secondary current limit

R_ILIM= 11.5 KΩ

RILIM = 9.53 KΩ

R_ILIM= 0 Ω (short to GND)

R_ILIM= 11.5 KΩ, T_J= 25℃

R_ILIM= 48.7 KΩ

R_ILIM= 19.1 KΩ

1217

1509

1874

2020

2438

2414

2133

849

1352

1677

2082

2245

2709

2840

2245

1061

2704

3354

4165

4490

5418

5680

4490

1487

1844

2290

2469

2980

3266

2357

1273

2974

3689

4581

4938

5960

6532

4714

R_ILIM= 15.4 KΩ

R_ILIM= 12.4 KΩ

I_{OS_BUS}(USB Port Port B BUS output short-circuit current

B)

limit

R_ILIM= 11.5 KΩ

RILIM = 9.53 KΩ

R_ILIM= 0 Ω (short to GND)

R_ILIM= 11.5 KΩ, T_J= 25℃

R_ILIM= 48.7 KΩ

R_ILIM= 19.1 KΩ

2434

3018

3748

4040

4876

4828

4265

R_ILIM= 15.4 KΩ

R_ILIM= 12.4 KΩ

I_{OS_HI}(USB Port

A)

Port A BUS output short-circuit

secondary current limit

R_ILIM= 11.5 KΩ

R_ILIM= 9.53 KΩ

R_ILIM= 0 Ω (short to GND)

R_ILIM= 11.5 KΩ, T_J= 25℃

10

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8.5 Electrical Characteristics (continued)

Limits apply over the recommended operating junction temperature (T_J) range of -40°C to +150°C; V_IN= 13.5 V, f_SW

=2.1MHz, VSET short to GND unless otherwise stated. Minimum and maximum limits are specified through test, design or

statistical correlation. Typical values represent the most likely parametric norm at T_J= 25°C, and are provided for reference

purposes only.

PARAMETER

TEST CONDITIONS

MIN

530.4

1521

TYP

MAX UNIT

R_ILIM= 48.7 KΩ

663

795.6

1859

mA

R_ILIM= 19.1 KΩ

1690

R_ILIM= 15.4 KΩ

1886.4

2342.7

2525.4

3047.4

3017.5

2666

2096 2305.6

2603 2863.3

2806 3086.6

3386 3724.6

3550 4082.5

R_ILIM= 12.4 KΩ

I_{OS_BUS}(USB Port Port A BUS output short-circuit current

A)

limit

R_ILIM= 11.5 KΩ

RILIM = 9.53 KΩ

R_ILIM= 0 Ω (short to GND)

R_ILIM= 11.5 KΩ, T_J= 25℃

Short circuit current limit

2806

450

2946

495

I_{OS_OUT}

OUT output short-circuit current limit

390

VCONN output short-circuit current

limit

I_{OS_VCONN}

Short circuit current limit

240

70

300

360

mA

CABLE COMPENSATION VOLTAGE

I_{PA_BUS}or I_{PB_BUS}= 2.4 A, VSET =

GND (set 5.17-V output)

V_{DROP_COM}

Cable compensation voltage

90

110

mV

CC CONNECT MANAGEMENT

I_{SRC_CC_3A}

Sourcing current

CC pin voltage: 0 V ≤ V_CCn≤ 2.45 V

304

167

330

180

356

194

µA

Sourcing current in thermal

management(Temp warm)

CC pin voltage: 0 V ≤ V_CCn≤ 1.5 V,

T_A> 85℃

I_{SRC_CC_1.5A}

Sourcing current in thermal

management(Temp hot)

CC pin voltage: 0 V ≤ V_CCn≤ 1.5 V ,

T_A> 85℃

I_{SRC_CC_DFLT}

64

80

105

10

µA

CCx is the CC pin under test, CCy

is the other CC pin. CC pin voltage

VCCx = 5.5 V, CCy floating, V_{EN_UV}

0 V or V_SENSE, 0 V ≤ V_IN≤ 26

I_REV

Reverse leakage current

=

2.75

V I_REVis current into CCx pin

Rising threshold voltage for VCONN

not discharged

CC pin that was providing VCONN in

previous SINK state

V_{TH_R}

670

700

100

730

mV

V_{TH_HYS}

Hysteresis

FAULT

PA_FAULT, PB_FAULT Output low

voltage

V_OL

I_OFF

I_{SNK_PIN}= 1 mA

V_PIN= 5.5 V

250

2.2

mV

µA

PA_FAULT, PB_FAULT Off-state

leakage

BC 1.2 DOWNSTREAM CHARGING PORT

R_{DPM_SHORT}

DIVIDER 3 MODE

V_{DP_DIV3}

DP and DM shorting resistance

70

200

Ω

DP output voltage

2.57

24

2.7

30

2.84

36

V

V_{DM_DIV3}

DM output voltage

DP output impedance

DM output impedance

R_{DP_DIV3}

I_{DP_IN}= –5 µA

I_{DM_IN}= –5 µA

kΩ

R_{DM_DIV3}

24

30

36

1.2-V MODE

V_{DP_1.2V}

DP output voltage

1.12

84

1.2

1.26

126

V

V_{DM_1.2V}

DM output voltage

DP output impedance

DM output impedance

R_{DP_1.2V}

I_{DP_IN}= –5 µA

I_{DM_IN}= –5 µA

100

kΩ

R_{DM_1.2V}

84

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8.5 Electrical Characteristics (continued)

Limits apply over the recommended operating junction temperature (T_J) range of -40°C to +150°C; V_IN= 13.5 V, f_SW

=2.1MHz, VSET short to GND unless otherwise stated. Minimum and maximum limits are specified through test, design or

statistical correlation. Typical values represent the most likely parametric norm at T_J= 25°C, and are provided for reference

purposes only.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

FREQ/SYNC THRESHOLD

FREQ/SYNC high threshold for

external clock synchronization

Amplitude of SYNC clock AC signal

(measured at FREQ/SYNC pin)

V_{IH_FREQ/SYNC}

V_{IL_FREQ/SYNC}

2

V

FREQ/SYNC low threshold for

external clock synchronization

Amplitude of SYNC clock AC signal

(measured at FREQ/SYNC pin)

0.8

V

TEMPERATURE SENSING

V_{WARN_HIGH}Temperature warning threshold rising As percentage to V_SENSE

V_{WARN_HYS}

0.475

0.5

0.1

0.525

V/V

Hysteresis

As percentage to V_SENSE

Temperature Hot assert threshold

rising to reduce SENS voltage

V_{HOT_HIGH}

V_{HOT_HYS}

V_{R_VSENS}

As percentage to V_SENSE

0.6175

0.65 0.6825

V/V

V

Hysteresis

As percentage to V_SENSE

0.1

V_SENSEvoltage decay when

Temperature Hot assert

TS pin voltage rise above 0.65*V_SENSE

4.77

THERMAL SHUTDOWN

T_{LS_SD}USB Load Switch Over Temperature

OTSD2&3 threshold

Recovery threshold

Shutdown threshold

Recovery threshold

160

150

166

154

°C

T_SD

Thermal shutdown

8.6 Timing Requirements

Over the recommended operating junction temperature range of -40 °C to 150 °C (unless otherwise noted)

MIN NOM MAX UNIT

FAULT DUE TO BUS OC AND THERMAL SD

(Thermal SD Fault assertion is

instantaneous, not subject to this timing)

t_{DEGLA_FAULT}Asserting deglitch time

2.94

4.1 5.42 ms

t_{DEGLD_FAULT}De-asserting deglitch time

11.09 16.38 23.03 ms

BUS DISCHARGE

t_{DEGA_BUS_DC}

Discharge asserting deglitch

5.6

12.3 21.2 ms

260 360 ms

HG

V_BUSdischarge time after sink termination

removed from CC lines

V_BUS= 1 V, time I_{SNK_OUT}> 1 mA after sink

termination removed from CC lines

t_{W_BUS_DCHG}

170

POWER SWITCH TIMING

Deglitch time for USB power switch current

limit enable

t_{IOS_HI_DEG}

t_{IOS_HI_RST}

t_{r_USB}

USB port enter overcurrent (per ILIM setting) 1.228 2.048 2.867 ms

MFi OCP reset timing

9.6

16 22.4 ms

C_L= 1 µF, R_L= 100 Ω (measured from 10%

to 90% of final value)

PA_BUS, PB_BUS voltage rise time

PA_BUS, PB_BUS voltage fall time

1.67

ms

C_L= 1 µF, R_L= 100 Ω (measured from 90%

to 10% of final value)

t_{f_USB}

0.49

t_{on_USB}

t_{off_USB}

PA_BUS, PB_BUS voltage turnon-time

PA_BUS, PB_BUS voltage turnoff-time

C_L= 1 µF, R_L= 100 Ω

2.59

2.07

ms

PA_BUS, PB_BUS short-circuit response

time

t_{IOS_USB}

t_{r_OUT}

C_L= 1 µF, R_L= 1 Ω

1

us

C_L= 1 µF, R_L= 100 Ω (measured from 10%

to 90% of final value)

OUT voltage rise time

0.12

0.2 0.28 ms

12

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8.6 Timing Requirements (continued)

Over the recommended operating junction temperature range of -40 °C to 150 °C (unless otherwise noted)

MIN NOM MAX UNIT

C_L= 1 µF, R_L= 100 Ω (measured from 90%

to 10% of final value)

t_{f_OUT}

OUT voltage fall time

0.16

0.22 0.28 ms

t_{on_OUT}

OUT voltage turnon-time

C_L= 1 µF, R_L= 100 Ω

C_L= 1 µF, R_L= 1 Ω

0.6

1.1 1.65 ms

0.38 0.55 ms

t_{off_OUT}

OUT voltage turnoff-time

0.22

t_{IOS_OUT}

t_{IOS_VCONN}

OUT short-circuit response time

CC-VCONN short circuit response time

1.4

1

4

us

3.5 µs

C_L= 1 µF, R_L= 100 Ω (measured from 10%

to 90% of final value); 5.1 KΩ on CC1 and 1

KΩ on CC2

t_{r_VCONN}

VCONN output voltage rise time

VCONN output voltage fall time

0.2

0.28 0.35 ms

0.23 0.28 ms

C_L= 1 µF, R_L= 100 Ω (measured from 90%

to 10% of final value); 5.1 KΩ on CC1 and 1

KΩ on CC2

t_{f_VCONN}

0.18

C_L= 1 µF, R_L= 100 Ω; 5.1 KΩ on CC1 and 1

KΩ on CC2

t_{on_VCONN}

VCONN output voltage turnon time

VCONN output voltage turnoff time

0.7

1.2

1.7 ms

C_L= 1 µF, R_L= 100 Ω; 5.1 KΩ on CC1 and 1

KΩ on CC2

t_{off_VCONN}

0.37

0.44 0.51 ms

4.1 5.42 ms

HICCUP MODE

T_{HICP_ON}

OUT, PA_BUS, PB_BUS output hiccup mode

ON time

OC, V_OUT, V_{PA_BUS}, V_{PB_BUS}drop 10%

2.94

367

OUT, PA_BUS, PB_BUS output hiccup mode OC, OUT, PA_BUS, PB_BUS connect to

OFF time GND

T_{HICP_OFF}

524

715 ms

8.7 Switching Characteristics

Over the recommended operating junction temperature range of -40 °C to 150 °C (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

SW (SW PIN)

T_{ON_MIN}

Minimum turnon-time

84

6

ns

µs

ns

%

Maximum turnon-time, HS timeout in

dropout

T_{ON_MAX}

T_{OFF_MIN}

D_max

Minimum turnoff time

81

98

Maximum switch duty cycle. While in

frequency fold-back

TIMING RESISTOR AND INTERNAL CLOCK

Switching frequency range using

FREQ mode

f_{SW_RANGE}

9 kΩ ≤ R_FREQ≤ 99 kΩ

200

3000

kHz

R_FREQ= 80.6 kΩ

R_FREQ= 49.9 kΩ

R_FREQ= 8.45 kΩ

228

360

253

400

278

440

kHz

f_SW

Switching frequency

1980

2200

2420

Frequency span of spread spectrum

operation

FS_SS

±6

%

EXTERNAL CLOCK(SYNC)

Switching frequency using external

f_FREQ/SYNC

200

3000

kHz

clock on FREQ/SYNC pin

Minimum SYNC input pulse width

PLL lock time

f_SYNC= 400 kHz, V_FREQ/SYNC

V_{IH_FREQ/SYNC}, V_FREQ/SYNC< V_{IL_FREQ/}

>

T_{SYNC_MIN}

T_{LOCK_IN}

100

ns

µs

SYNC

CC - CONNECT MANAGEMENT - ATTACH AND DETACH DEGLITCH

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8.7 Switching Characteristics (continued)

Over the recommended operating junction temperature range of -40 °C to 150 °C (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

Attach asserting deglitch in the

Detached Mode

t_{DEGA_CC_ATT_DETM}

1.29

2.05

3.05

18

ms

t_{DEGA_CC_DETACH_S}Detach asserting deglitch for exiting

8.2

12.5

SINK Mode

INKM

t_{DEGA_CC_SHORT}

t_{DEGA_CC_LONG}

Detach, Rd and Ra asserting deglitch

Long deglitch

92

192

148

339

200

µs

103

ms

8.8 Typical Characteristics

Unless otherwise specified the following conditions apply: V_IN= 13.5 V, f_SW= 2.1 MHz, L = 0.68 µH, C_SENSE= 66 µF, C_{PA_BUS}

= 1 µF, C_{PB_BUS}= 1 µF, T_A= 25 °C.

70

60

50

40

30

20

200

180

160

140

120

100

-40C

25C

150C

-40C

25C

150C

4

8

12

16 20

Input Voltage (V)

24

28

32

4

8

12

16 20

Input Voltage (V)

24

28

32

V_EN/EULVO= 0 V

PA_CC1 = R_d

V_EN/UVLO= V_SENSEPA_CC1/2 = OPEN

Figure 8-2. Standby Quiescent Current

Figure 8-1. Shutdown Quiescent Current

1.36

1.68

Vin = 5.5V

Vin = 13.5V

Vin = 26V

Vin = 5.5V

Vin = 13.5V

Vin = 26V

1.67

1.66

1.65

1.64

1.63

1.62

1.61

1.6

1.34

1.32

1.3

1.28

1.26

1.59

1.58

1.57

-50

-25

0

25

Temperature (C)

50

75

100

125

150

-40 -20

0

20

40

60

Temperature (C)

80 100 120 140 160

Figure 8-3. Precision Device Enable Threshold

Figure 8-4. Precision USB PA/PB Enable Threshold

5.2

5.46

Vin = 5.5V

Vin = 13.5V

Vin = 26V

Vin = 5.5V

Vin = 13.5V

Vin = 26V

5.19

5.18

5.17

5.16

5.15

5.14

5.44

5.42

5.4

5.38

5.36

5.34

-50

-25

0

25

Temperature (C)

50

75

100

125

150

-50

-25

0

25

Temperature (C)

50

75

100

125

150

VSET = GND

R_VSET= 80.6 kΩ

Figure 8-5. V_SENSEVoltage vs Junction Temperature

Figure 8-6. V_SENSEVoltage vs Junction Temperature

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8.8 Typical Characteristics (continued)

Unless otherwise specified the following conditions apply: V_IN= 13.5 V, f_SW= 2.1 MHz, L = 0.68 µH, C_SENSE= 66 µF, C_{PA_BUS}

= 1 µF, C_{PB_BUS}= 1 µF, T_A= 25 °C.

3.94

3.96

3.98

4

11.7

11.6

11.5

11.4

11.3

11.2

Vin = 5.5V

Vin = 13.5V

Vin = 26V

-40C

25C

150C

4.02

4.04

4.06

-50

-25

0

25

50

75

Temperature (C)

100

125

150

4

8

12

16

Input Voltage (V)

20

24

28

V_EN/EULVO= V_SENSE

PA_CC1 = R_d

Figure 8-8. High-side Current Limit vs Input Voltage

Figure 8-7. DCDC UVLO Threshold

10.3

40

-40C

25C

150C

Vin = 5.5V

Vin = 13.5V

Vin = 26V

10.2

10.1

10

35

30

25

20

15

9.9

9.8

4

8

12

16

Input Voltage (V)

20

24

28

-50

-25

0

25

50

75

Temperature (C)

100

125

150

Figure 8-9. Low-side Current Limit vs Input Voltage

I_{PA_BUS}= 3 A

I_{PB_BUS}= 2.4 A

Figure 8-10. High-side MOSFET on Resistance vs Junction

Temperature

18

16

14

12

3640

Vin = 5.5V

Vin = 13.5V

Vin = 26V

3600

3560

3520

3480

3440

3400

10

Vin = 5.5V

Vin = 13.5V

Vin = 26V

8

-50

-25

0

25

Temperature (C)

50

75

100

125

150

-50

-25

0

25

Temperature (C)

50

75

100

125

150

I_{PA_BUS}= 3 A

I_{PB_BUS}= 2.4 A

ILIM = GND

Figure 8-11. Low-side MOSFET on Resistance vs Junction

Temperature

Figure 8-12. USB Power Switch Current Limit vs Junction

Temperature

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8.8 Typical Characteristics (continued)

Unless otherwise specified the following conditions apply: V_IN= 13.5 V, f_SW= 2.1 MHz, L = 0.68 µH, C_SENSE= 66 µF, C_{PA_BUS}

= 1 µF, C_{PB_BUS}= 1 µF, T_A= 25 °C.

3520

3480

3440

3400

3360

3320

3280

2200

2160

2120

2080

2040

2000

1960

Vin = 5.5V

Vin = 13.5V

Vin = 26V

Vin = 5.5V

Vin = 13.5V

Vin = 26V

-50

-25

0

25

Temperature (C)

50

75

100

125

150

-50

-25

0

25

Temperature (C)

50

75

100

125

150

R_ILIM= 9.53 kΩ

R_ILIM= 15.4 kΩ

Figure 8-13. USB Power Switch Current Limit vs Junction

Temperature

Figure 8-14. USB Power Switch Current Limit vs Junction

Temperature

520

328

Vin = 5.5V

Vin = 13.5V

Vin = 26V

Vin = 5.5V

Vin = 13.5V

Vin = 26V

500

480

460

440

420

400

320

312

304

296

288

280

-50

-25

0

25

Temperature (C)

50

75

100

125

150

-50

-25

0

25

Temperature (C)

50

75

100

125

150

Figure 8-15. OUT Power Switch Current Limit vs Junction

Temperature

Figure 8-16. V_CONNPower Switch Current Limit vs Junction

Temperature

100

96

92

88

84

80

9.6

8.8

8

7.2

6.4

Vin = 5.5V

Vin = 13.5V

Vin = 26V

5.6

4.8

-50

-25

0

25

Temperature (C)

50

75

100

125

150

-50

-25

0

25

Temperature (C)

50

75

100

125

150

Figure 8-18. USB Power Switch On Resistance vs Junction

Temperature

I_{PA/B_BUS}= 2.4 A

VSET = GND

Figure 8-17. Cable Compensation Voltage vs Junction

Temperature

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8.8 Typical Characteristics (continued)

Unless otherwise specified the following conditions apply: V_IN= 13.5 V, f_SW= 2.1 MHz, L = 0.68 µH, C_SENSE= 66 µF, C_{PA_BUS}

= 1 µF, C_{PB_BUS}= 1 µF, T_A= 25 °C.

400

360

320

280

240

200

160

600

550

500

450

400

350

300

Vin = 5.5V

Vin = 13.5V

Vin = 26V

Vin = 5.5V

Vin = 13.5V

Vin = 26V

-50

-25

0

25

Temperature (C)

50

75

100

125

150

-50

-25

0

25

Temperature (C)

50

75

100

125

150

Figure 8-19. OUT Power Switch On Resistance vs Junction

Temperature

Figure 8-20. V_CONNPower Switch On Resistance vs Junction

Temperature

424

2280

Vin = 5.5V

Vin = 13.5V

Vin = 26V

Vin = 5.5V

Vin = 13.5V

Vin = 26V

416

408

400

392

384

376

2240

2200

2160

2120

2080

2040

-50

-25

0

25

Temperature (C)

50

75

100

125

150

-50

-25

0

25

Temperature (C)

50

75

100

125

150

R_FREQ= 49.9 kΩ

R_FREQ= 8.45 kΩ

Figure 8-21. Switching Frequency vs Junction Temperature

Figure 8-22. Switching Frequency vs Junction Temperature

450

0.56

UFP 1.5A

UFP 3A

400

0.54

0.52

0.5

350

300

250

200

150

0.48

0.46

0.44

-50

-25

0

25

Temperature (C)

50

75

100

125

150

-50

-25

0

25

Temperature (C)

50

75

100

125

150

Figure 8-23. CC Sourcing Current vs Junction Temperature

Figure 8-24. TS Temperature Wam Threshold vs Junction

Temperature

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8.8 Typical Characteristics (continued)

Unless otherwise specified the following conditions apply: V_IN= 13.5 V, f_SW= 2.1 MHz, L = 0.68 µH, C_SENSE= 66 µF, C_{PA_BUS}

= 1 µF, C_{PB_BUS}= 1 µF, T_A= 25 °C.

0.72

4.82

0.7

4.8

0.68

0.66

0.64

0.62

0.6

4.78

4.76

4.74

4.72

4.7

-50

-25

0

25

Temperature (C)

50

75

100

125

150

-50

-25

0

25

Temperature (C)

50

75

100

125

150

Figure 8-25. TS Temperature Hot Threshold vs Junction

Temperature

Figure 8-26. SENSE Voltage in Temperature Hot vs Junction

Temperature

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9 Parameter Measurement Information

OUT

90%

t_f

R_(L)

t_r

C_(L)

V_(OUT)

10%

Figure 9-1. OUT Rise-Fall Test Load Figure

Figure 9-2. Power-On and Power-Off Timing

V_(EN)

50%

5 V

t_on

t_off

t_(DCHG)

V_(OUT)

90%

V_(OUT)

0 V

10%

Figure 9-3. OUT Discharge During Mode Change

Figure 9-4. Enable Timing, Active-High Enable

I_OS

I_(OUT)

t_(IOS)

Figure 9-5. Output Short-Circuit Parameters

10 Detailed Description

10.1 Overview

The TPS2586x-Q1 is a full-featured solution for implementing a compact USB charging port with support for

both Type-C and BC1.2 standards. Both devices contain an efficient buck regulator power source. For Type-C

and Type-A dual ports, the TPS2586x-Q1 is capable of providing 6 A of output current at 5.17 V (nominal), 3

A for Type-C port, 2.4A for Type-A port, 200 mA for the OUT pin, and 200 mA for Port A VCONN power. The

TPS2586x-Q1 is an automotive-focused USB charging controller and offers a robust solution, so it is recommend

to add adequate protection (TVS3300 equivalent or better but auto qualified) on the IN pin to protect systems

from high-power transients or lightning strikes.

System designers can optimize efficiency or solution size through careful selection of switching frequency in

the range of 200 KHz–2400 KHz with sufficient margin to operate above or below the AM radio frequency

band. For switching frequency higher than 2400 KHz, the power dissipation significantly increases, so in a high

ambient temperature application, the 6-A output current capability is not ensured. In the TPS2586x-Q1, the

buck regulator operates in forced PWM mode, ensuring fixed switching frequency regardless of load current.

Spread-spectrum frequency dithering reduces harmonic peaks of the switching frequency, potentially simplifying

EMI filter design and easing compliance.

Current sensing through a precision FET current sense amplifier on the USB port enables an accurate, user-

programmable overcurrent limit setting, and linear cable compensation to overcome IR losses when powering

remote USB ports.

The TPS2586x-Q1 includes a TS input for user-programmable thermal protection using a negative temperature

coefficient (NTC) resistor.

Both devices can support the USB Type-C protocol on the port A. For the TPS25860-Q1, it also supports the

legacy Battery Charging Specification Rev 1.2 (BC1.2) DCP mode with an auto-detect feature to charge not only

BC1.2-compliant hand-held devices, but also popular phones and tablets that incorporate their own propriety

charging algorithm.

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10.2 Functional Block Diagram

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10.3 Feature Description

10.3.1 Power-Down or Undervoltage Lockout

The device is in power down mode if the IN terminal voltage is less than VUVLO, so the part is considered

“dead” and all the terminals are high impedance. Once the IN voltage rises above the VUVLO threshold, the IC

enters Sleep Mode or Active Mode, depending on the EN/UVLO voltage.

The voltage on the EN/UVLO pin controls the ON/OFF operation of the TPS2586x-Q1. An EN/UVLO pin voltage

higher than V_EN/UVLO-His required to start the internal regulator and begin monitoring the CCn lines for a valid

Type-C connection. The internal USB monitoring circuitry is on when V_INis within the operation range and the

EN/UVLO threshold is cleared. The buck regulator starts to operate, however, the USB ports load switch remains

OFF until a valid Type-C detection has been made. This feature ensures the "cold socket" (0 V) USB Type-C

V_BUSrequirement is met.

The EN/UVLO pin is an input and cannot be left open or floating. The simplest way to enable the operation of the

TPS2586x-Q1 is to connect EN to SENSE. This connection allows self-start-up of the TPS2586x-Q1 when V_INis

within the operation range. Note that you cannot connect the EN to IN pin directly for self-start-up.

Many applications benefit from the employment of enable dividers R_ENTand R_ENBto establish a precision

system UVLO level for the TPS2586x-Q1 shown in Figure 10-1. The system UVLO can be used for sequencing,

ensuring reliable operation, or supply protection, such as a battery discharge level. To ensure the USB port

V_BUSis within the 5-V operating range as required for USB compliance (refer to USB.org for the latest USB

specifications and requirements), it is suggested that the R_ENTand R_ENBresistors be chosen such that the

TPS2586x-Q1 enables when V_INis approximately 6 V. Considering the dropout voltage of the buck regulator and

IR losses in the system, 6 V provides adequate margin to maintain V_BUSwithin USB specifications. If system

requirements, such as a warm crank (start) automotive scenario, require operation with V_IN< 6 V, the values of

R_ENTand R_ENBcan be calculated assuming a lower V_IN. An external logic signal can also be used to drive the

EN/UVLO input when a microcontroller is present and it is desirable to enable or disable the USB port remotely

for other reasons.

IN

RENT

EN

RENB

Figure 10-1. System UVLO by Enable Divider

UVLO configuration using external resistors is governed by the following equations:

(1)

(2)

For example:

V_IN(ON)= 6 V

R_ENT= 20 kΩ

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R_ENB= [(V_EN-VOUT-H) / (V_IN(ON)– V_EN)] × R_ENT

(3)

R_ENB= 5 kΩ

Therefore, V_IN(OFF)= 5.5 V

10.3.2 Input Overvoltage Protection (OVP) - Continuously Monitored

The operation voltage range of the TPS2586x-Q1 is up to 26 V. If the input source applies an overvoltage, the

buck regulator HSFET/LSFET turns off immediately. Thus, the USB ports and OUT pin loses their power as well.

Once the overvoltage returns to a normal voltage, the buck regulator continues switching and provides power on

the USB ports and OUT pin.

During the overvoltage condition, the internal regulator regulates the SENSE voltage at 5 V, so the SENSE

always has power for the internal bias circuit and external NTC pullup reference.

10.3.3 Buck Converter

The following operating description of the TPS2586x-Q1 refers to the Functional Block Diagram. The TPS2586x-

Q1 integrates a monolithic, synchronous, rectified, step-down, switch-mode converter with internal power

MOSFETs and USB current-limit switches with charging ports auto-detection. The TPS2586x-Q1 offers a

compact and high efficiency solution with excellent load and line regulation over a wide input supply range.

The TPS2586x-Q1 supplies a regulated output voltage by turning on the high-side (HS) and low-side (LS)

NMOS switches with controlled duty cycle. During high-side switch ON time, the SW pin voltage swings up to

approximately V_IN. The inductor current i_Lincreases with linear slope (V_IN– V_OUT) / L. When the HS switch

is turned off by the control logic, the LS switch is turned on after an anti-shoot-through dead time. Inductor

current discharges through the LS switch with a slope of –V_OUT/ L. The control parameter of a buck converter is

defined as Duty Cycle D = t_ON/ T_SW, where t_ONis the high-side switch ON time and T_SWis the switching period,

shown in Figure 10-2. The regulator control loop maintains a constant output voltage by adjusting the duty cycle

D. In an ideal buck converter, where losses are ignored, D is proportional to the output voltage and inversely

proportional to the input voltage: D = V_OUT/ V_IN.

V_SW

D = t_ON/ T_SW

V_IN

t_ON

t_OFF

t

0

-V_D

T_SW

i_L

I_LPK

I_OUT

Di_L

t

0

Figure 10-2. SW Node and Inductor Current Waveforms in Continuous Conduction Mode (CCM)

The TPS2586x-Q1 operates in a fixed-frequency, peak-current-mode control to regulate the output voltage. A

voltage feedback loop is used to get accurate DC voltage regulation by adjusting the peak current command

based on voltage offset. The peak inductor current is sensed from the high-side switch and compared to the

peak current threshold to control the ON time of the high-side switch. The voltage feedback loop is internally

compensated, which allows for fewer external components, making it easy to design, and provides stable

operation with a reasonable combination of output capacitors. The TPS2586x-Q1 operates in FPWM mode for

low output voltage ripple, tight output voltage regulation, and constant switching frequency.

The TPS2586x-Q1 also has variants to support PFM mode. In PFM mode, the high-side FET is turned on in a

burst of one or more cycles to provide energy to the load. The frequency of these bursts is adjusted to regulate

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the output, while diode emulation is used to maximize efficiency. This mode provides high light-load efficiency

by reducing the amount of input supply current required to regulate the output voltage at small loads. A small

increase in the output voltage occurs in PFM. This mode trades off very good light load efficiency for larger

output voltage ripple and variable switching frequency.

10.3.4 FREQ/SYNC

The switching frequency of the TPS2586x-Q1 can be programmed by the resistor R_FREQfrom the FREQ/SYNC

pin and AGND pin. To determine the FREQ resistance, for a given switching frequency, use Equation 4.

-1.0483

R_FREQkW = 26660ì ƒ

kHz

(

)

(

)

SW

(4)

70

65

60

55

50

45

40

35

30

25

20

15

10

5

200 400 600 800 1000 1200 1400 1600 1800 2000 2200

Switching Frequency (kHz)

D024

Figure 10-3. FREQ Set Resistor vs Switching Frequency

The normal method of setting the buck regulator switching frequency is by selecting an appropriate value FREQ

resistor as shown in Table 10-1.

Table 10-1. Setting the Switching Frequency with FREQ

FREQ (KΩ)

80.6

SWITCHING FREQUENCY (KHz)

253

400

49.9

19.1

1000

2100

2200

8.87

8.45

The FREQ/SYNC pin can be used to synchronize the internal oscillator to an external clock. The internal

oscillator can be synchronized by AC coupling a positive edge into the FREQ/SYNC pin. When using a low

impedance signal source, the frequency setting resistor FREQ is connected in parallel with an AC coupling

capacitor, C_COUP, to a termination resistor, R_TERM(for example, 50 Ω). The two resistors in series provide the

default frequency setting resistance when the signal source is turned off. A 10-pF ceramic capacitor can be used

for C_COUP. The AC coupled peak-to-peak voltage at the FREQ/SYNC pin must exceed the SYNC amplitude

threshold of 1.2 V (typical) to trip the internal synchronization pulse detector, and the minimum SYNC clock

HIGH and LOW time must be longer than 100 ns (typical). A 2.5 V or higher amplitude pulse signal coupled

through a 1-nF capacitor, C_SYNC, is a good starting point. Figure 10-4 shows the device synchronized to an

external system clock. The external clock must be off before start-up to allow proper start-up sequencing.

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Figure 10-4. Synchronize to External Clock

The TPS2586x-Q1 switching action can be synchronized to an external clock from 200 KHz to 3 MHz. Even the

switching frequency can be set to higher than 2.4 MHz, but it is recommend to set the switching frequency below

2.4 MHz due to the power dissipation, the higher switching frequency results in more power loss on IC, cause

the junction temperature and also the board temperature rising, then the device may enter load shedding under

high ambient temperature.

Figure 10-5, Figure 10-6 and Figure 10-7 show the device switching frequency and behavior under different VIN

voltage and R_FREQ= 8.45 kΩ.

Figure 10-8, Figure 10-9 and Figure 10-10 show the device switching frequency and behavior under different

VIN voltage and synchronized to an external 2.2-MHz system clock.

VIN

10V/Div

VIN

10V/Div

SW

10V/Div

SW

10V/Div

IL

5A/Div

500.0ns/Div

VIN = 8 V L = 0.68 uH I_{PA_BUS}= 3 A I_{PB_BUS}= 2.4 A

VIN = 13.5 V L = 0.68 uH I_{PA_BUS}= 3 A I_{PB_BUS}= 2.4 A

Figure 10-5. Switching Frequency When R_FREQ

8.45 kΩ

=

Figure 10-6. Switching Frequency When R_FREQ

8.45 kΩ

=

VIN

5V/Div

SYNC

VIN

10V/Div

2V/Div

SW

10V/Div

SW

10V/Div

IL

5A/Div

IL

5A/Div

500.0ns/Div

VIN = 18 V L = 0.68 uH I_{PA_BUS}= 3 A I_{PB_BUS}= 2.4 A

VIN = 8 V L = 0.68 uH I_{PA_BUS}= 3 A I_{PB_BUS}= 2.4 A

Figure 10-7. Switching Frequency When R_FREQ

8.45 kΩ

=

Figure 10-8. Synchronizing to External 2.2-MHz

Clock

VIN

10V/Div

VIN

10V/Div

SYNC

2V/Div

SYNC

2V/Div

SW

10V/Div

SW

10V/Div

IL

5A/Div

IL

5A/Div

500.0ns/Div

VIN = 13.5 V L = 0.68 uH I_{PA_BUS}= 3 A I_{PB_BUS}= 2.4 A

VIN = 18 V L = 0.68 uH I_{PA_BUS}= 3 A I_{PB_BUS}= 2.4 A

Figure 10-9. Synchronizing to External 2.2-MHz

Clock

Figure 10-10. Synchronizing to External 2.2-MHz

Clock

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10.3.5 Bootstrap Voltage (BOOT)

The TPS2586x-Q1 provides an integrated bootstrap voltage regulator. A small capacitor between the BOOT and

SW pins provides the gate drive voltage for the high-side MOSFET. The BOOT capacitor is refreshed when the

high-side MOSFET is off and the low-side switch conducts. The recommended value of the BOOT capacitor

is 100 nF. A ceramic capacitor with an X7R or X5R grade dielectric with a voltage rating of 10 V or higher is

recommended for stable performance over temperature and voltage. The BOOT rail has a UVLO to protect the

chip from operation with too little bias, and is typically 2.2 V. If the BOOT capacitor voltage drops below the

UVLO threshold, the device initiates a charging sequence using the low-side FET before attempting to turn on

the high-side device.

10.3.6 Minimum ON-Time, Minimum OFF-Time

Minimum ON-time, T_{ON_MIN}, is the smallest duration of time that the HS switch can be on. T_{ON_MIN}is typically

84 ns in the TPS2586x-Q1. Minimum OFF-time, T_{OFF_MIN}, is the smallest duration that the HS switch can be

off. T_{OFF_MIN}is typically 81 ns in the TPS2586x-Q1. In CCM (FPWM) operation, T_{ON_MIN}and T_{OFF_MIN}limit the

voltage conversion range given in a selected switching frequency.

The minimum duty cycle allowed is:

D_MIN= T_{ON_MIN}× f_SW

(5)

And the maximum duty cycle allowed is:

D_MAX= 1 - T_{OFF_MIN}× f_SW

(6)

Given fixed T_{ON_MIN}and T_{OFF_MIN}, the higher the switching frequency, the narrower the range of the allowed

duty cycle.

Given an output voltage, the choice of the switching frequency affects the allowed input voltage range, solution

size, and efficiency. The maximum operation supply voltage can be found by:

V_OUT

V

=

IN_MAX

f

ì T_{ON_MIN}

(

)

SW

(7)

At lower supply voltage, the switching frequency is limited by T_{OFF_MIN}. The minimum V_INcan be approximated

by:

V_OUT

V

=

IN_MIN

1- f

(

ì T_{OFF _MIN}

)

SW

(8)

Considering power losses in the system with heavy load operation, V_{IN_MAX}is higher than the result calculated in

Equation 7.

If minimum ON-time or minimum OFF-time do not support the desired conversion ratio, frequency is reduced,

automatically allowing regulation to be maintained during load dump and with very low dropout during cold crank

even with high operating-frequency setting.

10.3.7 Internal Compensation

The TPS2586x-Q1 is internally compensated. The internal compensation is designed such that the loop

response is stable over the specified operating frequency and output voltage range. The TPS2586x-Q1 is

optimized for transient response over the range of 200 kHz ≤ fsw ≤ 3000 kHz.

10.3.8 Selectable Output Voltage (VSET)

The TPS2586x-Q1 provides four different output voltage options. The voltage can be set by an external resistor

across the VSET pin. The normal method of setting the buck output voltage is by selecting an appropriate value

VSET resistor as shown in Table 10-2.

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Table 10-2. VSET Configuration vs BUS Output Voltage

VSET CONFIGURATION

V_SENSE

Float or pull up to V_SENSE

5.1 V

Short to GND

R_VSET= 40.2 KΩ

R_VSET= 80.6 KΩ

5.17 V

5.3 V

5.4 V

Note that the VSET has an internal weak 20-µA current source to overdrive the pin to SENSE. If this pin is

floated, the voltage on this pin approaches the SENSE voltage, and sets the output voltage to 5.1 V. It is not

recommend to float this pin if there is external noise from the PCB board, since the noise interferes with the

VSET internal logic block.

10.3.9 Current Limit and Short Circuit Protection

For maximum versatility, the TPS2586x-Q1 includes both a precision, programmable current limit as well cycle-

by-cycle current limit to protect the USB port from extreme overload conditions. The R_ILIMresistor determines the

overload threshold on the USB ports in the event ILIM is shorted to ground to set the default USB current limit.

The cycle-by-cycle current limit serves as a backup means of protection.

10.3.9.1 USB Switch Programmable Current Limit (ILIM)

Since the TPS2586x-Q1 integrates two USB current-limit switches, it provides adjustable current limit to prevent

USB port overheating. It engages the Two-Level current limit scheme, which has one typical current limit,

I_{OS_BUS}, and the secondary current limit, I_{OS_HI}. The secondary current limit, I_{OS_HI}, is 1.6x the primary current

limit, I_{OS_BUS}. The secondary current limit acts as the current limit threshold for a deglitch time, t_{IOS_HI_DEG}, then

the USB power switch current limit threshold is set back to I_{OS_BUS}. Equation 9 calculates the value of resistor for

adjusting the port A typical current limit.

32273

R_ILIMKꢀ =

(

)

I_{OS _BUS Port A}₎(mA)

(

(9)

Note in TPS2586x-Q1, the Port A is the Type-C port, and Port B is the Type-A port, the Port B current limit is the

ration of Port A, which fix at 80% internally. R_ILIMis the resistor that can be changed to achieve different current

limit for Port A and Port B. Typical R_ILIMresistors value are listed inTable 10-3:

Table 10-3. Setting the Current Limit with R_ILIM

I_{OS_BUS}: Current-Limit Threshold (mA)

R_ILIM(kΩ)

Port A

2603

3386

3550

Port B (= 0.8 × Port A)

12.4

9.53

2082

2709

2840

0 (ILIM short to GND)

This equation assumes an ideal-no variation-external adjusting resistor. To take resistor tolerance into account,

first determine the minimum and maximum resistor values based on its tolerance specifications and use these

values in the equations. Because of the inverse relationship between the current limit and the adjusting resistor,

use the maximum resistor value in the I_OS(min)equation and the minimum resistor value in the I_OS(max)equation.

For the normal application, the ILIM pin can short to GND directly, which sets a default 3.55-A and 2.84-A current

limit with a maximum ±15% variation on USB port A and port B separately to follow the USB specification. The

TPS2586x-Q1 provides built-in soft-start circuitry that controls the rising slew rate of the output voltage to limit

inrush current and voltage surges.

The secondary current limit, I_{OS_HI}, allows the USB port pull out a larger current for a short time, which can

benefit USB port MFi OCP testing. In a normal application, once the device is powered on and USB port is not

in UVLO, the USB port current limit threshold is overridden by the secondary current limit, I_{OS_HI}, so the USB

port can output as high as a 1.6 × I_{OS_BUS}current for typically 2 ms. After the deglitch time, t_{IOS_HI_DEG}, the

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current limit threshold is set back to the typical current with I_{OS_BUS}. The secondary current limit threshold does

not resume until after the t_{IOS_HI_RST}deglitch time, which is typically 16 ms. If there is an inrush current higher

than the I_{OS_HI}threshold, the current limit is set back to I_{OS_BUS}immediately, without waiting for a t_{IOS_HI_DEG}

.

The TPS2586x-Q1 responds to overcurrent conditions by limiting output current to I_{OS_BUS}as shown in previous

equation. When an overload condition occurs, the device maintains a constant output current and the output

voltage reduces accordingly. Three possible overload conditions can occur:

•

The first condition is when a short circuit or overload is applied to the USB output when the device is powered

up or enabled. There can be inrush current and once it triggers the approximate 8-A threshold, a fast turnoff

circuit is activated to turn off the USB power switch within t_{IOS_USB}before the current limit control loop is

able to respond (shown in Figure 10-11). After the fast turnoff is triggered, the USB power switch turns off for

approximately 200 µs, and restarts with a soft start. If the USB port is still in overcurrent condition, the short

circuit and overload hold the output near zero potential with respect to ground and the power switch ramps

the output current to I_{OS_BUS}. If the overcurrent limit condition lasts longer than 4.1 ms, the corresponding

USB channel enters hiccup mode with 524 ms of off-time and 4.1 ms of on-time.

Figure 10-11. Response Time to BUS Short-Circuit

•

The second condition is the load current increases above I_{OS_BUS}but below the I_{OS_HI}setting. The device

allows the USB port to output this large current for t_{IOS_HI_DEG}, without limiting the USB port current to

I_{OS_BUS}. After the t_{IOS_HI_DEG}deglitch time, device will limit the output current to I_{OS_BUS}and works in a

constant current-limit mode. If the load demands a current greater than I_{OS_BUS}, the USB output voltage

decreases to I_{OS_BUS}× R_LOADfor a resistive load, which is shown in Figure 10-12. If the overcurrent limit

condition lasts longer than 4.1 ms, the corresponding USB channel enters hiccup mode with 524 ms of

off-time and 4.1 ms of on-time. Another USB channel still works normally.

Figure 10-12. BUS Overcurrent Protection

•

The third condition is the load current increases above the I_{OS_HI}setting. In this case, the USB power switch

current limit threshold is set back to the primary current limit, I_{OS_BUS}, immediately. If the load still demands a

current greater than I_{OS_BUS}, the USB output voltage decreases to I_{OS_BUS}× R_LOADfor a resistive load, which

is shown in Figure 10-13. If the overcurrent limit condition lasts longer than 4.1 ms, the corresponding USB

channel enters hiccup mode with 524 ms of off-time and 4.1 ms of on-time. Another USB channel still works

normally.

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Figure 10-13. BUS Overcurrent Protection: Two-Level Current Limit

The TPS2586x-Q1 thermal cycles if an overload condition is present long enough to activate thermal limiting

in any of the previously mentioned cases. Thermal limiting turns off the internal NFET and starts when the

NFET junction temperature exceeds 160°C (typical). The device remains off until the NFET junction temperature

cools 10°C (typical) and then restarts. This extra thermal protection mechanism can help prevent further junction

temperature rise, which can cause the device to turn off due to junction temperature exceeding the main thermal

shutdown threshold, T_SD

.

10.3.9.2 Interlocking for Two-Level USB Switch Current Limit

The TPS2586x-Q1 has two USB ports. Since the secondary current limit, I_{OS_HI}, is 1.6x of the primary current

limit, I_{OS_BUS}, if the two USB ports pull out larger current at the same time, then the DC-DC regulator

is overloaded, and DC-DC regulator output voltage can be crashed. To avoid these potential issues, the

TPS2586x-Q1 adopts the interlocking scheme to manage the current limits of the two USB ports.

For interlocking, if one USB port current is beyond the primary current limit threshold, I_{OS_BUS}, then another USB

port current limit threshold will be overridden to the primary current limit, I_{OS_BUS}, immediately. With this control

scheme, the TPS2586x-Q1 only allows one USB port to output a large current, which can as high as 1.6x of the

primary current limit, I_{OS_BUS}, at the same time. Ensure the DC-DC regulator has enough energy to sustain its

output voltage.

10.3.9.3 Cycle-by-Cycle Buck Current Limit

There is a buck regulator cycle-by-cycle current limit on both the peak and valley of the inductor current.

High-side MOSFET overcurrent protection is implemented by the nature of the Peak Current Mode control. The

HS switch current is sensed when the HS is turned on after a set blanking time. The HS switch current is

compared to the output of the Error Amplifier (EA) minus slope compensation every switching cycle. The peak

current of HS switch is limited by a clamped maximum peak current threshold, I_{HS_LIMIT}, which is constant. The

peak current limit of the high-side switch is not affected by the slope compensation and remains constant over

the full duty cycle range.

The current going through LS MOSFET is also sensed and monitored. When the LS switch turns on, the inductor

current begins to ramp down. The LS switch is turned OFF at the end of a switching cycle if its current is above

the LS current limit, I_{LS_LIMIT}. The LS switch is kept ON so that the inductor current keeps ramping down until

the inductor current ramps below the LS current limit, I_{LS_LIMIT}. Then, the LS switch is turned OFF and the HS

switch is turned on after a dead time. This action is somewhat different than the more typical peak current limit,

and results in Equation 10 for the maximum load current.

V

_IN- V_OUT

(

)

ì

V_OUT

I_{OUT _MAX}= I_{LS _LIMIT}

+

2ì f_SWìL

V

IN

(10)

10.3.9.4 OUT Current Limit

The TPS2586x-Q1 can provide 200-mA current at the OUT pin to power the auxiliary loads, such as USB HUB,

LEDs. The OUT regulator input comes from the buck output, so the voltage is the same with the SNESE pin,

which depends on the VSET setting.

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If the OUT current reaches the current limit level, the OUT pin MOSFET works in a constant current-limit mode.

If the overcurrent limit condition lasts longer than 4.1 ms, it enters hiccup mode with 4.1 ms of on-time and 524

ms of off-time.

10.3.10 Cable Compensation

When a load draws current through a long or thin wire, there is an IR drop that reduces the voltage delivered to

the load. In the vehicle from the voltage regulator output V_OUTto V_BUS(input voltage of portable device), the total

resistance of PCB trace, connector, and cable resistances causes an IR drop at the portable device input, so

the charging current of most portable devices is less than their expected maximum charging current. The voltage

drop is shown in Figure 10-14.

5.x

V(DROP)

VOUT with compensation

VBUS with compensation

VBUS without compensation

3

1

2

Output Current (A)

Figure 10-14. Voltage Drop

To handle this case, the TPS2586x-Q1 has a built-in cable compensation function where the droop

compensation linearly increases the voltage at the SENSE pin of the TPS2586x-Q1 as load current increases, to

maintain a fairly constant output voltage at the load-side voltage.

For the TPS2586x-Q1, the internal comparator compares the current-sense output voltage of the two current-

limit switches and uses the larger current-sense output voltage to compensate for the line drop voltage. The

cable compensation amplitude increases linearly as the load current increases. It also has an upper limitation.

The cable compensation at output currents greater than 2.4 A is 90 mV and is shown in Figure 10-15. Note the

cable compensation only works when you short the VSET to GND. For the other VSET configuration, the cable

compensation is not available.

Figure 10-15. Dual Ports Cable Compensation

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10.3.11 Thermal Management with Temperature Sensing (TS) and OTSD

The TS input pin allows for user-programmable thermal protection, see the Electrical Characteristics for the TS

pin thresholds. The TS input pin threshold is ratiometric with V_SENSE. The external resistor divider setting, V_TS,

must be connected to the TPS2586x-Q1 SENSE pin to achieve accurate results (refer to the Figure 10-16).

When V_TS= 0.5 × V_SENSE, the TPS2586x-Q1 performs two actions:

•

If you are operating with 3-A Type-C advertisement, the PA_CC1, PA_CC2 pin automatically reduces

advertisement to the 1.5-A level.

Figure 10-16. TS Input

If the overtemperature condition persists, causing V_TS= 0.65 × V_SENSE, the TPS2586x-Q1 operates at default

USB mode, which means it broadcasts the Default USB Power mode, and the output voltage at the SENS pin is

reduced to 4.77 V.

In Default USB Power, the charging is ideally reduced further per the USB2.0 and USB3.0 specification.

If the overtemperature condition persists, causing T_Jto reach the OTSD threshold, then the device thermal shuts

down.

If the overtemperature condition persists, causing T_Jto reach the OTSD threshold, then the device thermal shuts

down. Figure 10-17 shows the TPS2586x-Q1 behavior when TS pin voltage trigger the Temp Warm and Temp

Hot threshold.

ICCx (uA)

VBUS (V)

BUS Voltage

5.1

4.77

330

CC Broad Current

180

80

T1(Temp Warm)

T2(Temp Hot)

OTSD

Figure 10-17. TPS2586x-Q1 Behavior When Trigger Temp Warm/Hot Threshold

The NTC thermistor must be placed near the hottest point on the PCB. In most cases, this is close to the SW

node of the TPS2586x-Q1, near the buck inductor.

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Tuning the V_NTCtheshold levels of V_{TEMP_WARM}and V_{TEMP_HOT}is achieved by adding R_SER, R_PARA, or both R_SER

and R_PARAin conjunction with R_NTC. Figure 10-18 is an example illustrating how to set the V_{TEMP_WARM}threshold

between 81°C and 90°C with a ΔT between TEMP_WARM assertion and TEMP_HOT assertion of 18°C to 29°C.

Consult the chosen NTC manufacturer's specification for the value of β. It may take some iteration to establish

the desired warning and shutdown thresholds.

Below is NTC spec and resistor value used inFigure 10-18 example.

•

R₀= 470 kΩ. β = 4750. R_NTC= R₀× exp β × (1/T – 1/T₀).

R_PARA= 100 kΩ.

R_SER= 5.1 kΩ.

R_B= R_NTC(at TEMP_WARM) = 27 kΩ.

5

4.5

4

3.5

3

VTS (V)

VTS w/ top ser (V)

VTS w/ top || (V)

VTS w/ para + ser (V)

TEMP_WARM

TEMP_HOT

2.5

2

1.5

1

0.5

0

20

40

60

80

100

120

140

NTC Temperature (°C)

T NTC (°C)

90

Rising Thresholds

Temp Warm

Temp Hot

V (V)

T NTC || (°C) T NTC ser (°C) T NTC || + ser (°C)

=VSENSE * 0.5

=VSENSE * 0.65

2.55

3.315

81

103

22

95

121

26

89

118

29

108

TEMP_HOT - TEMP_WARM

18

Figure 10-18. V_TSThreshold Design Examples

10.3.12 Thermal Shutdown

The device has an internal overtemperature shutdown threshold, T_SD, to protect the device from damage and

overall safety of the system. When the device temperature exceeds T_SD, the device is turned off when thermal

shutdown activates. Once the die temperature falls below 154°C (typical), the device re-initiates the power-up

sequence controlled by the internal soft-start circuitry.

10.3.13 USB Enable On/Off Control (TPS25862-Q1)

The PA_EN and PB_EN are the on/off control input pins for PA_USB and PB_USB, respectively. The USB

switch is active when Px_EN is pulled high. Pull the Px_EN voltage to logic low to shut down the USB switch

with an output discharge. Connect Px_EN to SENSE for automatic start-up, or control them by an external on/off

signal from the microcontroller or USB HUB.

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10.3.14 FAULT Indication

For the TPS25862-Q1, PA_FAULT and PB_FAULT are the fault indication pins for PA_USB and PB_USB,

respectively. FAULT is in an open-drain state during shutdown, start-up, or normal condition. When the USB

switch enters hiccup mode, or overtemperature thermal shutdown (OTSD) is triggered, Px_FAULT is pulled low.

FAULT asserts (logic low) on an individual USB switch during an overcurrent or overtemperature condition.

Px_FAULT switches high after the fault condition is removed, and the USB output voltage goes high again.

The device features an active-low, open-drain fault output. Connect a 100-kΩ pull-up resistor from Px_FAULT to

SENSE or other suitable I/O voltage. Px_FAULT can be left open or tied to GND when not used.

Table 10-4 summarizes the conditions that generate a fault and actions taken by the device.

Table 10-4. Fault Conditions

EVENT

CONDITION

ACTION

Px_BUS load switch enter hiccup mode. The fault indicator

asserts with a 4.1-ms deglitch and de-asserts with a 16.4-

ms deglitch. The fault indicator remains asserted during the

Px_BUS overload condition.

Overcurrent on Px_BUS

I_{Px_BUS}> Programmed I_ILIM

The device immediately disables and asserts fault indicator

with no deglitch. The device attempts to power up once

the die temperature decreases below the thermal hysteresis

threshold as specified

TPS2586x-Q1

overtemperature

T_J> T_SD

10.3.15 USB Specification Overview

All USB ports are capable of providing a 5-V output, making them a convenient power source for operating

and charging portable devices. USB specification documents outline specific power requirements to ensure

interoperability. In general, a USB 2.0 port host port is required to provide up to 500 mA; a USB 3.0 or USB 3.1

port is required to provide up to 900 mA; ports adhering to the USB Battery Charging 1.2 Specification provide

up to 1500 mA; newer Type-C ports can provide up to 3000 mA. Though USB standards governing power

requirements exist, some manufacturers of popular portable devices created their own proprietary mechanisms

to extend allowed available current beyond the 1500 mA maximum per BC 1.2. While not officially part of

the standards maintained by the USB-IF, these proprietary mechanisms are recognized and implemented by

manufacturers of USB charging ports.

The TPS2586x-Q1 device supports five of the most-common USB-charging schemes found in popular hand-held

media and cellular devices:

•

USB Type-C (1.5-A and 3-A advertisement)

USB Battery Charging Specification BC1.2 DCP mode

Chinese Telecommunications Industry Standard YD/T 1591-2009

Divider 3 mode

1.2-V mode

10.3.16 USB Type-C^®Basics

For a detailed description of the Type-C specification, refer to the USB-IF website to download the latest

released version. Some of the basic concepts of the Type-C spec that pertains to understanding the operation of

the TPS2586x-Q1 (a DFP device) are described as follows.

USB Type-C removes the need for different plug and receptacle types for host and device functionality. The

Type-C receptacle replaces both the Type-A and Type-B receptacles since the Type-C cable is plug-able

in either direction between the host and device. A host-to-device logical relationship is maintained by the

configuration channel (CC). Optionally, hosts and devices can be either providers or consumers of power when

USB PD communication is used to swap roles.

All USB Type-C ports operate in one of following data modes:

•

Host mode: The port can only be a host (provider of power).

Device mode: The port can only be a device (consumer of power).

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•

Dual-Role mode: The port can be either a host or device.

Port types:

•

DFP (Downstream Facing Port): Host

UFP (Upstream Facing Port): Device

DRP (Dual-Role Port): Host or Device

Valid DFP-to-UFP connections:

•

Table 10-5 describes valid DFP-to-UFP connections.

Host-to-Host or Device-to-Device have no functions.

Table 10-5. DFP-to-UFP Connections

DEVICE-MODE

PORT

HOST-MODE PORT

DUAL-ROLE PORT

Host-Mode Port

Device-Mode Port

Dual-Role Port

No Function

Works

No Function

Works

Works⁽¹⁾

(1) This may be automatic or manually driven.

10.3.16.1 Configuration Channel

The function of the configuration channel is to detect connections and configure the interface across the USB

Type-C cables and connectors.

Functionally, the Configuration Channel (CC) is used to serve the following purposes:

•

Detect connect to the USB ports.

Resolve cable orientation and twist connections to establish USB data bus routing.

Establish DFP and UFP roles between two connected ports.

Discover and configure power: USB Type-C current modes or USB Power Delivery.

Discover and configure optional Alternate and Accessory modes.

Enhances flexibility and ease of use.

Typical flow of DFP-to-UFP configuration is shown in Figure 10-19.

Figure 10-19. Flow of DFP-to-UFP Configuration

10.3.16.2 Detecting a Connection

DFPs and DRPs fulfill the role of detecting a valid connection over USB Type-C. Figure 10-20 shows a DFP-to-

UFP connection made with a Type-C cable. As shown in Figure 10-20, the detection concept is based on being

able to detect terminations in the product that have been attached. A pull-up and pull-down termination model is

used. A pull-up termination can be replaced by a current source.

•

In the DFP-UFP connection, the DFP monitors both CC pins for a voltage lower than the unterminated

voltage.

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•

An UFP advertises Rd on both its CC pins (CC1 and CC2).

A powered cable advertises Ra on only one of the CC pins of the plug. Ra is used to inform the source to

apply VCONN.

•

An analog audio device advertises Ra on both CC pins of the plug, which identifies it as an analog audio

device. VCONN is not applied on either CC pin in this case.

UFP monitors for

connection

DFP monitors for

connection

Cable

CC

Rp

Rds

Ra

DFP monitors for

connection

UFP monitors for

connection

Figure 10-20. DFP-UFP Connection

For USB Type-C solutions, two pins (CC1, CC2) on the connector are used to establish and manage the

source-to-sink connection. The general concept for setting up a valid connection between a source and a sink

is based on being able to detect terminations residing in the product being attached. To aid in defining the

functional behavior of CC, a pull-up (Rp) and pull-down (Rd 5.1 kΩ) termination model is used based on a

pull-up resistor and pull-down resistor.

Initially, a source exposes independent Rp terminations on its CC1 and CC2 pins, and a sink exposes

independent Rd terminations on its CC1 and CC2 pins. The source-to-sink combination of this circuit

configuration represents a valid connection. To detect this, the source monitors CC1 and CC2 for a voltage

lower than its unterminated voltage. The choice of Rp is a function of the pull-up termination voltage and the

detection circuit of the source. This indicates that either a sink, a powered cable, or a sink connected by a

powered cable has been attached. Prior to the application of VCONN, a powered cable exposes Ra (typically 1

kΩ) on its VCONN pin. Ra represents the load on VCONN plus any resistive elements to ground. In some cable

plugs, this might be a pure resistance, and in others, it can simply be the load. The CC pin functional block is

shown in Figure 10-21.

Figure 10-21. Source Functional Model for CC1 and CC2 (From Type-C Specification)

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The source must be able to differentiate between the presence of Rd and Ra to know whether there is a sink

attached and where to apply VCONN. The source is not required to source VCONN unless Ra is detected. Two

special termination combinations on the CC pins as seen by a source are defined for directly attached accessory

modes: Ra/Ra for audio adapter accessory mode and Rd/Rd for debug accessory mode.

10.3.17 USB Port Operating Modes

10.3.17.1 USB Type-C^®Mode

The TPS2586x-Q1 port A is a Type-C controller that supports all Type-C functions in a downstream facing

port. It is also used to manage current advertisement and protection to a connected UFP and active cable.

When V_SENSEexceeds the undervoltage lockout threshold, the device samples the EN pin. A high level on this

pin enables the device and normal operation begins. Having successfully completed its start-up sequence, the

device now actively monitors its CC1 and CC2 pins for attachment to a UFP. When a UFP is detected on either

the CC1 or CC2 pin the USB power switch turn-ons. If Ra is detected on the other CC pin (not connected to

UFP), VCONN is applied to allow current to flow to the CC pin connected to Ra.

10.3.17.2 Dedicated Charging Port (DCP) Mode (TPS25860-Q1 Only)

A DCP only provides power and does not support data connection to an upstream port. As shown in the

following sections, a DCP is identified by the electrical characteristics of the data lines. The TPS25860-Q1

only emulates one state, DCP-auto state. In the DCP-auto state, the device charge-detection state machine is

activated to selectively implement charging schemes involved with the shorted, divider 3 and 1.2-V modes. The

shorted DCP mode complies with BC1.2 and Chinese Telecommunications Industry Standard YD/T 1591-2009,

whereas the divider 3 and 1.2-V modes are employed to charge devices that do not comply with the BC1.2 DCP

standard.

10.3.17.2.1 DCP BC1.2 and YD/T 1591-2009

Both standards specify that the D+ and D– data lines must be connected together with a maximum series

impedance of 200 Ω, as shown in Figure 10-22.

V_BUS

5 V

D–

200 Ω

(ma x.)

D+

GND

Figure 10-22. DCP Supporting BC1.2 and YD/T 1591-2009

10.3.17.2.2 DCP Divider-Charging Scheme

The device supports Divider 3, as shown in Figure 10-23. In the Divider 3 charging scheme the device applies

2.7 V and 2.7 V to D+ and D– data lines.

V_BUS

5 V

D–

D+

2.7 V

GND

Figure 10-23. Divider 3 Mode

10.3.17.2.3 DCP 1.2-V Charging Scheme

The DCP 1.2-V charging scheme is used by some hand-held devices to enable fast charging at 2 A. The

TPS25860-Q1 device supports this scheme in DCP-auto state before the device enters BC1.2 shorted mode. To

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simulate this charging scheme, the D+ and D– lines are shorted and pulled up to 1.2 V for a fixed duration. Then

the device moves to DCP shorted mode as defined in the BC1.2 specification and as shown in Figure 10-24.

V_BUS

5 V

200 Ω (ma x.) D–

D+

1.2 V

GND

Figure 10-24. 1.2-V Mode

10.3.17.3 DCP Auto Mode (TPS25860-Q1)

The TPS25860-Q1 device integrates an auto-detect state machine that supports all the DCP charging schemes

as shown in Figure 10-25. The auto-detect state machine starts in the Divider3 scheme. If a BC1.2 or YD/T

1591-2009 compliant device is attached, the TPS25860-Q1 device responds by turning the power switch back

on without output discharge and operating in 1.2-V mode briefly before entering BC1.2 DCP mode. Then,

the auto-detect state machine stays in that mode until the device releases the data line, in which case, the

auto-detect state machine goes back to the Divider 3 scheme. When a Divider 3-compliant device is attached,

the TPS25860-Q1 device stays in the Divider 3 state.

Figure 10-25. DCP Auto Mode

10.4 Device Functional Modes

10.4.1 Shutdown Mode

The EN pin provides electrical ON and OFF control for the TPS2586x-Q1. When V_ENis below 1.2 V (typical), the

device is in shutdown mode. The TPS2586x also employs V_INover voltage lock out protection and V_SENSEunder

voltage lock out protection. If V_INvoltage is above its respective OVLO level V_OVLO, or V_SENSEvoltage is below

its respective UVLO level V_{DCDC_UVLO}, the DC/DC converter will be turned off.

10.4.2 Active Mode

The TPS2586x-Q1 is in Active Mode when V_ENis above the precision enable threshold, V_SENSEis above its

respective UVLO levels and a valid detection has been made on the CC lines. The simplest way to enable the

TPS2586x-Q1 is to connect the EN pin to SENSE pin. This connection allows self startup when the input voltage

is in the operating range (5.5 V to 26 V) and a UFP detection is made.

In Active Mode, the TPS2586x-Q1 buck regulator operates with Forced Pulse Width Modulation (FPWM),

also referred to as Forced Continuous Conduction Mode (FCCM). This operation ensures the buck regulator

switching frequency remains constant under all load conditions. FPWM operation provides low output voltage

ripple, tight output voltage regulation, and constant switching frequency. Built-in spread-spectrum modulation

aids in distributing spectral energy across a narrow band around the switching frequency programmed by

the FREQ/SYNC pin. Under light load conditions the inductor current is allowed to go negative. A negative

current limit of IL_NEG is imposed to prevent damage to the regulator's low side FET. During operation the

TPS2586x-Q1 will synchronize to any valid clock signal on the FREQ/SYNC input.

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11 Application and Implementation

Note

Information in the following applications sections is not part of the TI component specification,

and TI does not warrant its accuracy or completeness. TI’s customers are responsible for

determining suitability of components for their purposes, as well as validating and testing their design

implementation to confirm system functionality.

11.1 Application Information

The TPS2586x-Q1 is a step down DC-to-DC regulator and USB charge port controller. The device is typically

used in automotive systems to convert a DC voltage from the vehicle battery to 5-V DC with a maximum output

current of 6-A in Type-C and Type-A dual ports applications. The TPS2586x-Q1 engages a high efficiency buck

converter, letting the device operate at as high as 85°C ambient temperature with full load. The following design

procedure can be used to select components for the TPS2586x-Q1.

11.2 Typical Applications

The TPS2586x-Q1 only requires a few external components to convert from a wide voltage range supply to a

5-V output to power USB devices. Figure 11-1 shows the TPS25860-Q1 typical application schematic for Type-A

and Type-C dual charging ports. Figure 11-2 shows the TPS25862-Q1 typical application schematic for Media

HUB.

Figure 11-1. TPS25860-Q1 Typical Application Circuit for 2.1-MHz f_SW

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Figure 11-2. TPS25862-Q1 Typical Application Circuit for 2.1-MHz f_SW

As a quick start guide, Table 11-1 provides typical component values for some of the most common

configurations. The values given in Table 11-1 are typical. Other values can be used to enhance certain

performance criterion as required by the application. The integrated buck regulator of TPS2586x-Q1 is internally

compensated and optimized for a reasonable selection of external inductance and capacitance. The external

components have to fulfill the needs of the application, but also the stability criteria of the control loop of the

device.

Table 11-1. L and C_OUTTypical Values

V_OUTWITHOUT CABLE

f_SW

L

C_HF+ C_IN

C_BOOT

RATED C_OUT

COMPENSATION

400 KHZ

2.1 MHz

5.17 V

3.3 µH

1 × 100 nF + 1 × 47 µF

1 × 100 nF + 1 × 22 µF

1 × 100 nF

3 × 47 µF

3 × 22 µF

5.17 V

0.68 µH

1. The inductance value is calculated based on max V_IN= 18 V.

2. All the C_OUTvalues are after derating and use low ESR ceramic capacitors.

3. The C_OUTis the buck regulator output capacitors at the SENSE pin.

11.2.1 Design Requirements

The detailed design procedure is described based on a design example. For this design example, use the

parameters listed in Table 11-2 as the input parameters.

Table 11-2. Design Example Parameters

Input Voltage, V_IN

13.5-V typical, range from 8 V to 18 V

Output Voltage, V_SENSE

Maximum Output Current

Switching Frequency f_SW

5.17 V

6 A

2.1 MHz

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11.2.2 Detailed Design Procedure

11.2.2.1 Output Voltage Setting

The output voltage of TPS2586x-Q1 is programmed by the VSET pin, and if short VSET to GND, sets the output

voltage at 5.17 V and enables the cable compensation function, and the output voltage increases linearly with

increasing load current. Refer to Table 10-2 for more details on output voltage setting. Cable compensation

can be used to increase the voltage on the SENSE pin linearly with increasing load current. Refer to list item

in Ground Plane and Thermal Considerations section for more details on cable compensation setting. If cable

compensation is not desired, use a 0-Ω R_IMONresistor.

11.2.2.2 Switching Frequency

The recommended switching frequency of the TPS2586x-Q1 is in the range of 250 KHz–2.2 MHz for high

efficiency. Choose R_FREQ= 49.9 kΩ for 400-KHz operation. To choose a different switching frequency, refer to

Table 10-1.

The choice of switching frequency is a compromise between conversion efficiency and overall solution size.

Lower switching frequency implies reduced switching losses and usually results in higher system efficiency.

However, higher switching frequency allows the use of smaller inductors and output capacitors, and hence, a

more compact design. In automotive USB charging applications, it tends to operate at either 400 kHz below the

AM band, or 2.1 MHz above the AM band. In this example, 2.1 MHz is chosen.

11.2.2.3 Inductor Selection

The most critical parameters for the inductor are the inductance, saturation current, and the rated current. The

inductance is based on the desired peak-to-peak ripple current, Δi_L. Since the ripple current increases with

the input voltage, the maximum input voltage is always used to calculate the minimum inductance L_MIN. Use

Equation 12 to calculate the minimum value of the output inductor. K_INDis a coefficient that represents the

amount of inductor ripple current relative to the maximum output current of the device. A reasonable value of

K_INDshould be 20% to 40%. Note that when selecting the ripple current for applications with much smaller

maximum load than the maximum available from the device, the maximum device current must still be used.

During an instantaneous short or overcurrent operation event, the RMS and peak inductor current can be high.

The inductor current rating must be higher than the current limit of the device.

V_OUTì V

- V_OUT

(

)

IN_MAX

Di_L=

V_{IN_MAX}ìL ì f_SW

(11)

(12)

V

- V_OUT

V_OUT

IN_MAX

L_MIN

=

ì

I_OUTìK_IND

V

_{IN_MAX}ì f_SW

In general, it is preferable to choose lower inductance in switching power supplies because it usually

corresponds to faster transient response, smaller DCR, and reduced size for more compact designs. Too low of

an inductance can generate too large of an inductor current ripple such that overcurrent protection at the full load

can be falsely triggered. It also generates more conduction loss and inductor core loss. Larger inductor current

ripple also implies larger output voltage ripple with the same output capacitors. With peak current mode control,

it is not recommended to have too small of an inductor current ripple. A larger peak current ripple improves the

comparator signal to noise ratio.

For this design example, choose K_IND= 0.3, and find an inductance of approximately 0.682 µH. Select the next

standard value of 0.68 μH.

11.2.2.4 Output Capacitor Selection

The output capacitor or capacitors, C_OUT, must be chosen with care since it directly affects the steady state

output voltage ripple, loop stability, and the voltage overshoot/undershoot during load current transients.

The value of the output capacitor and its ESR, determine the output voltage ripple and load transient

performance. The output capacitor is usually limited by the load transient requirements rather than the output

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voltage ripple if the system requires tight voltage regulation with presence of large current steps and fast slew

rate. When a fast large load increase happens, output capacitors provide the required charge before the inductor

current can slew up to the appropriate level. The control loop of the regulator usually needs four or more clock

cycles to respond to the output voltage droop. The output capacitance must be large enough to supply the

current difference for four clock cycles to maintain the output voltage within the specified range. Table 11-3 can

be used to find output capacitors for a few common applications. In this example, good transient performance is

desired giving 3 × 22-µF ceramic as the output capacitor.

Table 11-3. Selected Output Capacitor

FREQUENCY

2.1 MHz

C_OUT

SIZE/COST

Small size

Smallest size

Small size

TRANSIENT PERFORMANCE

3 × 22 µF ceramic

2 × 47 µF ceramic

2 × 22 µF ceramic

3 × 47 µF ceramic

2 × 47 µF ceramic

Good

Better

2.1 MHz

Minimum

Good

400 KHz

Minimum

Good

4 × 22 µF + 1 × 260 µF, < 50-mΩ electrolytic Larger size, low cost

1 × 4.7 µF + 2 × 10 µF + 1 × 260 µF, <

Lowest cost

400 KHz

Minimum

50-mΩ electrolytic

where

•

K_IND= Ripple ratio of the inductor ripple current (Δi_L/ I_OUT

I_OL= Low level output current during load transient

I_OH= High level output current during load transient

V_US= Target output voltage undershoot

)

V_OS= Target output voltage overshoot

11.2.2.5 Input Capacitor Selection

The TPS2586x-Q1 device requires a high frequency input decoupling capacitor or capacitors, depending on the

application. A high-quality ceramic capacitor type X5R or X7R with sufficient voltage rating is recommended.

The ceramic input capacitors provide a low impedance source to the converter in addition to supplying the ripple

current and isolating switching noise from other circuits. The typical recommended value for the high frequency

decoupling capacitor is 10 μF of ceramic capacitance. This must be rated for at least the maximum input voltage

that the application requires; preferably twice the maximum input voltage. This capacitance can be increased to

help reduce input voltage ripple, maintain the input voltage during load transients, or both. In addition, a small

case size 100-nF ceramic capacitor must be used at IN and PGND, immediately adjacent to the converter. This

provides a high frequency bypass for the control circuits internal to the device. For this example a 10-μF, 50-V,

X7R (or better) ceramic capacitor is chosen, and the 100-nF ceramic capacitor must also be rated at 50 V with

an X7R or better dielectric.

Additionally, an electrolytic capacitor on the input in parallel with the ceramics can be required, especially if long

leads from the automotive battery to the IN pin of the TPS2586x-Q1, cold or warm engine crank requirements,

and so forth. The moderate ESR of this capacitor is used to provide damping to the voltage spike due to the lead

inductance of the cable or the trace.

11.2.2.6 Bootstrap Capacitor Selection

The TPS2586x-Q1 design requires a bootstrap capacitor (C_BOOT). The recommended capacitor is 100 nF and

rated 16 V or higher. The bootstrap capacitor is located between the SW pin and the BOOT pin. The capacitor

stores energy that is used to supply the gate drivers for the power MOSFETs. The bootstrap capacitor must be a

high-quality ceramic type with an X7R or X5R grade dielectric for temperature stability.

11.2.2.7 Undervoltage Lockout Set-Point

The system undervoltage lockout (UVLO) is adjusted using the external voltage divider network of R_ENTand

R_ENB. The UVLO has two thresholds, one for power up when the input voltage is rising and one for power down

or brownouts when the input voltage is falling. Equation 13 can be used to determine the V_INUVLO level.

40

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R_ENT+ R_ENB

R_ENB

V

= V_ENHì

IN_RISING

(13)

The EN rising threshold (V_ENH) for the TPS2586x-Q1 is set to be 1.3 V (typical). Choose 10 kΩ for R_ENBto

minimize input current from the supply. If the desired V_INUVLO level is at 6.0 V, then the value of R_ENTcan be

calculated using Equation 14:

V

≈

’

IN_RISING

R_ENT

=

-1 ìR

∆

÷

ENB

÷

V_ENH

«

◊

(14)

Equation 14 yields a value of 36.1 kΩ. The resulting falling UVLO threshold equals 5.5 V and can be calculated

by Equation 15, where EN hysteresis (V_{EN_HYS}) is 0.1 V (typ.).

R_ENT+ R_ENB

R_ENB

V

= V_ENH- V_{EN_HYS}

(

ì

)

IN_FALLING

(15)

Note that it cannot connect EN to IN pin directly for self-start up. Because the voltage rating of EN pin is 11 V,

tying it to VIN directly damages the device. The simplest way to enable the operation of the TPS2586x-Q1 is to

connect the EN to V_SENSE. This allows the automatic start up when VIN is within the operation range.

11.2.2.8 Cable Compensation Set-Point

The TPS2586x-Q1 needs to short the VSET pin to ground to enable the cable compensation. With that

setting, the buck regulator increases its output voltage linearly as the load current increases, and the voltage

compensation at the currents of the USB ports greater than 2.4 A is 90 mV.

11.2.2.9 FAULT Resistor Selection

The FAULT pins are open-drain output flags. They can be connected to the TPS2586x-Q1 VSENSE with 100-kΩ

resistors, or connected to another suitable I/O voltage supply if actively monitored by a USB HUB or MCU. They

can be left floating if unused.

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11.2.3 Application Curves

Unless otherwise specified the following conditions apply: V_IN= 13.5 V, f_SW= 2100 kHz, L = 0.68 µH, C_SENSE= 66 µF,

C_{PA_BUS}= 1 µF, C_{PB_BUS}= 1 µF, ILIM = GND, T_A= 25 °C.

100

95

90

85

80

75

70

65

60

100

95

90

85

80

75

70

65

60

VIN=6V

VIN=13.5V

VIN=18V

VIN=26V

VIN=6V

VIN=13.5V

VIN=18V

0.1

1

6

0.1

1

6

Load Current(A)

VSET = GND

f_SW= 400 kHz

L = 3.3 uH

VSET = GND

f_SW= 2100 kHz

L = 0.68 uH

Figure 11-3. Buck Only Efficiency

Figure 11-4. Buck Only Efficiency

0.4

Level[dBuV]

VIN=6V

VIN=13.5V

0.2

VIN=18V

0

-0.2

-0.4

-0.6

-0.8

-1

Load = 6A

f_SW= 2100 kHz

L = 0.68 uH

-1.2

-1.4

Figure 11-5. 2.1-Mhz EMI Results (Without CM

Filter)

3

0

6

Load Current(A)

VSET = GND

f_SW= 2100 kHz

Figure 11-6. Load Regulation

Load=2A

0.1

Load=4A

Load=6A

VPA_BUS

200mV/Div

-0.1

-0.3

-0.5

-0.7

-0.9

-1.1

-1.3

-1.5

IPA_BUS

2A/Div

200.0us/Div

5

12

18

26

Input Voltage(V)

VSET = V_SENSE

I_{PA_BUS}= 0 A to 3 A

I_{PB_BUS}= 2.4 A

f_SW= 2100 kHZ

VSET = GND

f_SW= 2100 kHz

Figure 11-8. Load Transient Without Cable

Compensation

Figure 11-7. Line Regulation

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VPA_BUS

200mV/Div

IPA_BUS

2A/Div

VSET = V_SENSE

I_{PB_BUS}= 0 A to 2.4 A

I_{PA_BUS}= 3 A

f_SW= 2100 kHZ

200.0us/Div

Figure 11-9. Load Transient Without Cable

Compensation

VSET = V_SENSEI_{PA_BUS}= 0.75 A to 2.25 A

I_{PB_BUS}= 0 A

f_SW= 400 kHZ

Figure 11-10. Load Transient Without Cable

Compensation

VPA_BUS

200mV/Div

IPA_BUS

2A/Div

IPA_BUS

2A/Div

2.0ms/Div

VSET = GND I_{PA_BUS}= 0 A to 3 A

I_{PB_BUS}= 2.4 A

f_SW= 2100 kHZ

VSET = GND

I_{PA_BUS}= 0.75 A to 2.25 A

I_{PB_BUS}= 0 A

f_SW= 400 kHZ

Figure 11-11. Load Transient With Cable

Compensation

Figure 11-12. Load Transient With Cable

Compensation

5.2

Load=2A

Load=4A

SW

5V/Div

5.15

Load=6A

5.1

5.05

VPA_BUS

10mV/Div

5.0

4.95

500.0ns/Div

4.9

5.5

10.5

15.5

20.5

26

Input Voltage(V)

VSET = GND

I_{PA_BUS}= 3 A

I_{PB_BUS}= 2.4 A

f_SW= 2100 kHZ

Figure 11-13. Dropout Characteristic

Figure 11-14. 5.4-A Output Ripple

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SW

5V/Div

SW

5V/Div

VPA_BUS

10mV/Div

VPA_BUS

10mV/Div

500.0ns/Div

VSET = GND

I_{PA_BUS}= 0.1 A

I_{PB_BUS}= 0 A

f_SW= 2100 kHZ

VSET = GND

I_{PA_BUS}= 0 A

I_{PB_BUS}= 0 A

f_SW= 2100 kHZ

Figure 11-15. 100-mA Output Ripple

Figure 11-16. No Load Output Ripple

EN

5V/Div

EN

5V/Div

VIN

5V/Div

VIN

5V/Div

VPA_BUS

5V/Div

VPA_BUS

5V/Div

VSENSE

5V/Div

VSENSE

5V/Div

50ms/Div

20ms/Div

VIN = 0 V to 13.5 V

PA_CC1 = R_d

I_{PA_BUS}= 3 A

VIN = 13.5 V to 0 V

PA_CC1 = R_d

I_{PA_BUS}= 3 A

Figure 11-17. Startup Relate to VIN

Figure 11-18. Shutdown Relate to VIN

EN

5V/Div

EN

5V/Div

VIN

2V/Div

VIN

5V/Div

VPB_BUS

5V/Div

VPB_BUS

5V/Div

VSENSE

5V/Div

VSENSE

5V/Div

50ms/Div

EN = 0 V to 5 V

I_{PB_BUS}= 2.4 A

EN = 5 V to 0 V

I_{PB_BUS}= 2.4 A

Figure 11-19. Startup Relate to EN

Figure 11-20. Shutdown Relate to EN

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VIN

10V/Div

VIN

10V/Div

VPA_BUS

2V/Div

VPA_BUS

2V/Div

VPA_CC1

2V/Div

VPA_CC1

2V/Div

VPA_CC2

2V/Div

VPA_CC2

2V/Div

20ms/Div

50ms/Div

PA_CC1 = R_dto Open

PA_CC2 = Open

I_{PA_BUS}= 3 A

PA_CC1 = Open to R_d

PA_CC2 = Open

I_{PA_BUS}= 3 A

Figure 11-22. Rd Desert

Figure 11-21. Rd Assert

EN

5V/Div

EN

5V/Div

VPB_BUS

2V/Div

VPB_BUS

2V/Div

VPA_BUS

2V/Div

VPA_BUS

2V/Div

IPA_BUS

5A/Div

IPA_BUS

5A/Div

200.0ms/Div

EN to High

PA_BUS = GND

PB_BUS = GND

Figure 11-24. Short Circuit Recovery

Figure 11-23. Enable Into Short

EN

5V/Div

EN

5V/Div

VPB_BUS

2V/Div

VPB_BUS

2V/Div

VPA_BUS

3V/Div

VPA_BUS

3V/Div

IPA_BUS

3A/Div

IPA_BUS

3A/Div

500.0ms/Div

EN to High

PA_BUS = 1 Ω

PB_BUS = 1 Ω

Figure 11-26. 1-Ω Load Recovery

Figure 11-25. Enable Into 1-Ω Load

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VPA_CC1

2V/Div

EN

5V/Div

VPA_BUS

3V/Div

VPA_CC2

2V/Div

VPA_BUS

2V/Div

IPA_CC2

200mA/Div

IPA_BUS

5A/Div

2ms/Div

Figure 11-27. VBUS Hot Short to GND

PA_CC1 = R_d

PA_CC2 = R_a

Figure 11-28. PA_CC2 Hot Short to GND

EN

5V/Div

EN

5V/Div

VOUT

2V/Div

VOUT

2V/Div

VPA_BUS

2V/Div

VPA_BUS

2V/Div

IOUT

500mA/Div

IOUT

500mA/Div

5ms/Div

PA_CC1 = R_d

OUT = 5.1 Ω

PA/B_BUS NO LOAD

PA_CC1 = R_d

OUT = GND

PA/B_BUS NO LOAD

Figure 11-29. OUT Short to 5.1-Ω Load

Figure 11-30. OUT Hot Short to GND

VTS

2V/Div

VTS

2V/Div

VPA_BUS

5V/Div

VPA_BUS

5V/Div

VPA_CC1

2V/Div

VPA_CC1

2V/Div

SW

10V/Div

100.0ms/Div

SW

10V/Div

100.0ms/Div

V_TS= 0 V to 4 V

PA_CC1 = R_d

PA_CC2 = OPEN

V_TS= 0 V to 2.6 V

PA_CC1 = R_d

PA_CC2 = OPEN

Figure 11-32. Thermal Sensing - NTC Temperature

HOT Behavior

Figure 11-31. Thermal Sensing - NTC Temperature

WARM Behavior

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12 Power Supply Recommendations

The input supply must be able to withstand the maximum input current and maintain a stable voltage. The

resistance of the input supply rail must be low enough that an input current transient does not cause a high

enough drop at the TPS2586x-Q1 supply voltage that it causes a false UVLO fault triggering and system reset.

If the TPS2586x-Q1 is connected to the input supply through long wires or PCB traces, special care is required

to achieve good performance. An additional bulk capacitance can be required in addition to the ceramic input

capacitors. The amount of bulk capacitance is not critical, but a 100-μF electrolytic capacitor is a typical choice.

The input voltage must not be allowed to fall below the output voltage. In this scenario, such as a shorted input

test, the output capacitors discharge through the internal parasitic diode found between the VIN and SW pins of

the device. During this condition, the current can become uncontrolled, possibly causing damage to the device. If

this scenario is considered likely, then a Schottky diode between the input supply and the output must be used.

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13 Layout

13.1 Layout Guidelines

The PCB layout of any bulk converter is critical to the optimal performance of the design. Bad PCB layout can

disrupt the operation of an otherwise good schematic design. Even if the converter regulates correctly, bad PCB

layout can mean the difference between a robust design and one that cannot be mass produced. Furthermore,

the EMI performance of the converter is dependent on the PCB layout to a great extent. The following guidelines

will help users design a PCB with the best power conversion performance, thermal performance, and minimized

generation of unwanted EMI.

1. The input bypass capacitor, C_IN, must be placed as close as possible to the VIN and PGND pins. The high

frequency ceramic bypass capacitors at the input side provide a primary path for the high di/dt components

of the pulsing current. Use a wide VIN plane on a lower layer to connect both of the VIN pairs together to

the input supply. Grounding for both the input and output capacitors must consist of localized top-side planes

that connect to the PGND pin and PAD.

2. Use ground plane in one of the middle layers as noise shielding and heat dissipation path.

3. Have a single point ground connection to the plane. The ground connections for the feedback and enable

components must be routed to the ground plane. This prevents any switched or load currents from flowing in

the analog ground traces. If not properly handled, poor grounding can result in degraded load regulation or

erratic output voltage ripple behavior.

4. The SW pin connecting to the inductor must be as short as possible, and just wide enough to carry the

load current without excessive heating. Short, thick traces or copper pours (shapes) must be used for a high

current conduction path to minimize parasitic resistance. The output capacitors must be placed close to the

V_SENSEend of the inductor and closely grounded to PGND pin and exposed PAD.

5. Make V_IN, V_SENSE, and ground bus connections as wide as possible. This reduces any voltage drops on the

input or output paths of the converter and maximizes efficiency.

6. Provide enough PCB area for proper heat sinking. Enough copper area must be used to ensure a low R_θJA

commensurate with the maximum load current and ambient temperature. Make the top and bottom PCB

layers with two-ounce copper; and no less than one ounce. If the PCB design uses multiple copper layers

,

(recommended), thermal vias can also be connected to the inner layer heat-spreading ground planes. Note

that the package of this device dissipates heat through all pins. Wide traces must be used for all pins except

where noise considerations dictate minimization of area.

7. Use an array of heat-sinking vias to connect the exposed pad to the ground plane on the bottom PCB

layer. If the PCB has multiple copper layers, these thermal vias can also be connected to inner layer

heat-spreading ground planes. Ensure enough copper area is used for heat-sinking to keep the junction

temperature below 150°C.

8. R_ILIMand R_IMONresistors must be placed as close as possible to the ILIM and IMON pins and connected

to AGND. If needed, these components can be placed on the bottom side of the PCB with signals routed

through small vias.

9. Keep the CC lines close to the same length. Do not create stubs or test points on the CC lines.

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13.2 Layout Example

Figure 13-1. Layout Example

13.3 Ground Plane and Thermal Considerations

TI recommends to use one of the middle layers as a solid ground plane. Ground plane provides shielding for

sensitive circuits and traces. It also provides a quiet reference potential for the control circuitry. The AGND and

PGND pins must be connected to the ground plane using vias right next to the bypass capacitors. The PGND pin

is connected to the source of the internal low-side MOSFET switch, and also connected directly to the grounds

of the input and output capacitors. The PGND net contains noise at the switching frequency and can bounce

due to load variations. The PGND trace, as well as VIN and SW traces, must be constrained to one side of the

ground plane. The other side of the ground plane contains much less noise and should be used for sensitive

routes.

TI recommends to provide adequate device heat sinking by using the PAD of the IC as the primary thermal path.

Use a minimum 4 x 2 array of 12-mil thermal vias to connect the PAD to the system ground plane heat sink.

The vias must be evenly distributed under the PAD. Use as much copper as possible, for system ground plane,

on the top and bottom layers for the best heat dissipation. Use a four-layer board with the copper thickness for

the four layers, starting from the top of 2 oz / 1 oz / 1 oz / 2 oz. Four layer boards with enough copper thickness

provide low current conduction impedance, proper shielding, and lower thermal resistance.

The thermal characteristics of the TPS2586x-Q1 are specified using the parameter θ_JA, which characterizes

the junction temperature of silicon to the ambient temperature in a specific system. Although the value of θ_JA

is dependent on many variables, it still can be used to approximate the operating junction temperature of the

device. To obtain an estimate of the device junction temperature, one can use the following relationship:

T_J= P_D× θ_JA+ T_A

(16)

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where

•

T_J= Junction temperature in °C

P_D= V_IN× I_IN× (1 – Efficiency) – 1.1 × I_OUT²× DCR in Watt

DCR = Inductor DC parasitic resistance in Ω

θ_JA= Junction-to-ambient thermal resistance of the device in °C/W

T_A= Ambient temperature in °C

The maximum operating junction temperature of the TPS2586x-Q1 is 150°C. θ_JAis highly related to PCB size

and layout, as well as environmental factors such as heat sinking and air flow.

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14 Device and Documentation Support

14.1 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on

Subscribe to updates to register and receive a weekly digest of any product information that has changed. For

change details, review the revision history included in any revised document.

14.2 Support Resources

TI E2E^™support forums are an engineer's go-to source for fast, verified answers and design help — straight

from the experts. Search existing answers or ask your own question to get the quick design help you need.

Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do

not necessarily reflect TI's views; see TI's Terms of Use.

14.3 Trademarks

HotRod^™is a trademark of Texas Instruments.

TI E2E^™is a trademark of Texas Instruments.

USB Type-C^®is a registered trademark of USB Implementers Forum.

All trademarks are the property of their respective owners.

14.4 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled

with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may

be more susceptible to damage because very small parametric changes could cause the device not to meet its published

specifications.

14.5 Glossary

TI Glossary

This glossary lists and explains terms, acronyms, and definitions.

15 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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PACKAGE MATERIALS INFORMATION

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16-Oct-2021

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

A0

B0

K0

P1

W

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

TPS25860QRPQRQ1

TPS25862QRPQRQ1

VQFN-

HR

RPQ

25

3000

330.0

12.4

3.8

4.8

1.18

8.0

12.0

Q1

VQFN-

HR

330.0

12.4

3.8

4.8

1.18

8.0

12.0

Q1

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

16-Oct-2021

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

TPS25860QRPQRQ1

TPS25862QRPQRQ1

VQFN-HR

RPQ

25

3000

367.0

38.0

Pack Materials-Page 2

PACKAGE OUTLINE

RPQ0025A

VQFN - 1 mm max height

S

C

A

L

E

3

.

0

PLASTIC QUAD FLATPACK - NO LEAD

3.6

3.4

A

B

PIN 1 INDEX AREA

4.6

4.4

C

1.0

0.8

SEATING PLANE

0.08 C

0.05

0.00

1.325 0.1

0.975

0.775

4X

2X 1

8X (0.25)

EXPOSED

THERMAL PAD

SYMM

10

(0.2) TYP

12

9

13

1.45

1.25

3X

0.65 0.1

PKG

25

2X 4

PIN 1 ID

20X 0.5

0.3

0.2

24X

1

21

24

22

0.1

C A B

1.8

1.6

0.725

8X

3X

0.05

0.525

0.9

6X

0.7

4224966/A 04/2019

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

www.ti.com

EXAMPLE BOARD LAYOUT

RPQ0025A

VQFN - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

(1.325)

SYMM

4X (1.075)

3X

(1.9)

4X (0.675)

SEE SOLDER MASK

DETAIL

24

22

4X (0.575)

21

1

4X (0.25)

20X (0.5)

6X (1)

(1.5)

PKG

25

(0.65)

(R0.05) TYP

20X (0.25)

(1.675)

8X (0.825)

13

9

10

12

3X

(1.55)

(2.9)

(3.075)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE: 20X

0.07 MIN

ALL AROUND

0.07 MAX

ALL AROUND

METAL UNDER

SOLDER MASK

METAL EDGE

EXPOSED METAL

SOLDER MASK

OPENING

EXPOSED

METAL

SOLDER MASK

OPENING

NON SOLDER MASK

DEFINED

SOLDER MASK DEFINED

(PREFERRED)

SOLDER MASK DETAILS

4224966/A 04/2019

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown

on this view. It is recommended that vias under paste be filled, plugged or tented.

www.ti.com

EXAMPLE STENCIL DESIGN

RPQ0025A

VQFN - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

4X (1.075)

SYMM

6X (0.85)

4X (0.675)

22

24

4X (0.575)

21

1

4X (0.25)

20X (0.5)

(2.025)

(0.975)

6X (1)

2X

(0.563)

PKG

25

2X (0.325)

(1.237)

2X (0.65)

26X (0.25)

(2.112)

8X (0.825)

13

9

(R0.05) TYP

10

12

6X

(0.675)

EXPOSED METAL

TYP

(0.763)

(2.9)

(3.075)

SOLDER PASTE EXAMPLE

BASED ON 0.125 MM THICK STENCIL

SCALE: 20X

EXPOSED PAD 25

85% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE

4224966/A 04/2019

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

www.ti.com

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DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”

AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY

IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD

PARTY INTELLECTUAL PROPERTY RIGHTS.

These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate

TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable

standards, and any other safety, security, regulatory or other requirements.

These resources are subject to change without notice. TI grants you permission to use these resources only for development of an

application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license

is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you

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TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	TPS2586X-Q1
厂家：	TEXAS INSTRUMENTS
描述：	TPS2586x-Q1 2.2-MHz, Low EMI Dual USB Type-A and Type-CÂ® Charging Ports Controller With Sync DC/DC Converter and Programmable Current Limit
文件：	总59页 (文件大小：6105K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TPS2586X-Q1 [TI]

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