TPS259230DRCT [TI]
具有用于外部阻断 FET 的驱动器的 4.5V 至 5.5V、28mΩ、1A 至 5A 电子保险丝 | DRC | 10 | -40 to 85;
| 型号： | TPS259230DRCT |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有用于外部阻断 FET 的驱动器的 4.5V 至 5.5V、28mΩ、1A 至 5A 电子保险丝 | DRC | 10 | -40 to 85 电子 驱动 驱动器 |
| 文件： | 总34页 (文件大小：2069K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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TPS259230, TPS259231
ZHCSE39A –AUGUST 2015–REVISED AUGUST 2015
TPS25923x 具有过压保护和阻断 FET 控制功能的 5V 电子熔丝
1 特性
3 说明
1
•
•
5V 电子熔丝，VABSMAX = 20V
TPS25923x 系列电子熔丝是采用小型封装的高度集成
电路保护和电源管理解决方案。 该器件使用极少的外
部组件并可提供多重保护模式。 它们能够有效地防止
过载、短路、电压浪涌、过高浪涌电流和反向电流。
集成 28mΩ 导通金属氧化物半导体场效应晶体管
(MOSFET)
•
•
•
•
•
•
•
•
•
6.1V 固定过压钳位
1A 至 5A 可调电流 ILIMIT
±8% ILIMIT 精度（3.7A 时）
支持反向电流阻断
电流限制级别可通过一个外部电阻设定。 内部钳位电
路可将过电压限制在一个安全的固定最大值，无需使用
外部组件。 具有特殊电压斜坡要求的应用可以使用单
个电容来设定 dV/dT，以确保达到适当的输出斜坡速
率。
可编程 OUT（输出）转换率，欠压闭锁 (UVLO)
内置热关断
UL2367 认证正在处理中
单点故障测试期间安全 (UL60950)
许多系统（例如 SSD）禁止将储存的电容能量通过
FET 二极管倒流到降压或短路输入总线。 BFET 引脚
专用于这类系统。 外部 NFET 可与 TPS25923x 输出
形成“背靠背 (B2B)”连接，而由 BFET 驱动的栅极可防
止电流从负载流回电源（请参见Figure 43）。
小型封装尺寸 - 10L (3mm x 3mm) 超薄小外形尺寸
无引线封装 (VSON)
2 应用
•
•
•
•
•
•
适配器供电器件
器件信息(1)
硬盘 (HDD) 和固态硬盘 (SSD)
机顶盒
器件型号
TPS259230
TPS259231
封装
封装尺寸（标称值）
服务器/辅助 (AUX) 电源
风扇控制
VSON (10)
3.00mm × 3.00mm
(1) 要了解所有可用封装，请见数据表末尾的可订购产品附录。
PCI/PCIe 卡
应用电路原理图
瞬态：输出短路
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1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SLVSCV0
TPS259230, TPS259231
ZHCSE39A –AUGUST 2015–REVISED AUGUST 2015
www.ti.com.cn
目录
1
2
3
4
5
6
7
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Device Comparison Table..................................... 3
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
7.1 Absolute Maximum Ratings ..................................... 4
7.2 ESD Ratings ............................................................ 4
7.3 Recommended Operating Conditions...................... 4
7.4 Thermal Information ................................................. 5
7.5 Electrical Characteristics.......................................... 5
7.6 Timing Requirements ............................................... 6
7.7 Typical Characteristics.............................................. 7
Detailed Description ............................................ 13
8.1 Overview ................................................................. 13
8.2 Functional Block Diagram ....................................... 13
8.3 Feature Description................................................. 13
8.4 Device Functional Modes........................................ 16
9
Application and Implementation ........................ 17
9.1 Application Information............................................ 17
9.2 Typical Applications ............................................... 17
10 Power Supply Recommendations ..................... 23
10.1 Transient Protection.............................................. 23
10.2 Output Short-Circuit Measurements ..................... 23
11 Layout................................................................... 24
11.1 Layout Guidelines ................................................. 24
11.2 Layout Example .................................................... 24
12 器件和文档支持 ..................................................... 25
12.1 器件支持 ............................................................... 25
12.2 文档支持 ............................................................... 25
12.3 相关链接................................................................ 25
12.4 社区资源................................................................ 25
12.5 商标....................................................................... 25
12.6 静电放电警告......................................................... 25
12.7 Glossary................................................................ 25
13 机械、封装和可订购信息....................................... 25
8
4 修订历史记录
Changes from Original (August 2015) to Revision A
Page
•
已更改 产品预览至量产数据 ................................................................................................................................................... 1
2
Copyright © 2015, Texas Instruments Incorporated
TPS259230, TPS259231
www.ti.com.cn
ZHCSE39A –AUGUST 2015–REVISED AUGUST 2015
5 Device Comparison Table
PART NUMBER
TPS259231
UV
OV CLAMP
6.1 V
FAULT RESPONSE
Auto Retry
STATUS
Active
4.3 V
4.3 V
TPS259230
6.1 V
Latched
Active
6 Pin Configuration and Functions
DRC Package
10-Pin VSON
Top View
1
dV/dT
10 ILIM
EN/UVLO
BFET
OUT
OUT
GND
VIN
VIN
VIN
6
5
OUT
Pin Functions
PIN
NUMBER
DESCRIPTION
NAME
BFET
Connect this pin to the gate of a blocking NFET. See the Feature Description section. Leave this pin floating
9
if it is not used.
dV/dT
1
2
Tie a capacitor from this pin to GND to control the ramp rate of OUT at device turn-on.
EN/UVLO
This is a dual function control pin. When used as an ENABLE pin and pulled down, it shuts off the internal
pass MOSFET and pulls BFET to GND. When pulled high, it enables the device and BFET.
As an UVLO pin, it can be used to program different UVLO trip point via external resistor divider.
GND
ILIM
OUT
VIN
Thermal Pad
GND
10
6-8
3-5
A resistor from this pin to GND will set the overload and short circuit limit.
Output of the device
Input supply voltage
Copyright © 2015, Texas Instruments Incorporated
3
TPS259230, TPS259231
ZHCSE39A –AUGUST 2015–REVISED AUGUST 2015
www.ti.com.cn
7 Specifications
7.1 Absolute Maximum Ratings
over operating temperature range (unless otherwise noted)
(1) (2)
MIN
MAX
20
UNIT
VIN
Supply voltage(1)
–0.3
V
VIN (10 ms Transient)
22
OUT
Output voltage
–0.3
VIN + 0.3
V
V
OUT (Transient < 1 µs)
-1.2
7
ILIM
–0.3
–0.3
–0.3
–0.3
-65
EN/UVLO
7
Voltage
V
dV/dT
7
BFET
30
150
Storage temperature range, Tstg
°C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any conditions beyond those indicated under recommended operating conditions
is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values, except differential voltages, are with respect to network ground terminal.
7.2 ESD Ratings
VALUE
±2000
±500
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Charged device model (CDM), per JEDEC specification JESD22-C101(2)
V(ESD)
Electrostatic discharge
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN TYP
MAX UNIT
VIN
4.5
0
5
5.5
BFET
VIN+6
Input voltage range
V
6
dV/dT, EN/UVLO
0
ILIM
IOUT
0
3
Continuous output current
Resistance
0
5
162
A
ILIM
OUT
dV/dT
10
0.1
100
1
kΩ
µF
nF
°C
°C
1000
1000
125
External capacitance
1
Operating junction temperature range, TJ
Operating Ambient temperature range, TA
–40
–40
25
25
85
4
Copyright © 2015, Texas Instruments Incorporated
TPS259230, TPS259231
www.ti.com.cn
ZHCSE39A –AUGUST 2015–REVISED AUGUST 2015
7.4 Thermal Information(1)
over operating free-air temperature range (unless otherwise noted)
TPS25923x
THERMAL METRIC
DRC (VSON)
10 PINS
45.9
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
RθJCtop
RθJB
53
21.2
°C/W
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
1.2
ψJB
21.4
RθJCbot
5.9
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
7.5 Electrical Characteristics
–40°C ≤ TJ ≤ 125°C, VIN = 5 V, VEN /UVLO = 2 V, RILIM = 100 kΩ, CdVdT = OPEN. All voltages referenced to GND (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
4.15
0.35
TYP
MAX
UNIT
VIN (INPUT SUPPLY)
VUVR
UVLO threshold, rising
UVLO hysteresis(1)
4.3
5%
4.45
V
VUVhyst
IQON
Enabled: EN/UVLO = 2 V
0.47
0.1
0.6
mA
mA
Supply current
IQOFF
EN/UVLO = 0 V
0.225
VIN > 6.75 V, IOUT = 10 mA,
–40℃ ≤ TJ ≤ 85℃
5.5
6.1
6.1
6.75
6.75
VOVC
Over-voltage clamp
V
VIN > 6.75 V, IOUT = 10 mA,
–40℃ ≤ TJ ≤ 125℃
5.25
EN/UVLO (ENABLE/UVLO INPUT)
VENR
VENF
IEN
EN Threshold voltage, rising
1.37
1.32
–100
1.4
1.35
0
1.44
1.39
100
V
V
EN Threshold voltage, falling
EN Input leakage current
0 V ≤ VEN ≤ 5 V
nA
dV/dT (OUTPUT RAMP CONTROL)
IdVdT
dV/dT Charging current(1)
VdVdT = 0 V
220
75
nA
Ω
RdVdT_disch
VdVdTmax
GAINdVdT
dV/dT Discharging resistance
dV/dT Max capacitor voltage(1)
dV/dT to OUT gain(1)
EN/UVLO = 0 V, IdVdT = 10 mA sinking
50
100
5.5
V
ΔVdVdT
4.85
V/V
ILIM (CURRENT LIMIT PROGRAMMING)
IILIM
ILIM Bias current(1)
10
1.02
2.10
3.75
5.1
µA
A
RILIM = 10 kΩ, VVIN-OUT = 1 V
RILIM = 45.3 kΩ, VVIN-OUT = 1 V
RILIM = 100 kΩ, VVIN-OUT = 1 V
RILIM = 150 kΩ, VVIN-OUT = 1 V
1.79
3.46
4.5
2.42
4.03
5.7
IOL
Overload current limit(2)
RILIM = 0 Ω, Shorted Resistor Current Limit (Single Point
IOL-R-Short
IOL-R-Open
0.84
0.73
A
A
Failure Test: UL60950)(1)
RILIM = OPEN, Open Resistor Current Limit (Single Point
Failure Test: UL60950)(1)
RILIM = 10 kΩ, VVIN-OUT = 5 V
RILIM = 45.3 kΩ, VVIN-OUT = 5 V
RILIM = 100 kΩ, VVIN-OUT = 5 V
RILIM = 150 kΩ, VVIN-OUT = 5 V
1.01
2.05
3.56
4.95
1.72
3.14
4.22
2.42
3.98
5.69
ISCL
Short-circuit current limit(2)
A
(1) These parameters are provided for reference only and do not constitute part of TI's published device specifications for purposes of TI's
product warranty.
(2) Pulsed testing techniques used during this test maintain junction temperature approximately equal to ambient temperature.
Copyright © 2015, Texas Instruments Incorporated
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TPS259230, TPS259231
ZHCSE39A –AUGUST 2015–REVISED AUGUST 2015
www.ti.com.cn
Electrical Characteristics (continued)
–40°C ≤ TJ ≤ 125°C, VIN = 5 V, VEN /UVLO = 2 V, RILIM = 100 kΩ, CdVdT = OPEN. All voltages referenced to GND (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Fast-Trip comparator level w.r.t.
overload current limit(1)
RATIOFASTRIP
VOpenILIM
IFASTRIP : IOL
160%
ILIM Open resistor detect
threshold(1)
VILIM Rising, RILIM = OPEN
3.1
V
OUT (PASS FET OUTPUT)
TJ = 25°C
21
28
39
0
37
48
RDS(on)
FET ON resistance
mΩ
TJ = 125°C
IOUT-OFF-LKG
IOUT-OFF-SINK
BFET (BLOCKING FET GATE DRIVER)
VEN/UVLO = 0 V, VOUT = 0 V (Sourcing)
VEN/UVLO = 0V, VOUT = 300 mV (Sinking)
–5
10
1.2
20
OUT Bias current in off state
µA
15
IBFET
BFET Charging current(1)
VBFET = VOUT
2
µA
V
VVIN
+
6.4
VBFETmax
BFET Clamp voltage(1)
BFET Discharging resistance to
GND
RBFETdisch
VEN/UVLO = 0 V, IBFET = 100 mA
15
26
36
Ω
TSD (THERMAL SHUT DOWN)
TSHDN
TSD Threshold, rising(1)
TSD Hysteresis(1)
150
10
°C
°C
TSHDNhyst
TPS259230
TPS259231
LATCHED
AUTO-RETRY
Thermal fault: latched or autoretry
7.6 Timing Requirements
PARAMETER
TEST CONDITIONS
MIN
TYP
220
0.4
MAX UNIT
EN/UVLO → H to IVIN = 100 mA, 1-A resistive load at
TON
Turn-on delay(1)
Turn off delay(1)
µs
µs
OUT
tOFFdly
EN↓ to BFET↓, CBFET = 0
dV/dT (OUTPUT RAMP CONTROL)
EN/UVLO → H to OUT = 4.9 V, CdVdT = 0
0.28
0.4
5
0.52
ms
tdVdT Output ramp time
EN/UVLO → H to OUT = 4.9 V,
CdVdT = 1 nF(1)
ILIM (CURRENT LIMIT PROGRAMMING)
tFastOffDly
Fast-Trip comparator delay(1)
BFET (BLOCKING FET GATE DRIVER)
IOUT > IFASTRIP to IOUT = 0 (Switch Off)
300
ns
EN/UVLO → H to VBFET = 12 V, CBFET = 1 nF
EN/UVLO → H to VBFET = 12 V, CBFET = 10 nF
EN/UVLO → L to VBFET = 1 V, CBFET = 1 nF
EN/UVLO → L to VBFET = 1 V, CBFET = 10 nF
4.2
42
tBFET-ON
BFET Turn-On duration(1)
BFET Turn-Off duration(1)
ms
µs
0.4
1.4
tBFET-OFF
THERMAL SHUT DOWN (TSD)
Retry Delay after TSD Recovery,
tTSDdly
TPS259231 Only
100
µs
TJ < [TSHDN - 10oC](1)
(1) These parameters are provided for reference only and do not constitute part of TI's published device specifications for purposes of TI's
product warranty.
6
Copyright © 2015, Texas Instruments Incorporated
TPS259230, TPS259231
www.ti.com.cn
ZHCSE39A –AUGUST 2015–REVISED AUGUST 2015
7.7 Typical Characteristics
TJ = 25°C, VVIN = 5 V, VEN/UVLO = 2 V, RILIM = 100 kΩ, CVIN = 0.1 µF, COUT = 1 µF, CdVdT = OPEN (unless stated otherwise)
4.35
4.3
0.25
0.2
0.15
0.1
0.05
0
4.25
4.2
4.15
4.1
125 °C
85 °C
25 °C
-40 °C
4.05
4
-50
0
50
100
150
0
5
10
15
20
C001
C002
Temperature (°C)
VIN (V)
Figure 1. Input UVLO vs Temperature
Figure 2. IQ-OFF vs VIN
1
0.8
0.6
0.4
0.2
0
6.6
6.4
6.2
6
5.8
5.6
5.4
125 °C
85 °C
25 °C
-40 °C
10 mA
0
5
10
15
20
C004
VIN (V)
-50
0
50
100
150
Temperature (oC)
Figure 3. IVIN-ON vs VIN
Figure 4. VOVC vs Temperature
45
40
35
30
25
20
250
230
210
190
170
150
-50
0
50
100
150
-50
0
50
100
150
Temperature (oC)
Temperature (oC)
Figure 5. RDSON vs Temperature
Figure 6. TON vs Temperature
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TPS259230, TPS259231
ZHCSE39A –AUGUST 2015–REVISED AUGUST 2015
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Typical Characteristics (continued)
TJ = 25°C, VVIN = 5 V, VEN/UVLO = 2 V, RILIM = 100 kΩ, CVIN = 0.1 µF, COUT = 1 µF, CdVdT = OPEN (unless stated otherwise)
230
225
220
215
210
205
60
50
40
30
20
10
0
125 °C
85 °C
25 °C
-40 °C
-50
0
50
100
150
0
2
4
6
8
10
C010
C014
Temperature (°C)
CdVdT (nF)
Figure 7. IdVdT vs Temperature
Figure 8. TdVdT vs CdVdT
1.41
1.4
100
10
1
1.39
1.38
1.37
1.36
1.35
1.34
Rising
Falling
125°C
85°C
25°C
-40°C
0.1
0
1
2
3
4
5
-50
0
50
Temperature (oC)
100
150
V
(V)
EN
Figure 9. VEN-VIH, VEN-VIL vs Temperature
Figure 10. IEN (Leakage Current) vs VEN
6
5
4
3
2
1
4
3.5
3
2.5
2
125oC
125oC
85oC
25oC
-40oC
85oC
25oC
-40oC
1.5
1
0
0.5
1
1.5
2
0
0.5
1
1.5
2
V
(V)
V
(V)
VIN-OUT
VIN-OUT
RILIM = 150 kΩ
RILIM = 100 kΩ
Figure 11. IVOUT vs VVIN-OUT
Figure 12. IVOUT vs VVIN-OUT
8
Copyright © 2015, Texas Instruments Incorporated
TPS259230, TPS259231
www.ti.com.cn
ZHCSE39A –AUGUST 2015–REVISED AUGUST 2015
Typical Characteristics (continued)
TJ = 25°C, VVIN = 5 V, VEN/UVLO = 2 V, RILIM = 100 kΩ, CVIN = 0.1 µF, COUT = 1 µF, CdVdT = OPEN (unless stated otherwise)
2.2
2
0
2
-2
1.8
1.6
1.4
1.2
1
-4
-6
IOL-150k
ISC-150k
-8
-10
-12
-14
-16
125oC
85oC
25oC
-40oC
0
0.5
1
1.5
2
-50
0
50
100
150
Temperature (oC)
V
(V)
VIN-OUT
RILIM = 150 kΩ
RILIM = 45.3 kΩ
Figure 14. IOL, ISC vs Temperature
Figure 13. IVOUT vs VVIN-OUT
2
0
1
0
-2
-1
-2
-3
-4
-5
-4
IOL-45.3k
ISC-45.3k
IOL-100k
-6
ISC-100k
-8
-10
-12
-50
-6
0
50
100
150
-50
0
50
100
150
Temperature (oC)
Temperature (oC)
RILIM = 100 kΩ
RILIM = 45.3 kΩ
Figure 15. IOL, ISC vs Temperature
Figure 16. IOL, ISC vs Temperature
0.95
0.9
0.8
0.75
0.7
0.85
0.8
0.75
-50
0.65
-50
0
50
100
150
0
50
100
150
Temperature (oC)
Temperature (oC)
D001
D001
RILIM = 0Ω
RILIM = OPEN
Figure 17. IOL-R-Short vs Temperature
Figure 18. IOL-R-Open vs Temperature
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Typical Characteristics (continued)
TJ = 25°C, VVIN = 5 V, VEN/UVLO = 2 V, RILIM = 100 kΩ, CVIN = 0.1 µF, COUT = 1 µF, CdVdT = OPEN (unless stated otherwise)
3.1
3.09
3.08
3.07
3.06
3.05
35
30
25
20
15
10
5
0
-50
0
50
100
150
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
Temperature (oC)
Overload Current Limit (A)
D001
Figure 19. VOpenILIM vs Temperature
Figure 20. Accuracy vs Overload Current Limit
6
5
4
3
2
1
0
10000
1000
100
10
TA = -40oC
TA = 25oC
TA = 85oC
TA = 125oC
1
0.1
0
20
40
60
80
100
120
140
160
0.1
1
10
100
RILIM Resistor (kW)
Power Dissipation (W)
D001
D001
Figure 21. Overload Current Limit vs RILIM Resistor
Figure 22. Thermal Shutdown Time vs Power Dissipation
EN
EN
VIN
VIN
C1
C1
VOUT
C2
C3
C2
C3
VOUT
I_IN
I-IN
C4
C4
CdVdT = OPEN, COUT = 4.7 µF
CdVdT = 1 nF, COUT = 10 µF, ROUT = 2.5 Ω
Figure 23. Transient: Output Ramp
Figure 24. Transient: Output Ramp
10
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Typical Characteristics (continued)
TJ = 25°C, VVIN = 5 V, VEN/UVLO = 2 V, RILIM = 100 kΩ, CVIN = 0.1 µF, COUT = 1 µF, CdVdT = OPEN (unless stated otherwise)
VIN
VOUT
C2
C3
EN ↓
Figure 25. Transient: Turn Off Delay
Figure 26. Transient: Over Voltage Clamp
RILIM = 150 kΩ
RILIM = 150 kΩ
Figure 27. Transient: Output Short Circuit
Figure 28. Short Circuit (Zoom): Fast-Trip Comparator
TPS259231
TPS259231
Figure 29. Transient: Recovery From Short Circuit / Over
Current
Figure 30. Transient: Wake Up to Short Circuit
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Typical Characteristics (continued)
TJ = 25°C, VVIN = 5 V, VEN/UVLO = 2 V, RILIM = 100 kΩ, CVIN = 0.1 µF, COUT = 1 µF, CdVdT = OPEN (unless stated otherwise)
TPS259231
ILOAD Stepped from 65% to 125%, Back to 65%
Figure 32. Transient: Thermal Fault Auto-Retry
Figure 31. Transient: Overload Current Limit
EN ↓
TPS259230
Figure 34. Turn Off Delay to BFET
Figure 33. Transient: Thermal Fault Latched
VIN ↓
Figure 35. Turn Off Delay to BFET
12
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8 Detailed Description
8.1 Overview
The TPS25923x is an e-fuse with integrated power switch that is used to manage current/voltage/start-up voltage
ramp to a connected load. The device starts its operation by monitoring the VIN bus. When VIN exceeds the
undervoltage-lockout threshold (VUVR), the device samples the EN/UVLO pin. A high level on this pin enables
the internal MOSFET. As VIN rises, the internal MOSFET of the device will start conducting and allow current to
flow from VIN to OUT. When EN/UVLO is held low (below VENF), internal MOSFET is turned off. User also has
the ability to modify the output voltage ramp time by connecting a capacitor between dV/dT pin and GND.
After a successful start-up sequence, the device now actively monitors its load current and input voltage,
ensuring that the adjustable overload current limit IOL is not exceeded and input voltage spikes are safely
clamped to VOVC level at the output. This keeps the output device safe from harmful voltage and current
transients. The device also has built-in thermal sensor. In the event device temperature (TJ) exceeds TSHDN
,
typically 150°C, the thermal shutdown circuitry will shut down the internal MOSFET thereby disconnecting the
load from the supply. In TPS259230, the output will remain disconnected (MOSFET open) until power to device
is recycled or EN/UVLO is toggled (pulled low and then high). The TPS259231 device will remain off during a
cooling period until device temperature falls below TSHDN – 10°C, after which it will attempt to restart. This ON
and OFF cycle will continue until fault is cleared.
8.2 Functional Block Diagram
OUT
VIN
6,
7,
8
3,
4,
5
Current
Sense
28mW
+
UVLO
4.3V
Charge
Pump
4.08V
EN/
2mA
2
+
UVLO
EN
BFET
1.4V
Over
Voltage
9
1.35V
SWEN
6V
GATE
CONTROL
SWEN
22W
Thermal
Shutdown
6V
TSD
VIN
220nA
10mA
+
ILIMIT
dV/dT
GND
ILIM
1
4.8x
10
+
+
70pF
SWEN
Fast Trip
Comp
80W
EP
1.6*ILIMIT
8.3 Feature Description
8.3.1 GND
This is the most negative voltage in the circuit and is used as a reference for all voltage measurements unless
otherwise specified.
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Feature Description (continued)
8.3.2 VIN
Input voltage to the TPS25923x. A ceramic bypass capacitor close to the device from VIN to GND is
recommended to alleviate bus transients. The recommended operating voltage range is 4.5 V to 5.5 V for
TPS25923x. The device can continuously sustain a voltage of 20 V on VIN pin. However, above the
recommended maximum bus voltage, the device will be in over-voltage protection (OVP) mode, limiting the
output voltage to VOVC. The power dissipation in OVP mode is PD_OVP = (VVIN - VOVC) x IOUT, which can
potentially heat up the device and cause thermal shutdown.
8.3.3 dV/dT
Connect a capacitor from this pin to GND to control the slew rate of the output voltage at power-on. This pin can
be left floating to obtain a predetermined slew rate (minimum TdVdT) on the output. Equation governing slew rate
at start-up is shown below:
dVOUT
IdVdT ´GAINdVdT
=
dt
CdVdT + CINT
(1)
Where:
IdVdT = 220 nA (TYP)
CINT = 70 pF (TYP)
GAINdVdT = 4.85
dVOUT
= Desired output slew rate
dT
The total ramp time (TdVdT) for 0 to VIN can be calculated using the following equation:
TdVdT = 106 ´ V ´ C
+70 pF
dVdT
(
)
IN
(2)
For details on how to select an appropriate charging time/rate, refer to the applications section Setting Output
Voltage Ramp Time (TdVdT).
8.3.4 BFET
Connect this pin to an external NFET that can be used to disconnect input supply from rest of the system in the
event of power failure at VIN. The BFET pin is controlled by either input UVLO (VUVR) event or EN/UVLO (see
Table 1). BFET can source charging current of 2 µA (TYP) and sink (discharge) current from the gate of the
external FET via a 26-Ω internal discharge resistor to initiate fast turn-off, typically <1 µs. Due to 2 µA charging
current, it is recommended to use >10 MΩ impedance when probing the BFET node.
Table 1. BFET
EN/UVLO > VENR
VIN > VUVR
BFET MODE
Charge
H
X
L
H
L
Discharge
Discharge
X
8.3.5 EN/UVLO
As an input pin, it controls both the ON/OFF state of the internal MOSFET and that of the external blocking FET.
In its high state, the internal MOSFET is enabled and charging begins for the gate of external FET. A low on this
pin will turn off the internal MOSFET and pull the gate of the external FET to GND via the built-in discharge
resistor. High and Low levels are specified in the parametric table of the datasheet. The EN/UVLO pin is also
used to clear a thermal shutdown latch in the TPS259230 by toggling this pin (H→L).
The internal de-glitch delay on EN/UVLO falling edge is intentionally kept low (1 us typical) for quick detection of
power failure. When used with a resistor divider from supply to EN/UVLO to GND, power-fail detection on
EN/UVLO helps in quick turn-off of the BFET driver, thereby stopping the flow of reverse current (see typical
application diagram, Figure 43). For applications where a higher de-glitch delay on EN/UVLO is desired, or when
the supply is particularly noisy, it is recommended to use an external bypass capacitor from EN/UVLO to GND.
14
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8.3.6 ILIM
The device continuously monitors the load current and keeps it limited to the value programmed by RILIM. After
start-up event and during normal operation, current limit is set to IOL (over-load current limit).
IOL = 0.7 + 3´10-5 ´RILIM
(
)
(3)
When power dissipation in the internal MOSFET [PD = (VVIN – VOUT) × IOUT] exceeds 10 W, there is a 2% – 12%
thermal foldback in the current limit value so that IOL drops to ISC. In each of the two modes, MOSFET gate
voltage is regulated to throttle short-circuit and overload current flowing to the load. Eventually, the device shuts
down due to over temperature.
0
-2
-4
-6
-8
-10
-12
-14
0
10
20
30
40
50
60
Power (W)
Figure 36. Thermal Foldback in Current Limit
During a transient short circuit event, the current through the device increases very rapidly. The current-limit
amplifier cannot respond very quickly to this event due to its limited bandwidth. Therefore, the TPS2592
incorporates a fast-trip comparator, which shuts down the pass device very quickly when IOUT > IFASTRIP, and
terminates the rapid short-circuit peak current. The trip threshold is set to 60% higher than the programmed over-
load current limit (IFASTRIP = 1.6 x IOL). After the transient short-circuit peak current has been terminated by the
fast-trip comparator, the current limit amplifier smoothly regulates the output current to IOL (see figure below).
Figure 38. Fast-Trip and Current Limit Amplifier Response
for Short Circuit
Figure 37. Fast-Trip Current
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8.4 Device Functional Modes
The TPS25923x is
a hot-swap controller with integrated power switch that is used to manage
current/voltage/start-up voltage ramp to a connected load. The device starts its operation by monitoring the VIN
bus. When VVIN exceeds the undervoltage-lockout threshold (VUVR), the device samples the EN/UVLO pin. A high
level on this pin enables the internal MOSFET and also start charging the gate of external blocking FET (if
connected) via the BFET pin. As VIN rises, the internal MOSFET of the device and external FET (if connected)
will start conducting and allow current to flow from VIN to OUT. When EN/UVLO is held low (that is, below VENF),
the internal MOSFET is turned off and BFET pin is discharged, thereby, blocking the flow of current from VIN to
OUT. User also has the ability to modify the output voltage ramp time by connecting a capacitor between dV/dT
pin and GND.
Having successfully completed its start-up sequence, the device now actively monitors its load current and input
voltage, ensuring that the adjustable overload current limit IOL is not exceeded and input voltage spikes are safely
clamped to VOVC level at the output. This keeps the output device safe from harmful voltage and current
transients. The device also has built-in thermal sensor. In the event device temperature (TJ) exceeds TSHDN
,
typically 150°C, the thermal shutdown circuitry will shut down the internal MOSFET thereby disconnecting the
load from the supply. In the TPS259230, the output will remain disconnected (MOSFET open) until power to
device is recycled or EN/UVLO is toggled (pulled low and then high). The TPS259231 device will remain off
during a cooling period until device temperature falls below TSHDN – 10°C, after which it will attempt to restart.
This ON and OFF cycle will continue until fault is cleared.
16
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The TPA25923x is a smart eFuse. It is typically used for Hot-Swap and Power rail protection applications. It
operates from 4.5 V to 18 V with programmable current limit and undervoltage protection. The device aids in
controlling the in-rush current and provides precise current limiting during overload conditions for systems such
as Set-Top-Box, DTVs, Gaming Consoles, SSDs/HDDs and Smart Meters. The device also provides robust
protection for multiple faults on the sub-system rail.
The following design procedure can be used to select component values for the device. Alternatively, the
WEBENCH® software may be used to generate a complete design. The WEBENCH® software uses an iterative
design procedure and accesses a comprehensive database of components when generating a design.
Additionally, a spreadsheet design tool TPS2592xx Design Calculator (SLUC570) is available on web folder. This
section presents a simplified discussion of the design process.
9.2 Typical Applications
9.2.1 Simple 3.7-A eFuse Protection for Set Top Boxes
ëLb = 4.ꢁ to 18 ë
ëhÜÇ, LhÜÇ < 3.4!
Lb
hÜÇ
*
/
ëLb
w1
1aO
/
1µC
hÜÇ
28mO
0.1µC
9bꢀÜë[h
**
ꢂC9Ç
L[La
w2
dëdÇ
Db5
Çt{25923x
wL[La
100kO
**hptional & only needed for external Üë[h
*hptional & only for noise suppression
Figure 39. Typical Application Schematic: Simple 3.7-A eFuse for STBs
9.2.1.1 Design Requirements
Table 2. Design Parameters
DESIGN PARAMETER
Input voltage range, VIN
EXAMPLE VALUE
5 V
Undervoltage lockout set point, V(UV)
Overvoltage protection set point, V(OV)
Load at start-up, RL(SU)
Default: VUVR = 4.3 V
Default: VOVC = 6.1 V
2 Ω
3.7 A
1 µF
85°C
Current limit, IOL = IILIM
Load capacitance, COUT
Maximum ambient temperature, TA
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9.2.1.2 Detailed Design Procedure
The following design procedure can be used to select component values for the TPS25923x.
9.2.1.2.1 Step by Step Design Procedure
This design procedure below seeks to control the junction temperature of device under both static and transient
conditions by proper selection of output ramp-up time and associated support components. The designer can
adjust this procedure to fit the application and design criteria.
9.2.1.2.2 Programming the Current-Limit Threshold: RILIM Selection
The RILIM resistor at the ILIM pin sets the over load current limit, this can be set using Equation 4.
I
- 0.7
ILIM
R
=
ILIM
-5
3 x 10
(4)
For IOL = IILIM = 3.7 A, from Equation 4, RILIM = 100 kΩ. Choose closest standard value resistor with 1%
tolerance.
9.2.1.2.3 Undervoltage Lockout Set Point
The undervoltage lockout (UVLO) trip point is adjusted using the external voltage divider network of R1 and R2 as
connected between IN, EN/UVLO and GND pins of the device. The values required for setting the undervoltage
are calculated solving Equation 5.
R +R
1
2
V
=
´ V
ENR
(UV)
R
2
(5)
Where VENR = 1.4 V, is enable voltage rising threshold.
Since R1 and R2 will leak the current from input supply (VIN), these resistors should be selected based on the
acceptable leakage current from input power supply (VIN). The current drawn by R1 and R2 from the power
supply {IR12 = VIN/(R1 + R2)}.
However, leakage currents due to external active components connected to the resistor string can add error to
these calculations. So, the resistor string current, IR12 must be chosen to be 20x greater than the leakage current
expected.
For default UVLO of VUVR = 4.3 V, select R2 = OPEN, and R1 = 1 MΩ. Since EN/UVLO pin is rated only to 7 V, it
cannot be connected directly to VIN > 7 V. It has to be connected through R1 = 1 MΩ only, so that the pull-up
current for EN/UVLO pin is limited to < 20 µA.
The power failure threshold is detected on the falling edge of supply. This threshold voltage is 4% lower than the
rising threshold, VUVR. This is calculated using Equation 6.
V(PFAIL) = 0.96 x VUVR
(6)
Where VUVR is 4.3V, Power fail threshold set is : V(PFAIL) = 4.1 V.
9.2.1.2.4 Setting Output Voltage Ramp Time (TdVdT
)
For a successful design, the junction temperature of device should be kept below the absolute-maximum rating
during both dynamic (start-up) and steady state conditions. Dynamic power stresses often are an order of
magnitude greater than the static stresses, so it is important to determine the right start-up time and in-rush
current limit required with system capacitance to avoid thermal shutdown during start-up with and without load.
The ramp-up capacitor CdVdT needed is calculated considering the two possible cases:
9.2.1.2.4.1 Case 1: Start-Up without Load: Only Output Capacitance COUT Draws Current During Start-Up
During start-up, as the output capacitor charges, the voltage difference as well as the power dissipated across
the internal FET decreases. The average power dissipated in the device during start-up is calculated using
Equation 8.
For TPS25923x, the inrush current is determined as,
V
(IN)
I
= C x
(OUT)
(INRUSH)
T
dVdT
(7)
18
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Power dissipation during start-up is:
P
= 0.5 x V x I
(IN) (INRUSH)
D(INRUSH)
(8)
Equation 8 assumes that load does not draw any current until the output voltage has reached its final value.
9.2.1.2.4.2 Case 2: Start-Up with Load: Output Capacitance COUT and Load Draws Current During Start-Up
When load draws current during the turn-on sequence, there will be additional power dissipated. Considering a
resistive load during start-up (RL(SU)), load current ramps up proportionally with increase in output voltage during
TdVdT time. The average power dissipation in the internal FET during charging time due to resistive load is given
by:
2
V
æ
ö
÷
÷
ø
1
6
(IN)
÷
x
÷
ç
P
=
ç
D(LOAD)
ç
è
R
L(SU)
(9)
(10)
(11)
Total power dissipated in the device during startup is:
P
=
P + P
D(INRUSH) D(LOAD)
D(STARTUP)
Total current during startup is given by:
I
=
I
+ I (t)
(STARTUP)
(INRUSH) L
If I(STARTUP) > IOL, the device limits the current to IOL and the current limited charging time is determined by:
é
ê
ê
ê
ê
ê
ê
ê
ë
ù
ö
æ
ç
ç
ç
ç
ç
ç
ç
ç
ç
çI
÷
ú
÷
÷
ú
÷
I
÷
I
(INRUSH)
ú
÷
OL
÷
ú
÷
÷
T
=
C
x R
L(SU)
x
-1+LN
dVdT(Current-Limited)
OUT
V
I
ú
(IN)
÷
(INRUSH)
÷
-
ú
÷
OL
ç
÷
ú
÷
L(SU) ø
û
R
ç
è
(12)
The power dissipation, with and without load, for selected start-up time should not exceed the shutdown limits as
shown in Figure 40.
10000
1000
100
10
TA = -40oC
1
TA = 25oC
TA = 85oC
TA = 125oC
0.1
0.1
1
10
100
Power Dissipation (W)
D001
Figure 40. Thermal Shutdown Limit Plot
For the design example under discussion, select ramp-up capacitor CdVdT = OPEN. Then, using Equation 2.
6
T
= 10 x 5 x 0 + 70 pF = 350 ms
)
(
dVdT
(13)
The inrush current drawn by the load capacitance (COUT) during ramp-up using Equation 7.
5
I
= 1 mF x
= 14.3 mA
(INRUSH)
350 ms
(14)
(15)
The inrush Power dissipation is calculated, using Equation 8.
P
= 0.5 x 5 x 14.3 m = 36 mW
D(INRUSH)
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For 36 mW of power loss, the thermal shut down time of the device should not be less than the ramp-up time
TdVdT to avoid the false trip at maximum operating temperature. From thermal shutdown limit graph Figure 40 at
TA = 85°C, for 36 mW of power, the shutdown time is infinite. So it is safe to use 350 µs as start-up time without
any load on output.
Considering the start-up with load 2 Ω, the additional power dissipation, when load is present during start up is
calculated, using Equation 9.
5 x 5
P
=
= 2.08 W
D(LOAD)
6 ´ 2
(16)
The total device power dissipation during start up, using Equation 10 is:
P
= 2.08 + 36 m = 2.44 W
D(STARTUP)
(17)
From thermal shutdown limit graph at TA = 85°C, the thermal shutdown time for 2.44 W is more than 100 ms. So
it is well within acceptable limits to use no external capacitor (CdV/dT) with start-up load of 2 Ω.
If, due to large COUT, there is a need to decrease the power loss during start-up, it can be done with increase of
CdVdT capacitor.
9.2.1.2.5 Support Component Selection - CVIN
CVIN is a bypass capacitor to help control transient voltages, unit emissions, and local supply noise. Where
acceptable, a value in the range of 0.001 μF to 0.1 μF is recommended for CVIN
.
9.2.1.3 Application Curves
Figure 41. Output Ramp without Load on Output
Figure 42. Output Ramp with 2-Ω Load at Start Up
9.2.2 Inrush and Reverse Current Protection for Hold-Up Capacitor Application (for example, SSD)
.locking C9Ç
ëLb
w1
hÜÇ
ëhÜÇ, LhÜÇ < 2ꢀ7!
ëLb
*
ꢁIh[5-Üt
4700mC
ꢁëLb
0ꢀ1mC
28mW
ꢁ{516411
C[Çꢃ
1aW
9b/Üë[h
dëdÇ
.C9Ç
L[La
w2
4ꢂ3kW
ùóa61t03C
wL[La
76ꢀ8kW
ꢁdëdÇ
22nC
Db5
Çt{25923x
*hptional & only for noise suppression
Figure 43. Inrush and Reverse Current Protection for Hold-Up Capacitor Application (for example, SSD)
(TPS25923x UVLO is used as power fail comparator)
20
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9.2.2.1 Design Requirements
Table 3. Design Parameters
DESIGN PARAMETER
EXAMPLE VALUE
Input voltage range, VIN
Undervoltage lockout set point, V(UV)
Overvoltage protection set point, V(OV)
Load at start-up, RL(SU)
5 V
4.5 V
Default: VOVC = 6.1 V
1000 Ω
Current limit, IOL= IILIM
3 A
Load capacitance, COUT
4700 µF
85°C
Maximum ambient temperature, TA
9.2.2.2 Detailed Design Procedure
9.2.2.2.1 Programming the Current-Limit Threshold: RILIM Selection
The RILIM resistor at the ILIM pin sets the over load current limit, this can be set using Equation 4.
For IOL= IILIM = 3 A, from Equation 4, RILIM = 76.8 kΩ, choose closest standard value resistor with 1% tolerance.
9.2.2.2.2 Undervoltage Lockout Set Point
The undervoltage lockout (UVLO) trip point is adjusted using the external voltage divider network of R1 and R2 as
connected between IN, EN/UVLO and GND pins of the device. The values required for setting the undervoltage
are calculated solving Equation 5.
For UVLO of V(UV) = 4.5 V, select R2 = 453 kΩ, and R1 = 1 MΩ.
The power failure threshold is detected on the falling edge of supply. This threshold voltage is 4% lower than the
rising threshold, V(UV). This is calculated using Equation 6.
Where V(UV) = 4.5 V, Power fail threshold set is V(PFAIL) = 4.33 V.
9.2.2.2.3 Setting Output Voltage Ramp Time (TdVdT
)
For a successful design, the junction temperature of device should be kept below the absolute-maximum rating
during both dynamic (start-up) and steady state conditions. Dynamic power stresses often are an order of
magnitude greater than the static stresses, so it is important to determine the right start-up time and in-rush
current limit required with system capacitance to avoid thermal shutdown during start-up with and without load.
For the design example under discussion, select ramp-up capacitor CdVdT = 22 nF. Then, using Equation 2.
6
T
= 10 x 5 x 22 nF + 70 pF = 110 ms
)
(
dVdT
(18)
The inrush current drawn by the load capacitance (COUT) during ramp-up using Equation 7.
5
I
= 4700 mF x
= 213 mA
(INRUSH)
110 ms
(19)
(20)
The inrush Power dissipation is calculated, using Equation 8.
P
= 0.5 x 5 x 213 m = 533 mW
D(INRUSH)
Considering the start-up with load 1000 Ω, the additional power dissipation, when load is present during start up
is calculated, using Equation 9.
5 x 5
P
=
= 4.2 mW
D(LOAD)
6 ´ 1000
(21)
The total device power dissipation during start up is:
P
= 533 + 4.2 = 537 mW
D(STARTUP)
(22)
From thermal shutdown limit graph at TA = 85°C, the thermal shutdown time for 537 mW is more than 300 ms.
So the device will start safely.
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9.2.2.2.4 Support Component Selection - CVIN
CVIN is a bypass capacitor to help control transient voltages, unit emissions, and local supply noise. Where
acceptable, a value in the range of 0.001 μF to 0.1 μF is recommended for CVIN
.
9.2.2.3 Application Curves
COUT = CHOLD-UP
=
CdVdT = 22 nF
COUT = CHOLD-UP
=
V(PFAIL) = 4.33 V
RLOAD = 5 Ω
4700 µF
4700 µF
Figure 44. Output Ramp Up
Figure 45. Hold-Up Power when VIN fails
22
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ZHCSE39A –AUGUST 2015–REVISED AUGUST 2015
10 Power Supply Recommendations
The device is designed for supply voltage range of 4.5 V ≤ VIN ≤ 18 V. If the input supply is located more than a
few inches from the device an input ceramic bypass capacitor higher than 0.1 μF is recommended. Power supply
should be rated higher than the current limit set to avoid voltage droops during over current and short-circuit
conditions.
10.1 Transient Protection
In case of short circuit and over load current limit, when the device interrupts current flow, input inductance
generates a positive voltage spike on the input and output inductance generates a negative voltage spike on the
output. The peak amplitude of voltage spikes (transients) is dependent on value of inductance in series to the
input or output of the device. Such transients can exceed the Absolute Maximum Ratings of the device if steps
are not taken to address the issue.
Typical methods for addressing transients include:
•
•
•
•
Minimizing lead length and inductance into and out of the device
Using large PCB GND plane
Schottky diode across the output to absorb negative spikes
A low value ceramic capacitor (C(IN) = 0.001 µF to 0.1 µF) to absorb the energy and dampen the transients.
The approximate value of input capacitance can be estimated with Equation 23.
L
(IN)
V
= V
(IN)
+ I x
(LOAD)
SPIKE(Absolute)
C
(IN)
(23)
Where:
•
•
•
•
V(IN) is the nominal supply voltage
I(LOAD) is the load current
L(IN) equals the effective inductance seen looking into the source
C(IN) is the capacitance present at the input
Some applications may require the addition of a Transient Voltage Suppressor (TVS) to prevent transients from
exceeding the Absolute Maximum Ratings of the device.
The circuit implementation with optional protection components (a ceramic capacitor, TVS and schottky diode) is
shown in Figure 46.
ëLb
ëhÜÇ
Lb
hÜÇ
*
/
ëLb
28mO
w1
/
hÜÇ
0.1µC
9bꢀÜë[h
dëdÇ
*
*
ꢁC9Ç
L[La
w2
/
dëdÇ
Db5
Çt{25923x
*hptional components for
transient suppression
wL[La
Figure 46. Circuit Implementation with Optional Protection Components
10.2 Output Short-Circuit Measurements
It is difficult to obtain repeatable and similar short-circuit testing results. Source bypassing, input leads, circuit
layout and component selection, output shorting method, relative location of the short, and instrumentation all
contribute to variation in results. The actual short itself exhibits a certain degree of randomness as it
microscopically bounces and arcs. Care in configuration and methods must be used to obtain realistic results. Do
not expect to see waveforms exactly like those in the data sheet; every setup differs.
Copyright © 2015, Texas Instruments Incorporated
23
TPS259230, TPS259231
ZHCSE39A –AUGUST 2015–REVISED AUGUST 2015
www.ti.com.cn
11 Layout
11.1 Layout Guidelines
•
For all applications, a 0.01-µF or greater ceramic decoupling capacitor is recommended between IN terminal
and GND. For hot-plug applications, where input power path inductance is negligible, this capacitor can be
eliminated/minimized.
•
The optimum placement of decoupling capacitor is closest to the IN and GND terminals of the device. Care
must be taken to minimize the loop area formed by the bypass-capacitor connection, the IN terminal, and the
GND terminal of the IC. See Figure 47 for a PCB layout example.
•
•
•
High current carrying power path connections should be as short as possible and should be sized to carry at
least twice the full-load current.
The GND terminal must be tied to the PCB ground plane at the terminal of the IC. The PCB ground should be
a copper plane or island on the board.
Locate all support components: RILIM, CdVdT and resistors for EN/UVLO, close to their connection pin. Connect
the other end of the component to the GND pin of the device with shortest trace length. The trace routing for
the RILIM and CdVdT components to the device should be as short as possible to reduce parasitic effects on
the current limit and soft start timing. These traces should not have any coupling to switching signals on the
board.
•
•
Protection devices such as TVS, snubbers, capacitors, or diodes should be placed physically close to the
device they are intended to protect, and routed with short traces to reduce inductance. For example, a
protection Schottky diode is recommended to address negative transients due to switching of inductive loads,
and it should be physically close to the OUT pins.
Obtaining acceptable performance with alternate layout schemes is possible; however this layout has been
shown to produce good results and is intended as a guideline.
11.2 Layout Example
Çop layer
.ottom layer signal ground plane
ëia to signal ground plane
Dround -
.ottom
layer
1
2
3
4
5
dëꢄdÇ
ꢂbꢄÜë[ꢀ
ëLb
10
9
L[Lꢃ
.CꢂÇ
8
ꢀÜÇ
ꢀÜÇ
ꢀÜÇ
7
6
ëLb
ëLb
ëLb
ëhÜÇ
*
*
ëLb
Iigh Crequency
.ypass /apacitor
tower Dround
* ꢀptional: beeded only to suppress the transients caused ꢁy inductive load switching
Figure 47. Layout Example
24
版权 © 2015, Texas Instruments Incorporated
TPS259230, TPS259231
www.ti.com.cn
ZHCSE39A –AUGUST 2015–REVISED AUGUST 2015
12 器件和文档支持
12.1 器件支持
12.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
12.2 文档支持
12.2.1 相关文档
《TPS2592xx 设计计算器》（文献编号：SLUC570）
12.3 相关链接
以下表格列出了快速访问链接。 范围包括技术文档、支持与社区资源、工具和软件，并且可以快速访问样片或购买
链接。
表 4. 相关链接
器件
产品文件夹
请单击此处
请单击此处
样片与购买
请单击此处
请单击此处
技术文档
请单击此处
请单击此处
工具与软件
请单击此处
请单击此处
支持与社区
请单击此处
请单击此处
TPS259230
TPS259231
12.4 社区资源
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.5 商标
E2E is a trademark of Texas Instruments.
WEBENCH is a registered trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.6 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
12.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 机械、封装和可订购信息
以下页中包括机械、封装和可订购信息。 这些信息是针对指定器件可提供的最新数据。 这些数据会在无通知且不
对本文档进行修订的情况下发生改变。 欲获得该数据表的浏览器版本，请查阅左侧的导航栏。
版权 © 2015, Texas Instruments Incorporated
25
PACKAGE OPTION ADDENDUM
www.ti.com
18-Jul-2023
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS259230DRCR
TPS259230DRCT
TPS259231DRCR
TPS259231DRCT
ACTIVE
ACTIVE
ACTIVE
ACTIVE
VSON
VSON
VSON
VSON
DRC
DRC
DRC
DRC
10
10
10
10
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 85
-40 to 85
-40 to 85
-40 to 85
259230
Samples
Samples
Samples
Samples
NIPDAU
NIPDAU
NIPDAU
259230
259231
259231
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
18-Jul-2023
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Apr-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS259230DRCR
TPS259230DRCT
TPS259231DRCR
TPS259231DRCR
TPS259231DRCT
TPS259231DRCT
VSON
VSON
VSON
VSON
VSON
VSON
DRC
DRC
DRC
DRC
DRC
DRC
10
10
10
10
10
10
3000
250
330.0
180.0
330.0
330.0
180.0
180.0
12.4
12.4
12.4
12.4
12.4
12.4
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
1.1
1.1
1.1
1.1
1.1
1.1
8.0
8.0
8.0
8.0
8.0
8.0
12.0
12.0
12.0
12.0
12.0
12.0
Q2
Q2
Q2
Q2
Q2
Q2
3000
3000
250
250
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Apr-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPS259230DRCR
TPS259230DRCT
TPS259231DRCR
TPS259231DRCR
TPS259231DRCT
TPS259231DRCT
VSON
VSON
VSON
VSON
VSON
VSON
DRC
DRC
DRC
DRC
DRC
DRC
10
10
10
10
10
10
3000
250
367.0
210.0
367.0
346.0
210.0
210.0
367.0
185.0
367.0
346.0
185.0
185.0
35.0
35.0
35.0
33.0
35.0
35.0
3000
3000
250
250
Pack Materials-Page 2
GENERIC PACKAGE VIEW
DRC 10
3 x 3, 0.5 mm pitch
VSON - 1 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4226193/A
www.ti.com
PACKAGE OUTLINE
DRC0010J
VSON - 1 mm max height
SCALE 4.000
PLASTIC SMALL OUTLINE - NO LEAD
3.1
2.9
B
A
PIN 1 INDEX AREA
3.1
2.9
1.0
0.8
C
SEATING PLANE
0.08 C
0.05
0.00
1.65 0.1
2X (0.5)
(0.2) TYP
EXPOSED
THERMAL PAD
4X (0.25)
5
6
2X
2
11
SYMM
2.4 0.1
10
1
8X 0.5
0.30
0.18
10X
SYMM
PIN 1 ID
0.1
C A B
C
(OPTIONAL)
0.05
0.5
0.3
10X
4218878/B 07/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
DRC0010J
VSON - 1 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(1.65)
(0.5)
10X (0.6)
1
10
10X (0.24)
11
(2.4)
(3.4)
SYMM
(0.95)
8X (0.5)
6
5
(R0.05) TYP
(
0.2) VIA
TYP
(0.25)
(0.575)
SYMM
(2.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:20X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
EXPOSED METAL
EXPOSED METAL
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
SOLDER MASK
DEFINED
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4218878/B 07/2018
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
DRC0010J
VSON - 1 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
2X (1.5)
(0.5)
SYMM
EXPOSED METAL
TYP
11
10X (0.6)
1
10
(1.53)
10X (0.24)
2X
(1.06)
SYMM
(0.63)
8X (0.5)
6
5
(R0.05) TYP
4X (0.34)
4X (0.25)
(2.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 11:
80% PRINTED SOLDER COVERAGE BY AREA
SCALE:25X
4218878/B 07/2018
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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Copyright © 2023，德州仪器 (TI) 公司
相关型号：
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