TPS259271DRCR [TI]
具有用于外部阻断 FET 的驱动器的 4.5V 至 18V、28mΩ、1A 至 5A 电子保险丝 | DRC | 10 | -40 to 85;
| 型号： | TPS259271DRCR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有用于外部阻断 FET 的驱动器的 4.5V 至 18V、28mΩ、1A 至 5A 电子保险丝 | DRC | 10 | -40 to 85 电子 驱动 驱动器 |
| 文件： | 总35页 (文件大小：1985K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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TPS259270, TPS259271
ZHCSE37E –AUGUST 2015–REVISED NOVEMBER 2017
TPS25927x 具有阻断 FET 控制功能的 4.5V 至 18V 电子熔丝
1 特性
3 说明
1
•
4.5V 至 18V 保护
TPS25927x 系列电子熔丝是采用小型封装的高度集成
电路保护和电源管理解决方案。该器件使用极少的外部
组件并可提供多重保护模式。它们能够有效地防止过
载、短路、过高浪涌电流和反向电流。
•
集成 28mΩ 导通金属氧化物半导体场效应晶体管
(MOSFET)
•
•
•
•
•
•
•
最大绝对电压 20V
1A 至 5A 可调电流 ILIMIT
±8% ILIMIT 精度（3.7A 时）
支持反向电流阻断
电流限制级别可通过单个外部电阻设定。对于 电压斜
坡有特别要求的应用可以通过单个电容器来设定 dV/dT
引脚，以确保合适的输出斜率。
可编程 OUT（输出）转换率，欠压闭锁 (UVLO)
内置热关断
许多系统（例如 SSD）禁止将储存的电容能量通过
FET 二极管倒流到降压或短路输入总线。BFET 引脚
专用于这类系统。外部 NFET 可与 TPS25927x 输出
形成“背靠背 (B2B)”连接，而由 BFET 驱动的栅极可防
止电流从负载流回电源。
通过 UL 2367 认证 – 文件编号 E339631*
–
*RILIM ≤ 130 kΩ（最大电流 5A）
•
•
单点故障测试期间安全 (UL60950)
小型封装尺寸 - 10L (3mm x 3mm) 超薄小外形尺寸
无引线封装 (VSON)
器件信息(1)
器件型号
TPS259270
TPS259271
封装
封装尺寸（标称值）
2 应用
•
•
•
•
•
•
硬盘 (HDD) 和固态硬盘 (SSD)
VSON (10)
3.00mm × 3.00mm
机顶盒
(1) 要了解所有可用封装，请参阅数据表末尾的可订购产品附录。
服务器/辅助 (AUX) 电源
风扇控制
PCI/PCIe 卡
适配器供电器件
应用电路原理图
瞬态：输出短路
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1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SLVSCU8
TPS259270, TPS259271
ZHCSE37E –AUGUST 2015–REVISED NOVEMBER 2017
www.ti.com.cn
目录
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings ............................................................ 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information ................................................. 5
6.5 Electrical Characteristics........................................... 5
6.6 Timing Requirements ............................................... 6
6.7 Typical Characteristics.............................................. 7
Detailed Description ............................................ 13
7.1 Overview ................................................................. 13
7.2 Functional Block Diagram ....................................... 13
7.3 Feature Description................................................. 13
7.4 Device Functional Modes........................................ 16
8
9
Application and Implementation ........................ 17
8.1 Application Information............................................ 17
8.2 Typical Application ................................................. 17
Power Supply Recommendations...................... 22
9.1 Transient Protection................................................ 22
9.2 Output Short-Circuit Measurements ....................... 23
10 Layout................................................................... 24
10.1 Layout Guidelines ................................................. 24
10.2 Layout Example .................................................... 24
11 器件和文档支持 ..................................................... 25
11.1 器件支持 ............................................................... 25
11.2 文档支持 ............................................................... 25
11.3 相关链接................................................................ 25
11.4 接收文档更新通知 ................................................. 25
11.5 社区资源................................................................ 25
11.6 商标....................................................................... 25
11.7 静电放电警告......................................................... 25
11.8 Glossary................................................................ 26
12 机械、封装和可订购信息....................................... 26
7
4 修订历史记录
Changes from Revision D (January 2017) to Revision E
Page
•
已删除 删除了功能方框图 中的过压........................................................................................................................................ 1
Changes from Revision C (September 2017) to Revision D
Page
•
Changed status of TPS259270 from Preview to Active in the Table 1 .................................................................................. 3
Changes from Revision B (September 2016) to Revision C
Page
•
Added Transient junction temperature to Absolute Maximum Ratings table ......................................................................... 4
Changes from Revision A (August 2015) to Revision B
Page
•
Added section:Controlled Power Down using TPS25927x ................................................................................................. 20
Changes from Original (August 2015) to Revision A
Page
•
已更改 “产品预览”至“量产数据”............................................................................................................................................... 1
2
Copyright © 2015–2017, Texas Instruments Incorporated
TPS259270, TPS259271
www.ti.com.cn
ZHCSE37E –AUGUST 2015–REVISED NOVEMBER 2017
Table 1. Device Comparison Table
PART NUMBER
UV
OV CLAMP
FAULT RESPONSE
Auto-retry
STATUS
Active
TPS259271
TPS259270
4.3 V
4.3 V
—
—
Latched
Active
5 Pin Configuration and Functions
DRC Package
10-Pin VSON
Top View
1
dV/dT
10 ILIM
EN/UVLO
BFET
OUT
OUT
GND
VIN
VIN
VIN
6
5
OUT
Pin Functions
PIN
I/O
DESCRIPTION
NAME
BFET
NO.
Connect this pin to the gate of a blocking NFET. See the Feature Description
section. This pin can be left floating if it is not used
9
O
dV/dT
Connect a capacitor from this pin to GND to control the ramp rate of OUT at
device turnon
1
2
O
I
EN/UVL
O
This is a dual function control pin. When used as an ENABLE pin and pulled
down, it shuts off the internal pass MOSFET and pulls BFET to GND. When
pulled high, it enables the device and BFET.
As an UVLO pin, it can be used to program different UVLO trip point via
external resistor divider
GND
Thermal
Pad
—
GND
ILIM
OUT
VIN
10
6-8
3-5
O
O
I
A resistor from this pin to GND sets the overload and short circuit limit
Output of the device
Input supply voltage
Copyright © 2015–2017, Texas Instruments Incorporated
3
TPS259270, TPS259271
ZHCSE37E –AUGUST 2015–REVISED NOVEMBER 2017
www.ti.com.cn
6 Specifications
6.1 Absolute Maximum Ratings
over operating temperature range (unless otherwise noted)
(1) (2)
MIN
MAX
20
UNIT
VIN
–0.3
Supply voltage(1)
VIN (10 ms Transient)
V
22
OUT
–0.3
VIN + 0.3
V
V
Output voltage
OUT (Transient < 1 µs)
–1.2
7
ILIM
–0.3
–0.3
–0.3
–0.3
–65
EN/UVLO
Voltage
dV/dT
7
V
7
BFET
30
Transient junction temperature
TSHDN
150
°C
°C
Tstg
Storage temperature
–65
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values, except differential voltages, are with respect to network ground terminal.
6.2 ESD Ratings
MAX
±2000
±500
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Charged device model (CDM), per JEDEC specification JESD22-C101(2)
V(ESD)
Electrostatic discharge
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN TYP
MAX UNIT
VIN
4.5
18(1)
BFET
0
VIN+6
Input voltage
V
6
dV/dT, EN/UVLO
0
ILIM
IOUT
ILIM
OUT
dV/dT
TJ
0
3
Continuous output current
Resistance
0
5
162
A
10 100
kΩ
µF
nF
°C
°C
0.1
1
1
1000
1000
125
External capacitance
Operating junction temperature
Operating Ambient temperature
–40
–40
25
25
TA
85
(1) Maximum voltage (including input transients) at VIN pin must not exceed absolute maximum rating as specified in the Absolute
Maximum Ratings table.
4
Copyright © 2015–2017, Texas Instruments Incorporated
TPS259270, TPS259271
www.ti.com.cn
ZHCSE37E –AUGUST 2015–REVISED NOVEMBER 2017
6.4 Thermal Information(1)
over operating free-air temperature range (unless otherwise noted)
TPS25927x
THERMAL METRIC
DRC (VSON)
10 PINS
45.9
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJCtop
RθJB
53
21.2
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
1.2
ψJB
21.4
RθJCbot
5.9
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Electrical Characteristics
–40°C ≤ TJ ≤ +125°C, VIN = 12 V, VEN /UVLO = 2 V, RILIM = 100 kΩ, CdVdT = OPEN. All voltages referenced to GND (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
4.15
0.3
TYP
MAX
UNIT
VIN (INPUT SUPPLY)
VUVR
UVLO threshold, rising
UVLO hysteresis(1)
4.3
5%
4.45
V
VUVhyst
IQON
Enabled: EN/UVLO = 2 V
0.42
0.13
0.55
mA
mA
Supply current
IQOFF
EN/UVLO = 0 V
0.225
EN/UVLO (ENABLE/UVLO INPUT)
VENR
VENF
IEN
EN threshold voltage, rising
1.37
1.32
–100
1.4
1.35
0
1.44
1.39
100
V
V
EN threshold voltage, falling
EN Input leakage current
0 V ≤ VEN ≤ 5 V
nA
dV/dT (OUTPUT RAMP CONTROL)
IdVdT
dV/dT charging current(1)
VdVdT = 0 V
220
73
nA
Ω
RdVdT_disch
VdVdTmax
GAINdVdT
dV/dT discharging resistance
dV/dT Max capacitor voltage(1)
dV/dT to OUT gain(1)
EN/UVLO = 0 V, IdVdT = 10 mA sinking
50
100
5.5
V
ΔVdVdT
4.85
V/V
ILIM (CURRENT LIMIT PROGRAMMING)
IILIM
ILIM bias current(1)
10
1.02
2.10
3.75
5.1
µA
A
RILIM = 10 kΩ, VVIN – OUT = 1 V
RILIM = 45.3 kΩ, VVIN – OUT = 1 V
RILIM = 100 kΩ, VVIN – OUT = 1 V
RILIM = 150 kΩ, VVIN – OUT = 1 V
1.79
3.46
4.5
2.42
4.03
5.7
IOL
Overload current limit(2)
RILIM = 0 Ω, shorted resistor current limit (single point failure
IOL-R-Short
IOL-R-Open
0.84
0.73
A
A
test: UL60950)(1)
RILIM = OPEN, open resistor current limit (single point failure
test: UL60950)(1)
RILIM = 10 kΩ, VVIN – OUT = 12 V
RILIM = 45.3 kΩ, VVIN – OUT = 12 V
RILIM = 100 kΩ, VVIN – OUT = 12 V
RILIM = 150 kΩ, VVIN – OUT = 12 V
1
1.98
3.32
4.5
1.66
2.90
3.7
2.37
3.85
5.5
ISCL
Short-circuit current limit(2)
A
Fast-trip comparator level w.r.t.
overload current limit(1)
RATIOFASTRIP
VOpenILIM
IFASTRIP : IOL
160%
3.1
ILIM open resistor detect
threshold(1)
VILIM Rising, RILIM = OPEN
V
(1) These parameters are provided for reference only and do not constitute part of TI's published device specifications for purposes of TI's
product warranty.
(2) Pulsed testing techniques used during this test maintain junction temperature approximately equal to ambient temperature.
Copyright © 2015–2017, Texas Instruments Incorporated
5
TPS259270, TPS259271
ZHCSE37E –AUGUST 2015–REVISED NOVEMBER 2017
www.ti.com.cn
Electrical Characteristics (continued)
–40°C ≤ TJ ≤ +125°C, VIN = 12 V, VEN /UVLO = 2 V, RILIM = 100 kΩ, CdVdT = OPEN. All voltages referenced to GND (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OUT (PASS FET OUTPUT)
TJ = 25°C
21
28
39
0
37
48
RDS(on)
FET ON resistance
mΩ
TJ = 125°C
IOUT-OFF-LKG
IOUT-OFF-SINK
VEN/UVLO = 0 V, VOUT = 0 V (sourcing)
VEN/UVLO = 0 V, VOUT = 300 mV (sinking)
–5
10
1.2
20
OUT Bias current in off state
µA
15
BFET (BLOCKING FET GATE DRIVER)
IBFET
BFET charging current(1)
VBFET = VOUT
2
µA
V
VVIN
+
6.4
VBFETmax
BFET clamp voltage(1)
BFET discharging resistance to
GND
RBFETdisch
VEN/UVLO = 0 V, IBFET = 100 mA
15
26
36
Ω
TSD (THERMAL SHUT DOWN)
TSHDN
TSD threshold, rising(1)
TSD hysteresis(1)
150
10
°C
°C
TSHDNhyst
TPS259270
TPS259271
Latched
Auto-retry
Thermal fault: latched or auto-retry
6.6 Timing Requirements
PARAMETER
TEST CONDITIONS
MIN
TYP
220
0.4
MAX UNIT
EN/UVLO → H to IVIN = 100 mA, 1-A resistive load at
TON
Turnon delay(1)
Turnoff delay(1)
µs
µs
OUT
tOFFdly
EN↓ to BFET↓, CBFET = 0
dV/dT (OUTPUT RAMP CONTROL)
EN/UVLO → H to OUT = 11.7 V, CdVdT = 0
EN/UVLO → H to OUT = 11.7 V, CdVdT = 1 nF(1)
0.7
1
1.3
ms
tdVdT Output ramp time
12
ILIM (CURRENT LIMIT PROGRAMMING)
tFastOffDly
Fast-trip comparator delay(1)
BFET (BLOCKING FET GATE DRIVER)
IOUT > IFASTRIP to IOUT = 0 (Switch off)
300
ns
EN/UVLO → H to VBFET = 12 V, CBFET = 1 nF
EN/UVLO → H to VBFET = 12 V, CBFET = 10 nF
EN/UVLO → L to VBFET = 1 V, CBFET = 1 nF
EN/UVLO → L to VBFET = 1 V, CBFET = 10 nF
4.2
42
tBFET-ON
BFET turnon duration(1)
BFET Turnoff duration(1)
ms
µs
0.4
1.4
tBFET-OFF
Thermal Shutdown (TSD)
Retry delay after TSD recovery,
TJ < [TSHDN – 10°C](1)
tTSDdly
TPS259271 only
100
µs
(1) These parameters are provided for reference only and do not constitute part of TI's published device specifications for purposes of TI's
product warranty.
6
Copyright © 2015–2017, Texas Instruments Incorporated
TPS259270, TPS259271
www.ti.com.cn
ZHCSE37E –AUGUST 2015–REVISED NOVEMBER 2017
6.7 Typical Characteristics
TJ = 25°C, VVIN = 12 V, VEN/UVLO = 2 V, RILIM = 100 kΩ, CVIN = 0.1 µF, COUT = 1 µF, CdVdT = OPEN (unless stated otherwise)
4.35
4.3
0.25
0.2
0.15
0.1
0.05
0
4.25
4.2
4.15
4.1
125 °C
85 °C
25 °C
-40 °C
4.05
4
-50
0
50
100
150
0
5
10
15
20
C001
C002
Temperature (°C)
VIN (V)
Figure 1. Input UVLO vs Temperature
Figure 2. IQ-OFF vs VIN
0.6
0.5
0.4
0.3
0.2
0.1
0
250
230
210
190
170
150
125 °C
85 °C
25 °C
-40 °C
0
5
10
15
20
C003
VIN (V)
-50
0
50
100
150
Temperature (oC)
Figure 3. IVIN-ON vs VIN
Figure 4. TON vs Temperature
230
225
220
215
210
205
150
100
50
0
125 °C
85 °C
25 °C
-40 °C
-50
0
50
100
150
0
2
4
6
8
10
C010
C013
Temperature (°C)
CdVdT (nF)
Figure 5. IdVdT vs Temperature
Figure 6. TdVdT vs CdVdT
Copyright © 2015–2017, Texas Instruments Incorporated
7
TPS259270, TPS259271
ZHCSE37E –AUGUST 2015–REVISED NOVEMBER 2017
www.ti.com.cn
Typical Characteristics (continued)
TJ = 25°C, VVIN = 12 V, VEN/UVLO = 2 V, RILIM = 100 kΩ, CVIN = 0.1 µF, COUT = 1 µF, CdVdT = OPEN (unless stated otherwise)
1.41
100
10
1
1.4
1.39
1.38
1.37
1.36
1.35
1.34
Rising
Falling
125èC
85èC
25èC
-40èC
0.1
-50
0
50
Temperature (oC)
100
150
0
1
2
3
4
5
VEN (V)
D016
Figure 7. VEN-VIH, VEN-VIL vs Temperature
Figure 8. IEN (Leakage Current) vs VEN
45
2.2
2
40
35
30
25
20
1.8
1.6
1.4
1.2
1
125èC
85èC
25èC
-40èC
-50
0
50
100
150
0
0.5
1
1.5
2
Temperature (oC)
VVIN-OUT (V)
D029
RILIM = 45.3 kΩ
Figure 9. RDSON vs Temperature
Figure 10. IVOUT vs VVIN-OUT
6
5
4
3
2
1
0
-1
-2
-3
-4
-5
-6
IOL-45.3k
ISC-45.3k
125èC
85èC
25èC
-40èC
1
0
-50
0
50
100
150
0.5
1
1.5
2
Temperature (oC)
VVIN-OUT (V)
D027
RILIM = 45.3 kΩ
RILIM = 150 kΩ
Figure 11. IOL, ISC vs Temperature
Figure 12. IVOUT vs VVIN-OUT
8
Copyright © 2015–2017, Texas Instruments Incorporated
TPS259270, TPS259271
www.ti.com.cn
ZHCSE37E –AUGUST 2015–REVISED NOVEMBER 2017
Typical Characteristics (continued)
TJ = 25°C, VVIN = 12 V, VEN/UVLO = 2 V, RILIM = 100 kΩ, CVIN = 0.1 µF, COUT = 1 µF, CdVdT = OPEN (unless stated otherwise)
2
4
3.5
3
0
-2
-4
-6
2.5
2
IOL-150k
ISC-150k
-8
-10
-12
-14
-16
125èC
85èC
25èC
-40èC
1.5
1
-50
0
50
100
150
0
0.5
1
1.5
2
Temperature (oC)
VVIN-OUT (V)
D028
RILIM = 150 kΩ
RILIM = 100 kΩ
Figure 13. IOL, ISC vs Temperature
Figure 14. IVOUT vs VVIN-OUT
0.95
0.9
2
0
-2
-4
0.85
0.8
IOL-100k
ISC-100k
-6
-8
-10
-12
-50
0.75
-50
0
50
100
150
0
50
100
150
Temperature (oC)
Temperature (oC)
D001
RILIM = 100 kΩ
RILIM = 0 Ω
Figure 15. IOL, ISC vs Temperature
Figure 16. IOL-R-Short vs Temperature
0.8
4
3.5
3
0.75
0.7
2.5
2
1.5
1
0.5
0.65
-50
0
0
0
50
100
150
20
40
60
80
100
120
Temperature (oC)
RILIM Resistor (kW)
D001
D001
RILIM = OPEN
Figure 17. IOL-R-Open vs Temperature
Figure 18. Overload Current Limit vs RILIM Resistor
Copyright © 2015–2017, Texas Instruments Incorporated
9
TPS259270, TPS259271
ZHCSE37E –AUGUST 2015–REVISED NOVEMBER 2017
www.ti.com.cn
Typical Characteristics (continued)
TJ = 25°C, VVIN = 12 V, VEN/UVLO = 2 V, RILIM = 100 kΩ, CVIN = 0.1 µF, COUT = 1 µF, CdVdT = OPEN (unless stated otherwise)
3.1
3.09
3.08
3.07
3.06
3.05
35
30
25
20
15
10
5
0
-50
0
50
100
150
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
Temperature (oC)
Overload Current Limit (A)
D001
Figure 20. Accuracy vs Overload Current Limit
Figure 19. VOpenILIM vs Temperature
10000
1000
100
10
EN
CC12
VIN
C2
C3
VOUT
I_IN
TA = -40oC
TA = 25oC
TA = 85oC
TA = 125oC
1
C4
0.1
0.1
1
10
100
Power Dissipation (W)
D001
TPS25927x, CdVdT = OPEN, COUT = 4.7 μF
Figure 21. Thermal Shutdown Time vs Power Dissipation
Figure 22. Transient: Output Ramp
EN
EN
C1
C1
VIN
VOUT
C22
C3
VOUT
I_IN
C3
C4
I_OUT
C4
EN ↓
TPS25927x, VIN = 18 V, CdVdT = OPEN, COUT = 10 μF
Figure 24. Transient: Turnoff Delay
Figure 23. Transient: Output Ramp
10
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ZHCSE37E –AUGUST 2015–REVISED NOVEMBER 2017
Typical Characteristics (continued)
TJ = 25°C, VVIN = 12 V, VEN/UVLO = 2 V, RILIM = 100 kΩ, CVIN = 0.1 µF, COUT = 1 µF, CdVdT = OPEN (unless stated otherwise)
EN
VIN
C1
VOUT
VOUT
C1
BFET
BFET
C3
C2
C3
C2
EN ↓
VIN ↓
Figure 25. Turnoff Delay to BFET
Figure 26. Turnoff Delay to BFET
Figure 28. Short Circuit (Zoom): Fast-Trip Comparator
Figure 27. Transient: Output Short Circuit
EN
EN
VIN
VIN
C1
C2
C1
VOUT
C2
C3
C2
C3
VOUT
I_IN
I_IN
C4
C4
TPS259271
TPS259271
Figure 30. Transient: Wake Up to Short Circuit
Figure 29. Transient: Recovery from Short Circuit-Over
Current
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Typical Characteristics (continued)
TJ = 25°C, VVIN = 12 V, VEN/UVLO = 2 V, RILIM = 100 kΩ, CVIN = 0.1 µF, COUT = 1 µF, CdVdT = OPEN (unless stated otherwise)
EN
VIN
C1
VOUT
C2
C3
I_IN
C4
TPS259271
ILOAD Stepped from 50% to 120%, Back to 50%
Figure 32. Transient: Thermal Fault Auto-Retry
Figure 31. Transient: Overload Current Limit
TPS259270, VIN = 5 V
Figure 33. Transient: Thermal Fault Latched
12
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7 Detailed Description
7.1 Overview
The TPS25927x is an e-fuse with integrated power switch that is used to manage current, voltage and start-up
voltage ramp to a connected load. The device starts its operation by monitoring the VIN bus. When VIN exceeds
the undervoltage-lockout threshold (VUVR), the device samples the EN/UVLO pin. A high level on this pin enables
the internal MOSFET. As VIN rises, the internal MOSFET of the device starts conducting and allow current to
flow from VIN to OUT. When EN/UVLO is held low (below VENF), internal MOSFET is turned off. User also has
the ability to modify the output voltage ramp time by connecting a capacitor between dV/dT pin and GND.
After a successful start-up sequence, the device now actively monitors its load current, ensuring that the
adjustable overload current limit IOL is not exceeded. The device also has built-in thermal sensor. In the event
device temperature (TJ) exceeds TSHDN, typically 150°C, the thermal shutdown circuitry shuts down the internal
MOSFET thereby disconnecting the load from the supply. In TPS259270, the output remains disconnected
(MOSFET open) until power to device is recycled or EN/UVLO is toggled (pulled low and then high). The
TPS259271 device remains off during a cooling period until device temperature falls below TSHDN – 10°C, after
which it attempts to restart. This ON and OFF cycle continues until fault is cleared.
7.2 Functional Block Diagram
3,
4,
5
6,
7,
8
OUT
VIN
Current
Sense
28 mW
+
+
UVLO
EN
4.3 V
Charge
Pump
4.08 V
EN/
UVLO
2 mA
2
1.4 V
9
BFET
1.35 V
SWEN
6 V
SWEN
GATE
CONTROL
22 W
Thermal
Shutdown
6 V
TSD
VIN
220 nA
10 mA
+
ILIMIT
1
4.8x
dV/dT
GND
10
+
ILIM
+
70 pF
SWEN
Fast Trip
Comp
80 W
EP
1.6*ILIMIT
Copyright © 2017, Texas Instruments Incorporated
7.3 Feature Description
7.3.1 GND
This is the most negative voltage in the circuit and is used as a reference for all voltage measurements unless
otherwise specified.
7.3.2 VIN
Input voltage to the TPS25927x. A ceramic bypass capacitor close to the device from VIN to GND is
recommended to alleviate bus transients. The recommended operating voltage range is 4.5 V to 18 V for
TPS25927x. The device can continuously sustain a voltage of 20 V on VIN pin. However, above the
recommended maximum bus voltage, the device is going to be in over-voltage protection (OVP) mode, limiting
the output voltage to VOVC. The power dissipation in OVP mode is PD_OVP = (VVIN – VOVC) × IOUT, which can
potentially heat up the device and cause thermal shutdown.
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Feature Description (continued)
7.3.3 dV/dT
Connect a capacitor from this pin to GND to control the slew rate of the output voltage at power-on. This pin can
be left floating to obtain a predetermined slew rate (minimum TdVdT) on the output. Equation governing slew rate
at start-up is shown in Equation 1:
dVOUT
IdVdT ´GAINdVdT
=
dt
CdVdT + CINT
where
•
•
•
IdVdT = 220 nA (Typical)
CINT = 70 pF (Typical)
GAINdVdT = 4.85
dVOUT
dT
= Desired output slew rate
(1)
(2)
The total ramp time (TdVdT) for 0 to VIN can be calculated using Equation 2:
TdVdT = 106 ´ V ´ C
+70 pF
(
)
IN
dVdT
For details on how to select an appropriate charging time/rate, refer to the applications section Setting Output
Voltage Ramp Time (TdVdT).
7.3.4 BFET
Connect this pin to an external NFET that can be used to disconnect input supply from rest of the system in the
event of power failure at VIN. The BFET pin is controlled by either input UVLO (VUVR) event or EN/UVLO (see
Table 2). BFET can source charging current of 2 µA (typical) and sink (discharge) current from the gate of the
external FET via a 26-Ω internal discharge resistor to initiate fast turnoff, typically <1 µs. Due to 2-µA charging
current, it is recommended to use >10 MΩ impedance when probing the BFET node.
Table 2. BFET
EN/UVLO > VENR
VIN>VUVR
BFET MODE
Charge
H
X
L
H
L
Discharge
Discharge
X
7.3.5 EN/UVLO
As an input pin, it controls both the ON and OFF state of the internal MOSFET and that of the external blocking
FET. In its high state, the internal MOSFET is enabled and charging begins for the gate of external FET. A low
on this pin turns off the internal MOSFET and pull the gate of the external FET to GND via the built-in discharge
resistor. High and Low levels are specified in the parametric table of the datasheet. The EN/UVLO pin is also
used to clear a thermal shutdown latch in the TPS259270 by toggling this pin (H→L).
The internal de-glitch delay on EN/UVLO falling edge is intentionally kept low (1 us typical) for quick detection of
power failure. When used with a resistor divider from supply to EN/UVLO to GND, power-fail detection on
EN/UVLO helps in quick turnoff of the BFET driver, thereby stopping the flow of reverse current. For applications
where a higher de-glitch delay on EN/UVLO is desired, or when the supply is particularly noisy, it is
recommended to use an external bypass capacitor from EN/UVLO to GND.
7.3.6 ILIM
The device continuously monitors the load current and keeps it limited to the value programmed by RILIM. After
start-up event and during normal operation, current limit is set to IOL (over-load current limit). as shown in
Equation 3:
IOL = 0.7 + 3´10-5 ´RILIM
(
)
(3)
14
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When power dissipation in the internal MOSFET [PD = (VVIN – VOUT) × IOUT] exceeds 10 W, there is a 2% – 12%
thermal foldback in the current limit value so that IOL drops to ISC. In each of the two modes, MOSFET gate
voltage is regulated to throttle short-circuit and overload current flowing to the load. Eventually, the device shuts
down due to over temperature. See Figure 34.
0
-2
-4
-6
-8
-10
-12
-14
0
10
20
30
40
50
60
Power (W)
Figure 34. Thermal Foldback in Current Limit
During a transient short circuit event, the current through the device increases very rapidly. The current-limit
amplifier cannot respond very quickly to this event due to its limited bandwidth. Therefore, the TPS25927x
incorporates a fast-trip comparator, which shuts down the pass device very quickly when IOUT > IFASTRIP, and
terminates the rapid short-circuit peak current. The trip threshold is set to 60% higher than the programmed over-
load current limit (IFASTRIP = 1.6 × IOL). After the transient short-circuit peak current has been terminated by the
fast-trip comparator, the current limit amplifier smoothly regulates the output current to IOL (see Figure 35 and
Figure 36).
Figure 36. Fast-Trip and Current Limit Amplifier Response
for Short Circuit
Figure 35. Fast-Trip Current
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7.4 Device Functional Modes
The TPS25927x is a hot-swap controller with integrated power switch that is used to manage current, voltage
and start-up voltage ramp to a connected load. The device starts its operation by monitoring the VIN bus. When
VVIN exceeds the undervoltage-lockout threshold (VUVR), the device samples the EN/UVLO pin. A high level on
this pin enables the internal MOSFET and also start charging the gate of external blocking FET (if connected) via
the BFET pin. As VIN rises, the internal MOSFET of the device and external FET (if connected) starts conducting
and allow current to flow from VIN to OUT. When EN/UVLO is held low (that is, below VENF), the internal
MOSFET is turned off and BFET pin is discharged, thereby, blocking the flow of current from VIN to OUT. User
also has the ability to modify the output voltage ramp time by connecting a capacitor between dV/dT pin and
GND.
Having successfully completed its start-up sequence, the device now actively monitors its load current, ensuring
that the adjustable overload current limit IOL is not exceeded. This keeps the output device safe from harmful
current transients. The device also has built-in thermal sensor. In the event device temperature (TJ) exceeds
TSHDN , typically 150°C, the thermal shutdown circuitry shuts down the internal MOSFET thereby disconnecting
the load from the supply. In the TPS259270, the output remains disconnected (MOSFET open) until power to
device is recycled or EN/UVLO is toggled (pulled low and then high). The TPS259271 device remains off during
a cooling period until device temperature falls below TSHDN – 10°C, after which it attempts to restart. This ON and
OFF cycle continues until fault is cleared.
16
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TPA25927x is a smart eFuse. It is typically used for Hot-Swap and Power rail protection applications. It
operates from 4.5 V to 18 V with programmable current limit and undervoltage protection. The device aids in
controlling the in-rush current and provides precise current limiting during overload conditions for systems such
as Set-Top-Box, DTVs, Gaming Consoles, SSDs/HDDs and Smart Meters. The device also provides robust
protection for multiple faults on the sub-system rail.
The following design procedure can be used to select component values for the device. Alternatively, the
WEBENCH® software may be used to generate a complete design. The WEBENCH® software uses an iterative
design procedure and accesses a comprehensive database of components when generating a design.
Additionally, a spreadsheet design tool TPS2592xx Design Calculator (SLUC570) is available on web folder. This
section presents a simplified discussion of the design process.
8.2 Typical Application
8.2.1 Simple 2.1-A eFuse Protection for Set Top Boxes
ëLb = 4.ꢁ to 18 ë
ëhÜÇ, LhÜÇ < 1.7!
Lb
hÜÇ
*
/
ëLb
0.1µC
w1
1aO
/
hÜÇ
1µC
28mO
9bꢀÜë[h
**
ꢂC9Ç
L[La
w2
dëdÇ
Db5
Çt{25927x
wL[La
4ꢁ.3kO
**hptional & only needed for external Üë[h
*hptional & only for noise suppression
Figure 37. Typical Application Schematic: Simple e-Fuse for STBs
8.2.1.1 Design Requirements
Table 3 shows the design parameters for this application.
Table 3. Design Parameters
DESIGN PARAMETER
Input voltage range, VIN
EXAMPLE VALUE
12 V
Undervoltage lockout set point, V(UV)
Load at start-up, RL(SU)
Default: VUVR = 4.3 V
8 Ω
2.1 A
1 µF
Current limit, IOL = IILIM
Load capacitance, COUT
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Typical Application (continued)
Table 3. Design Parameters (continued)
DESIGN PARAMETER
EXAMPLE VALUE
Maximum ambient temperature, TA
85°C
8.2.1.2 Detailed Design Procedure
The following design procedure can be used to select component values for the TPS25927x.
8.2.1.2.1 Step by Step Design Procedure
This design procedure below seeks to control the junction temperature of device under both static and transient
conditions by proper selection of output ramp-up time and associated support components. The designer can
adjust this procedure to fit the application and design criteria.
8.2.1.2.2 Programming the Current-Limit Threshold: RILIM Selection
The RILIM resistor at the ILIM pin sets the over load current limit, this can be set using Equation 4:
I
- 0.7
ILIM
R
=
ILIM
-5
3 x 10
(4)
For IOL = IILIM = 2.1 A, from Equation 4, RILIM = 45.3 kΩ, choose closest standard value resistor with 1%
tolerance.
8.2.1.2.3 Undervoltage Lockout Set Point
The undervoltage lockout (UVLO) trip point is adjusted using the external voltage divider network of R1 and R2 as
connected between IN, EN/UVLO and GND pins of the device. The values required for setting the undervoltage
are calculated solving Equation 5:
R +R
1
2
V
=
´ V
ENR
(UV)
R
2
(5)
Where VENR = 1.4 V is enable voltage rising threshold.
Since R1 and R2 leak the current from input supply (VIN), these resistors must be selected based on the
acceptable leakage current from input power supply (VIN). The current drawn by R1 and R2 from the power
supply {IR12 = VIN/(R1 + R2)}.
However, leakage currents due to external active components connected to the resistor string can add error to
these calculations. So, the resistor string current, IR12 must be chosen to be 20x greater than the leakage current
expected.
For default UVLO of VUVR = 4.3 V, select R2 = OPEN, and R1 = 1 MΩ. Since EN/UVLO pin is rated only to 7 V, it
cannot be connected directly to VIN = 12 V. It has to be connected through R1 = 1 MΩ only, so that the pull-up
current for EN/UVLO pin is limited to < 20 µA.
The power failure threshold is detected on the falling edge of supply. This threshold voltage is 4% lower than the
rising threshold, VUVR. This is calculated using Equation 6:
V(PFAIL) = 0.96 x VUVR
(6)
Where VUVR is 4.3 V, Power fail threshold set is : 4.1 V.
8.2.1.2.4 Setting Output Voltage Ramp Time (TdVdT
)
For a successful design, the junction temperature of device must be kept below the absolute-maximum rating
during both dynamic (start-up) and steady state conditions. Dynamic power stresses often are an order of
magnitude greater than the static stresses, so it is important to determine the right start-up time and in-rush
current limit required with system capacitance to avoid thermal shutdown during start-up with and without load.
The ramp-up capacitor CdVdT needed is calculated considering the two possible cases:
18
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8.2.1.2.4.1 Case 1: Start-Up without Load: Only Output Capacitance COUT Draws Current During Start-Up
During start-up, as the output capacitor charges, the voltage difference as well as the power dissipated across
the internal FET decreases. The average power dissipated in the device during start-up is calculated using
Equation 8.
For TPS25927x, the inrush current is determined using Equation 7:
V
(IN)
I
= C x
(OUT)
(INRUSH)
T
dVdT
(7)
(8)
Power dissipation during start-up is given by Equation 8:
P
= 0.5 x V x I
(IN) (INRUSH)
D(INRUSH)
Equation 8 assumes that load does not draw any current until the output voltage has reached its final value.
8.2.1.2.4.2 Case 2: Start-Up with Load: Output Capacitance COUT and Load Draws Current During Start-Up
When load draws current during the turnon sequence, there is additional power dissipated. Considering a
resistive load during start-up (RL(SU)), load current ramps up proportionally with increase in output voltage during
TdVdT time. The average power dissipation in the internal FET during charging time due to resistive load is given
by Equation 9:
2
V
æ
ö
÷
÷
ø
1
6
(IN)
÷
x
÷
ç
P
=
ç
D(LOAD)
ç
è
R
L(SU)
(9)
(10)
(11)
Total power dissipated in the device during startup is given by Equation 10:
P
=
P + P
D(INRUSH) D(LOAD)
D(STARTUP)
Total current during start-up is given by Equation 11:
I
=
I
+ I (t)
(STARTUP)
(INRUSH) L
If I(STARTUP) > IOL, the device limits the current to IOL and the current limited charging time is determined by
Equation 12:
é
ê
ê
ê
ê
ê
ê
ê
ë
ù
ö
æ
ç
ç
ç
ç
ç
ç
ç
ç
ç
çI
÷
ú
÷
÷
ú
÷
I
÷
I
(INRUSH)
ú
÷
OL
÷
ú
÷
÷
T
=
C
x R
L(SU)
x
-1+LN
dVdT(Current-Limited)
OUT
V
I
ú
(IN)
÷
(INRUSH)
÷
-
ú
÷
OL
ç
÷
ú
÷
L(SU) ø
û
R
ç
è
(12)
The power dissipation, with and without load, for selected start-up time must not exceed the shutdown limits as
shown in Figure 38.
10000
1000
100
10
TA = -40oC
1
TA = 25oC
TA = 85oC
TA = 125oC
0.1
0.1
1
10
100
Power Dissipation (W)
D001
Figure 38. Thermal Shutdown Limit Plot
For the design example under discussion, select ramp-up capacitor CdVdT = OPEN. Then, using Equation 2 we
get Equation 13:
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www.ti.com.cn
6
T
= 10 x 12 x 0 + 70 pF = 840 ms
)
(
dVdT
(13)
The inrush current drawn by the load capacitance (COUT) during ramp-up using Equation 7 is given by
Equation 14:
12
I
= 1 mF x
= 15 mA
(INRUSH)
840 ms
(14)
The inrush power dissipation is calculated, using Equation 8 as shown in Equation 15:
P
= 0.5 x 12 x 15 m = 90 mW
D(INRUSH)
(15)
For 90 mW of power loss, the thermal shut down time of the device must not be less than the ramp-up time TdVdT
to avoid the false trip at maximum operating temperature. From thermal shutdown limit graph Figure 38 at TA =
85°C, for 90 mW of power, the shutdown time is infinite. So it is safe to use 0.79 ms as start-up time without any
load on output.
Considering the start-up with load 8 Ω, the additional power dissipation, when load is present during start-up is
calculated, using Equation 9 we get Equation 16:
12 x 12
P
=
= 3 W
D(LOAD)
6 ´ 8
(16)
The total device power dissipation during start-up is given by Equation 17:
P
= 3 + 90 m = 3.09 W
D(STARTUP)
(17)
From thermal shutdown limit graph at TA = 85°C, the thermal shutdown time for 3.09 W is more than 100 ms. So
it is well within acceptable limits to use no external capacitor (CdV/dT) with start-up load of 8 Ω.
If, due to large COUT, there is a need to decrease the power loss during start-up, it can be done with increase of
CdVdT capacitor.
8.2.1.2.5 Support Component Selection—CVIN
CVIN is a bypass capacitor to help control transient voltages, unit emissions, and local supply noise. Where
acceptable, a value in the range of 0.001 μF to 0.1 μF is recommended for CVIN
.
8.2.1.3 Application Curves
Figure 39. Output Ramp without Load on Output
Figure 40. Output Ramp with 4-Ω Load at Start-Up
8.2.2 Controlled Power Down using TPS25927x
When the device is disabled, the output voltage is left floating and power down profile is entirely dictated by the
load. In some applications, this can lead to undesired activity as the load is not powered down to a defined state.
Controlled output discharge can ensure the load is turned off completely and not in an undefined operational
state. The BFET pin in TPS25927x family of eFuses facilitates Quick Output Discharge (QOD) function as
illustrated in Figure 41 . When the device is/gets disabled, the BFET pin pulls low which enables the external P-
MOSFET Q1 for discharge feature to function. The output voltage discharge rate is dictated by the output
capacitor COUT, the discharge resistance RDCHG and the load.
20
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ZHCSE37E –AUGUST 2015–REVISED NOVEMBER 2017
OUT
VOUT
VIN
VIN
*
CIN
28mW
R1
RDCHG
EN/UVLO
dVdT
BFET
ILIM
COUT
Q1
ZXM61P03F
R2
TPS25927x
GND
CdVdT
RILIM
*Optional & only for noise suppression
Figure 41. Circuit Implementation with Quick Output Discharge Function
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9 Power Supply Recommendations
The device is designed for supply voltage range of 4.5 V ≤ VIN ≤ 18 V. If the input supply is located more than a
few inches from the device an input ceramic bypass capacitor higher than 0.1 μF is recommended. Power supply
must be rated higher than the current limit set to avoid voltage droops during over current and short-circuit
conditions.
9.1 Transient Protection
In case of short circuit and over load current limit, when the device interrupts current flow, input inductance
generates a positive voltage spike on the input and output inductance generates a negative voltage spike on the
output. The peak amplitude of voltage spikes (transients) is dependent on value of inductance in series to the
input or output of the device. Such transients can exceed the Absolute Maximum Ratings of the device if steps
are not taken to address the issue.
Typical methods for addressing transients include:
•
•
•
•
Minimizing lead length and inductance into and out of the device
Using large PCB GND plane
Schottky diode across the output to absorb negative spikes
A low value ceramic capacitor (C(IN) = 0.001 µF to 0.1 µF) to absorb the energy and dampen the transients.
The approximate value of input capacitance can be estimated with Equation 18:
L
(IN)
V
= V
(IN)
+ I x
(LOAD)
SPIKE(Absolute)
C
(IN)
where
•
•
•
•
V(IN) is the nominal supply voltage
I(LOAD) is the load current
L(IN) equals the effective inductance seen looking into the source
C(IN) is the capacitance present at the input
(18)
Some applications may require the addition of a Transient Voltage Suppressor (TVS) to prevent transients from
exceeding the Absolute Maximum Ratings of the device.
The circuit implementation with optional protection components (a ceramic capacitor, TVS and schottky diode) is
shown in Figure 42.
ëLb
ëhÜÇ
Lb
hÜÇ
*
/
ëLb
28mO
w1
/
hÜÇ
0.1µC
9bꢀÜë[h
dëdÇ
*
*
ꢁC9Ç
L[La
w2
/
dëdÇ
Db5
Çt{25927x
*hptional components for
transient suppression
wL[La
Figure 42. Circuit Implementation with Optional Protection Components
22
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TPS259270, TPS259271
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ZHCSE37E –AUGUST 2015–REVISED NOVEMBER 2017
9.2 Output Short-Circuit Measurements
It is difficult to obtain repeatable and similar short-circuit testing results. Source bypassing, input leads, circuit
layout and component selection, output shorting method, relative location of the short, and instrumentation all
contribute to variation in results. The actual short itself exhibits a certain degree of randomness as it
microscopically bounces and arcs. Care in configuration and methods must be used to obtain realistic results. Do
not expect to see waveforms exactly like those in the data sheet; every setup differs.
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10 Layout
10.1 Layout Guidelines
•
For all applications, a 0.01-uF or greater ceramic decoupling capacitor is recommended between IN terminal
and GND. For hot-plug applications, where input power path inductance is negligible, this capacitor can be
eliminated/minimized.
•
The optimum placement of decoupling capacitor is closest to the IN and GND terminals of the device. Care
must be taken to minimize the loop area formed by the bypass-capacitor connection, the IN terminal, and the
GND terminal of the IC. See Figure 43 for a PCB layout example.
•
•
•
High current carrying power path connections must be as short as possible and must be sized to carry at
least twice the full-load current.
The GND terminal must be tied to the PCB ground plane at the terminal of the IC. The PCB ground must be a
copper plane or island on the board.
Locate all support components: RILIM, CdVdT and resistors for EN/UVLO, close to their connection pin. Connect
the other end of the component to the GND pin of the device with shortest trace length. The trace routing for
the RILIM and CdVdT components to the device must be as short as possible to reduce parasitic effects on the
current limit and soft start timing. These traces must not have any coupling to switching signals on the board.
•
•
Protection devices such as TVS, snubbers, capacitors, or diodes must be placed physically close to the
device they are intended to protect, and routed with short traces to reduce inductance. For example, a
protection Schottky diode is recommended to address negative transients due to switching of inductive loads,
and it must be physically close to the OUT pins.
Obtaining acceptable performance with alternate layout schemes is possible; however this layout has been
shown to produce good results and is intended as a guideline.
10.2 Layout Example
Çop layer
.ottom layer signal ground plane
ëia to signal ground plane
Dround -
.ottom
layer
1
2
3
4
5
dëꢄdÇ
ꢂbꢄÜë[ꢀ
ëLb
10
9
L[Lꢃ
.CꢂÇ
8
ꢀÜÇ
ꢀÜÇ
ꢀÜÇ
7
6
ëLb
ëLb
ëLb
ëhÜÇ
*
*
ëLb
Iigh Crequency
.ypass /apacitor
tower Dround
* ꢀptional: beeded only to suppress the transients caused ꢁy inductive load switching
Figure 43. Layout Example
24
版权 © 2015–2017, Texas Instruments Incorporated
TPS259270, TPS259271
www.ti.com.cn
ZHCSE37E –AUGUST 2015–REVISED NOVEMBER 2017
11 器件和文档支持
11.1 器件支持
11.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
11.1.2 开发支持
有关 TPS259270 PSpice 瞬态模型，请参阅 SLVMB88
有关 TPS259271 PSpice 瞬态模型，请参阅 SLVMB91
11.2 文档支持
11.2.1 相关文档
请参阅如下相关文档：
《TPS2592xx 设计计算器》
11.3 相关链接
下面的表格列出了快速访问链接。类别包括技术文档、支持与社区资源、工具和软件，以及申请样片或购买产品的
快速链接。
表 4. 相关链接
器件
产品文件夹
请单击此处
请单击此处
样片与购买
请单击此处
请单击此处
技术文档
请单击此处
请单击此处
工具和软件
请单击此处
请单击此处
支持和社区
请单击此处
请单击此处
TPS259270
TPS259271
11.4 接收文档更新通知
如需接收文档更新通知，请访问 ti.com 上的器件产品文件夹。单击右上角的通知我 进行注册，即可每周接收产品
信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
11.5 社区资源
下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，
并且不一定反映 TI 的观点；请参阅 TI 的 《使用条款》。
TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在
e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。
设计支持
TI 参考设计支持 可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。
11.6 商标
E2E is a trademark of Texas Instruments.
WEBENCH is a registered trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.7 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
版权 © 2015–2017, Texas Instruments Incorporated
25
TPS259270, TPS259271
ZHCSE37E –AUGUST 2015–REVISED NOVEMBER 2017
www.ti.com.cn
11.8 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。这些数据如有变更，恕不另行通知
和修订此文档。如欲获取此数据表的浏览器版本，请参阅左侧的导航。
26
版权 © 2015–2017, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS259270DRCR
TPS259270DRCT
TPS259271DRCR
TPS259271DRCT
ACTIVE
ACTIVE
ACTIVE
ACTIVE
VSON
VSON
VSON
VSON
DRC
DRC
DRC
DRC
10
10
10
10
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 85
-40 to 85
-40 to 85
-40 to 85
259270
NIPDAU
NIPDAU
NIPDAU
259270
259271
259271
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Apr-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS259270DRCR
TPS259270DRCR
TPS259270DRCT
TPS259270DRCT
TPS259271DRCR
TPS259271DRCT
VSON
VSON
VSON
VSON
VSON
VSON
DRC
DRC
DRC
DRC
DRC
DRC
10
10
10
10
10
10
3000
3000
250
330.0
330.0
180.0
180.0
330.0
180.0
12.4
12.4
12.4
12.4
12.4
12.4
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
1.1
1.1
1.1
1.1
1.1
1.1
8.0
8.0
8.0
8.0
8.0
8.0
12.0
12.0
12.0
12.0
12.0
12.0
Q2
Q2
Q2
Q2
Q2
Q2
250
3000
250
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Apr-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPS259270DRCR
TPS259270DRCR
TPS259270DRCT
TPS259270DRCT
TPS259271DRCR
TPS259271DRCT
VSON
VSON
VSON
VSON
VSON
VSON
DRC
DRC
DRC
DRC
DRC
DRC
10
10
10
10
10
10
3000
3000
250
346.0
367.0
210.0
210.0
346.0
210.0
346.0
367.0
185.0
185.0
346.0
185.0
33.0
35.0
35.0
35.0
33.0
35.0
250
3000
250
Pack Materials-Page 2
GENERIC PACKAGE VIEW
DRC 10
3 x 3, 0.5 mm pitch
VSON - 1 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4226193/A
www.ti.com
PACKAGE OUTLINE
DRC0010J
VSON - 1 mm max height
SCALE 4.000
PLASTIC SMALL OUTLINE - NO LEAD
3.1
2.9
B
A
PIN 1 INDEX AREA
3.1
2.9
1.0
0.8
C
SEATING PLANE
0.08 C
0.05
0.00
1.65 0.1
2X (0.5)
(0.2) TYP
EXPOSED
THERMAL PAD
4X (0.25)
5
6
2X
2
11
SYMM
2.4 0.1
10
1
8X 0.5
0.30
0.18
10X
SYMM
PIN 1 ID
0.1
C A B
C
(OPTIONAL)
0.05
0.5
0.3
10X
4218878/B 07/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
DRC0010J
VSON - 1 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(1.65)
(0.5)
10X (0.6)
1
10
10X (0.24)
11
(2.4)
(3.4)
SYMM
(0.95)
8X (0.5)
6
5
(R0.05) TYP
(
0.2) VIA
TYP
(0.25)
(0.575)
SYMM
(2.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:20X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
EXPOSED METAL
EXPOSED METAL
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
SOLDER MASK
DEFINED
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4218878/B 07/2018
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
DRC0010J
VSON - 1 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
2X (1.5)
(0.5)
SYMM
EXPOSED METAL
TYP
11
10X (0.6)
1
10
(1.53)
10X (0.24)
2X
(1.06)
SYMM
(0.63)
8X (0.5)
6
5
(R0.05) TYP
4X (0.34)
4X (0.25)
(2.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 11:
80% PRINTED SOLDER COVERAGE BY AREA
SCALE:25X
4218878/B 07/2018
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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