TPS25940L [TI]
18V eFuse with True Reverse Blocking and DevSleep Support for SSDs;
| 型号： | TPS25940L |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 18V eFuse with True Reverse Blocking and DevSleep Support for SSDs |
| 文件： | 总50页 (文件大小：4089K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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TPS25940-Q1
SLVSDJ0D –MAY 2016–REVISED SEPTEMBER 2018
TPS25940x-Q1 2.7-V to 18-V eFuse with Integrated Short-to-Battery Protection
1 Features
3 Description
The TPS25940x-Q1 eFuse Power Switches are
compact, feature rich power management devices
with a full suite of protection functions. The wide
operating range allows control of many popular DC
bus voltages. Integrated back-to-back FETs provide
bidirectional current control making the device well
suited for systems with load side holdup energy that
must not drain back to a failed supply bus.
1
•
Qualified for Automotive Applications
•
AEC-Q100 Qualified With the Following Results:
–
Device Temperature Grade 1: –40°C to
+125°C Ambient Operating Temperature
Range
–
–
Device HBM ESD Classification Level 2
Device CDM ESD Classification Level C5
Load, source and device protection are provided with
many programmable features including overcurrent,
•
•
•
•
•
•
•
•
•
•
•
•
•
2.7-V to 18-V Operating Voltage, 20 V (Maximum)
Total RON: 42 mΩ (Typical)
dVo/dt
ramp
and
overvoltage,
undervoltage
0.6-A to 5.3-A Adjustable Current Limit (±8%)
IMON Current Indicator Output (±8%)
Adjustable Under-, Overvoltage Threshold (±2%)
Reverse Current Blocking
thresholds. For system status monitoring and
downstream load control, the device provides
PGOOD, FLT and precise current monitor output.
Precise programmable undervoltage, overvoltage
thresholds and mode simplify power management
design.
1-μs Reverse Voltage Shutoff
Programmable dVo/dt Control
The TPS25940x-Q1 monitor V(IN) and V(OUT) to
provide true reverse current blocking when V(IN)
(V(OUT) – 66 mV). This function supports supply bus
protection from over-voltages during output short to
battery faults.
<
Power Good and Fault Outputs
Short-to-Battery Protection
Short-to-Ground Protection
TPS25940-Q1: Auto-Retry
Device Information(1)
TPS25940L-Q1: Latch-Off
PART NUMBER
TPS25940-Q1
PACKAGE
BODY SIZE (NOM)
2 Applications
WQFN (20)
3.00 mm x 4.00 mm
TPS25940L-Q1
•
•
•
•
•
Automotive Infotainment
ADAS Cameras and Radar Sensors
USB Hubs
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Power MUXing
Holdup Power Management
Simplified Schematic
Output Short-to-Battery Detection and Protection
5 V Power Bus
R1
IN
OUT
IN
OUT
USB Connector
*
CIN
COUT
42mΩ
R4
VBUS
D-
EN/UVLO
OVP
FLT
PGTH
PGOOD
D+
R2
R3
DEVSLP
dVdT
GND
IMON
ILIM
GND
CdVdT
RILIM
TPS25940-Q1
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. UNLESS OTHERWISE NOTED, this document contains PRODUCTION
DATA.
TPS25940-Q1
SLVSDJ0D –MAY 2016–REVISED SEPTEMBER 2018
www.ti.com
Table of Contents
8.4 Device Functional Modes........................................ 22
Application and Implementation ........................ 24
9.1 Application Information............................................ 24
9.2 Typical Application .................................................. 24
1
2
3
4
5
6
Features.................................................................. 1
Applications ........................................................... 1
Description ............................................................. 1
Revision History..................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings ............................................................ 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 5
6.5 Electrical Characteristics........................................... 5
6.6 Timing Requirements................................................ 7
6.7 Typical Characteristics.............................................. 8
Parametric Measurement Information ............... 15
Detailed Description ............................................ 16
8.1 Overview ................................................................. 16
8.2 Functional Block Diagram ....................................... 17
8.3 Feature Description................................................. 18
9
10 Power Supply Recommendations ..................... 37
10.1 Transient Protection.............................................. 37
10.2 Output Short-Circuit Measurements ..................... 38
11 Layout................................................................... 39
11.1 Layout Guidelines ................................................. 39
11.2 Layout Example .................................................... 40
12 Device and Documentation Support ................. 41
12.1 Documentation Support ........................................ 41
12.2 Community Resources.......................................... 41
12.3 Trademarks........................................................... 41
12.4 Electrostatic Discharge Caution............................ 41
12.5 Glossary................................................................ 41
7
8
13 Mechanical, Packaging, and Orderable
Information ........................................................... 41
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C (July 2018) to Revision D
Page
•
Changed internal ramp rate of 12 V/ms for output to 30 V/ms ............................................................................................ 19
Changes from Revision B (November 2017) to Revision C
Page
•
•
Changed from Production Data to Prod Mixed ..................................................................................................................... 1
Added the latch-off variant (TPS25940L-Q1) ......................................................................................................................... 1
Changes from Revision A (June 2016) to Revision B
Page
•
Added subsection 9.2.4.3 Overload Detection Using TPS25940-Q1 to the Application Information section ....................... 1
Changes from Original (May 2016) to Revision A
Page
•
Changed device status from Product Preview to Production Data ....................................................................................... 1
2
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Copyright © 2016–2018, Texas Instruments Incorporated
Product Folder Links: TPS25940-Q1
TPS25940-Q1
www.ti.com
SLVSDJ0D –MAY 2016–REVISED SEPTEMBER 2018
5 Pin Configuration and Functions
RVC Package
20-Pin WQFN
Top View
16
15
GND
OVP
1
2
DEVSLP
PGOOD
PGTH
3
4
14 EN
OUT
OUT
OUT
13
IN
IN
IN
Thermal
Pad
5
6
12
11
Pin Functions
PIN
TYPE
DESCRIPTION
NO.
NAME
Active high. DevSleep mode control. A high at this pin activates the DevSleep
mode (low power mode). If unused, leave floating or connect it to GND
1
2
DEVSLP
I
Active high. A high indicates PGTH has crossed the threshold value. It is an open
drain output. If unused, leave floating
PGOOD
PGTH
O
I
3
Positive input of PGOOD comparator. If unused connect to OUT or GND
Power output of the device
4
5
6
OUT
O
7
8
9
10
11
12
13
IN
I
Power input and supply voltage of the device
Input for setting programmable undervoltage lockout threshold. An undervoltage
event opens internal FET and assert FLT to indicate power-failure
14
15
EN/UVLO
OVP
I
I
Input for setting programmable overvoltage protection threshold. An overvoltage
event opens the internal FET and assert FLT to indicate overvoltage
Ground. The GND terminal must be connected to the exposed PowerPAD. This
PowerPAD must be connected to a PCB ground plane using multiple vias for
good thermal performance
16
GND
—
17
18
ILIM
I/O
I/O
A resistor from this pin to GND sets the overload and short-circuit current limit
A capacitor from this pin to GND sets the ramp rate of output voltage
dVdT
This pin sources a scaled down ratio of current through the internal FET. A
resistor from this pin to GND converts current to proportional voltage, used as
analog current monitor. If unused, leave floating
19
20
IMON
FLT
O
O
Fault event indicator, goes low to indicate fault condition because of
undervoltage, overvoltage, reverse voltage and thermal shutdown event. It is an
open drain output. If unused, leave floating
Copyright © 2016–2018, Texas Instruments Incorporated
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TPS25940-Q1
SLVSDJ0D –MAY 2016–REVISED SEPTEMBER 2018
www.ti.com
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
20
UNIT
IN, OUT, PGTH, PGOOD, EN/UVLO, OVP, DEVSLP, FLT
–0.3
IN, OUT (10 ms transient)
dVdT, ILIM
22
Input voltage
Sink current
V
–0.3
–0.3
3.6
7
IMON
PGOOD, FLT, dVdT
10
mA
A
Maximum continuous switch current,
TA = 85°C(2)
IMAX
4.78
Source current
dVdT, ILIM, IMON
Internally Limited
See the Thermal Information table
Continuous power dissipation
Maximum junction temperature
Storage temperature
TJ
–40
–65
150
150
°C
°C
Tstg
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Assumes 15 K power-on-hours at 100% duty cycle. This information is provided solely for your convenience and does not extend or
modify the warranty provided under TI's standard terms and conditions for TI's semiconductor products.
6.2 ESD Ratings
VALUE
±3000
±1000
UNIT
Human-body model (HBM), per AEC Q100-002(1)
Charged-device model (CDM), per AEC Q100-011
V(ESD)
Electrostatic discharge
V
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
IN
2.7
18
EN/UVLO, OVP, DEVSLP, OUT,
PGTH, PGOOD, FLT
0
18
Input voltage
Resistance
V
dVdT, ILIM
IMON
ILIM
0
0
3
6
16.9
1
150
kΩ
IMON
OUT
0.1
µF
nF
°C
External capacitance
dVdT
TJ
470
Operating junction temperature
–40
25 125
4
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Product Folder Links: TPS25940-Q1
TPS25940-Q1
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SLVSDJ0D –MAY 2016–REVISED SEPTEMBER 2018
6.4 Thermal Information
TPS25940x-Q1
THERMAL METRIC(1)
RVC (WQFN)
20 PINS
38.1
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJCtop
RθJB
40.5
13.6
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.6
ψJB
13.7
RθJCbot
3.4
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Electrical Characteristics
–40°C ≤ TJ = TA ≤ 125°C, 2.7 V ≤ V(IN) = 18 V, V(EN/UVLO) = 2 V, V(OVP) = V(DEVSLP) = V(PGTH) = 0 V, R(ILIM) = 150 kΩ, C(OUT) = 1
µF, C(dVdT) = OPEN, PGOOD = FLT = IMON = OPEN. Positive current into terminals. All voltages referenced to GND (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY VOLTAGE AND INTERNAL UNDERVOLTAGE LOCKOUT
V(IN)
Operating input voltage
2.7
2.2
105
140
140
140
4
18
2.4
125
300
260
270
15
V
V
V(UVR)
V(UVRhys)
Internal UVLO threshold, rising
Internal UVLO hysteresis
2.3
116
210
199
202
8.6
mV
V(EN/UVLO) = 2 V, V(IN) = 3 V
IQ(ON)
Supply current, enabled
V(EN/UVLO) = 2 V, V(IN) = 12 V
V(EN/UVLO) = 2 V, V(IN) = 18 V
V(EN/UVLO) = 0 V, V(IN) = 3 V
V(EN/UVLO) = 0 V, V(IN) = 12 V
V(EN/UVLO) = 0 V, V(IN) = 18 V
V(DEVSLP) = 0 V, V(IN) = 2.7 V to 18 V
µA
IQ(OFF)
Supply current, disabled
6
15
20
µA
µA
8
18.5
95
25
IQ(DEVSLP)
Supply current, devSleep mode
70
130
ENABLE AND UNDERVOLTAGE LOCKOUT (EN/UVLO) INPUT
V(ENR)
V(ENF)
EN/UVLO threshold voltage, rising
EN/UVLO threshold voltage, falling
0.97
0.9
0.99
0.92
1.01
0.94
V
V
EN threshold voltage for Low IQ
shutdown, falling
V(SHUTF)
0.3
0.47
0.63
V
EN hysteresis for low IQ shutdown,
hysteresis(1)
V(SHUTFhys)
IEN
66
0
mV
nA
EN Input leakage current
0 V ≤ V(EN/UVLO) ≤ 18 V
–100
100
OVER VOLTAGE PROTECTION (OVP) INPUT
V(OVPR)
V(OVPF)
I(OVP)
Overvoltage threshold voltage, rising
0.97
0.9
0.99
0.92
0
1.01
0.94
100
V
V
Overvoltage threshold voltage,
falling
OVP input leakage current
0 V ≤ V(OVP) ≤ 5 V
–100
nA
DEVSLP MODE INPUT (DEVSLP): ACTIVE HIGH
V(DEVSLPR)
V(DEVSLPF)
I(DEVSLP)
DEVSLP threshold voltage, rising
DEVSLP threshold voltage, falling
DEVSLP input leakage current
1.6
0.8
0.6
1.85
0.96
1
2
1.1
V
V
0.2 V ≤ V(DEVSLP) ≤ 18 V
1.25
µA
OUTPUT RAMP CONTROL (dVdT)
I(dVdT)
dVdT charging current
V(dVdT) = 0 V
0.85
1
16
1.15
24
µA
Ω
R(dVdT)
dVdT discharging resistance
dVdT maximum capacitor voltage
dVdT to OUT gain
EN/UVLO = 0 V, I(dVdT) = 10 mA sinking
V(dVdTmax)
GAIN(dVdT)
2.6
2.88
11.9
3.1
V
ΔV(OUT)/ΔV(dVdT)
11.65
12.05
V/V
CURRENT LIMIT PROGRAMMING (ILIM)
(1) These parameters are provided for reference only and do not constitute part of TI's published device specifications for purposes of TI's
product warranty.
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SLVSDJ0D –MAY 2016–REVISED SEPTEMBER 2018
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Electrical Characteristics (continued)
–40°C ≤ TJ = TA ≤ 125°C, 2.7 V ≤ V(IN) = 18 V, V(EN/UVLO) = 2 V, V(OVP) = V(DEVSLP) = V(PGTH) = 0 V, R(ILIM) = 150 kΩ, C(OUT) = 1
µF, C(dVdT) = OPEN, PGOOD = FLT = IMON = OPEN. Positive current into terminals. All voltages referenced to GND (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
0.87
0.58
0.99
2.08
4.45
5.2
MAX
UNIT
V(ILIM)
ILIM bias voltage
V
R(ILIM) = 150 kΩ, (V(IN) – V(OUT)) = 1 V
R(ILIM) = 88.7 kΩ, (V(IN) – V(OUT)) = 1 V
R(ILIM) = 42.2 kΩ, (V(IN) – V(OUT)) = 1 V
R(ILIM) = 20 kΩ, (V(IN) – V(OUT)) = 1 V
R(ILIM) = 16.9 kΩ, (V(IN) – V(OUT)) = 1 V
0.53
0.9
0.63
1.07
2.25
4.81
5.62
1.92
4.09
4.78
I(LIM)
Current limit(2)
A
R(ILIM) = OPEN, Open resistor current limit (single point
failure test: UL60950)
0.35
0.55
0.45
0.67
0.55
0.8
R(ILIM) = SHORT, Shorted resistor current limit (single
point failure test: UL60950)
I(DEVSLP(LIM))
DevSleep mode current limit
0.55
1.91
4
0.67
2.07
4.4
0.8
2.24
4.7
A
A
R(ILIM) = 42.2 kΩ, V(VIN) = 12 V, (V(IN) – V(OUT)) = 5 V
R(ILIM) = 20 kΩ, V(VIN) = 12 V, (V(IN) – V(OUT)) = 5 V
R(ILIM) = 16.9 kΩ, V(VIN) = 12 V, (V(IN) – V(OUT)) = 5 V
(2)
IOS
Short-circuit current limit
4.7
5.11
1.5 x
5.52
I(FASTRIP)
Fast-trip comparator threshold(1)(2)
I(LIM)
+
A
0.375
CURRENT MONITOR OUTPUT (IMON)
GAIN(IMON) Gain factor I(IMON):I(OUT)
MOSFET – POWER SWITCH
1 A ≤ I(OUT) ≤ 5 A
47.78
52.3
57.23
µA/A
1 A ≤ I(OUT) ≤ 5 A, TJ = 25°C
34
26
26
42
42
42
49
58
64
RON
IN to OUT - ON resistance
1 A ≤ I(OUT) ≤ 5 A, –40°C ≤ TJ ≤ +85°C
1 A ≤ I(OUT) ≤ 5 A, –40°C ≤ TJ ≤ +125°C
mΩ
PASS FET OUTPUT (OUT)
V(IN) = 18 V, V(EN/UVLO) = 0 V, V(OUT) = 0 V (sourcing)
V(IN) = 2.7 V, V(EN/UVLO) = 0 V, V(OUT) = 18 V (sinking)
–2
6
0
2
Ilkg(OUT)
OUT leakage current in off state
µA
13
20
V(IN) – V(OUT) threshold for reverse
protection comparator, falling
V(REVTH)
V(FWDTH)
–77
86
–66
100
–55
114
mV
mV
V(IN) – V(OUT) threshold for reverse
protection comparator, rising
FAULT FLAG (FLT): ACTIVE LOW
R(FLT) FLT internal pull-down resistance
I(FLT) FLT input leakage current
V(OVP) = 2 V, I(FLT) = 5 mA sinking
10
–1
18
0
30
1
Ω
0 V ≤ V(FLT) ≤ 18 V
µA
POSITIVE INPUT for POWER-GOOD COMPARATOR (PGTH)
V(PGTHR)
V(PGTHF)
I(PGTH)
PGTH threshold voltage, rising
PGTH threshold voltage, falling
PGTH input leakage current
0.97
0.9
0.99
0.92
0
1.01
0.94
100
V
V
0 V ≤ V(PGTH) ≤ 18 V
–100
nA
POWER-GOOD COMPARATOR OUTPUT (PGOOD): ACTIVE HIGH
PGOOD internal pull-down
resistance
R(PGOOD)
I(PGOOD)
V(PGTH) = 0V, I(PGOOD) = 5 mA sinking
10
–1
20
0
35
1
Ω
PGOOD input leakage current
0 V ≤ V(PGOOD) ≤ 18 V
µA
THERMAL SHUT DOWN (TSD)
T(TSD)
TSD threshold(1)
TSD hysteresis(1)
160
12
°C
°C
T(TSDhys)
Thermal fault response
TPS25940-Q1
TPS25940L-Q1
Auto-retry
Latch-off
(2) Pulse-testing techniques maintain junction temperature close to ambient temperature. Thermal effects must be taken into account
separately.
6
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SLVSDJ0D –MAY 2016–REVISED SEPTEMBER 2018
6.6 Timing Requirements
–40°C ≤ TJ = TA ≤ 125°C, 2.7 V ≤ V(IN) = 18 V, V(EN/UVLO) = 2 V, V(OVP) = V(DEVSLP) = V(PGTH) = 0 V, R(ILIM) = 150 kΩ, C(OUT) = 1
µF, C(dVdT) = OPEN, PGOOD = FLT = IMON = OPEN. Positive current into terminals. All voltages referenced to GND (unless
otherwise noted). See Figure 42 for the timing diagrams.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ENABLE and UVLO INPUT
EN/UVLO ↑ (100 mV above V(ENR)) to V(OUT) = 100 mV,
C(dVdT) < 0.8 nF
220
µs
tON(dly)
EN turnon delay
EN turnoff delay
EN/UVLO ↑ (100 mV above V(ENR)) to V(OUT) = 100 mV,
100 + 150 ×
C(dVdT)
µs
µs
C(dVdT) ≥ 0.8 nF, [C(dVdT) in nF]
tOFF(dly)
EN/UVLO ↓ (100 mV below V(ENF)) to FLT↓
2
OVERVOLTAGE PROTECTION INPUT (OVP)
tOVP(dly) OVP disable delay
OUTPUT RAMP CONTROL (dV/dT )
OVP↑ (100 mV above V(OVPR)) to FLT↓
2
µs
ms
ns
EN/UVLO ↑ to V(OUT) = 4.5 V, with C(dVdT) = open
EN/UVLO ↑ to V(OUT) = 11 V, with C(dVdT) = open
EN/UVLO ↑ to V(OUT) = 11 V, with C(dVdT) = 1 nF
0.12
0.37
0.97
tdVdT
Output ramp time
0.25
0.5
CURRENT LIMIT
tFASTRIP(dly)
Fast-trip comparator delay
I(OUT) > I(FASTRIP)
200
REVERSE PROTECTION COMPARATOR
(V(IN) – V(OUT))↓ (1 mV overdrive below V(REVTH)) to FLT↓
(V(IN) – V(OUT))↓ (10 mV overdrive below V(REVTH)) to FLT↓
(V(IN) – V(OUT))↑ (10 mV overdrive above V(FWDTH)) to FLT↑
10
1
tREV(dly)
Reverse protection comparator
delay
µs
tFWD(dly)
3.1
POWER-GOOD COMPARATOR OUTPUT (PGOOD): ACTIVE HIGH
tPGOODR
tPGOODF
THERMAL SHUT DOWN (TSD)
Retry delay in TSD
Rising edge
Falling edge
0.42
0.42
0.54
0.54
0.66
0.66
ms
ms
PGOOD delay (de-glitch) time
TPS25940-Q1 Only
128
ms
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6.7 Typical Characteristics
Conditions are –40°C ≤ TA = TJ ≤ 125°C, V(IN) = 12 V, V(EN/UVLO) = 2 V, V(OVP) = V(DEVSLP) = V(PGTH) = 0 V, R(ILIM) = 150 kΩ,
C(OUT) = 1 µF, C(dVdT) = OPEN, PGOOD = FLT = IMON = OPEN. (unless stated otherwise)
300
250
200
150
100
50
2.35
2.30
2.25
2.20
2.15
2.10
V(UVR)
V
(UVF)
o
TA = -40 C
o
TA = 25 C
T= 85oC
A
T
= 125oC
TA = 125 0C
A
0
œ50
œ20
10
40
70
100
130
0
5
10
15
20
Temperature (oC)
Input Voltage (V)
C014
C014
Figure 1. UVLO Threshold Voltage vs Temperature
Figure 2. Input Supply Current vs Supply Voltage during
Normal Operation
25
150
125
100
75
20
15
10
5
50
o
TA = -40 C
o
TA = -40 C
o
o
TA = 25 C
TA = 25 C
25
T= 85oC
T= 85oC
A
A
T
= 125oC
T
= 125oC
A
A
0
0
0
5
10
15
20
0
5
10
15
20
Input Voltage (V)
Input Voltage (V)
C014
C014
Figure 3. Input Supply Current vs Supply Voltage at
Shutdown
Figure 4. Input Supply Current vs Supply Voltage in
DevSleep Mode
1.00
1.00
0.98
0.96
0.94
0.92
0.90
0.98
0.96
0.94
0.92
0.90
V(ENR)
V(OVPR)
V(OVPF)
V
(ENF)
œ50
œ20
10
40
70
100
130
œ50
œ20
10
40
70
100
130
Temperature (oC)
Temperature (oC)
C014
C014
Figure 5. EN Threshold Voltage vs Temperature
Figure 6. OVP Threshold Voltage vs Temperature
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Typical Characteristics (continued)
Conditions are –40°C ≤ TA = TJ ≤ 125°C, V(IN) = 12 V, V(EN/UVLO) = 2 V, V(OVP) = V(DEVSLP) = V(PGTH) = 0 V, R(ILIM) = 150 kΩ,
C(OUT) = 1 µF, C(dVdT) = OPEN, PGOOD = FLT = IMON = OPEN. (unless stated otherwise)
1.00
0.98
0.96
0.94
0.92
0.90
0.60
0.55
0.50
0.45
0.40
E
V(SHUTR)
V
E
(SHUTF)
V(PGTHR)
V
(PGHTF)
œ50
œ20
10
40
70
100
130
œ50
œ20
10
40
70
100
130
Temperature (oC)
Temperature (oC)
C014
C014
Figure 7. PGTH Threshold Voltage vs Temperature
Figure 8. EN Threshold Voltage for Low IQ Mode vs
Temperature
300
3.0
250
200
150
100
50
2.6
2.2
1.8
1.4
1.0
œ50
œ20
10
40
70
100
130
œ50
œ20
10
40
70
100
130
Temperature (oC)
Temperature (oC)
C014
C014
Figure 9. Enable Turn ON Delay vs Temperature
Figure 10. Enable Turn OFF Delay vs Temperature
3.0
2.6
2.2
1.8
1.4
1.0
2.1
1.9
1.7
1.5
1.3
1.1
0.9
V(DEVSLPR)
V
(DEVSLPF)
œ50
œ20
10
40
70
100
130
œ50
œ20
10
40
70
100
130
Temperature (oC)
Temperature (oC)
C014
C014
Figure 11. OVP Disable Delay vs Temperature
Figure 12. DEVSLP Threshold Voltage vs Temperature
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Typical Characteristics (continued)
Conditions are –40°C ≤ TA = TJ ≤ 125°C, V(IN) = 12 V, V(EN/UVLO) = 2 V, V(OVP) = V(DEVSLP) = V(PGTH) = 0 V, R(ILIM) = 150 kΩ,
C(OUT) = 1 µF, C(dVdT) = OPEN, PGOOD = FLT = IMON = OPEN. (unless stated otherwise)
1.2
1.1
1.0
0.9
11.90
11.89
11.88
11.87
11.86
11.85
11.84
11.83
11.82
œ50
œ20
10
40
70
100
130
œ50
œ20
10
40
70
100
130
Temperature (oC)
Temperature (oC)
C014
C014
Figure 13. DEVSLP Pull Down Current vs Temperature
Figure 14. GAIN(dVdT) vs Temperature
10
1000
100
10
1
1
0
0
10
100
1
10
100
1000
C(dVdT) (nF)
R(ILIM) Resistor (kW)
C014
C014
Figure 15. Output Ramp Time vs C(dVdT)
Figure 16. Current Limit vs Current Limit Resistor
6
5
4
3
2
1
0
9.5
9.0
8.5
8.0
7.5
150 kW
88.6 kW
42.4 kW
20 kW
16.9 kW
0
1
2
3
4
5
6
-50
0
50
100
150
200
Current Limit(A)
C014
Temperature (èC)
D030
Figure 17. Current Limit Accuracy vs Current Limit
Figure 18. Current Limit vs Temperature Across R(ILIM)
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Typical Characteristics (continued)
Conditions are –40°C ≤ TA = TJ ≤ 125°C, V(IN) = 12 V, V(EN/UVLO) = 2 V, V(OVP) = V(DEVSLP) = V(PGTH) = 0 V, R(ILIM) = 150 kΩ,
C(OUT) = 1 µF, C(dVdT) = OPEN, PGOOD = FLT = IMON = OPEN. (unless stated otherwise)
2%
1.5%
1%
0.5%
I=1.0A
(LIM)
150 k
88.6 k
42.4 k
20 k
I(LIM) = 2.1 A
0.0%
I(LIM) = 3.6 A
-0.5%
-1.0%
-1.5%
-2.0%
-2.5%
-3.0%
I(LIM) = 5.3 A
16.9 k
0.5%
0
-0.5%
-1%
-1.5%
-2%
0
2
4
6
8
10
12
-50
0
50
100
150
V(IN) - V(OUT) (V)
C014
Temperature (èC)
D031
Thermal shutdown occurs when I(LIM)
5.3 A
=
[V(IN) - V(OUT)] > 8 V
Figure 19. Current Limit (% Normalized) vs R(LIMIT) Resistor
Figure 20. Current Limit Normalized (%) vs V(IN) – V(OUT)
0.70
0.70
0.65
0.60
0.69
0.68
0.67
0.66
0.65
R(ILIM) = Short
R
= Open
(ILIM)
0.55
0.50
0.45
0.40
œ50
0
50
100
150
œ50
œ20
10
40
70
100
130
Temperature (oC)
Temperature (oC)
C014
C014
Figure 22. Current Limit in DevSleep Mode vs Temperature
Figure 21. Current Limit for R(ILIM) = Open and Short vs
Temperature
1.2
1.1
1
9
8
7
6
5
4
3
2
1
0
0.9
0.8
0.7
0.6
0
1
2
3
4
5
6
-50
-20
10
40
70
100
130
Current Limit I(LIM) (A)
C014
Temperature (èC)
D022
Figure 23. Fast Trip Threshold vs Current Limit
Figure 24. IMON Offset vs Temperature
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Typical Characteristics (continued)
Conditions are –40°C ≤ TA = TJ ≤ 125°C, V(IN) = 12 V, V(EN/UVLO) = 2 V, V(OVP) = V(DEVSLP) = V(PGTH) = 0 V, R(ILIM) = 150 kΩ,
C(OUT) = 1 µF, C(dVdT) = OPEN, PGOOD = FLT = IMON = OPEN. (unless stated otherwise)
500
50
5
54.0
53.5
53.0
52.5
52.0
51.5
51.0
o
TA = -40 C
T
T
T
= 25oC
A
= 85oC
A
= 125oC
A
0.1
1.0
10.0
œ50
œ20
10
40
70
100
130
Temperature (oC)
Output Current , IOUT (A)
C014
C014
Figure 26. Current Monitor Output vs Output Current
Figure 25. GAIN(IMON) vs Temperature
60
55
50
45
40
35
30
25
16
14
12
10
V(OUT) = 0 V
8
6
V(OUT) = 18 V
4
1A
2A
3A
4A
5A
2
0
œ2
œ50
0
50
100
150
œ50
0
50
100
150
Temperature (oC)
Temperature (oC)
C014
C014
Figure 27. RON vs Temperature Across Load Current
Figure 28. OUT Leakage Current in Off State vs Temperature
-65
102.0
-65.2
-65.4
-65.6
-65.8
-66
101.5
101.0
100.5
100.0
99.5
-66.2
-66.4
-66.6
-66.8
-67
99.0
98.5
98.0
œ50
0
50
100
150
Temperature (oC)
-50
-20
10
40
70
100
130
C014
Temperature (èC)
D032
Figure 30. V(FWDTH) vs Temperature
Figure 29. V(REVTH) vs Temperature
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Typical Characteristics (continued)
Conditions are –40°C ≤ TA = TJ ≤ 125°C, V(IN) = 12 V, V(EN/UVLO) = 2 V, V(OVP) = V(DEVSLP) = V(PGTH) = 0 V, R(ILIM) = 150 kΩ,
C(OUT) = 1 µF, C(dVdT) = OPEN, PGOOD = FLT = IMON = OPEN. (unless stated otherwise)
100000
o
TA = -40 C
TA =25oC
10000
T
= 85oC
A
TA = 125oC
1000
100
10
1
0.1
1
10
100
C014
Power Dissipation (W)
V(IN) = 4.5 V
Taken on 2-Layer board, 2 oz.(0.08-mm thick) with GND plane
area: 14 cm2 (Top) and 20 cm2 (bottom)
Figure 32. Turn ON with Enable
Figure 31. Thermal Shutdown Time vs Power Dissipation
V(IN) = 11 V
R(FLT)=100 kΩ
Figure 34. EN Turn ON Delay : EN ↑ to Output Ramp ↑
Figure 33. Turn ON and OFF with Enable
R(FLT)=100 kΩ
V(IN) = 12 V
RL = 12 Ω
R(FLT)=100 kΩ
Figure 35. EN Turn OFF Delay : EN ↓ to Fault ↓
Figure 36. OVP Turn OFF Delay: OVP ↑ to Fault ↓
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Typical Characteristics (continued)
Conditions are –40°C ≤ TA = TJ ≤ 125°C, V(IN) = 12 V, V(EN/UVLO) = 2 V, V(OVP) = V(DEVSLP) = V(PGTH) = 0 V, R(ILIM) = 150 kΩ,
C(OUT) = 1 µF, C(dVdT) = OPEN, PGOOD = FLT = IMON = OPEN. (unless stated otherwise)
V(IN) = 12 V
RL = 12 Ω
R(FLT)=100 kΩ
V(IN) = 12 V
RL = 12 Ω
R(FLT)= 100 kΩ
Figure 37. OVP Turn ON Delay: OVP ↓ to Output Ramp ↑
Figure 38. Power Good Delay (Rising)
R(FLT) = 100 kΩ
R(IMON) = 16.9 kΩ
R(ILIM) = 17.8 kΩ
V(IN) = 12 V
RL = 12 Ω
R(FLT)= 100 kΩ
Figure 40. Hot-Short: Fast Trip Response and Current
Regulation
Figure 39. Power Good Delay (Falling)
R(FLT)= 100 kΩ
R(IMON) = 16.9 kΩ
Figure 41. Hot-Short: Fast Trip Response (Zoomed)
R(ILIM) = 17.8 kΩ
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7 Parametric Measurement Information
V(OUT)
VEN
FLT
V(ENF)-0.1V
0.1V
VEN
V(ENR)+0.1V
10%
time
0
time
0
tON(dly)
tOFF(dly)
-20mV
110mV
90%
V(IN)-V(OUT)
V(IN)-V(OUT)
FLT
FLT
10%
0
time
tREV(dly)
0
time
tFWD(dly)
I(FASTRIP)
V(OVPR) + 0.1V
V(OVP)
I(LIM)
I(OUT)
FLT
10%
0
time
0
time
tOVP(dly)
tFASTRIP(dly)
Figure 42. Timing Diagrams
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8 Detailed Description
8.1 Overview
The TPS25940x-Q1 device is a smart eFuse with integrated back-to-back FETs and enhanced built-in protection
circuitry. It provides robust protection for all systems and applications powered from 2.7 V to 18 V.
For hot-plug-in boards, the device provides hot-swap power management with in-rush current control and
programmable output ramp-rate. The device integrates overcurrent and short circuit protection. The precision
overcurrent limit helps to minimize over design of the input power supply, while the fast response short circuit
protection immediately isolates the load from input when a short circuit is detected. The device allows the user to
program the overcurrent limit threshold between 0.6 A and 5.3 A via an external resistor.
The device provides precise monitoring of voltage bus for brown-out and overvoltage conditions and asserts fault
for downstream system. Its overall threshold accuracy of 2% ensures tight supervision of bus, eliminating the
need for a separate supply voltage supervisor chip.
The device is designed to protect systems such as USB hubs against sudden output short to battery events. The
device monitors V(IN) and V(OUT) to provide true reverse blocking from output when output short to battery fault
condition or input power fail condition is detected.
The additional features include:
•
•
Precise current monitor output for health monitoring of the system
Additional power good comparator with precision internal reference for output or any other rail voltage
monitoring
•
•
•
Over temperature protection to safely shutdown in the event of an overcurrent event
De-glitched fault reporting for brown-out and overvoltage faults
A choice of latched or automatic restart mode
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8.2 Functional Block Diagram
IN
OUT
4-8
9-13
42 mΩ
-66 mV
+
UVLOb
Charge
Pump
+100 mV
2.30 V
2.18 V
Current
X52 µ
EN/UVLO
+
CP
Sense
14
+
+
EN
0.99 V
0.92 V
REVERSE
TSD
OVP
SWEN
IMON
15
1
Gate Control Logic
OVP
0.99 V
0.92 V
19
Thermal
Shutdown
Current Limit Amp
Fast-Trip Comp
DEVSLP
+
Low current
Mode
(Threshold=1.5xIOL
)
1.85 V
0.96 V
1 µA
0.87 V
Shutdown
ILIM
FLT
17
20
EN/UVLO
Short Detect
Ramp Control
12x
1 µA
dVdT
GND
SWEN
18
16
16 Ω
16 Ω
UVLO
EN
TSD
PGOOD
2
dVdT
over
0.5 ms
0.5 ms
+
Solid Blocks will be
Turned Off During
DEVSLP
16 Ω
0.99 V
0.92 V
TPS25940-Q1
3
PGTH
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8.3 Feature Description
8.3.1 Enable and Adjusting Undervoltage Lockout
The EN/UVLO pin controls the ON and OFF state of the internal FET. A voltage V(EN/UVLO) < V(ENF) on this pin
turns off the internal FET, thus disconnecting IN from OUT, while voltage below V(SHUTF) takes the device into
shutdown mode, with IQ less than 15 µA to ensure minimal power loss. Cycling EN/UVLO low and then back high
resets the TPS25940L-Q1 that has latched off due to a fault condition.
The internal de-glitch delay on EN/UVLO falling edge is kept low for quick detection of power failure. For
applications where a higher de-glitch delay on EN/UVLO is desired, or when the supply is particularly noisy, it is
recommended to use an external bypass capacitor from EN/UVLO terminal to GND.
The undervoltage lock out can be programmed by using an external resistor divider from supply IN terminal to
EN/UVLO terminal to GND as shown in Figure 43. When an undervoltage or input power fail event is detected,
the internal FET is quickly turned off, and FLT is asserted. If the Under-Voltage Lock-Out function is not needed,
the EN/UVLO terminal must be connected to the IN terminal. EN/UVLO terminal must not be left floating.
The device also implements internal undervoltage-lockout (UVLO) circuitry on the IN terminal. The device
disables when the IN terminal voltage falls below internal UVLO Threshold V(UVF). The internal UVLO threshold
has a hysteresis of 115 mV.
V(IN)
IN
TPS25940-Q1
R1
EN/UVLO
+
EN
0.99V
R2
0.92V
OVP
+
OVP
0.99V
R3
0.92V
GND
Figure 43. UVLO and OVP Thresholds Set By R1, R2 and R3
8.3.2 Overvoltage Protection (OVP)
The device incorporates circuit to protect system during overvoltage conditions. A resistor divider connected from
the supply to OVP terminal to GND (as shown in Figure 43) programs the overvoltage threshold. A voltage more
than V(OVPR) on OVP pin turns off the internal FET and protects the downstream load. This pin must be tied to
GND when not used.
8.3.3 Hot Plug-In and In-Rush Current Control
The device is designed to control the in-rush current upon insertion of a card into a live backplane or other "hot"
power source. This limits the voltage sag on the backplane’s supply voltage and prevents unintended resets of
the system power. A slew rate controlled startup (dVdT) also helps to eliminate conductive and radiative
interferences. An external capacitor connected from the dVdT pin to GND defines the slew rate of the output
voltage at power-on (as shown in Figure 44). Equation governing slew rate at start-up is shown in Equation 1.
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Feature Description (continued)
TPS25940-Q1
1 uA
dVdT
GND
16 Ω
C(dVdT)
SWEN
Figure 44. Output Ramp Up Time tdVdT is Set by C(dVdT)
æ
ç
ç
è
ö
÷
÷
ø
C
dV
(OUT)
æ
ö
(dVdT)
GAIN
I
=
x
ç
÷
(dVdT)
ç
÷
dt
(dVdT)
è
ø
where
•
I(dVdT) = 1 µA (typical)
dV
(OUT)
•
•
dt
= Desired output slew rate
GAIN(dVdT) = dVdT to OUT gain = 12
(1)
(2)
(3)
The total ramp time (tdVdT) of V(OUT) for 0 to V(IN) can be calculated using Equation 2.
tdVdT = 8.3 x 104 x V(IN) x C(dVdT)
The inrush current, I(INRUSH) can be calculated as shown in Equation 3.
I(INRUSH) = C(OUT) x V(IN) / tdVdT
.
The dVdT pin can be left floating to obtain a predetermined slew rate (tdVdT) on the output. When terminal is left
floating, the device sets an internal ramp rate of 30 V/ms for output (V(OUT)) ramp.
Figure 57 and Figure 58 illustrate the inrush current control behavior of the device. For systems where load is
present during start-up, the current never exceeds the overcurrent limit set by R(ILIM) resistor for the application.
For defining appropriate charging time-rate under different load conditions, see the Setting Output Voltage Ramp
Time (tdVdT) section.
8.3.4 Overload and Short Circuit Protection
At all times load current is monitored by sensing voltage across an internal sense resistor. During overload
events, current is limited to the current limit (I(LIM)) programmed by R(ILIM) resistor as shown in Equation 4.
89
(LIM)
I
=
R
(ILIM)
where
•
•
I(LIM) is overload current limit in Ampere
R(ILIM) is the current limit resistor in kΩ
(4)
The device incorporates two distinct levels: a current limit (I(LIM)) and a fast-trip threshold (I(FASTRIP)). Fast trip and
current limit operation are shown in Figure 45.
Bias current on ILIM pin directly controls current-limiting behavior of the device, and PCB routing of this node
must be kept away from any noisy (switching) signals.
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Feature Description (continued)
8.3.4.1 Overload Protection
For overload conditions, the internal current-limit amplifier regulates the output current to I(LIM). The output
voltage droops during the current regulation, resulting in increased power dissipation in the device. If the device
junction temperature reaches the thermal shutdown threshold (T(TSD)), the internal FET is turned off. When in
thermal shutdown, the TPS25940L-Q1 version stays latched off, whereas the TPS25940-Q1 commences an
auto-retry cycle 128 ms after TJ < [T(TSD) – 12°C]. During thermal shutdown, the fault pin FLT pulls low to signal a
fault condition. Figure 61 and Figure 62 illustrate overload behavior.
8.3.4.2 Short Circuit Protection
During a transient short circuit event, the current through the device increases very rapidly. As current-limit
amplifier cannot respond quickly to this event because of its limited bandwidth, the device incorporates a fast-trip
comparator, with a threshold I(FASTRIP). This comparator shuts down the pass device within 1µs, when the current
through internal FET exceeds I(FASTRIP) (I(OUT) > I(FASTRIP)), and terminates the rapid short-circuit peak current. The
trip threshold is set to more than 50% of the programmed overload current limit ( I(FASTRIP) = 1.5 x I(LIM)+ 0.375 ).
The fast-trip circuit holds the internal FET off for only a few microseconds, after which the device turns back on
slowly, allowing the current-limit loop to regulate the output current to I(LIM). Then, device behaves similar to
overload condition. Figure 63 through Figure 64 illustrate the behavior of the system when the current exceeds
the fast-trip threshold.
8.3.4.3 Start-Up with Short on Output
During start-up into a short circuit current is limited to I(LIM). Figure 45 and Figure 65 illustrate start-up with a short
on the output. This feature helps in quick fault isolation and hence ensures stability of the DC bus.
8.3.4.4 Constant Current Limit Behavior During Overcurrent Faults
When power dissipation in the internal FET [PD = (V(IN) – V(OUT)) × I(OUT)] > 10 W, there is approximately 0% to
5% thermal fold back in the current limit value so that I(LIM) drops to IOS. Eventually, the device shuts down
because of over temperature.
I(FASTRIP)
I
(FASTRIP) = 1.5 x I(LIM) + 0.375
I(LIM)
IOS
Thermal Foldback
0-5%
Figure 45. Fast-Trip Current
8.3.5 FAULT Response
The FLT open-drain output is asserted (active low) during undervoltage, overvoltage, reverse voltage-current and
thermal shutdown conditions. The FLT signal remains asserted until the fault condition is removed and the device
resumes normal operation. The device is designed to eliminate false fault reporting by using an internal "de-
glitch" circuit for undervoltage and overvoltage (2.2 µs typical) conditions without the need for external circuitry.
This ensures that fault is not accidentally asserted during transients on input bus.
Connect FLT with a pull up resistor to Input or Output voltage rail. FLT may be left open or tied to ground when
not used. V(IN) falling below V(UVF) = 2.1 V resets FLT.
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Feature Description (continued)
8.3.6 Current Monitoring
The current source at IMON terminal is configured to be proportional to the current flowing from IN to OUT. This
current can be converted to a voltage using a resistor R(IMON) from IMON terminal to GND terminal. This voltage,
computed using Equation 6, can be used as a means of monitoring current flow through the system.
The maximum voltage range for monitoring the current (V(IMONmax)) is limited to minimum([V(IN) – 2.2 V], 6 V) to
ensure linear output. This puts limitation on maximum value of R(IMON) resistor and is determined by Equation 5.
minimum (V
- 2.2, 6)
(IN)
x GAIN
R
=
(IMONmax)
1.6 x I
(LIM)
(IMON)
(5)
The output voltage at IMON terminal is calculated from Equation 6.
é
ù
x R
(IMON)
V
=
I
x GAIN
(OUT) (IMON) (IMON_OS)
+ I
(IMON)
ë
û
where
•
•
•
GAIN(IMON) = Gain factor I(IMON):I(OUT) = 52 µA/A
I(OUT) = Load current
I(IMON_OS) = 0.8 µA (typical)
(6)
This pin must not have a bypass capacitor to avoid delay in the current monitoring information.
The voltage at IMON pin can be digitized using an ADC (such as ADS1100, SBAS239) to read the current
monitor information over an I2C bus.
8.3.7 Power Good Comparator
The device incorporates a Power Good comparator for co-ordination of status to downstream DC-DC converters
or system monitoring circuits. The comparator has an internal reference of V(PGTHR) = 0.99 V at negative terminal
and positive terminal PGTH can be utilized for monitoring of either input or output of the device. The comparator
output PGOOD is an open-drain active high signal, which can be used to indicate the status to downstream units.
PGOOD is asserted high when internal FET is fully enhanced and PGTH pin voltage is higher than internal
reference V(PGTHR)
.
The PGOOD signal has deglitch time incorporated to ensure that internal FET is fully enhanced before heavy
load is applied by downstream converters. Rising de-glitch delay is determined by Equation 7.
tPGOOD(degl) = Maximum{(3.5 x 106 x C(dVdT)), tPGOODR
}
(7)
Connect the PGOOD pin with a pull up resistor to Input or Output voltage rail. PGOOD may be left open or tied
to ground when not used.
8.3.8 IN, OUT and GND Pins
The device has multiple pins for input (IN) and output (OUT).
All IN pins must be connected together and to the power source. A ceramic bypass capacitor close to the device
from IN to GND is recommended to alleviate bus transients. The recommended operating voltage range is
2.7 V – 18 V.
Similarly all OUT pins must be connected together and to the load. V(OUT) in the ON condition, is calculated using
Equation 8.
V
= V
- (R
ON
× I )
(OUT)
(OUT)
(IN)
(8)
where, RON is the total ON resistance of the internal FET.
GND terminal is the most negative voltage in the circuit and is used as a reference for all voltage reference
unless otherwise specified.
8.3.9 Thermal Shutdown
Internal over temperature shutdown disables turns off the FET when TJ > 160°C (typical). The TPS25940L-Q1
version stays latched off, whereas TPS25940-Q1 commences an auto-retry cycle128 ms after TJ drops below
[T(TSD) – 12°C]. During the thermal shutdown, the fault pin FLT pulls low to signal a fault condition.
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8.4 Device Functional Modes
8.4.1 DevSleep Mode
The TPS25940x-Q1 device provides a dedicated DevSleep interface terminal (DEVSLP) to drive the device in
low power mode. When pulled high, it puts the device in low power DevSleep mode. In this mode, the quiescent
current consumption of the device is limited to less than 130 µA (95 µA typical). During this mode, the output
voltage remains active, the overload current limit is set to I(DEVSLP(LIM)) and functionality of reverse comparator and
current monitoring is disabled. All other protections are kept active ensuring the safety of the system even in
DevSleep mode.
User must ensure that load currents on the bus are limited to less than I(DEVSLP(LIM)), when the device is driven to
DevSleep mode. Also, while coming out of DevSleep, it is important to sequence the TPS25940x-Q1 earlier than
the load. Otherwise, the load can exceed I(DEVSLP(LIM)) and cause the TPS25940x-Q1 to enter the overload mode.
Figure 46 through Figure 49 illustrate the behavior of the system in DevSleep mode.
V(IN) = 12 V
l(LIM) = 5.3 A
RL = 22 Ω
V(IN) = 12 V
l(LIM) = 5.3 A
RL = 15 Ω
C(OUT) = 1 µF
C(OUT) = 1 µF
Figure 46. IN and OUT of DevSleep Mode with 550-mA
Load
Figure 47. IN and OUT of DevSleep Mode with 800-mA
Load. In DevSleep, Load Current gets Limited to
I(DEVSLP(LIM))
RL = 22 Ω
l(LIM) = 5.3 A
C(OUT) = 1 µF
l(LIM–) = 5.3 A
C(OUT) = 1 µF
Figure 48. IMON Disabled in DevSleep Mode
Figure 49. TPS25940-Q1 Hot Short and Retry in DevSleep
Mode
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Device Functional Modes (continued)
8.4.2 Shutdown Control
The internal FET and hence the load current can be remotely switched off by taking the UVLO pin below its 0.6 V
threshold with an open collector or open drain device as shown in Figure 50. The device quiescent current is
reduced to less than 20 µA in this state. Upon releasing the UVLO pin the device turns on with soft-start cycle.
V(IN)
IN
TPS25940-Q1
R1
EN/UVLO
+
EN
0.99V
from µC
R2
0.92V
GND
Figure 50. Shutdown Control
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The TPS25940x-Q1 device is a smart eFuse. It is typically used for Hot-Swap and Power rail protection
applications. It operates from 2.7 V to 18 V with programmable current limit, overvoltage and undervoltage
protection. The device aids in controlling the in-rush current and provides fast turn-off during reverse voltage
conditions for systems such as USB ports prone to Short-to-Battery faults, Servers, Power Back-up Storage units
and RAID cards. The device also provides robust protection for multiple faults on the sub-system rail.
The Detailed Design Procedure section can be used to select component values for the device.
Alternatively, the WEBENCH® software may be used to generate a complete design. The WEBENCH® software
uses an iterative design procedure and accesses a comprehensive database of components when generating a
design. Additionally, a spreadsheet design tool TPS25940 Design Calculator is available on web folder.
9.2 Typical Application
2.7 V to 18 V
OUT
R7
IN
IN
OUT
COUT
100 µF
CIN
0.1 µF
R1
R4
475 kꢀ
42 mꢀ
R6
475 kꢀ
(See Note A)
EN/UVLO
OVP
FLT
PGOOD
PGTH
Health
Monitor
R2
16.7 kꢀ
from µC
DEVSLP
dVdT
Load
Monitor
IMON
ILIM
GND
R3
31.2 kꢀ
CdVdT
1.5 nF
RIMON
19.1 kꢀ
R5
47 kꢀ
RILIM
17.8 kꢀ
TPS25940-Q1
A. CIN: Optional and only for noise suppression.
Figure 51. Typical Application Schematic
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Typical Application (continued)
9.2.1 Design Requirements
Table 1 lists the Design Parameters.
Table 1. Design Parameters
DESIGN PARAMETER
Input voltage, V(IN)
EXAMPLE VALUE
12 V
Undervoltage lockout set point, V(UV)
Overvoltage protection set point , V(LIM)
Load at Start-Up , RL(SU)
10.8 V
16.5 V
4.8 Ω
Current limit, I(LIM)
5 A
Load capacitance , C(OUT)
100 µF
85°C
Maximum ambient temperatures , TA
9.2.2 Detailed Design Procedure
The following design procedure can be used to select component values for the TPS25940x-Q1.
9.2.2.1 Step by Step Design Procedure
To begin the design process a few parameters must be decided upon. The designer must know the following:
•
•
•
•
•
Normal input operation voltage
Maximum output capacitance
Maximum current Limit
Load during start-up
Maximum ambient temperature of operation
This design procedure below seeks to control the junction temperature of device under both static and transient
conditions by proper selection of output ramp-up time and associated support components. The designer can
adjust this procedure to fit the application and design criteria.
9.2.2.2 Programming the Current-Limit Threshold: R(ILIM) Selection
The R(ILIM) resistor at the ILIM pin sets the over load current limit, this can be set using Equation 9.
89
(ILIM)
R
=
= 17.8kW
5
(9)
Choose closest standard value: 17.8 k, 1% standard value resistor.
9.2.2.3 Undervoltage Lockout and Overvoltage Set Point
The undervoltage lockout (UVLO) and overvoltage trip point are adjusted using the external voltage divider
network of R1, R2 and R3 as connected between IN, EN, OVP and GND pins of the device. The values required
for setting the undervoltage and overvoltage are calculated solving Equation 10 and Equation 11.
R
3
R +R +R
V
=
x V
(OV)
(OVPR)
1
2
3
(10)
R
+R
2
3
V
=
x V
(UV)
(ENR)
R +R +R
3
1
2
(11)
For minimizing the input current drawn from the power supply {I(R123) = V(IN)/(R1 + R2 + R3)}, it is recommended to
use higher values of resistance for R1, R2 and R3.
However, leakage currents because of the external active components connected to the resistor string can add
error to these calculations. So, the resistor string current, I(R123) must be chosen to be 20 times greater than the
leakage current expected.
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From the device electrical specifications, V(OVPR) = 0.99 V and V(ENR) = 0.99 V. For design requirements, V(OV) is
16.5 V and V(UV) is 10.8 V. To solve the equation, first choose the value of R3 = 31.2 kΩ and use Equation 10 to
solve for (R1 + R2) = 488.8 kΩ. Use Equation 11 and value of (R1 + R2) to solve for R2 = 16.47 kΩ and finally R1=
472.33 kΩ.
Using the closest standard 1% resistor values gives R1 = 475 kΩ, R2 = 16.7 kΩ, and R3 = 31.2 kΩ.
The power failure threshold is detected on the falling edge of supply. This threshold voltage is 7% lower than the
rising threshold, V(UV). This is calculated using Equation 12.
V(PFAIL) = 0.93 x V(UV)
(12)
9.2.2.4 Programming Current Monitoring Resistor—RIMON
Voltage at IMON pin V(IMON) represents the voltage proportional to load current. This can be connected to an
ADC of the downstream system for health monitoring of the system. The R(IMON) need to be configured based on
the maximum input voltage range of the ADC used. R(IMON) is set using Equation 13.
V
(IMONmax)
R
=
kW
(IMON)
-6
I
x 52 x 10
(LIM)
(13)
For I(LIM) = 5 A, and considering the operating range of ADC from 0 V to 5 V, V(IMONmax) is 5 V and R(IMON) is
determined by:
5
R
=
= 19.23 kW
(IMON)
-6
5 x 52 x 10
(14)
Selecting R(IMON) value less than determined by Equation 14 ensures that ADC limits are not exceeded for
maximum value of load current.
If the IMON pin voltage is not being digitized with an ADC, R(IMON) can be selected to produce a 1V/1A voltage at
the IMON pin, using Equation 13.
Choose closest 1 % standard value: 19.1 kΩ.
If current monitoring up to I(FASTRIP) is desired, R(IMON) can be reduced by a factor of 1.6, as in Equation 5.
9.2.2.5 Setting Output Voltage Ramp Time (tdVdT
)
For a successful design, the junction temperature of device must be kept below the absolute-maximum rating
during both dynamic (start-up) and steady state conditions. Dynamic power stresses often are an order of
magnitude greater than the static stresses, so it is important to determine the right start-up time and in-rush
current limit required with system capacitance to avoid thermal shutdown during start-up with and without load.
The ramp-up capacitor C(dVdT) needed is calculated considering the two possible cases Case1: Start-up Without
Load: Only Output Capacitance C(OUT) Draws Current During Start-up and Case 2: Start-Up With Load: Output
Capacitance C(OUT) and Load Draws Current During Start-Up.
9.2.2.5.1 Case1: Start-up Without Load: Only Output Capacitance C(OUT) Draws Current During Start-up
During start-up, as the output capacitor charges, the voltage difference across the internal FET decreases, and
the power dissipated decreases as well. Typical ramp-up of output voltage V(OUT) with inrush current limit of 1.2 A
and power dissipated in the device during start-up is shown in Figure 52. The average power dissipated in the
device during start-up is equal to area of triangular plot (red curve in Figure 52) averaged over tdVdT
.
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16
14
12
10
8
16
Input Current (A)
Power Dissioation (W)
14
Output Voltage (V)
12
10
8
6
6
4
4
2
2
0
0
0
20
40
60
80
100
Start-Up Time, tdVdt (%)
C013
V(IN) = 12 V
C(dVdT) = 1 nF
C(OUT)=100 µF
V(IN) = 12 V
C(dVdT) = 1 nF
C(OUT)=100 µF
Figure 53. PD(INRUSH) Due to Inrush Current
Figure 52. Start-Up Without Load
For the TPS25940-Q1 device, the inrush current is determined as shown in Equation 15.
V
dV
(IN)
I = C x
=> I
(INRUSH)
= C x
(OUT)
dT
t
dVdT
(15)
(16)
Power dissipation during start-up is given by Equation 16.
P
= 0.5 x V x I
(IN) (INRUSH)
D(INRUSH)
Equation 16 assumes that load does not draw any current until the output voltage has reached its final value.
9.2.2.5.2 Case 2: Start-Up With Load: Output Capacitance C(OUT) and Load Draws Current During Start-Up
When load draws current during the turn-on sequence, there is additional power dissipated. Considering a
resistive load RL(SU) during start-up, load current ramps up proportionally with increase in output voltage during
tdVdT time. Typical ramp-up of output voltage, Load current and power dissipation in the device is shown in
Figure 54 and power dissipation with respect to time is plotted in Figure 55. The additional power dissipation
during start-up phase is calculated as shown in Equation 17 and Equation 18.
æ
ö
÷
÷
÷
t
ç
(V - V )(t) = V
(IN)
x ç1-
I
O
ç
ç
è
÷
ø
t
dVdT
(17)
æ
ç
ç
ç
ç
ö
V
÷
÷
÷
÷
÷
t
(IN)
I (t) =
x
L
R
t
dVdT
ç
è
L(SU) ø
(18)
Where RL(SU) is the load resistance present during start-up. Average energy loss in the internal FET during
charging time due to resistive load is given by Equation 19.
tdVdT
æ
ç
ç
ç
ö
÷
÷
÷
÷
÷
æ
ç
ç
è
ö
÷
÷
÷
V
t
t
(IN)
ç
W
=
V
x ç1 -
x
x
dt
t
(IN)
ç
ç
è
ò
÷
ø
t
R
t
dVdT
L(SU)
dVdT ø
0
(19)
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14
12
10
8
14
12
10
8
Output Voltage (V)
Power Dissipoation (W)
Load Current (A)
6
6
4
4
2
2
0
0
0
20
40
60
80
100
Start-Up Time, tdVdT (%)
C013
V(IN) = 12 V
C(dVdT) = 1 nF
RL(SU) = 4.8 Ω
V(IN) = 12 V
C(dVdT) = 1 nF
RL(SU) = 4.8 Ω
Figure 55. PD(LOAD) in Load During Start-Up
Figure 54. Start-Up With Load
On solving Equation 19 the average power loss in the internal FET due to load is shown in Equation 20.
2
V
æ
ö
÷
÷
ø
1
6
(IN)
÷
x
÷
ç
P
=
ç
D(LOAD)
ç
è
R
L(SU)
(20)
(21)
(22)
Total power dissipated in the device during startup is shown is Equation 21.
P
=
P + P
D(INRUSH) D(LOAD)
D(STARTUP)
Total current during startup is given by Equation 22.
I
=
I
+ I (t)
(STARTUP)
(INRUSH) L
If I(STARTUP) > I(LIM), the device limits the current to I(LIM) and the current limited charging time is determined by
Equation 23.
V
(IN)
t
=
C
x
dVdT(current limited)
(OUT)
I
(LIM)
(23)
The power dissipation, with and without load, for selected start-up time must not exceed the shutdown limits as
shown in Figure 56.
100000
o
TA = -40 C
TA =25oC
10000
T
= 85oC
A
TA = 125oC
1000
100
10
1
0.1
1
10
100
C014
Power Dissipation (W)
Taken on 2-Layer board, 2oz.(0.08-mm thick) with GND plane area: 14 cm2 (Top) and 20 cm2 (bottom)
Figure 56. Thermal Shutdown Limit Plot
For the design example under discussion,
Select ramp-up capacitor C(dVdT) = 1nF, using Equation 24.
4
8.3 x 10 x 12 x 1 x 10
-9
t
=
= 0.996ms = : 1ms
dvdt
(24)
The inrush current drawn by the load capacitance (C(OUT)) during ramp-up using Equation 25.
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æ
ç
ç
è
ö
÷
÷
÷
12
-6
I
=
100 x 10
(
x ç
ç
= 1.2 A
)
(INRUSH)
-3
÷
ø
1 x 10
(25)
(26)
The inrush Power dissipation is calculated, using Equation 26.
P
= 0.5 x 12 x 1.2 = 7.2 W
D(INRUSH)
For 7.2 W of power loss, the thermal shut down time of the device must not be less than the ramp-up time tdVdT
to avoid the false trip at maximum operating temperature. From thermal shutdown limit graph Figure 56 at TA =
85°C, for 7.2 W of power the shutdown time is approximately 60 ms. So it is safe to use 1 ms as start-up time
without any load on output.
Considering the start-up with load 4.8 Ω, the additional power dissipation, when load is present during start up is
calculated, using Equation 27.
æ
ö
÷
÷
ø
1
12 x 12
÷
ç
P
=
x
= 5 W
÷
ç
D(LOAD)
ç
è
6
4.8
(27)
(28)
The total device power dissipation during start up is given by Equation 28.
P
=
7.2 + 5 = 12.2 W
( )
D(STARTUP)
From thermal shutdown limit graph at TA = 85°C, the thermal shutdown time for 12.2 W is close to 7.5 ms. It is
safe to have 30% margin to allow for variation of system parameters such as load, component tolerance, and
input voltage. So it is well within acceptable limits to use the 1 nF capacitor with start-up load of 4.8 Ω.
If there is a need to decrease the power loss during start-up, it can be done with increase of C(dVdT) capacitor.
To illustrate, choose C(dVdT) = 1.5 nF as an option and recalculate:
t
= 1.5ms
dvdt
(29)
æ
ç
ç
è
ö
÷
÷
÷
12
-6
I
=
100 x 10
(
x ç
ç
= 0.8 A
)
(INRUSH)
-3
÷
ø
1.5 x 10
(30)
(31)
P
= 0.5 x 12x 0.8 = 4.8 W
D(INRUSH)
æ
ö
æ
ö
÷
÷
1
6
12 x 12
ø
4.8
÷
÷
= 5 W
÷
ç
ç
P
=
x
÷
ç
ç
D(LOAD)
÷
÷
ç
è
ç
è
ø
(32)
(33)
P
= 4.8 + 5 = 9.8 W
D(STARTUP)
From thermal shutdown limit graph at TA = 85°C, the shutdown time for 10 W power dissipation is approximately
17 ms, which increases the margins further for shutdown time and ensures successful operation during start up
and steady state conditions.
The spreadsheet tool available on the web can be used for iterative calculations.
9.2.2.6 Programing the Power Good Set Point
As shown in Figure 51, R4 and R5 sets the required limit for PGOOD signal as needed for the downstream
converters. Considering a power good threshold of 11 V for this design, the values of R4 and R5 are calculated
using Equation 34.
æ
ö
÷
÷
÷
R
R
ç
4
5
V
= 0.99 x ç1 +
(PGTH)
ç
ç
è
÷
ø
(34)
It is recommended to have high values for these resistors to limit the current drawn from the output node.
Choosing a value of R4 = 475 kΩ, R5 = 47 kΩ provides V(PGTH) = 11 V.
9.2.2.7 Support Component Selections—R6, R7 and CIN
Reference to application schematics, R6 and R7 are required only if PGOOD and FLT are used; these resistors
serve as pull-ups for the open-drain output drivers. The current sunk by each of these pins must not exceed 10
mA (refer to the Absolute Maximum Ratings table). CIN is a bypass capacitor to help control transient voltages,
unit emissions, and local supply noise. Where acceptable, a value in the range of 0.001 μF to 0.1 μF is
recommended for C(IN)
.
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9.2.3 Application Curves
Figure 57. Hot-Plug Start-Up: Output Ramp Without Load
on Output
Figure 58. Hot-Plug Start-Up: Output Ramp With Start-Up
Load of 4.8 Ω
Figure 59. Overvoltage Shutdown
Figure 60. Overvoltage Recovery
IMON
IMON
Figure 61. Over Load: Step Change in Load from 12 Ω to
2 Ω and Back
Figure 62. Overload Condition: Auto Retry and Recovery -
TPS25940-Q1
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Figure 63. Hot Short: Fast Trip and Current Regulation
Figure 64. Hot Short: Auto-Retry and Recovery from Short
Circuit - TPS25940-Q1
Figure 65. Hot Plug-In with Short on Output: Auto-Retry -
TPS25940-Q1
Figure 66. Power Good Response During Turn-ON
Figure 67. Power Good Response During Turn-OFF
Figure 68. Hot Short: Latched - TPS25940L-Q1
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Figure 69. Hot Plug-in with Short on Output: Latched - TPS25940L-Q1
9.2.4 System Examples
9.2.4.1 VBUS Short-to-Battery, Short-to-Ground Protection of USB Port in Automotive Systems
The TPS25940x-Q1 eFuse offers robust protection for the 5 V Power rail of USB ports under faults conditions
like Short-to-Ground, Short-to-Battery and Overload.
5-V Power rail gets disconnected from the output within approximately 200 nsec during short circuit to Ground
fault.
The eFuse monitors the reverse voltage from IN to OUT and when it exceeds –66 mV, it stops the flow of
reverse current. This operation protects the 5-V power rail from Short-to-Battery faults.
Typical application schematic of TPS25940x-Q1 usage in USB port protection for automotive application is
shown in Figure 70.
OUT
5 V Power Bus
R1
IN
IN
OUT
USB Connector
*
CIN
COUT
42mΩ
R4
VBUS
D-
EN/UVLO
OVP
FLT
PGTH
PGOOD
D+
R2
R3
DEVSLP
dVdT
GND
IMON
ILIM
GND
CdVdT
RILIM
TPS25940-Q1
Figure 70. Automotive USB Hub-Port – VBUS Short to Battery, VBUS Short to GND Protection
Figure 71 and Figure 72 show the performance of TPS25940-Q1 under Short-to-Battery and Short-to-Ground
faults.
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Figure 71. VBUS Short-to-Battery Protection
V(IN) = 5 V C(OUT) = 4.7 µF
Figure 72. VBUS Short-to-Ground Protection
9.2.4.2 Power Failure Protection for Holdup Power
For certain applications, it is necessary to have hold-up circuit and capacitor bank to ensure that critical user data
is never lost during power-failure to the drive. The power-failure event could be because of the momentary loss
of power regulation (transient brown-out condition) or because of the loss of power when system is hot-plugged
out.
The TPS25940x-Q1 device continuously monitors the supply voltage at EN/UVLO pin and swiftly disconnects the
input bus from output when the voltage drops below a predefined threshold (power fail detection). Reverse
current flow from output side to input supply gets blocked when reverse voltage from IN to OUT exceeds –66
mV. In addition, it provides an instant warning signal (FLT) to the controller. Its swift true reverse blocking feature
reacts in 1 µs (typical) ensuring that the capacitor bank charge is retained. This helps the drive to have power for
longer time to harden data and reduces the capacitance required in the hold-up bank, saving system cost.
The typical application diagram of TPS25940x-Q1 usage for holdup power is shown in Figure 73.
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2.7 V to 18 V
R1
IN
OUT
COUT
IN
OUT
Hold Up
Capacitor Bank
CIN
(See Note A)
42 mꢀ
R6
R4
R7
EN/UVLO
OVP
FLT
PGOOD
PGTH
Power Good
Load Monitor
System Load
R2
R3
DEVSLP
IMON
ILIM
dVdT
GND
CdVdT
RIMON
RILIM
R5
TPS25940-Q1
A. CIN: Optional and only for noise suppression.
Figure 73. Holdup Capacitor Implementation Using TPS25940-Q1
The oscilloscope plots demonstrating the true reverse blocking, fast turn-off and FLT signal delay are shown in
Figure 74 through Figure 76.
V(IN) = 12 V
C(OUT) = 1500 µF
RL = 5.6 Ω
V(IN) = 12 V
C(OUT) = 1500 µF
RL = 5.6 Ω
Figure 74. Hot-Plug Out Condition
Figure 75. Hot-Plug Out Condition: FLT Delay
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V(IN) = 12 V
C(OUT) = 1500 µF
RL = 5.6 Ω
Figure 76. Standard Power Shutdown or Brownout Conditions
9.2.4.3 Overload Detection Using TPS25940x-Q1
The TPS25940x-Q1 device has enhanced features such as load current monitoring output IMON and an
integrated power good comparator for voltage monitoring. These two functional blocks can be utilized as per
circuit configuration shown in Figure 77, to FLAG the overload event.
OUT
IN
*
CIN
IN
R1
R2
42mꢀ
0.1µF
EN/UVLO
OVP
FLT
PGOOD
PGTH
OL_Status
VIMON
DEVSLP
dVdT
IMON
ILIM
GND
R3
RIMON
RILIM
CdVdT
TPS25940-Q1
*Optional & only for noise suppression
Figure 77. Circuit Configuration for Overload Detection Using TPS25940-Q1
The output voltage at IMON terminal VIMON can be used as a means of monitoring current flow through the
system and its value can be calculated from Equation 6.
The power good comparator of TPS25940x-Q1 has an internal reference of VPGTHR = 0.99 V at the negative
terminal and the positive terminal PGTH can be utilized for monitoring voltage of any specific rail. As shown in
the Figure 77, the output voltage at IMON terminal (VIMON) is fed to the positive terminal PGTH (VPGTH) of the
comparator. When the PGTH pin voltage (VPGTH = VIMON) is higher than the internal reference VPGTHR, the open-
drain comparator output PGOOD asserts HIGH to indicate overload event.
For example, to detect overcurrent event at load current IOUT of 300 mA, the value of RIMON can be calculated
using Equation 35.
VIMON = VPGTHR = IOUT ×GAINIMON +IIMON_OS ×R
IMON
(35)
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VPGTHR
0.99 V
RIMON
=
=
= 60.36 kꢀ
ꢁA
≈
’
I
OUT ×GAINIMON +IIMON_OS
(
)
300 mA ×52
+0.8 ꢁA
∆
«
÷
◊
A
(36)
A close value of 61.9 kΩ is chosen for RIMON
.
Figure 78 shows the overload flag status when the load is changed from 150 mA to 600 mA and back. As seen
in the Figure 78, the overload status (OL_Status) becomes active HIGH when the load current crosses 300 mA.
Figure 78. Overload Flag Status for Change in Load from 150 mA to 600 mA and Back
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10 Power Supply Recommendations
The TPS25940x-Q1 device is designed for supply voltage range of 2.7 V ≤ VIN ≤ 18 V. If the input supply is
located more than a few inches from the device an input ceramic bypass capacitor higher than 0.1 μF is
recommended. Power supply must be rated higher than the current limit set to avoid voltage droops during over
current and short-circuit conditions.
10.1 Transient Protection
In case of short circuit and over load current limit, when the device interrupts current flow, input inductance
generates a positive voltage spike on the input and output inductance generates a negative voltage spike on the
output. The peak amplitude of voltage spikes (transients) is dependent on value of inductance in series to the
input or output of the device. In case of sudden Output short-to-Battery faults with a long external cable, the
cable inductance and output capacitance generates over voltage spike at the output. Such transients can exceed
the Absolute Maximum Ratings of the device if steps are not taken to address the issue.
Typical methods for addressing transients include
•
•
•
Minimizing lead length and inductance into and out of the device
Using large PCB GND plane
A 18-V TVS across output to GND to absorb positive spikes. Schottky diode across the output to absorb
negative spikes
•
A low value ceramic capacitor (C(IN) = 0.001 µF to 0.1 µF) to absorb the energy and dampen the transients.
The approximate value of input capacitance can be estimated with Equation 37.
L
(IN)
V
= V
(IN)
+ I x
(LOAD)
SPIKE(Absolute)
C
(IN)
where
•
•
•
•
V(IN) is the nominal supply voltage
I(LOAD) is the load current,
L(IN) equals the effective inductance seen looking into the source
C(IN) is the capacitance present at the input
(37)
Some applications may require the addition of a Transient Voltage Suppressor (TVS) to prevent transients from
exceeding the Absolute Maximum Ratings of the device.
The circuit implementation with optional protection components (a ceramic capacitor, TVS and schottky diode) is
shown in Figure 79.
IN
2.7 V to 18 V
OUT
IN
OUT
COUT
CIN
(See Note A)
R1
R2
42 mꢀ
R6
R7
R4
EN/UVLO
OVP
FLT
PGOOD
PGTH
DEVSLP
IMON
ILIM
dVdT
GND
R3
CdVdT
RILIM
R5 RIMON
TPS25940-Q1
A. Optional components needed for suppression of transients
Figure 79. Circuit Implementation with Optional Protection Components
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10.2 Output Short-Circuit Measurements
It is difficult to obtain repeatable and similar short-circuit testing results. Source bypassing, input leads, circuit
layout and component selection, output shorting method, relative location of the short, and instrumentation all
contribute to variation in results. The actual short itself exhibits a certain degree of randomness as it
microscopically bounces and arcs. Care in configuration and methods must be used to obtain realistic results. Do
not expect to see waveforms exactly like those in the data sheet; every setup differs.
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11 Layout
11.1 Layout Guidelines
•
For all applications, a 0.1-uF or greater ceramic decoupling capacitor is recommended between IN terminal
and GND. For hot-plug applications, where input power path inductance is negligible, this capacitor can be
eliminated/minimized.
•
The optimum placement of decoupling capacitor is closest to the IN and GND terminals of the device. Care
must be taken to minimize the loop area formed by the bypass-capacitor connection, the IN terminal, and the
GND terminal of the IC. See Figure 80 for a PCB layout example.
•
•
•
•
High current carrying power path connections must be as short as possible and must be sized to carry at
least twice the full-load current.
Low current signal ground (SGND), which is the reference ground for the device must be a copper plane or
island.
Locate all TPS25940x-Q1 support components: R(ILIM), CdVdT, R(IMON), and resistors for UVLO and OVP, close
to their connection pin. Connect the other end of the component to the SGND with shortest trace length.
The trace routing for the RILIM and R(IMON) components to the device must be as short as possible to reduce
parasitic effects on the current limit and current monitoring accuracy. These traces must not have any
coupling to switching signals on the board.
•
•
The SGND plane must be connected to high current ground (main power ground) at a single point, that is at
the negative terminal of input capacitor.
Protection devices such as TVS, snubbers, capacitors, or diodes must be placed physically close to the
device they are intended to protect, and routed with short traces to reduce inductance. For example, a
protection Schottky diode is recommended to address negative transients due to switching of inductive loads,
and it must be physically close to the OUT pins.
•
Thermal Considerations: When properly mounted the PowerPAD™ package provides significantly greater
cooling ability than an ordinary package. To operate at rated power, the PowerPAD must be soldered directly
to the board GND plane directly under the device. The PowerPAD is at GND potential and can be connected
using multiple vias to inner layer GND. Other planes, such as the bottom side of the circuit board can be used
to increase heat sinking in higher current applications. See the Technical Briefs, PowerPad™ Thermally
Enhanced Package, SLMA002) and PowerPAD™ Made Easy, SLMA004) for more information on using this
PowerPAD™ package.
•
•
The thermal via land pattern specific to TPS25940x-Q1 can be downloaded from the TPS25940 device
webpage.
Obtaining acceptable performance with alternate layout schemes is possible; however this layout has been
shown to produce good results and is intended as a guideline.
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11.2 Layout Example
Top layer
Top layer signal ground plane
Bottom layer signal ground plane
Via to signal ground plane
Power Ground
High
(See Note A)
Frequency
Bypass
Capacitor
Input
Output
VI
VO
11
12
6
5
IN
IN
OUT
OUT
OUT
IN
13
4
3
EN 14
PGTH
PGOOD
DEVSLP
2
1
OVP
15
16
GND
Signal
Ground
Bottom
layer
Signal Ground
Top Layer
A. Optional: Needed only to suppress the transients caused by inductive load switching
Figure 80. Board Layout
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12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documetation see the following:
•
•
High-Efficiency Backup Power Supply, SLVA676
TPS25940 Evaluation Module User's Guide, SLVUA44
12.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.3 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
30-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS259401AQRVCRQ1
TPS25940AQRVCRQ1
TPS25940AQRVCTQ1
TPS25940LQRVCRQ1
ACTIVE
ACTIVE
ACTIVE
ACTIVE
WQFN
WQFN
WQFN
WQFN
RVC
RVC
RVC
RVC
20
20
20
20
3000 RoHS & Green
3000 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 125
-40 to 125
-40 to 125
-40 to 125
9401AQ
NIPDAU
NIPDAU
NIPDAU
2594AQ
2594AQ
T594LQ
250
RoHS & Green
3000 RoHS & Green
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
30-Dec-2020
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TPS25940-Q1 :
Catalog: TPS25940
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
18-Sep-2018
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS25940AQRVCRQ1
TPS25940AQRVCTQ1
TPS25940LQRVCRQ1
WQFN
WQFN
WQFN
RVC
RVC
RVC
20
20
20
3000
250
330.0
180.0
330.0
12.4
12.4
12.4
3.3
3.3
3.3
4.3
4.3
4.3
1.1
1.1
1.1
8.0
8.0
8.0
12.0
12.0
12.0
Q1
Q1
Q1
3000
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
18-Sep-2018
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPS25940AQRVCRQ1
TPS25940AQRVCTQ1
TPS25940LQRVCRQ1
WQFN
WQFN
WQFN
RVC
RVC
RVC
20
20
20
3000
250
367.0
210.0
367.0
367.0
185.0
367.0
35.0
35.0
35.0
3000
Pack Materials-Page 2
PACKAGE OUTLINE
RVC0020A
WQFN - 0.8 mm max height
S
C
A
L
E
3
.
7
0
0
PLASTIC QUAD FLATPACK - NO LEAD
3.1
2.9
A
B
PIN 1 INDEX AREA
0.45
0.35
4.1
3.9
0.25
0.15
DETAIL
OPTIONAL TERMINAL
TYPICAL
C
0.8 MAX
SEATING PLANE
0.08
0.05
0.00
2X 1.5
SYMM
(0.2) TYP
EXPOSED
THERMAL PAD
7
10
16X 0.5
11
6
2X
SYMM
21
2.5
2.6 0.1
SEE TERMINAL
DETAIL
1
16
0.25
20X
0.15
20
17
PIN 1 ID
(OPTIONAL)
0.1
C A B
1.6 0.1
0.05
0.45
0.35
20X
4219150/B 03/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.
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EXAMPLE BOARD LAYOUT
RVC0020A
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(1.6)
SYMM
(R0.05)
TYP
17
20
20X (0.6)
1
16
20X (0.2)
(1)
TYP
21
(3.8)
(2.6)
SYMM
16X (0.5)
11
6
(
0.2) TYP
VIA
7
10
(1 TYP)
(2.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:18X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
EXPOSED METAL
EXPOSED METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4219150/B 03/2017
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
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EXAMPLE STENCIL DESIGN
RVC0020A
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
2X (1.47)
20
17
20X (0.6)
1
21
16
20X (0.2)
(R0.05) TYP
SYMM
2X
(1.15)
(3.8)
(0.675)
TYP
16X (0.5)
11
6
METAL
TYP
7
10
SYMM
(2.8)
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
EXPOSED PAD X
81% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:20X
4219150/B 03/2017
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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