TPS259470ARPW [TI]
TPS25947xx, 2.7 - 23 V, 5.5 A, 28 mΩ True Reverse Current Blocking eFuse with Input Reverse Polarity Protection;
| 型号： | TPS259470ARPW |
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TEXAS INSTRUMENTS |
| 描述： | TPS25947xx, 2.7 - 23 V, 5.5 A, 28 mΩ True Reverse Current Blocking eFuse with Input Reverse Polarity Protection |
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TPS25947
SLVSFC9 – OCTOBER 2020
TPS25947xx, 2.7 - 23 V, 5.5 A, 28 mΩ True Reverse Current Blocking eFuse with Input
Reverse Polarity Protection
•
Patient Monitors
1 Features
3 Description
•
•
•
•
Wide operating input voltage range: 2.7 V to 23 V
28-V absolute maximum
Withstands negative voltages up to (VOUT – 19 V)
Integrated back-to-back FETs with low On-
Resistance: RON = 28 mΩ (typ)
The TPS25947xx family of eFuses is a highly
integrated circuit protection and power management
solution in a small package. The devices provide
multiple protection modes using very few external
components and are a robust defense against
overloads, short-circuits, voltage surges, reverse
polarity and excessive inrush current. With integrated
back-to-back FETs, reverse current flow from output
to input is blocked at all times, making the device well
suited for power MUX/ORing applications as well as
systems which need load side energy hold up storage
in case input power supply fails.
•
•
Ideal diode operation with true reverse current
blocking
Fast overvoltage protection
– Overvoltage clamp (OVC) with pin-selectable
threshold (3.8 V, 5.7 V, 13.8 V) with 5-μs (typ)
response time OR
– Adjustable overvoltage lockout (OVLO) with
1.2-μs (typ) response time
Output current limit level can be set with a single
external resistor. It is also possible to get an accurate
sense of the output load current by measuring the
voltage drop across the current limit resistor.
•
Overcurrent protection with load current monitor
output (ILM)
– Active current limit OR circuit breaker options
– Adjustable threshold with ±10% accuracy over
ILIM = 0.5 A to 6 A
Applications
with
particular
inrush
current
requirements can set the output slew rate with a
single external capacitor. Loads are protected from
input overvoltage conditions, either by clamping the
output to a safe fixed maximum voltage (pin
selectable), or by cutting off the output if input
exceeds an adjustable overvoltage threshold.
– Adjustable transient blanking timer
– Output load current monitor accuracy: ±15%
over IOUT = 0.5 A to 5.5 A
Fast-trip response for short-circuit protection
– 500-ns (typ) response time
– Adjustable (2 x ILIM) and fixed thresholds
Active High Enable input with adjustable
undervoltage lockout threshold (UVLO)
Adjustable output slew rate control (dVdt)
Overtemperature protection
•
•
The devices are available in a 2-mm x 2-mm, 10-pin
HotRod QFN package for improved thermal
performance and reduced system footprint.
•
•
•
The devices are characterized for operation over a
junction temperature range of –40°C to +125°C.
Digital outputs
– Priority power MUX control (AUXOFF) and
Fault indication (FLT) OR
Device Information
PART NUMBER
PACKAGE(1)
BODY SIZE (NOM)
– Power Good indication (PG) with adjustable
threshold (PGTH)
UL 2367 recognition (pending)
TPS25947xxRPW
QFN (10)
2 mm x 2 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
•
•
•
IEC 62368 CB certification (pending)
Small footprint: QFN 2 mm x 2 mm, 0.45-mm pitch
VOUT
VIN
= 2.7 to 23 V
IN
OUT
VLOGIC
COUT
2 Applications
EN/UVLO
TPS259470x
AUXOFF
FLT
•
•
•
•
•
•
Power MUX/ORing
Adapter Input Protection
USB PD port protection
Server/PC Motherboard/Add-on cards
Enterprise storage - RAID/HBA/SAN/eSSD
Monitors/Docks
OVLO
ITIMER dVdt
GND
ILM
RILM
CITIMER
CDVDT
Figure 3-1. Simplified Schematic
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. ADVANCE INFORMATION for preproduction products; subject to change
without notice.
TPS25947
SLVSFC9 – OCTOBER 2020
www.ti.com
Table of Contents
1 Features............................................................................1
2 Applications.....................................................................1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Device Comparison Table...............................................3
6 Pin Configuration and Functions...................................4
7 Specifications.................................................................. 5
7.1 Absolute Maximum Ratings ....................................... 5
7.2 ESD Ratings .............................................................. 5
7.3 Recommended Operating Conditions ........................6
7.4 Thermal Information ...................................................6
7.5 Electrical Characteristics ............................................7
7.6 Timing Requirements .................................................9
7.7 Switching Characteristics .........................................10
7.8 Typical Characteristics.............................................. 11
8 Detailed Description......................................................14
8.1 Overview...................................................................14
8.2 Functional Block Diagram.........................................15
8.3 Feature Description...................................................18
8.4 Device Functional Modes..........................................31
9 Application and Implementation..................................32
9.1 Application Information............................................. 32
9.2 Single Device, Self-Controlled.................................. 32
9.3 Active ORing.............................................................35
9.4 Priority Power MUXing..............................................37
9.5 USB PD Port Protection............................................44
9.6 Parallel Operation..................................................... 46
9.7 Application Limitations.............................................. 49
10 Power Supply Recommendations..............................50
10.1 Transient Protection................................................50
10.2 Output Short-Circuit Measurements....................... 51
11 Layout...........................................................................52
11.1 Layout Guidelines................................................... 52
11.2 Layout Example...................................................... 53
12 Device and Documentation Support..........................55
12.1 Documentation Support.......................................... 55
12.2 Receiving Notification of Documentation Updates..55
12.3 Support Resources................................................. 55
12.4 Trademarks.............................................................55
12.5 Electrostatic Discharge Caution..............................55
12.6 Glossary..................................................................55
13 Mechanical, Packaging, and Orderable
Information.................................................................... 56
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
DATE
REVISION
NOTES
October 2020
*
Initial Release
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5 Device Comparison Table
Table 5-1. Device Comparison
Overvoltage
Part Number
Overcurrent
AUXOFF or PG
Response
FLT or PGTH
Response to Fault
Response
TPS259470ARPW
Adjustable OVLO
TPS259470LRPW
Auto-Retry
Latch-Off
Auto-Retry
Latch-Off
Auto-Retry
Latch-Off
AUXOFF
FLT
Active Current Limit
TPS259472ARPW
Pin Selectable OVC
(3.8 V/5.7 V/13.8 V)
TPS259472LRPW
PG
PGTH
TPS259474ARPW
Adjustable OVLO
TPS259474LRPW
Circuit Breaker
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6 Pin Configuration and Functions
VIN VOUT
EN/UVLO
ITIMER
OVLO/
ILM
OVCSEL
PG/
GND
DVDT
AUXOFF
PGTH/
FLT
Figure 6-1. TPS25947xx RPW Package 10-Pin QFN Top View
Table 6-1. Pin Functions
PIN
TYPE
DESCRIPTION
NAME
NO.
Active High Enable for the device. A Resistor Divider on this pin from input supply to GND
can be used to adjust the Undervoltage Lockout threshold. Do not leave floating. Refer to
Section 8.3.2 for details.
Analog
Input
EN/UVLO
1
TPS259470x/4x: A Resistor Divider on this pin from supply to GND can be used to adjust
the Overvoltage Lockout threshold. This pin can also be used as an Active Low Enable for
the device. Do not leave floating. Refer to Section 8.3.3 for details.
Analog
Input
OVLO
OVCSEL
PG
2
Analog
Input
TPS259472x: Overvoltage Clamp Threshold Select Pin. Refer to Section 8.3.4 for details.
TPS259472x/4x: Power Good indication. This is an Open Drain signal which is asserted
High when the internal powerpath is fully turned ON and PGTH input exceeds a certain
threshold. Refer to Section 8.3.11 for more details.
Digital
Output
TPS259470x: Auxiliary channel control signal. This is an Open Drain signal which is
asserted High when the input supply is valid and channel has completed inrush sequence.
This can be used to enable/disable the auxiliary supply eFuse to facilitate smooth
switchover in a Priority power MUXing configuration. Refer to Section 8.3.10 for more
details.
3
4
Digital
Output
AUXOFF
Digital TPS259470x: Active low Fault event indicator. This is an Open Drain signal which will be
Output pulled low when a fault is detected. Refer to Section 8.3.9 for more details.
FLT
Analog
Input
PGTH
TPS259472x/4x: Power Good Threshold. Refer to Section 8.3.11 for more details.
IN
5
6
Power Power Input.
Power Power Output.
OUT
Analog A capacitor from this pin to GND sets the output turn on slew rate. Leave this pin floating
Output for the fastest turn on slew rate. Refer to Section 8.3.5.1 for details.
DVDT
GND
7
8
Ground This is the ground reference for all internal circuits and must be connected to system GND.
This is a dual function pin used to limit and monitor the output current. An external resistor
Analog from this pin to GND sets the output current limit threshold during start-up as well as
Output steady state. The pin voltage can also be used as analog output load current monitor
signal. Do not leave floating. Refer to Section 8.3.5.2 or Section 8.3.5.3 for more details.
ILM
9
A capacitor from this pin to GND sets the overcurrent blanking interval during which the
output current can temporarily exceed set current limit (but lower than fast-trip threshold)
Analog
ITIMER
10
before the device overcurrent response takes action. Leave this pin open for fastest
Output
response to overcurrent events. Refer to Section 8.3.5.2 or Section 8.3.5.3 for more
details.
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
Parameter
Pin
MIN
MAX UNIT
Maximum Input Voltage Range, -40 ℃ ≤ TJ ≤ 125 ℃
Maximum Input Voltage Range, -10 ℃ ≤ TJ ≤ 125 ℃
Maximum Output Voltage Range, -40 ℃ ≤ TJ ≤ 125 ℃
Maximum Output Voltage Range, -10 ℃ ≤ TJ ≤ 125 ℃
Minimum Output Voltage Pulse (< 1 µs)
max(-19, VOUT - 21)
28
28
V
V
VIN
IN
max(-19, VOUT - 22)
–0.3
–0.3
–0.8
–0.3
min (28, VIN + 21)
min (28, VIN + 22)
VOUT
OUT
OUT
VOUT,PLS
VEN/UVLO Maximum Enable Pin Voltage Range (2)
EN/UVLO
OVLO
6.5
6.5
V
V
Maximum OVLO Pin Voltage Range (TPS259470x/4x)
VOVLO
–0.3
(2)
VOVCSEL
VdVdT
Maximum OVCSEL Pin Voltage Range (TPS259472x)
Maximum dVdT Pin Voltage Range
OVCSEL
dVdt
Internally Limited
V
V
V
Internally Limited
Internally Limited
VITIMER
Maximum ITIMER Pin Voltage Range
ITIMER
Maximum PGTH Pin Voltage Range (TPS259472x/4x)
VPGTH
PGTH
–0.3
6.5
V
(2)
VAUXOFF
VPG
Maximum AUXOFF Pin Voltage Range (TPS259470x)
Maximum PG Pin Voltage Range (TPS259472x/4x)
Maximum FLT Pin Voltage Range (TPS259470x) (2)
Maximum ILM Pin Voltage Range
AUXOFF
PG
–0.3
6.5
6.5
6.5
V
V
–0.3
VFLTB
VILM
FLT
–0.3
V
ILM
Internally Limited
Internally Limited
Internally Limited
V
IMAX
Maximum Continuous Switch Current
Junction temperature
IN to OUT
A
TJ
°C
°C
°C
TLEAD
TSTG
Maximum Lead Temperature
300
150
Storage temperature
–65
(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2) If this pin has a pull-up up to VIN, it is recommended to use a resistance of 350 kΩ or higher to limit the current under conditions where
IN can be exposed to reverse polarity.
7.2 ESD Ratings
VALUE
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001,
all pins(1)
±2000
V(ESD)
Electrostatic discharge
V
Charged device model (CDM), per JEDEC specification
JESD22-C101, all pins(2)
±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process precautions.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
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MAX UNIT
SLVSFC9 – OCTOBER 2020
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
Parameter
Input Voltage Range
Output Voltage Range
Pin
MIN
VIN
IN
2.7
23 (1)
V
V
V
V
V
V
V
V
V
V
Ω
A
°C
VOUT
OUT
min (23, VIN + 20)
VEN/UVLO Enable Pin Voltage Range
EN/UVLO
OVLO
dVdt
5 (3)
VOVLO
VdVdT
VFLTB
VPGTH
VAUXOFF
VPG
OVLO Pin Voltage Range (TPS259470x/4x)
0.5
1.5
dVdT Capacitor Voltage Rating
VIN + 5 V (2)
FLT Pin Voltage Range (TPS259470x)
PGTH Pin Voltage Range (TPS259472x/4x)
AUXOFF Pin Voltage Range (TPS259470x)
PG Pin Voltage Range (TPS259472x/4x)
ITIMER Pin Capacitor Voltage Rating
ILM Pin Resistance
FLT
5 (4)
5 (4)
5 (4)
5 (4)
PGTH
AUXOFF
PG
VITIMER
RILM
ITIMER
ILM
4
549
6650
5.5
IMAX
Continuous Switch Current, , TJ ≤ 125 ℃
Junction temperature
IN to OUT
TJ
–40
125
(1) For TPS259472x variants, the input operating voltage should be limited to the selected Output Voltage Clamp threshold as listed in the
Electrical Characteristics section
(2) In a PowerMUX/ORing scenario with unequal supplies, the dVdt capacitor rating for each device should be chosen based on the
highest of the 2 rails.
(3) For supply voltages below 5V, it is okay to pull up the EN pin to IN directly. For supply voltages greater than 5V or systems which can
be exposed to reverse polarity on input supply, it is recommended to use a pull-up resistor with a minimum value of 350 kΩ.
(4) For systems which can be exposed to reverse polarity on input supply, if this pin is referred to input supply, it is recommended to use a
pull-up resistor with a minimum value of 350 kΩ to limit the current through the pin.
7.4 Thermal Information
TPS25947
THERMAL METRIC (1)
RPW (QFN)
10 PINS
41.7 (2)
74.5 (3)
1
UNIT
°C/W
°C/W
°C/W
°C/W
°C/W
RθJA
ΨJT
ΨJB
Junction-to-ambient thermal resistance
Junction-to-top characterization parameter
Junction-to-board characterization parameter
20 (2)
27.6 (3)
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
(2) Based on simulations conducted with the device mounted on a custom 4-layer PCB (2s2p) with 8 thermal vias under device
(3) Based on simulations conducted with the device mounted on a JEDEC 4-layer PCB (2s2p) with no thermal vias under device
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7.5 Electrical Characteristics
(Test conditions unless otherwise noted) –40°C ≤ TJ ≤ 125°C, VIN = 12 V, OUT = Open, VEN/UVLO = 2 V, VOVLO
0 V for TPS259470x/4x, OVCSEL = 390 kΩ to GND for TPS259472x, RILM = 549 Ω , dVdT = Open, ITIMER =
=
Open, AUXOFF = Open for TPS259470x, FLT = Open for TPS259470x, PGTH = Open for TPS259472x/4x, PG
= Open for TPS259472x/4x. All voltages referenced to GND.
Test
Parameter
Description
MIN
TYP
MAX
UNITS
INPUT SUPPLY (IN)
VUVP(R)
VUVP(F)
IN Supply UVP Rising threshold
IN Supply UVP Falling threshold
2.53
2.42
428
426
429
196
445
74
V
V
IN Supply Quiescent Current (TPS259470x)
IN Supply Quiescent Current (TPS259472x)
IN Supply Quiescent Current (TPS259474x)
IN Supply Quiescent Current during RCB, VOUT > VIN
IN Supply Current during OVC (TPS259472x)
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
IQ(ON)
IQ(OFF)
IN Supply OFF State Current (VSD < VEN < VUVLO
IN Supply Shutdown Current (VEN < VSD
)
ISD
)
4.5
IQ(OVLO)
IOUTLKG(ON)
IINLKG(IRPP)
IN Supply OFF Current (OVLO condition), VOUT > VIN
OUT Leakage Current during RCB, VOUT > VIN
IN Supply Leakage Current (VIN = -19 V, VOUT = 0 V)
191
246
-3.7
0
IOUTLKG(IRPP) OUT Leakage Current (VIN = -19 V, VOUT = 0 V)
IOUTLKG(OVLO) OUT Leakage Current (OVLO condition), VOUT > VIN
ON RESISTANCE (IN - OUT)
319
RON
ON Resistance, IOUT = 3 A
28
mΩ
ENABLE/UNDERVOLTAGE LOCKOUT (EN/UVLO)
VUVLO(R)
VUVLO(F)
VSD(R)
UVLO Rising threshold
1.2
1.1
V
V
UVLO Falling threshold
EN/UVLO Rising Threshold for lowest shutdown current
EN/UVLO Falling Threshold for lowest shutdown current
EN leakage current
0.85
0.75
V
VSD(F)
V
IENLKG
0.1
0.1
µA
OVERVOLTAGE LOCKOUT (OVLO) - TPS259470x/4x
VOV(R)
VOV(F)
IOVLKG
OVLO Rising threshold
1.2
1.1
V
V
OVLO Falling threshold
OVLO pin leakage current, 0.5 V < VOVLO < 1.5 V
-0.1
µA
OUTPUT VOLTAGE CLAMP (OUT) - TPS259472x
Overvoltage Clamp Threshold, OVCSEL = GND
3.87
5.73
V
V
V
V
V
V
VOVC
Overvoltage Clamp Threshold, OVCSEL = Open
Overvoltage Clamp Threshold, OVCSEL = 390 kΩ to GND
Output Voltage During Clamping, OVCSEL = GND
Output Voltage During Clamping, OVCSEL = Open
Output Voltage During Clamping, OVCSEL = 390 kΩ to GND
13.84
3.72
VCLAMP
5.57
13.66
OVERCURRENT PROTECTION (OUT)
Current Limit Threshold, RILM = 6.65 kΩ
0.5
1
A
A
A
A
A
Current Limit Threshold, RILM = 3.32 kΩ
Current Limit Threshold, RILM = 1.65 kΩ
Current Limit Threshold, RILM = 750 Ω
Current Limit Threshold, RILM = 549 Ω
ILIM
2
4.44
6
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(Test conditions unless otherwise noted) –40°C ≤ TJ ≤ 125°C, VIN = 12 V, OUT = Open, VEN/UVLO = 2 V, VOVLO
0 V for TPS259470x/4x, OVCSEL = 390 kΩ to GND for TPS259472x, RILM = 549 Ω , dVdT = Open, ITIMER =
=
Open, AUXOFF = Open for TPS259470x, FLT = Open for TPS259470x, PGTH = Open for TPS259472x/4x, PG
= Open for TPS259472x/4x. All voltages referenced to GND.
Test
Parameter
Description
MIN
TYP
0.1
MAX
UNITS
Circuit Breaker Threshold, ILM Pin Open (Single point
failure)
A
A
IFLT
Circuit Breaker Threshold, ILM Pin Short to GND (Single
point failure)
1.5
ISCGain
VDSComp
VFB
Scalable Fast Trip Threshold (ISC) : ILIM Ratio
VDS comparator threshold for Fixed Fast Trip
VOUT threshold to exit Current Limit Foldback
200
350
1.9
%
mV
V
OVERCURRENT FAULT TIMER (ITIMER)
IITIMER
RITIMER
VINT
ITIMER pin internal discharge current, IOUT > ILIM
1.8
15.4
2.57
1.5
µA
kΩ
V
ITIMER pin internal pull-up resistance
ITIMER pin internal pull-up voltage
ITIMER discharge voltage
ΔVITIMER
V
OUTPUT LOAD CURRENT MONITOR (ILM)
Current Monitor Gain (IMON : IOUT), IOUT = 0.5 A to 5.5 A, IOUT
< ILIM
REVERSE CURRENT BLOCKING (IN - OUT)
GIMON
182
µA/A
VFWD
VIN - VOUT Forward regulation voltage, IOUT = 10 mA
16.8
29.5
mV
mV
VOUT - VIN threshold for fast BFET turn off (enter reverse
current blocking)
VREVTH
VIN - VOUT threshold for fast BFET turn on (exit reverse
current blocking)
VFWDTH
IREVLKG
105.3
0.5
mV
µA
Reverse leakage current
POWER GOOD INDICATION (PG) - TPS259472x/4x or AUXILIARY CHANNEL CONTROL (AUXOFF) - TPS259470x
PG/AUXOFF pin low voltage VIN < VUVP(F), VEN < VSD, Weak
pull-up
0.67
V
V
VPGD
PG/AUXOFF pin low voltage VIN < VUVP(F), VEN
VSD, Strong pull-up
<
0.78
PG/AUXOFF pin low voltage VIN > VUVP(R)
0
V
IPGLKG
PG/AUXOFF Pin leakage current, PG/AUXOFF asserted
0.9
µA
POWERGOOD THRESHOLD (PGTH) - TPS259472x/4x
VPGTH(R)
VPGTH(F)
IPGTHLKG
PGTH Rising threshold
PGTH Falling threshold
PGTH leakage current
1.2
1.1
V
V
-1
-1
1
1
µA
FAULT INDICATION (FLT) - TPS259470x
IFLTLKG
RFLT
FLT leakage current
µA
Ω
FLT Internal Pull down resistance
13
OVERTEMPERATURE PROTECTION (OTP)
TSD
Thermal Shutdown Rising Threshold
Thermal Shutdown Hysteresis
154
10
°C
°C
TSDHYS
DVDT
IdVdt
dVdt Pin Charging Current
2.2
µA
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7.6 Timing Requirements
PARAMETER
TEST CONDITIONS
VOVLO > VOV(R) to VOUT
VIN > VOVC to VOUT
MIN TYP MAX
UNIT
Overvoltage lock-out response time
(TPS259470x/4x)
tOVLO
↓
1.2
µs
Overvoltage clamp response time
(TPS259472x)
tOVC
tCB
↓
5
2
µs
µs
µs
Circuit breaker response time (TPS259474x) IOUT > 1.2 x ILIM & ITIMER expired to IOUT
↓
IOUT > 1.2 x ILIM & ITIMER expired to IOUT
Current limit response time (TPS259470x/2x)
tLIM
336
settling to within 5 % of ILIM
tSC
tFT
Scalable fast-trip response time
IOUT > 3 x ILIM to IOUT
IOUT > IFT to IOUT
↓
500
500
110
ns
ns
Fixed fast-trip response time
↓
tRST
Auto-Retry Interval after fault (TPS25947xA)
ms
OVLO fast recovery response
time (TPS259470x)
tSWOV
tSWRCB
tRCB
VOVLO < VOV(F) to VOUT
↑
90
30
1
µs
µs
µs
Reverse Current Blocking recovery time
(VIN - VOUT) > VFWDTH to VOUT
↑
Reverse Current Blocking comparator
response time
(VOUT - VIN) > 1.3 x VREVTH to BFET OFF
tPGA
tPGD
PG Assertion de-glitch (TPS259472x/4x)
PG De-assertion de-glitch (TPS259472x/4x)
12
12
µs
µs
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7.7 Switching Characteristics
The output rising slew rate is internally controlled and constant across the entire operating voltage range to
ensure the turn on timing is not affected by the load conditions. The rising slew rate can be adjusted by adding
capacitance from the dVdt pin to ground. As CdVdt is increased it will slow the rising slew rate (SR). See Slew
Rate and Inrush Current Control (dVdt) section for more details. The Turn-Off Delay and Fall Time, however, are
dependent on the RC time constant of the load capacitance (COUT) and Load Resistance (RL). The Switching
Characteristics are only valid for the power-up sequence where the supply is available in steady state condition
and the load voltage is completely discharged before the device is enabled.Typical Values are taken at TJ =
25°C unless specifically noted otherwise. RL = 100 Ω, COUT = 1 µF
CdVdt
3300 pF
=
PARAMETER
VIN
CdVdt = Open CdVdt = 1800 pF
UNIT
2.7 V
12 V
23 V
2.7 V
12 V
23 V
2.7 V
12 V
23 V
2.7 V
12 V
23 V
2.7 V
12 V
23 V
12.14
28.1
44.78
0.09
0.1
0.87
1.09
1.25
0.6
0.5
SRON
tD,ON
tR
Output Rising slew rate
0.61
V/ms
0.71
0.97
Turn on delay
Rise time
1.32
1.99
2.51
8.1
2.35
ms
ms
ms
µs
0.11
3.69
0.17
0.35
0.40
0.27
0.45
0.50
64.44
25.32
23.02
4.33
15.37
25.89
5.31
14.4
3.11
10.08
16.41
64.44
25.32
23.02
tON
Turn on time
Turn off delay
17.72
29.57
64.44
25.32
23.02
tD,OFF
VEN/UVLO
EN/UVLO
VUVLO(R)
VUVLO(F)
0
tON
SRON
tD,OFF
90%
VIN
OUT
10%
0V
tR
tF
tD,ON
Time
Figure 7-1. TPS25947xx switching times
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7.8 Typical Characteristics
VEN/UVLO = 3.3 V, COUT = 22 μF, CdVdt = Open, VIN ramped up
to 12 V
VIN = 12 V, COUT = 22 μF, CdVdt = Open, VEN/UVLO stepped up
to 3.3 V
Figure 7-3. Start Up with Supply
Figure 7-2. Start Up with Enable
VIN = 12 V, COUT = 470 μF, CdVdt = 3300 pF, VEN/UVLO stepped
up to 3.3 V
VIN = 12 V, COUT = 470 μF, ROUT = 5 Ω, CdVdt = 3300 pF, VEN/
UVLO stepped up to 3.3 V
Figure 7-4. Inrush Current with Capacitive Load
Figure 7-5. Inrush Current with Resistive and
Capacitive Load
COUT = 220 μF, ROUT = 100 Ω, VIN ramped down from 0 V to -
19 V and then ramped up to 0 V
COUT = 220 μF, ROUT = 100 Ω, VIN stepped down from 0 V to -
19 V
Figure 7-7. Input Reverse Polarity Protection -
Slow Ramp
Figure 7-6. Input Reverse Polarity Protection - Fast
Ramp
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ROVCSEL = GND, COUT = 10 μF, IOUT = 100 mA, VIN ramped up
from 3.3 V to 5.8 V
COUT = 10 μF, ROUT = 100 Ω, VIN ramped up from 10 V to 13 V
Figure 7-8. Overvoltage Lockout Response -
TPS259470x/4x
Figure 7-9. Overvoltage Clamp Response -
TPS259472x
ROVCSEL = Open, COUT = 10 μF, IOUT = 100 mA, VIN ramped up
from 5 V to 7.6 V
ROVCSEL = 390 kΩ, COUT = 10 μF, IOUT = 100 mA, VIN ramped
up from 12 V to 15.8 V
Figure 7-10. Overvoltage Clamp Response -
TPS259472x
Figure 7-11. Overvoltage Clamp Response -
TPS259472x
A.
VIN = 12 V, CITIMER = 470 nF, COUT = 220 μF, RILM = 6650 Ω,
IOUT stepped from 0 A → 750 mA → 250 mA → 750 mA
VIN = 12 V, CITIMER = Open, COUT = Open, RILM = 549 Ω, IOUT
ramped from 0 A → 7 A
Figure 7-12. Active Current Limit Response -
TPS259470x
Figure 7-13. Circuit Breaker Response -
TPS259474x
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VIN = 12 V, RILM = 549 Ω, VEN/UVLO = 3.3 V, OUT stepped from
Open → Short-circuit to GND
VIN = 23 V, COUT = Open, OUT short-circuit to GND, RILM = 549
Ω, VEN/UVLO stepped from 0 V to 3.3 V
Figure 7-14. Output Short-Circuit During Steady
State
Figure 7-15. Power Up into Short-Circuit
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8 Detailed Description
8.1 Overview
The TPS25947xx is an eFuse with integrated power path that is used to ensure safe power delivery in a system.
The device starts its operation by monitoring the IN bus. When the input supply voltage (VIN) exceeds the
Undervoltage Protection threshold (VUVP), the device samples the EN/UVLO pin. A high level (> VUVLO) on this
pin enables the internal power path (BFET+HFET) to start conducting and allow current to flow from IN to OUT.
When EN/UVLO is held low (< VUVLO), the internal power path is turned off. In case of reverse voltages
appearing at the input, the power path remains OFF thereby protecting the output load.
After a successful start-up sequence, the device now actively monitors its load current and input voltage, and
controls the internal HFET to ensure that the user adjustable overcurrent limit threshold (ILIM) is not exceeded
and overvoltage spikes are either safely clamped to the selected threshold voltage (VOVC) or cut-off once they
cross the user adjustable overvoltage lockout threshold (VOVLO). The device also provides fast protection against
severe overcurrent during short-circuit events. This keeps the system safe from harmful levels of voltage and
current. At the same time, a user adjustable overcurrent blanking timer allows the system to pass moderate
transient peaks in the load current profile without tripping the eFuse. This ensures a robust protection solution
against real faults which is also immune to transients, thereby ensuring maximum system uptime.
The device has integrated reverse current blocking FET (BFET) which operates like an ideal diode. The BFET is
linearly regulated to maintain a small constant forward drop (VFWD) in forward conduction mode and turned off
completely to block reverse current if output voltage exceeds the input voltage.
The device also has a built-in thermal sensor based shutdown mechanism to protect itself in case the device
temperature (TJ) exceeds the recommended operating conditions.
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8.2 Functional Block Diagram
FFT
TPS259470x
VFWD
VDSCOMP
Temp Sense &
Overtemperature
protection
TSD
5
IN
OUT
6
7
INRUSH_DONE
BFET
HFET
IRPP
DVDT
CP
2.8 V
2.2 ꢀA
+
UVPb
2.53V9
2.42V;
-
182 ꢀA/A
GHI
FFT
GHI
RCB
-
2x
1x
-
HFET Control
SC
OC
2
OVLO
OVLOb
UVLOb
1.2V9
1.1V;
+
-
+
BFET Control
Current Limit
Amplifier
+
1
EN/UVLO
+
9
ILM
1.2V9
1.1V;
-
SWEN
Short
Detect
-
SD
ILM Pin Short
+
0.75 V
RETRY#
2.57 V
1.07V;
SD
UVPb
R
S
/Q
Q
RETRY#
RETRY
TIMER#
+
ITIMER_EXPIRED
TSD
FLT
RCB
10 ITIMER
-
ILM Pin Short
OC
ITIMER_EXPIRED
1.8 ꢀA
8
GND
4
3
FLT
AUXOFF
# Not applicable to Latch-off variants (TPS259470L)
Figure 8-1. TPS259470x Block Diagram
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FFT
TPS259472x
VFWD
VDSCOMP
Temp Sense &
Overtemperature
protection
TSD
6
7
OUT
5
IN
INRUSH_DONE
BFET
HFET
IRPP
DVDT
CP
+
2.8 V
UVPb
2.2 ꢀA
2.53V9
2.42V;
-
+
182 ꢀA/A
GHI
FFT
GHI
-
OVC
OVC Threshold
Select
-
2x
1x
OVCSEL
EN/UVLO
2
1
SC
OC
HFET Control
RCB
+
-
BFET Control
Current Limit
Amplifier
+
UVLOb
+
9
ILM
1.2V9
1.1V;
-
SWEN
Short
Detect
-
SD
ILM Pin Short
+
0.75 V
2.57 V
PG_int
1.07V;
OVC
INRUSH_DONE
+
SD
UVPb
R
ITIMER_EXPIRED
PG_int
/Q
Q
RETRY#
RCB
PG_int
10 ITIMER
-
TSD
FLT
OC
S
ILM Pin Short
1.8 ꢀA
8
GND
R
Q
S
RETRY
TIMER#
RETRY#
/Q
1.2V9
4
3
PG
PGTH
# Not applicable to Latch-off variants (TPS259472L)
Figure 8-2. TPS259472x Block Diagram
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FFT
TPS259474x
VFWD
VDSCOMP
Temp Sense &
Overtemperature
protection
TSD
OUT
5
6
7
IN
INRUSH_DO
NE
BFET
HFET
IRPP
DVDT
CP
2.8 V
2.2 ꢀA
+
UVPb
2.53V9
2.42V;
-
182 ꢀA/A
GHI
FFT
GHI
RCB
2x
1x
-
-
HFET Control
SC
OC
OVLO
2
1
OVLOb
UVLOb
1.2V9
1.1V;
+
+
-
BFET Control
Current Limit
Amplifier
+
EN/UVLO
+
9
ILM
1.2V9
-
SWEN
1.1V;
Short
Detect
INRUSH_DONE
-
SD
ILM Pin Short
+
0.75 V
2.57 V
PG_int
1.07V;
INRUSH_DONE
+
SD
UVPb
R
S
/Q
Q
ITIMER_EXPIRED
PG_int
RETRY#
RCB
PG_int
10
ITIMER
-
TSD
ILM Pin Short
ITIMER_EXPIRED
FLT
OC
1.8 ꢀA
8
GND
R
Q
S
RETRY
TIMER#
RETRY#
/Q
1.2V9
3
4
PG
PGTH
# Not applicable to Latch-off variants (TPS259474L)
Figure 8-3. TPS259474x Block Diagram
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8.3 Feature Description
The TPS25947xx eFuse is a compact, feature rich power management device that provides detection, protection
and indication in the event of system faults.
8.3.1 Input Reverse Polarity Protection
The TPS25947xx device is internally protected against steady state negative voltages applied at the input supply
pin. The device blocks the negative voltage from appearing at the output, thereby protecting the load circuits.
There’s no reverse current flowing from output to the input in this condition. The maximum continuous reverse
voltage the device can handle at the input is limited to (VOUT – 19 V). It’s also recommended that all signal pins
(e.g. EN/UVLO, OVLO, PGTH) which are connected to input supply should have a sufficiently large pull-up
resistor to limit the current flowing out of these pins during reverse polarity conditions.
8.3.2 Undervoltage Lockout (UVLO & UVP)
The TPS25947xx implements Undervoltage Protection on IN in case the applied voltage becomes too low for the
system or device to properly operate. The Undervoltage Protection has a default lockout threshold of VUVP which
is fixed internally. Also, the UVLO comparator on the EN/UVLO pin allows the Undervoltage Protection threshold
to be externally adjusted to a user defined value. The Figure 8-4 and Equation 1 show how a resistor divider can
be used to set the UVLO set point for a given voltage supply.
Power
Supply
IN
R1
EN/UVLO
R2
GND
Figure 8-4. Adjustable Undervoltage Protection
VUVLO x (R1 + R2)
VIN(UV)
=
R2
(1)
8.3.3 Overvoltage Lockout (OVLO)
The TPS259470x/4x variants allow the user to implement Overvoltage Lockout to protect the load from input
overvoltage conditions. The OVLO comparator on the OVLO pin allows the Overvoltage Protection threshold to
be adjusted to a user defined value. Once the voltage at the OVLO pin crosses the OVLO rising threshold
VOV(R), the device turns off the power to the output. Thereafter, the devices wait for the voltage at the OVLO pin
to fall below the OVLO falling threshold VOV(F) before the output power is turned ON again. The rising and falling
thresholds are slightly different to provide hysterisis. The Figure 8-5 and Equation 2 show how a resistor divider
can be used to set the OVLO set point for a given voltage supply.
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Power
Supply
IN
R1
OVLO
R2
GND
Figure 8-5. Adjustable Overvoltage Protection
VOV x (R1 + R2)
R2
VIN(OV)
=
(2)
While recovering from a OVLO event, the TPS259470x variants bypass the inrush control (dVdt) and start up in
a current limited manner to provide faster turn ON and minimize power supply droop.
Input Overvoltage Event
Input Overvoltage Removed
IN
0
VOV(R)
VOV(F)
OVLO
tOVLO
0
tSWOV
Current
Limited
OUT
0
VFLT
FLT
0
VAUXOFF
AUXOFF
0
Time
Figure 8-6. TPS259470x Overvoltage Lockout and Recovery
While recovering from a OVLO event, the TPS259474x variants start up with inrush control (dVdt).
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Input Overvoltage Event
Input Overvoltage Removed
IN
0
VOV(R)
VOV(F)
OVLO
tOVLO
0
dVdt
Limited
OUT
PG
0
VPG
0
tPGA
tPGD
Time
Figure 8-7. TPS259474x Overvoltage Lockout and Recovery
8.3.4 Overvoltage Clamp (OVC)
The TPS259472x variants implement a voltage clamp on the output to protect the system in the event of input
overvoltage. When the device detects the input has exceeded the Overvoltage Clamp Threshold (VOVC), it
quickly responds within tOVC and stops the output from rising further and then regulates the HFET linearly to
clamp the output voltage below VCLAMP as long as an overvoltage condition is present on the input.
If the part stays in clamping state for an extended period of time, there will be higher power dissipation inside the
part which may eventually lead to thermal shut-down (TSD). Once the part shuts down due to TSD fault, it would
either stay latched off (TPS259472L variant) or restart automatically after a fixed delay (TPS259472A variant).
See Overtemperature Protection (OTP) for more details on device response to overtemperature.
Input Overvoltage Event
Input Overvoltage Removed
VOVC
IN
Thermal
Shutdown
Retry Timer Expired (1)
tOVC
0
VCLAMP
tRST
dVdt
Limited
OUT
PG
TJ
0
VPG
0
tPGD
tPGA
TSD
TSDHYS
Time
(1) Applicable only for TPS259472A (Auto-retry variant)
Figure 8-8. TPS259472x Overvoltage Response (Auto-Retry)
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There are 3 available overvoltage clamp threshold options which can be configured using the OVCSEL pin.
Table 8-1. TPS259472x Overvoltage Clamp Threshold selection
OVCSEL Pin Connection
Shorted to GND
Overvoltage Clamp Threshold
3.8 V
5.7 V
13.8 V
Open
Connected to GND through 390-kΩ resistor
8.3.5 Inrush Current, Overcurrent, and Short Circuit Protection
TPS25947xx incorporates four levels of protection against overcurrent:
1. Adjustable slew rate (dVdt) for inrush current control
2. Adjustable threshold (ILIM) for overcurrent protection during start-up or steady-state
3. Adjustable threshold (ISC) for fast-trip response to severe overcurrent during start-up or steady-state
4. Fixed threshold (IFT) for fast-trip response to quickly protect against hard output short-circuits during steady-
state
8.3.5.1 Slew Rate (dVdt) and Inrush Current Control
During hot-plug events or while trying to charge a large output capacitance at start-up, there can be a large
inrush current. If the inrush current is not managed properly, it can damage the input connectors and/or cause
the system power supply to droop leading to unexpected restarts elsewhere in the system. The inrush current
during turn on is directly proportional to the load capacitance and rising slew rate. Equation 3 can be used to find
the slew rate (SR) required to limit the inrush current (IINRUSH) for a given load capacitance (COUT):
IINRUSH (mA)
SR (V/ms) =
C
OUT (µF)
(3)
A capacitor can be connected to the dVdt pin to control the rising slew rate and lower the inrush current during
turn on. The required CdVdt capacitance to produce a given slew rate can be calculated using Equation 4.
2000
CdVdt (pF) =
SR (V/ms)
(4)
The fastest output slew rate is achieved by leaving the dVdt pin open.
Note
For CdVdt > 10 nF, it's recommended to add a 100-Ω resistor in series with the capacitor on the dVdt
pin.
8.3.5.2 Circuit Breaker
The TPS259474x (Circuit Breaker) variants respond to output overcurrent conditions by turning off the output
after a user adjustable transient fault blanking interval. When the load current exceeds the set overcurrent
threshold (ILIM) set by the ILM pin resistor (RILM), but stays lower than the fast-trip threshold (2 x ILIM), the device
starts discharging the ITIMER pin capacitor using an internal 1.8-μA pull-down current. If the load current drops
below ILIM before the ITIMER pin capacitor (CITIMER) discharges by ΔVITIMER, the ITIMER is reset by pulling it up
to VINT internally and the circuit breaker action is not engaged. This allows short load transient pulses to pass
through the device without tripping the circuit. If the overcurrent condition persists, the CITIMER continues to
discharge and once it discharges by ΔVITIMER, the circuit breaker action turns off the HFET immediately. At the
same time, the CITIMER is charged up to VINT again so that it is at its default state before the next overcurrent
event. This ensures the full blanking timer interval is provided for every overcurrent event. Equation 5 can be
used to calculate the RILM value for a overcurrent threshold.
3334
: ;
RILM À =
: ;
A
ILIM
(5)
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Note
1. Leaving the ILM pin Open sets the current limit to nearly zero and results in the part breaking the
circuit with the slightest amount of loading at the output.
2. Shorting the ILM pin to ground at any point during normal operation is detected as a fault and the
part shuts down. There’s a minimum current (IFLT) which the part allows in this condition before the
pin short condition is detected.
The duration for which transients are allowed can be adjusted using an appropriate capacitor value from ITIMER
pin to ground. The CITIMER value needed to set the desired transient overcurrent blanking interval can be
calculated using Equation 6.
¿VITIMER (V) x CITIMER (nF)
tITIMER (ms) =
IITIMER (µA)
(6)
ITIMER expired
Transient
Overcurrent
Persistent Output
Overload
2 x ILIM
Circuit Breaker
operation
IOUT
ILIM
0
tITIMER
∆VITIMER
ITIMER
0
VIN
OUT
0
VPGTH
PGTH
0
tPGD
VPG
PG
TJ
0
TSD
TSDHYS
TJ
Time
Figure 8-9. TPS259474x Overcurrent Response
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Note
1. Leave the ITIMER pin open to allow the part to break the circuit with the minimum possible delay.
2. Shorting the ITIMER pin to ground results in minimum overcurrent response delay (similar to
ITIMER pin open condition), but increases the device current consumption. This is not a
recommended mode of operation.
3. Increasing the ITIMER cap value extends the overcurrent blanking interval, but it also extends the
time needed for the ITIMER cap to recharge up to VINT. If the next overcurrent event occurs before
the ITIMER cap is recharged fully, it will take lesser time to discharge to the ITIMER expiry
threshold, thereby providing a shorter blanking interval than intended.
Once the part shuts down due to a Circuit Breaker fault, it would either stay latched off (TPS259474L variant) or
restart automatically after a fixed delay (TPS259474A variant).
8.3.5.3 Active Current Limiting
The TPS259470x/2x (Active Current Limit) variants respond to output overcurrent conditions by actively limiting
the current after a user adjustable transient fault blanking interval. When the load current exceeds the set
overcurrent threshold (ILIM) set by the ILM pin resistor (RILM), but stays lower than the short-circuit threshold (2 x
ILIM), the device starts discharging the ITIMER pin capacitor using an internal 1.8-μA pull-down current. If the
load current drops below the overcurrent threshold before the ITIMER capacitor (CITIMER) discharges by
ΔVITIMER, the ITIMER is reset by pulling it up to VINT internally and the current limit action is not engaged. This
allows short load transient pulses to pass through the device without getting current limited. If the overcurrent
condition persists, the CITIMER continues to discharge and once it discharges by ΔVITIMER, the current limit starts
regulating the HFET to actively limit the current to the set overcurrent threshold (ILIM). At the same time, the
CITIMER is charged up to VINT again so that it is at its default state before the next overcurrent event. This
ensures the full blanking timer interval is provided for every overcurrent event. Equation 7 can be used to
calculate the RILM value for a desired overcurrent threshold.
3334
: ;
RILM À =
: ;
A
ILIM
(7)
Note
1. Leaving the ILM pin Open sets the current limit to nearly zero and results in the part entering
current limit with the slightest amount of loading at the output.
2. The current limit circuit employs a foldback mechanism. The current limit threshold in the foldback
region (0 V < VOUT < VFB) is lower than the steady state current limit threshold (ILIM).
3. Shorting the ILM pin to ground at any point during normal operation is detected as a fault and the
part shuts down. There’s a minimum current (IFLT) which the part allows in this condition before the
pin short condition is detected.
The duration for which transients are allowed can be adjusted using an appropriate capacitor value from ITIMER
pin to ground. The CITIMER value needed to set the desired transient overcurrent blanking interval can be
calculated using Equation 8 below.
¿VITIMER (V) x CITIMER (nF)
tITIMER (ms) =
IITIMER (µA)
(8)
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Overload
Removed
Persistent Output
Overload
ITIMER expired
ITIMER expired
Transient
Overcurrent
Persistent Output
Overload
Thermal shutdown
2 x ILIM
tLIM
tLIM
IOUT
ILIM
Current limiting
operation
Current limiting
operation
0
tITIMER
tITIMER
∆VITIMER
ITIMER
OUT
0
VIN
0
1.2 V
(1)
PGTH
tPGD
tPGD
tPGA
0
VPG
(1)
PG
0
VFLT
(2)
FLT
0
TSD
TSDHYS
TJ
TJ
Time
(1) Available only for TPS259472x/4x variants
(2) Available only for TPS259470x variants
Figure 8-10. TPS259470x/2x Active Current Limit Response
Note
1. Leave the ITIMER pin open to allow the part to limit the current with the minimum possible delay.
2. Shorting the ITIMER pin to ground results in minimum overcurrent response delay (similar to
ITIMER pin open condition), but increases the device current consumption. This is not a
recommended mode of operation.
3. Active current limiting based on RILM is active during startup for both TPS259470x/2x (Current
Limit) and TPS259474x (Circuit Breaker) variants. In case the startup current exceeds ILIM, the
device regulates the current to the set limit. However, during startup the current limit is engaged
without waiting for the ITIMER delay.
4. For the TPS259472x variants, during overvoltage clamp condition, if an overcurrent event occurs,
the current limit is engaged without waiting for the ITIMER delay.
5. Increasing the CITIMER value extends the overcurrent blanking interval, but it also extends the time
needed for the CITIMER to recharge up to VINT. If the next overcurrent event occurs before the
CITIMER is recharged fully, it will take lesser time to discharge to the ITIMER expiry threshold,
thereby providing a shorter blanking interval than intended.
During active current limit, the output voltage will drop resulting in increased device power dissipation across the
HFET. If the device internal temperature (TJ) exceeds the thermal shutdown threshold (TSD), the HFET is turned
off. Once the part shuts down due to TSD fault, it would either stay latched off (TPS25947xL variants) or restart
automatically after a fixed delay (TPS25947xA variants). See Overtemperature Protection (OTP) for more details
on device response to overtemperature.
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8.3.5.4 Short-Circuit Protection
During an output short-circuit event, the current through the device increases very rapidly. When a severe
overcurrent condition is detected, the device triggers a fast-trip response to limit the current to a safe level. The
internal fast-trip comparator employs a scalable threshold (ISC) which is equal to 2 × ILIM. This enables the user
to adjust the fast-trip threshold rather than using a fixed threshold which can be too high for some low current
systems. The device also employs a fixed fast-trip threshold (IFT) to protect fast protection against hard short-
circuits during steady state. The fixed fast-trip threshold is higher than the maximum recommended user
adjustable scalable fast-trip threshold. Once the current exceeds ISC or IFT, the HFET is turned off completely
within tFT. Thereafter, the devices tries to turn the HFET back ON after a short de-glitch interval (30 μs) in a
current limited manner instead of a dVdt limited manner. This ensures that the HFET has a faster recovery after
a transient overcurrent event and minimizes the output voltage droop. However, if the fault is persistent, the
device will stay in current limit causing the junction temperature to rise and eventually enter thermal shutdown.
See Overtemperature Protection (OTP) section for details on the device response to overtemperature.
Persistent Severe
Overcurrent
Transient Severe
Overcurrent
Output Hard Short-
circuit to ground
Thermal Shutdown
Short-circuit Removed
Retry Timer Elapsed (3)
Thermal Shutdown
Overcurrent Removed
Retry Timer Elapsed (3)
IN
0
IFT
tFT
tSC
tSC
2 x ILIM
IOUT
ILIM
0
VIN
OUT
dVdt Limited
Start-up
dVdt Limited
Start-up
Current Limited
Start-up
0
tPGD
tPGD
tPGD
VPG
PG (1)
0
VFLT
FLT (2)
0
tRST
tRST
TSD
TSDHYS
TJ
Time
(1) Available only for TPS259472x/4x variants
(2) Available only for TPS259470x variants
(3) Available only for TPS25947xA variants
Figure 8-11. TPS25947x Short Circuit Response
8.3.6 Analog Load Current Monitor
The device allows the system to accurately monitor the output load current by providing an analog current sense
output on the ILM pin which is proportional to the current through the FET. The user can sense the voltage (VILM
)
across the RILM to get a measure of the output load current.
VILM (V) x 10-6
IOUT (A) =
RILM :À; ∏ GIMON (µA/A)
(9)
The waveform below shows the ILM signal response to a load step at the output.
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VIN = 12 V, COUT = 22 μF, RILM = 549 Ω, IOUT stepped up from 0 A to 5 A
Figure 8-12. Analog Load Current Monitor Response
Note
The ILM pin is sensitive to capacitive loading. Careful design and layout is needed to ensure the
parasitic capacitive loading on the ILM pin is < 50 pF for stable operation.
8.3.7 Reverse Current Protection
The device functions like an ideal diode and blocks reverse current flow from OUT to IN under all conditions. The
device has integrated back-to-back MOSFETs connected in a common drain configuration. The voltage drop
between the IN and OUT pins is constantly monitored and the gate drive of the blocking FET (BFET) is adjusted
as needed to regulate the forward voltage drop at VFWD. This closed loop regulation scheme enables graceful
turn off of the MOSFET during a reverse current event and ensures there's no DC reverse current flow.
The device also uses a conventional comparator (VREVTH) based reverse blocking mechanism to provide fast
response (tRCB) to transient reverse currents.Once the device enters reverse current blocking condition, it waits
for the (VIN - VOUT) forward drop to exceed the VFWDTH before it performs a fast recovery to reach full forward
conduction state. This provides sufficient hysterisis to prevent supply noise or ripple from affecting the reverse
current blocking response. The recovery from reverse current blocking is very fast (tSWRCB). This ensures
minimum supply droop which is helpful in applications such as supply MUXing/ORing and USB Fast Role Swap
(FRS).
VFWD
IN
OUT
OUT
IN
BFET regulation mode
BFET full conduction mode
VFWTH
BFET turned OFF
VREVTH
VFWD
0 V
VIN - VOUT
Figure 8-13. Reverse Current Blocking Response
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The waveforms below illustrate the reverse current blocking performance in various scenarios.
During fast voltage step at output (e.g. hot-plug), the fast comparator based reverse blocking mechanism
ensures minimum jump/glitch on the input rail.
Figure 8-14. Reverse Current Blocking Performance During Fast Voltage Step at Output
During slow voltage ramp at output, the linear ORing based reverse blocking mechanism ensures there's no DC
current flow from OUT to IN, thereby avoiding input rail from getting slowly charged up to output voltage.
Figure 8-15. Reverse Current Blocking Performance During Slow Voltage Ramp at Output
When the input supply droops or gets disconnected while the output storage element (bulk capacitor or super
capacitor) is charged to the full voltage, the linear ORing scheme minimizes the self-discharge from OUT to IN.
This ensures maximum hold-up time for the output storage element in critical power back-up applications.
It also prevents incorrect supply presence indication in applications which sense the input voltage to detect if the
supply is connected.
Figure 8-16. Reverse Current Blocking Performance During Input Supply Failure
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8.3.8 Overtemperature Protection (OTP)
The device monitors the internal die temperature (TJ) at all times and shuts down the part as soon as the
temperature exceeds a safe operating level (TSD) thereby protecting the device from damage. The device will
not turn back on until the junction cools down sufficiently, that is the die temperature falls below (TSD - TSDHYS).
When the TPS25947xL (latch-off variant) detects thermal overload, it will be shut down and remain latched-off
until the device is power cycled or re-enabled. When the TPS25947xA (auto-retry variant) detects thermal
overload, it will remain off until it has cooled down by TSDHYS. Thereafter, it will remain off for an additional delay
of tRST after which it will automatically retry to turn on if it is still enabled.
Table 8-2. Thermal Shutdown
Device
Enter TSD
Exit TSD
TJ < TSD - TSDHYS
TPS25947xL (Latch-Off)
TJ ≥ TSD
VIN cycled to 0 V and then above VUVP(R) OR
EN/UVLO toggled below VSD(F)
TJ < TSD - TSDHYS
VIN cycled to 0 V and then above VUVP(R) OR
EN/UVLO toggled below VSD(F) OR tRST timer
expired
TPS25947xA (Auto-Retry)
TJ ≥ TSD
8.3.9 Fault Response and Indication (FLT)
The following table summarizes the device response to various fault conditions. Additionally, an active low
external fault indication (FLT) pin is available on the TPS259470x variants.
Table 8-3. Fault Summary
Event
Protection Response
Fault latched internally
FLT Pin status (1)
FLT assertion delay(1)
Overtemperature
Shutdown
Y
L
Undervoltage (UVP or
UVLO)
Shutdown
N
H
Input Reverse Polarity
Overvoltage
Shutdown
N
N
N
H
Shutdown(1) (2)
Voltage Clamp(2)
H
N/A
Transient Overcurrent (ILIM
None
N
N
< IOUT < 2 x ILIM
)
Persistent Overcurrent
Overcurrent
Circuit Breaker(3)
Current Limit(4)
Y
N
N/A
L
tITIMER
Circuit Breaker followed by
Current Limit
Short-Circuit
N
H
ILM Pin Open
Shutdown
N
Y
N
L
L
L
tITIMER
(During Steady State)
ILM Pin Short to GND
Shutdown
tITIMER
Reverse Current ((VOUT
-
Reverse Current Blocking
VIN) > VREVTH
)
(1) Applicable to TPS259470x variants only
(2) Applicable to TPS259472x variants only
(3) Applicable to TPS259474x variants only
(4) Applicable to TPS259470x/2x variants only
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Faults which are latched internally can be cleared either by power cycling the part (pulling VIN to 0 V) or by
pulling the EN/UVLO pin voltage below VSD. This also releases the FLT pin for the TPS259470x variants and
resets the tRST timer for the TPS25947xA (auto-retry) variants.
During a latched fault, pulling the EN/UVLO just below the UVLO threshold has no impact on the device. This is
true for both TPS25947xL (latch-off) & TPS25947xA (auto-retry) variants.
For TPS25947xA (auto-retry) variants, on expiry of the tRST timer after a fault, the device restarts automatically
and the FLT pin is de-asserted (TPS259470A variant).
8.3.10 Auxiliary Channel Control (AUXOFF)
The TPS259470x variants provide an active high digital output (AUXOFF) which is asserted to indicate when the
priority input supply is in a valid range (above UVP/UVLO and below OVLO thresholds) and the device has
successfully completed its inrush sequence. The AUXOFF pin is an open-drain signal which needs to be pulled
up to an external supply.
After power up, AUXOFF pin is pulled low initially. The device initiates a inrush sequence in which the HFET is
turned on in a controlled manner. When the FET gate voltage has reached the full overdrive indicating that the
inrush sequence is complete and device is capable of delivering full power, the AUXOFF pin is asserted high.
Thereafter, the AUXOFF pin is de-asserted only if the input supply becomes invalid (below UVP/UVLO or above
OVLO thresholds). No load side events/faults have any control over the AUXOFF de-assertion.
This pin is used to control the auxiliary channel when 2 TPS259470x devices are connected in a priority power
MUX configuration. It can also be used as a supply valid status indication to the downstream load or system
supervisor.
Table 8-4. TPS259470x AUXOFF Indication Summary
Event
AUXOFF Pin
Undervoltage (UVP or UVLO)
Input Reverse Polarity
Overvoltage (OVLO)
Inrush
L
L
L
L
Steady State
H
H
H
H
H
H
H
Overcurrent
Short-Circuit
ILM Pin Open
ILM Pin Short to GND
Reverse current ((VOUT - VIN) > VREVTH
Overtemperature
)
When there is no supply to the device, the AUXOFF pin is expected to stay low. However, there is no active pull-
down in this condition to drive this pin all the way down to 0 V. If the AUXOFF pin is pulled up to an independent
supply which is present even if the device is unpowered, there can be a small voltage seen on this pin
depending on the pin sink current, which is a function of the pull-up supply voltage and resistor. Minimize the
sink current to keep this pin voltage low enough not to be detected as a logic HIGH by associated external
circuits in this condition. This also ensures that the auxiliary channel is not turned off inadvertently in a priority
power MUX configuration.
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8.3.11 Power Good Indication (PG)
The TPS259472x/4x variants provide an active high digital output (PG) which serves as a power good indication
signal and is asserted high depending on the voltage at the PGTH pin along with the device state information.
The PG is an open-drain pin and needs to be pulled up to an external supply.
After power up, PG is pulled low initially. The device initiates a inrush sequence in which the HFET is turned on
in a controlled manner. When the HFET gate voltage reaches the full overdrive indicating that the inrush
sequence is complete and the voltage at PGTH is above VPGTH(R), the PG is asserted after a de-glitch time
(tPGA).
PG is de-asserted if at any time during normal operation, the voltage at PGTH falls below VPGTH(F), or the device
detects a fault (except overcurrent). The PG de-assertion de-glitch time is tPGD
.
Overload Removed
Device Enabled
Overload Event
Overcurrent blanking
timer expired
VUVLO(R)
0
EN/UVLO
IN
Slew rate (dVdt) controlled
startup/Inrush current limiting
0
VIN
Active Current
limiting (1)
OUT
0
VPGTH(R)
VPGTH(F)
PGTH
PG
0
VPG
tPGA
tPGD
tPGA
0
VIN
dVdt
0
VOUT + 2.8V
VHGate
tITIMER
0
ILIM
IINRUSH
0
IOUT
Time
(1) Applicable to TPS259472x only
Figure 8-17. TPS259472x/74x PG Timing Diagram
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Table 8-5. TPS259472x/4x PG Indication Summary
Event
Protection Response
PG Pin
PG Delay
Undervoltage (UVP or UVLO)
Input Reverse Polarity
Shutdown
L
Shutdown
L
Overvoltage (OVC)
(TPS259472x only)
H (If PGTH > VPGTH(R)
)
tPGA
tPGD
Clamp
L (If PGTH < VPGTH(F)
L (If PGTH < VPGTH(F)
H (If PGTH > VPGTH(R)
)
Overvoltage (OVLO)
(TPS259474x only)
Shutdown
)
tPGD
)
)
)
tPGA
tPGD
Soft overload
Steady State
Short-Circuit
Limiting
L (If PGTH < VPGTH(F)
)
H (If PGTH > VPGTH(R)
tPGA
tPGD
NA
L (If PGTH < VPGTH(F)
)
H (If PGTH > VPGTH(R)
tPGA
tPGD
Fast trip followed by Current Limit
L (If PGTH < VPGTH(F)
L (If PGTH < VPGTH(F)
L (If PGTH < VPGTH(F)
)
ILM Pin Open
Shutdown
Shutdown
)
tPGD
tPGD
tPGD
tPGD
ILM Pin Short to GND
Reverse current ((VOUT - VIN) >
)
Reverse current blocking
Shutdown
L
VREVTH
)
Overtemperature
L (If PGTH < VPGTH(F)
)
When there is no supply to the device, the PG pin is expected to stay low. However, there is no active pull-down
in this condition to drive this pin all the way down to 0 V. If the PG pin is pulled up to an independent supply
which is present even if the device is unpowered, there can be a small voltage seen on this pin depending on the
pin sink current, which is a function of the pull-up supply voltage and resistor. Minimize the sink current to keep
this pin voltage low enough not to be detected as a logic HIGH by associated external circuits in this condition.
8.4 Device Functional Modes
Table 8-6. TPS259472x Overvoltage Clamp Threshold Selection
OVCSEL Pin Connection
Shorted to GND
Overvoltage Clamp Threshold
3.8 V
5.7 V
13.8 V
Open
Connected to GND through 390-kΩ resistor
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9 Application and Implementation
The TPS25947xx can be used in a variety of configurations.
Note
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.
9.1 Application Information
9.2 Single Device, Self-Controlled
VOUT
VIN = 2.7 to 23 V
VOUT
VIN = 2.7 to 23 V
IN
OUT
IN
OUT
VLOGIC
COUT
COUT
VLOGIC
PGTH
EN/UVLO
OVCSEL
EN/UVLO
OVLO
TPS259472x
TPS259470x
AUXOFF
FLT
PG
ITIMER dVdt
ITIMER dVdt
GND
ILM
ILM
GND
VOUT
IN
OUT
VIN = 2.7 to 23 V
COUT
VLOGIC
PGTH
EN/UVLO
OVLO
TPS259474x
PG
ITIMER dVdt
GND
ILM
Figure 9-1. Single Device, Self-Controlled
Other variations:
In a Host MCU controlled system, EN/UVLO or OVLO can also be driven from the host GPIO to control the
device.
ILM pin can be connected to the MCU ADC input for current monitoring purpose.
Note
It's recommended to keep parasitic capacitance on ILM pin below 50 pF to ensure stable operation.
For the TPS259472x/4x variants, either VIN or VOUT can be used to drive the PGTH resistor divider depending
on which supply needs to be monitored for power good indication.
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9.2.1 Typical Application
9.2.1.1 Application
VOUT
VIN = 12 V
IN
OUT
R4
47 kO
R1
470 kO
COUT
470 …F
D2*
PGTH
EN/UVLO
OVLO
3.3 V
TPS259474L
R2
5.6 kO
R2
11 kO
CIN
1 …F
D1*
47 kO
PG
ITIMER dVdt
ILM
GND
R3
47 kO
RILM
549 O
CITIMER
2.2 nF
CdVdt
3300 pF
* Optional circuit components needed for transient protection depending on input and output inductance. Please
refer to Transient Protection section for details.
Figure 9-2. PCIe Card Input Power Protection
9.2.1.2 Design Requirements
Table 9-1. Design Parameters
PARAMETER
VALUE
12 V
Input supply voltage (VIN)
Undervoltage threshold (VIN(UV)
)
10.8 V
13.2 V
11.4 V
Overvoltage threshold (VIN(OV)
)
Output power good threshold (VPG
Max continuous current
)
5.5 A
Load transient blanking interval (tITIMER
)
2 ms
Output capacitance (COUT
Output rise time (tR)
)
470 μF
20 ms
Overcurrent threshold (ILIM
Overcurrent response
Fault response
)
6 A
Circuit breaker
Latch-off
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9.2.1.3 Detailed Design Procedure
9.2.1.3.1 Device Selection
Since the application requires circuit-breaker response to overcurrent with latch-off response after a fault, the
TPS259474L variant is selected after refering to the Device Comparison Table.
9.2.1.3.2 Setting Undervoltage and Overvoltage Thresholds
The supply undervoltage and overvoltage thresholds are set using the resistors R1, R2 & R3 whose values can
be calculated using Equation 10 and Equation 11:
VUVLO(R) x (R1 + R2 + R3)
VIN(UV)
=
R2 + R3
(10)
VOV(R) x (R1 + R2 + R3)
R3
VIN(OV)
=
(11)
Where VUVLO(R) is the UVLO rising threshold and VOV(R) is the OVLO rising threshold . Because R1, R2 and R3
leak the current from input supply VIN, these resistors must be selected based on the acceptable leakage current
from input power supply VIN. The current drawn by R1, R2 and R3 from the power supply is IR123 = VIN / (R1 +
R2 + R3). However, leakage currents due to external active components connected to the resistor string can add
error to these calculations. So, the resistor string current, IR123 must be chosen to be 20 times greater than the
leakage current expected on the EN/UVLO and OVLO pins.
From the device electrical specifications, both the EN/UVLO and OVLO leakage currents are 0.1 μA (max),
VOV(R) = 1.2 V and VUVLO(R) = 1.2 V. From design requirements, VIN(OV) = 13.2 V and VIN(UV) = 10.8 V. To solve
the equation, first choose the value of R1 = 470 kΩ and use the above equations to solve for R2 = 10.7 kΩ and
R3 = 48 kΩ.
Using the closest standard 1% resistor values, we get R1 = 470 kΩ, R2 = 11 kΩ, and R3 = 47 kΩ.
9.2.1.3.3 Setting Output Voltage Rise Time (tR)
The slew rate (SR) needed to achieve the desired output rise time can be calculated as:
VIN (V)
12 V
SR (V/ms) =
=
= 0.6 V/ms
tR (ms) 20 ms
(12)
(13)
The CdVdt needed to achieve this slew rate can be calculated as:
2000
2000
0.6
:
;
CdVdt pF =
=
= 3333 pF
:
SR V/ms
;
Choose the nearest standard capacitor value as 3300 pF.
For this slew rate, the inrush current can be calculated as:
:
;
:
IINRUSH mA = SR (V/ms) x COUT µF = 0.6 x 470 = 282 mA
;
(14)
(15)
The average power dissipation inside the part during inrush can be calculated as:
: ;
IINRUSH A T VIN
: ;
8
0.282 x 12
2
:
;
PDINRUSH W =
=
= 1.69 W
2
9.2.1.3.4 Setting Power Good Assertion Threshold
The Power Good assertion threshold can be set using the resistors R4 & R5 connected to the PGTH pin whose
values can be calculated as:
VPGTH(R) x (R4 + R5)
VPG
=
R5
(16)
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Because R4 and R5 leak the current from the output rail VOUT, these resistors must be selected to minimize the
leakage current. The current drawn by R4 and R5 from the power supply is IR45 = VOUT / (R4 + R5). However,
leakage currents due to external active components connected to the resistor string can add error to these
calculations. So, the resistor string current, IR123 must be chosen to be 20 times greater than the PGTH
leakage current expected.
From the device electrical specifications, PGTH leakage current is 1 μA (max), VPGTH(R) = 1.2 V and from design
requirements, VPG = 11.4 V. To solve the equation, first choose the value of R4 = 47 kΩ and calculate R5 = 5.52
kΩ. Choose nearest 1% standard resistor value as R5 = 5.6 kΩ.
9.2.1.3.5 Setting Overcurrent Threshold (ILIM
)
The overcurrent protection (Circuit breaker) threshold can be set using the RILM resistor whose value can be
calculated as:
3334
3334
6 A
: ;
RILM À =
=
= 555.6 À
: ;
A
ILIM
(17)
Choose nearest 1% standard resistor value as 549 Ω.
9.2.1.3.6 Setting Overcurrent Blanking Interval (tITIMER
)
The overcurrent blanking timer interval can be set using the CITIMER capacitor whose value can be calculated as:
tITIMER (ms) x IITIMER (µA) 2 x 1.8
=
CITIMER (nF) =
= 2.4 nF
¿VITIMER (V)
1.5
(18)
Choose nearest standard capacitor value as 2.2 nF.
9.3 Active ORing
A typical redundant power supply configuration is shown in Figure 9-3 below. Schottky ORing diodes have been
popular for connecting parallel power supplies, such as parallel operation of wall adapter with a battery or a hold-
up storage capacitor. The disadvantage of using ORing diodes is high voltage drop and associated power loss.
The TPS259470x/4x with integrated, low-ohmic, back-to-back FETs provide a simple and efficient solution.
Figure 9-3 below shows the Active ORing implementation using TPS249474x devices.
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VOUT
IN
OUT
VIN1
VLOGIC
EN/UVLO
OVLO
COUT
PGTH
TPS259474x
PG_SYS
PG
VIN1
VIN2
Hotswap
protection
IN
OUT
VIN2
VLOGIC
EN/UVLO
OVLO
PGTH
TPS259474x
PG
Figure 9-3. Two Devices, Active ORing Configuration
The linear ORing mechanism in TPS25947x ensures that there's no reverse current flowing from one power
source to the other during fast or slow ramp of either supply.
The following waveforms illustrate the active ORing behavior when the supply rails are being ramped up or
down.
Figure 9-4. Active ORing Response - Supply Ramp Up
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Figure 9-5. Active ORing Response - Supply Ramp Down
When the bus voltages (IN1 and IN2) are matched, device in each path sees a forward voltage drop and is ON
delivering the load current. During this period, current is shared between the rails in the ratio of differential
voltage drop across each device.
In addition to supply ORing, the devices protect the system from overvoltage, excessive inrush current, overload
and short-circuit faults at all times.
Note
1. The TPS259472x (OVC variants) are not recommended for use in ORing applications. While the
device is in clamping state, if the output is forced to a higher voltage by the other channel, the
device can get damaged.
2. ORing can be done either between two similar rails or between dissimilar rails. For ORing cases
with skewed voltage combinations, care must be taken to design circuit components on PGTH/EN/
OVLO pins for the lower voltage channel devices such that the Absolute maximum ratings on those
pins are not exceeded when higher voltage is present on the other channel. Also, the dVdt pin
capacitor rating should be chosen based on the highest of the 2 supplies. Refer to Recommended
Operating Conditions table for more details.
9.4 Priority Power MUXing
Applications having two energy sources such as PCIe cards, Tablets and Portable battery powered equipment
require preference of one source to another. For example, mains power (wall-adapter) has the priority over the
internal battery back-up power. These applications demand for switchover from mains power to backup power
only when main input voltage falls below a user defined threshold. The TPS25947x devices provide a simple
solution for priority power multiplexing needs.
Figure 9-6 below shows a typical priority power multiplexing implementation using TPS259470x devices. When
primary (priority) power source (IN1) is present and within the valid range (not in UV/OV condition), the primary
path device path powers the OUT bus irrespective of whether auxiliary supply voltage (VIN2) is greater than,
equal to or less than primary supply voltage (VIN1). The device in auxiliary path is held in off condition by forcing
its OVLO pin to high using the AUXOFF signal from the primary path device.
Once the primary supply voltage falls outside the user-defined valid operating range (UV/OV condition), the
primary path device de-asserts the AUXOFF which signals the auxiliary path device to turn on and the system
starts operating from the auxiliary supply. During this transition, the auxiliary path device bypasses its dVdt
limited startup and performs a fast recovery to start delivering power within tSWOV
.
When the primary supply is restored, the primary path device turns on fully at a defined slew rate and then
asserts its AUXOFF pin high to turn the auxiliary path device off, allowing a seamless transition from auxiliary to
the primary supply with minimal output voltage droop and with no shoot-through current.
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A key consideration in power MUXing applications is the minimum voltage the output bus droops to during the
switchover from one supply to another. This in turn depends on multiple factors including the output load current
(ILOAD), output bus hold-up capacitance (COUT) and switchover time (tSW).
While switching from primary supply (VIN1) to auxiliary supply (VIN2), the minimum bus voltage can be calculated
using Equation 19. Here, the switchover time (tSW) is equal to the fast OVLO recovery time (tSWOV) taken by the
TPS259470x variants to turn on fully and start delivering current to the load.
t SW ꢀs ì I
A
( )
(
)
LOAD
VOUT
V
(
)
= min VIN1,VIN2
-
)
(
)
min
(
COUT ꢀF
(
)
(19)
While switching from auxiliary supply (VIN2) to primary supply (VIN1), the minimum bus voltage can be calculated
using Equation 20. Here the maximum switchover time is equal to the RCB recovery time (tSWRCB), depending
on whether VIN1 is equal to or lower than VIN2 to start with.
t SWRCB ꢀs ì I
A
( )
(
)
LOAD
VOUT
V
(
)
= min VIN1,VIN2 - V
V -
)
FWDTH
)
(
(
)
min
(
COUT ꢀF
(
)
(20)
The AUXOFF pins of the devices can be used as a digital indication to identify which of the 2 supplies is active
and delivering power to the load.
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VOUT
IN
OUT
VIN1
VLOGIC
EN/UVLO
OVLO
COUT
TPS259470x
FLT
AUXOFF
IN1 supply active
IN
OUT
VIN2
VLOGIC
EN/UVLO
TPS259470x
FLT
IN2 supply active
AUXOFF
OVLO
Figure 9-6. Priority Power MUXing with 2 x TPS259470x - Option 1
This configuration provides the most compact priority power MUXing solution with multiple benefits, including
active current limit protection on both channels as well as overvoltage protection on primary channel. It also
provides the fast switchover time from primary to auxiliary, but at the cost of a slightly increased quiescent
current on the auxiliary path while primary path is active. Also, it uses the fewest external components, but at the
cost of bypassing overvoltage protection on auxiliary channel.
The following waveforms illustrate the TPS259470x performance in a priority power MUXing configuration.
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Figure 9-7. TPS259470x Power MUX - Switchover from Primary to Auxiliary Supply
Figure 9-8. TPS259470x Power MUX - Switchover from Auxiliary to Primary Supply
There's a possible variation to the above configuration in case overvoltage protection is needed on both
channels. This needs an additional signal N-FET to drive the OVLO pin of the auxiliary path device as shown in
Figure 9-9 below. The switchover times are similar to the previous configuration.
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VOUT
IN
OUT
VIN1
VLOGIC
EN/UVLO
OVLO
COUT
TPS259470x
FLT
AUXOFF
IN1 supply active
IN
OUT
VIN2
VLOGIC
EN/UVLO
OVLO
TPS259470x
FLT
AUXOFF
IN2 supply active
Figure 9-9. Priority Power MUXing with 2 x TPS259470x - Option 2
Another variation of the previous configuration ensures minimum quiescent current on the auxiliary chanel while
primary channel is active, but at the cost of additional N-FET to drive the EN/UVLO pin of auxiliary path device
as shown in Figure 9-10 below. At the same time, it has a higher switchover delay from primary to auxiliary
supply as compared to the previous configuration.
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VOUT
IN
OUT
VIN1
VLOGIC
EN/UVLO
OVLO
COUT
TPS259470x
FLT
AUXOFF
IN1 supply active
IN
OUT
VIN2
VLOGIC
EN/UVLO
OVLO
TPS259470x
FLT
IN2 supply active
AUXOFF
Figure 9-10. Priority Power MUXing with 2 x TPS259470x - Option 3
While switching from a higher supply rail to lower supply rail, the minimum bus voltage can be calculated using
Equation 21. Here, the switchover time is equal to the time taken by the device to come out of reverse current
blocking state (tSWRCB).
t SWRCB ꢀs ì I
A
( )
(
)
LOAD
VOUT
V
(
)
= min VIN1,VIN2 - V
V -
)
FWDTH
)
(
(
)
min
(
COUT ꢀF
(
)
(21)
While switching from a lower supply rail to higher supply rail, the minimum bus voltage can be calculated using
Equation 22. Here, the switchover time (tSW) is the time taken by the device to turn on fully and start delivering
current to the load, which is equal to the device turn-on time (tON), which in turn includes the turn-on delay (tD,ON
)
and rise time (tR) determined by the dVdt capacitor (CdVdt) and bus voltage.
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t SW ꢀs ì I
A
( )
(
)
LOAD
VOUT
V
= min VIN1,VIN2
-
(
)
(
)
min
(
)
COUT ꢀF
(
)
(22)
All the preceding configurations provide a priority power MUXing solution with active current limit protection
response. In case circuit breaker response is prefered, it is possible to implement a solution using 2
TPS259474x devices as shown in Figure 9-11 below. Here, the EN/UVLO signal of the primary path device is
used to control the OVLO of the auxiliary path device. This ensures that auxiliary path device is turned on only
when the primary supply falls below a user-defined undervoltage (UVLO) threshold. In this configuration, supply
overvoltage protection is not available on both channels. The PG pins of the devices can be used as a digital
indication to identify which of the 2 supplies is active and delivering power to the load.
VOUT
IN
OUT
VIN1
VLOGIC
EN/UVLO
PGTH
COUT
TPS259474x
OVLO
IN1 supply active
PG
IN
OUT
VIN2
VLOGIC
EN/UVLO
PGTH
TPS259474x
IN2 supply active
PG
OVLO
Figure 9-11. Priority power MUXing with 2 x TPS259474x
While switching from one supply rail to the other, the minimum bus voltage can be calculated using Equation 23.
Here, the maximum switchover time (tSW) is the time taken by the device to turn on and start delivering power to
the load, which is equal to the device turn-on time (tON), which in turn includes the turn-on delay (tD,ON) and rise
time (tR) determined by the dVdt capacitor (CdVdt) and bus voltage.
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t SW ꢀs ì I
A
( )
(
)
LOAD
VOUT
V
(
)
= min VIN1,VIN2
-
)
(
)
min
(
COUT ꢀF
(
)
(23)
Note
1. The TPS259472x (OVC variants) are not recommended for use in power MUXing or ORing
applications. While the device is in clamping state, if the output is forced to a higher voltage by the
other channel, the device can get damaged.
2. Power MUXing can be done either between two similar rails (such as 12-V Primary & 12-V Aux,
3.3-V Primary & 3.3-V Aux) or between dissimilar rails (such as 12-V Primary & 5-V Aux or or vice
versa).
3. For power MUXing cases with skewed voltage combinations, care must be taken to design circuit
components on PGTH/EN/OVLO pins for the lower voltage channel devices such that the Absolute
maximum ratings on those pins are not exceeded when higher voltage is present on the other
channel. Also, the dVdt pin capacitor rating should be chosen based on the highest of the 2
supplies. Refer to Recommended Operating Conditions table for more details.
9.5 USB PD Port Protection
End equipments like PC, Notebooks, Docking Stations, Monitors etc.. have USB PD ports which can be
configured as DFP (Source), UFP (Sink) or DRP (Source+Sink). TPS259470x can be used independently or in
conjunction with LM73100 to handle the power path protection requirements of USB PD ports as shown in
Figure 9-12 below.
TPS259470x provides Overcurrent & Short-Circuit protection in the source path, while blocking any reverse
current from the port to the internal source power rail. The fast recovery (tSWRCB) from reverse current blocking
ensures minimum supply droop during Fast Role Swap (FRS) events. The PD controller can also use the OVLO
pin as an active low enable signal to control the power path. Holding the OVLO pin high keeps the device in OFF
state in sink mode and blocks current in both directions. Once the PD controller determines the need to start
sourcing power, it can pull the OVLO pin low to trigger a fast recovery from OFF to ON state within tSWOV
meeting the FRS timing requirements.
,
The LM73100 provides overvoltage protection on the sink path, while blocking reverse current from internal sink
rail to the port.
The linear ORing mechanism in TPS259470x & LM73100 ensures that there's no reverse current flowing from
one power source to the other during fast or slow ramp of either supply.
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VOUT = 5 V to 20 V
IN
OUT
OVLO
IMON
LM73100
PGTH
dVdt
PG
EN/UVLO
GND
VBUS = 5 V to 20V
CDVDT
PD Controller
EN/UVLO
OVLO
FLT
IN
OUT
VIN = 5 V to 20 V
TPS259470L
AUXOFF
ITIMER dVdt
ILM
GND
RILM
CDVDT
CITIMER
Figure 9-12. USB PD Port Protection
The waveform below shows the TPS259470x behavior when a 20 V source connected at the USB bus is
suddenly disconnected. The TPS259470x is initially in reverse current blocking condition. As the bus voltage
starts drooping, the TPS259470x exits the condition and performs a fast charge to restore the bus voltage above
vSafe5V(min) within tSWRCB, thereby meeting the USB Fast Role Swap requirements.
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VIN = 5 V, COUT = 10 μF, ROUT = 8 Ω, VOUT = 20 V initially and then disconnected
Figure 9-13. TPS259470x 5-V Source Path - USB Fast Role Swap Response
9.6 Parallel Operation
Applications which need higher steady current can use 2 TPS25947xx devices connected in parallel as shown in
Figure 9-14 below. In this configuration, the first device turns on initially to provide the inrush current limiting. The
second device is held in an OFF state by driving its EN/UVLO pin low using the AUXOFF/PG signal of the first
device. Once the inrush sequence is complete, the first device asserts its AUXOFF/PG pin high and turns on the
second device. The second device asserts its AUXOFF/PG signal to indicate when it has turned on fully, thereby
indicating to the system that the parallel combination is ready to deliver the full steady state current.
Once in steady state, both devices share current nearly equally. There could be a slight skew in the currents
depending on the part-to-part variation in the RON as well as the PCB trace resistance mismatch.
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IN
OUT
VLOGIC
EN/UVLO
OVLO
TPS259470x
AUXOFF
FLT
ITIMER dVdt
ILM
GND
VIN = 2.7 to 23 V
VOUT
COUT
IN
OUT
EN/UVLO
OVLO
TPS259470x
To
downstream
enable
AUXOFF
FLT
ITIMER dVdt
ILM
GND
Figure 9-14. Two Devices Connected in Parallel for Higher Steady State Current Capability
The waveforms below illustrate the behavior of the parallel configuration during start-up as well as during steady
state.
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Figure 9-15. Parallel Devices Sequencing During Start-Up
Figure 9-16. Parallel Devices Response to Overload During Steady State
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9.7 Application Limitations
This section highlights some limitations in the application which were identified during bench evaluation of the
existing TPS25947xx silicon on the evaluation module (EVM). A design fix will be included in the final release of
the IC.
Device behavior during output hard short-circuit
During a output hot-short event, the device will perform a fast-trip and protect the system and itself. After a fast-
trip, the device is expected to attempt one retry in a current limited manner for fast recovery. However, if the
current through the device exceeds 30 A before the fast-trip, the device may undergo a reset and will restart in a
dVdt limited manner instead. This is applicable to all TPS25947xx variants. In addition, for the TPS259470x
variants, the AUXOFF signal will get de-asserted even if the input supply is still valid.
This is most likely to happen at higher supply voltages and very severe shorts where the current can build up
very quickly to high levels before the device can respond.
This effect is more pronounced if the device is carrying no or very low load current (< ~1 A) before the short-
circuit event.
System Impact:
1. For single channel eFuse use cases, there’s little/no impact on the protection response and overall
functionality. After restarting into short, the device will enter current limit followed by thermal shutdown
eventually. For the TPS259470x variants, there may be a false de-assertion of the AUXOFF pin even if the
input supply is still valid.
2. In priority power MUXing configuration, during an output hot-short event, the system could switch over to the
auxiliary power channel for some time even if the primary channel supply is still valid.
Workaround:
1. At lower supply voltages and/or in practical system conditions, multiple factors (the nature/location of the
short, higher power path inductance, limtied power supply capacity, higher output capacitor) could prevent the
current through the power switch from building up to very high levels and prevent this scenario.
2. This effect is also less pronounced if there’s a steady state load current of ~1 A or higher through the device
at all times when it’s enabled.
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10 Power Supply Recommendations
The TPS25947xx devices are designed for a supply voltage range of 2.7 V ≤ VIN ≤ 23 V. An input ceramic
bypass capacitor higher than 0.1 μF is recommended if the input supply is located more than a few inches from
the device. The power supply must be rated higher than the set current limit to avoid voltage droops during
overcurrent and short-circuit conditions.
The maximum reverse voltage the devices can handle at the input is limited to (VOUT – 19 V). Any low voltage
signals (e.g. EN/UVLO, OVLO, PGTH) derived from the input supply must have a sufficiently large pull-up
resistor to limit the current through those pins to < 10 μA during reverse polarity conditions.
10.1 Transient Protection
In the case of a short-circuit and overload current limit when the device interrupts current flow, the input
inductance generates a positive voltage spike on the input, and the output inductance generates a negative
voltage spike on the output. The peak amplitude of voltage spikes (transients) is dependent on the value of
inductance in series to the input or output of the device. Such transients can exceed the absolute maximum
ratings of the device if steps are not taken to address the issue. Typical methods for addressing transients
include:
• Minimize lead length and inductance into and out of the device.
• Use a large PCB GND plane.
• Use a Schottky diode across the output to absorb negative spikes.
• Use a low-value ceramic capacitor CIN = 1 μF to absorb the energy and dampen the transients. The capacitor
voltage rating should be atleast twice the input supply voltage to be able to withstand the positive voltage
excursion during inductive ringing.
The approximate value of input capacitance can be estimated with Equation 24:
LIN
VSPIKE(Absolute) = VIN + ILOAD x
CIN
(24)
where
• VIN is the nominal supply voltage.
• ILOAD is the load current.
• LIN equals the effective inductance seen looking into the source.
• CIN is the capacitance present at the input.
Some applications may require the addition of a Transient Voltage Suppressor (TVS) to prevent transients from
exceeding the absolute maximum ratings of the device. In some cases, even if the maximum amplitude of the
transients is below the absolute maximum rating of the device, a TVS can help to absorb the excessive energy
dump and prevent it from creating very fast transient voltages on the input supply pin of the IC, which can couple
to the internal control circuits and cause unexpected behavior.
Note
If there's a likelihood of input reverse polarity in the system, it's recommended to use a bi-directional
TVS, or a reverse blocking diode in series with the TVS.
For applications such as USB-C ports where a powered cable can be plugged to the output of the device, there
could be excess voltage stress from OUT to IN which exceeds the absolute maximum rating of the device. It's
recommended to add a TVS diode from OUT to IN to clamp the voltage to a safe level.
The circuit implementation with optional protection components is shown in Figure 10-1.
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D3
D4
VOUT
VIN = 2.7 to 23 V
IN
OUT
R1
R2
COUT
D2
EN/UVLO
OVLO
TPS259470x
CIN
AUXOFF
FLT
D1
ITIMER dVdt
ILM
GND
R3
RILM
CITIMER
CDVDT
Figure 10-1. Circuit Implementation with Optional Protection Components
10.2 Output Short-Circuit Measurements
It is difficult to obtain repeatable and similar short-circuit testing results. The following contribute to variation in
results:
• Source bypassing
• Input leads
• Circuit layout
• Component selection
• Output shorting method
• Relative location of the short
• Instrumentation
The actual short exhibits a certain degree of randomness because it microscopically bounces and arcs. Ensure
that configuration and methods are used to obtain realistic results. Do not expect to see waveforms exactly like
those in this data sheet because every setup is different.
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11 Layout
11.1 Layout Guidelines
•
•
For all applications, a ceramic decoupling capacitor of 0.1 μF or greater is recommended between the IN
terminal and GND terminal.
The optimal placement of the decoupling capacitor is closest to the IN and GND terminals of the device. Care
must be taken to minimize the loop area formed by the bypass-capacitor connection, the IN terminal, and the
GND terminal of the IC.
•
•
High current-carrying power-path connections must be as short as possible and must be sized to carry at
least twice the full-load current.
The GND terminal must be tied to the PCB ground plane at the terminal of the IC with the shortest possible
trace. The PCB ground must be a copper plane or island on the board. It's recommended to have a separate
ground plane island for the eFuse. This plane doesn't carry any high currents and serves as a quiet ground
reference for all the critical analog signals of the eFuse. The device ground plane should be connected to the
system power ground plane using a star connection.
•
•
The IN and OUT pins are used for heat dissipation. Connect to as much copper area on top and bottom PCB
layers using as possible with thermal vias. The vias under the device also help to minimize the voltage
gradient accross the IN and OUT pads and distribute current unformly through the device, which is essential
to achieve the best on-resistance and current sense accuracy.
Locate the following support components close to their connection pins:
– RILM
– CdVdT
– CITIMER
– Resistors for the EN/UVLO, OVLO/OVCSEL and PGTH pins
•
Connect the other end of the component to the GND pin of the device with shortest trace length. The trace
routing for the RILM, CITIMER and CdVdt components to the device must be as short as possible to reduce
parasitic effects on the current limit , overcurrent blanking interval and soft start timing. It's recommended to
keep parasitic capacitance on ILM pin below 50 pF to ensure stable operation. These traces must not have
any coupling to switching signals on the board.
•
•
Since the bias current on ILM pin directly controls the overcurrent protection behavior of the device, the PCB
routing of this node must be kept away from any noisy (switching) signals.
Protection devices such as TVS, snubbers, capacitors, or diodes must be placed physically close to the
device they are intended to protect. These protection devices must be routed with short traces to reduce
inductance. For example, a protection Schottky diode is recommended to address negative transients due to
switching of inductive loads, and it must be physically close to the OUT pins.
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11.2 Layout Example
Inner GND layer
IN
OUT
Power layer
Top layer
Figure 11-1. Layout Example - Single TPS259474x with PGTH Referred to OUT
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Inner GND layer
OUT
IN1
Power layer
Top layer
IN2
Figure 11-2. Layout Example - 2 x TPS259470x in PowerMUX Configuration
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12 Device and Documentation Support
TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device,
generate code, and develop solutions are listed below.
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation see the following:
•
•
•
TPS25947EVM eFuse Evaluation Board
Application note - eFuses for USB Type-C protection
Application note - eFuses in smart e-meters
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
12.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.6 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
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13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OUTLINE
VQFN-HR - 1 mm max height
RPW0010A
PLASTIC QUAD FLATPACK - NO LEAD
2.1
1.9
A
B
2.1
1.9
PIN 1 IDENTIFICATION
(0.1) TYP
1 MAX
C
SEATING PLANE
0.05
0.00
0.08
C
2X 1.45
PKG
4X
SQ (0.15) TYP
4X 0.475
2X 0.25
6
5
4
7
0.35
0.25
4X
4X 0.475
0.1
C A B
0.05
C
2.1
1.9
2X
2X 0.45
PKG
0.3
4X
0.2
0.1
0.05
C A B
1
10
C
0.3
0.2
PIN 1 ID
(OPTIONAL)
4X
0.5
0.3
0.35
0.25
8X
2X
0.1
C A B
0.1
C A B
0.05
C
0.05
C
4225183/A 08/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
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EXAMPLE BOARD LAYOUT
VQFN-HR - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
RPW0010A
(1.8)
(1.45)
4X (0.475)
2X (0.25)
1
10
4X (0.25)
4X
(0.225)
PKG
2X
(2.4)
2X
(1.75)
4X (0.3)
4X (0.475)
7
4
4X
(0.65)
(R0.05) TYP
6
4X (0.25)
5
2X (0.3)
PKG
8X (0.6)
LAND PATTERN EXAMPLE
SCALE: 30X
SOLDER MASK
OPENING
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
METAL
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
EXPOSED METAL
EXPOSED METAL
SOLDER MASK
DEFINED
NON- SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
NOT TO SCALE
4225183/A 08/2019
NOTES: (continued)
3. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271).
4. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
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58
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Product Folder Links: TPS25947
TPS25947
SLVSFC9 – OCTOBER 2020
www.ti.com
EXAMPLE STENCIL DESIGN
VQFN-HR - 1 mm max height
RPW0010A
PLASTIC QUAD FLATPACK - NO LEAD
(1.8)
(1.425)
4X (0.4625)
2X (0.25)
METAL TYP
1
10
4X (0.25)
4X
(0.63)
PKG
2X
(1.75)
4X (0.225)
4X (0.275)
4X
4X (0.4625)
(1.06)
7
4X
4
(0.65)
(R0.05)
TYP
6
4X (0.225)
5
4X (0.28)
PKG
8X (0.6)
SOLDER PASTE EXAMPLE
BASED ON 0.100 mm THICK STENCIL
PADS 1, 4,7 & 10: 93%; PADS 5 & 6: 82%
SCALE: 30X
4225183/A 08/2019
NOTES: (continued)
5.
Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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Submit Document Feedback
59
Product Folder Links: TPS25947
PACKAGE OPTION ADDENDUM
www.ti.com
12-Oct-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
PTPS259470LRPWR
PTPS259472ARPWR
PTPS259474LRPWR
ACTIVE
ACTIVE
ACTIVE
VQFN-HR
VQFN-HR
VQFN-HR
RPW
RPW
RPW
10
10
10
3000
3000
3000
TBD
TBD
TBD
Call TI
Call TI
Call TI
Call TI
-40 to 125
-40 to 125
-40 to 125
Call TI
Call TI
TPS259470ARPWR
TPS259470LRPWR
TPS259472ARPWR
TPS259472LRPWR
TPS259474ARPWR
TPS259474LRPWR
PREVIEW VQFN-HR
PREVIEW VQFN-HR
PREVIEW VQFN-HR
PREVIEW VQFN-HR
PREVIEW VQFN-HR
PREVIEW VQFN-HR
RPW
RPW
RPW
RPW
RPW
RPW
10
10
10
10
10
10
3000
3000
3000
3000
3000
3000
TBD
TBD
TBD
TBD
TBD
TBD
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
12-Oct-2020
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
permission to use these resources only for development of an application that uses the TI products described in the resource. Other
reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third
party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims,
damages, costs, losses, and liabilities arising out of your use of these resources.
TI’s products are provided subject to TI’s Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on
ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable
warranties or warranty disclaimers for TI products.
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2020, Texas Instruments Incorporated
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