TPS259530DSGR [TI]
采用小型 WSON 封装、具有过压保护功能的 2.7V 至 18V、34mΩ、0.5A 至 4A 电子保险丝 | DSG | 8 | -40 to 125;
| 型号： | TPS259530DSGR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 采用小型 WSON 封装、具有过压保护功能的 2.7V 至 18V、34mΩ、0.5A 至 4A 电子保险丝 | DSG | 8 | -40 to 125 电子 光电二极管 |
| 文件： | 总49页 (文件大小：5565K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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TPS2595
ZHCSHV0C –JUNE 2017–REVISED APRIL 2018
TPS2595xx 2.7V 至 18V、4A、34mΩ 电子保险丝，具有快速过压保护
1 特性
3 说明
1
•
宽输入电压范围：2.7V 至 18V
TPS2595xx 系列电子保险丝（集成式 FET 热插拔设
备）是小型封装内高度集成电路的保护和电源管理解决
方案。这些设备只需很少的外部组件即可提供多种保护
模式，能够非常有效地抵御过载、短路、电压浪涌和过
多浪涌电流。
–
–
绝对最大值为 20V
TPS2595x5 版本：3V 至 18V
•
•
低导通电阻：RON = 34mΩ（典型值）
快速过压保护钳位（3.8V、5.7V 和 13.7V），响应
时间 5µs（典型值）
输出电流限制级别可通过单个外部电阻设定。还可能通
过测量整个电流限制电阻的压降实现对输出负载电流的
准确感应。对 浪涌电流有特别要求的应用可以通过单
个外部电容器设定输出转换率。过压事件由内部钳位电
路快速限制在一个安全的固定最大值，而无需外部组
件。TPS259573 型号提供可以设置用户定义过压截止
阈值的选项。
•
•
•
TPS2595x0、TPS2595x1、TPS2595x5：带有可
调节欠压锁定 (UVLO) 的高电平有效使能输入
TPS2595x3：带有可调节过压锁定 (OVLO) 的低电
平有效使能输入
配备负载电流监控器输出 (ILM) 的可调节电流限制
–
–
电流范围：0.5A 至 4A
电流限制准确度：±7.5%
•
•
•
•
可调节的输出转换率控制 (dVdt)
过热保护 (OTP)
在 TPS2595x5 型号中，可通过将 OUT 引脚连接到
QOD 引脚实施快速输出放电功能。
故障指示引脚 (FLT)
这些器件的独特运行温度范围为 –40°C 至 +125°C。
UL 2367 认证 – 文件号E169910
器件信息(1)
–
RILM >= 487Ω（最大电流 4.42A）
器件型号
封装
WSON (8)
封装尺寸（标称值）
•
•
IEC 62368-1 认证
TPS2595xxDSG
2.00mm x 2.00mm
单点故障测试期间安全 (IEC 62368-1)
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
–
ILM 引脚断开/短路检测
2 应用
•
•
•
•
•
•
•
•
热插拔
适配器供电型系统
多功能打印机
固态硬盘 (SSD) 和硬盘 (HDD)
工业系统
白色家电
机顶盒
数字电视
简化原理图
TPS25953x 过压钳位响应时间
TPS2595xx
Power
Supply
IN
OUT
VFLT
RVL1
RFLT
0.7 μs
EN/UVLO
dVdt
FLT
ILM
Fault
CIN
COUT
ROUT
GND
RVL2
CdVdt
RILM
Copyright © 2017, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SLVSE57
TPS2595
ZHCSHV0C –JUNE 2017–REVISED APRIL 2018
www.ti.com.cn
目录
8.4 Device Functional Modes........................................ 25
Application and Implementation ........................ 27
9.1 Application Information............................................ 27
9.2 Typical Application ................................................. 27
1
2
3
4
5
6
7
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Device Comparison Table..................................... 3
Pin Configuration and Functions......................... 4
Specifications......................................................... 5
7.1 Absolute Maximum Ratings ...................................... 5
7.2 ESD Ratings ............................................................ 5
7.3 Recommended Operating Conditions....................... 5
7.4 Thermal Information ................................................. 6
7.5 Electrical Characteristics........................................... 7
7.6 Switching Characteristics.......................................... 8
7.7 Typical Characteristics............................................ 10
Detailed Description ............................................ 18
8.1 Overview ................................................................. 18
8.2 Functional Block Diagram ....................................... 18
8.3 Feature Description................................................. 18
9
10 Power Supply Recommendations ..................... 33
10.1 Transient Protection.............................................. 33
10.2 Output Short-Circuit Measurements ..................... 34
11 Layout................................................................... 34
11.1 Layout Guidelines ................................................. 34
11.2 Layout Example .................................................... 35
12 器件和文档支持 ..................................................... 36
12.1 文档支持................................................................ 36
12.2 接收文档更新通知 ................................................. 36
12.3 社区资源................................................................ 36
12.4 商标....................................................................... 36
12.5 静电放电警告......................................................... 36
12.6 术语表 ................................................................... 36
13 机械、封装和可订购信息....................................... 37
8
4 修订历史记录
Changes from Revision B (March 2018) to Revision C
Page
•
•
已添加 将 (IEC 62368-1) 添加到特性 部分中的单点故障测试期间安全 .................................................................................. 1
Changed UL 60950 to IEC 62368-1 in the Specifications Electrical Characteristics table .................................................... 5
Changes from Revision A (December 2017) to Revision B
Page
•
已更改 multiplication symbol to an equal symbol before 229.2 mW in 公式 15 ................................................................... 29
Changes from Original (June 2017) to Revision A
Page
•
将状态从预告信息更改成了生产数据 ..................................................................................................................................... 1
2
Copyright © 2017–2018, Texas Instruments Incorporated
TPS2595
www.ti.com.cn
ZHCSHV0C –JUNE 2017–REVISED APRIL 2018
5 Device Comparison Table
RESPONSE TO THERMAL
SHUTDOWN (TSD)
QUICK OUTPUT
ENABLE
DEVICE NUMBER
OUTPUT VOLTAGE CLAMP
DISCHARGE
TPS259520DSG
TPS259521DSG
TPS259530DSG
TPS259531DSG
TPS259533DSG
TPS259540DSG
TPS259541DSG
TPS259570DSG
TPS259571DSG
3.8 V (typ)
3.8 V (typ)
Latch-off
Auto-retry
Latch-off
Auto-retry
Auto-retry
Latch-off
Auto-retry
Latch-off
Auto-retry
Active high
Active high
Active high
Active high
Active low
Active high
Active high
Active high
Active high
No
No
No
No
No
No
No
No
No
5.7 V (typ)
5.7 V (typ)
5.7 V (typ)
13.7 V (typ)
13.7 V (typ)
No OV clamp
No OV clamp
Programmable Overvoltage
Lockout
TPS259573DSG
Auto-retry
Active low
No
TPS259525DSG
TPS259535DSG
3.8 V (typ)
5.7 V (typ)
Auto-retry
Auto-retry
Active high
Active high
Yes
Yes
Copyright © 2017–2018, Texas Instruments Incorporated
3
TPS2595
ZHCSHV0C –JUNE 2017–REVISED APRIL 2018
www.ti.com.cn
6 Pin Configuration and Functions
TPS2595x0/1 DSG Package
8-Pin WSON
TPS2595x5 DSG Package
8-Pin WSON
Top View
Top View
GND
dVdt
8
1
GND
dVdt
8
1
7
6
2
3
ILM
FLT
EN/UVLO
IN
7
6
2
ILM
EN/UVLO
IN
GND
(PAD)
GND
(PAD)
3
QOD
OUT
OUT
5
4
IN
5
4
IN
TPS2595x3 DSG Package
8-Pin WSON
Top View
GND
dVdt
8
1
7
6
2
ILM
FLT
EN/OVLO
IN
GND
(PAD)
3
OUT
5
4
IN
Pin Functions
PIN
TYPE
DESCRIPTION
NO.
NAME
A capacitor from this pin to GND sets the output turn on slew rate. Leave this pin
floating for the fastest turn on slew rate. (See Switching Characteristics).
1
dVdt
Analog I/O
Active high enable for the TPS2595x0, TPS2595x1, TPS2595x5 variants. A resistor
divider can be used to adjust the undervoltage lockout threshold. Do not leave floating.
EN/UVLO
EN/OVLO
2
Analog input
Active low enable for the TPS2595x3 variants. A resistor divider can be used to adjust
the overvoltage lockout threshold. Do not leave floating.
3,4
5
IN
Power
Power
Power input
OUT
Power output
TPS2595x0, TPS2595x1, TPS2595x3: Fault event indicator which is pulled low when a
fault is detected. It is an open drain output that requires an external pull up resistance.
FLT
6
7
Digital output
TPS2595x5: Quick Output Discharge Pin, when tied to OUT directly or through external
resistor.
QOD
This is a dual function pin used to limit and monitor the output current. An external
resistor from this pin to GND sets the output current limit. The pin voltage can also be
used to monitor the output load current. Do not leave floating.
ILM
Analog I/O
Ground
8
GND
GND
Ground
PAD
Thermal/Ground The exposed pad is used primarily for heat dissipation and must be connected to GND.
4
Copyright © 2017–2018, Texas Instruments Incorporated
TPS2595
www.ti.com.cn
ZHCSHV0C –JUNE 2017–REVISED APRIL 2018
7 Specifications
7.1 Absolute Maximum Ratings
Over operating free-air temperature range (unless otherwise noted)(1)
MIN
–0.3
–0.3
–1.2
–0.3
MAX
20
UNIT
VIN
Maximum input voltage
IN
V
V
V
V
VOUT
VOUT,PLS
VEN
Maximum output voltage
OUT
OUT
VIN + 0.3
Minimum output voltage pulse (< 1 µs)
Maximum enable pin voltage
EN/UVLO or
EN/OVLO
7
VFLTB
VQOD
VdVdt
IFLTB
Maximum fault pin voltage (TPS2595x0/1/3)
Maximum QOD pin voltage (TPS2595x5)
Maximum dVdt pin voltage
FLT
–0.3
–0.3
7
7
V
V
QOD
dVdt
2.5
10
V
Maximum fault pin sink current
Maximum continuous switch current
Maximum junction temperature
Maximum lead temperature
FLT
mA
IMAX
IN to OUT
Internally limited
Internally limited
300
–65 150
TJ,MAX
TLEAD
TSTG
°C
°C
Storage temperature
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
7.2 ESD Ratings
VALUE
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
±2500
V(ESD)
Electrostatic discharge
V
Charged-device model (CDM), per JEDEC specification JESD22-
C101(2)
±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
Over operating free-air temperature range (unless otherwise noted)
MIN
MAX
UNIT
(1)
VIN
Input voltage range (TPS2595x0/1/3)
Input voltage range (TPS2595x5)
Output voltage
IN
2.7
3.0
0
18
V
V
V
VIN
IN
18(1)
VOUT
OUT
VIN + 0.3
EN/UVLO or
EN/OVLO
VEN
Enable pin voltage
0
6(2)
V
VFLTB
VQOD
Fault pin voltage (TPS2595x0/1/3)
Fault pin voltage (TPS2595x5)
FLT
0
0
6
6
V
V
QOD
Continuous output current (TJ = –40 to 125οC)
Continuous output current (TJ = –40 to 105οC)
ILM pin resistance (Active Current Limiting Operation)
dVdt capacitor value
IN to OUT
IN to OUT
ILM
4
5(3)
A
IMAX
A
RILM
CdVdt
VdVdt
TJ
487
3300
4
5000
Ω
dVdt
pF
V
dVdt pin capacitor voltage rating
dVdt
Operating junction temperature
–40
125
°C
(1) The nominal input voltage should be limited to the output clamp voltage for the selected device option as listed in the Electrical
Characteristics section
(2) For supply voltages below 6V, it is okay to pull up the EN pin to IN directly. For supply voltages greater than 6V, it is recommended to
use an appropriate resistor divider between IN, EN and GND to ensure the voltage at the EN pin is within the specified limits.
(3) Guaranteed by design. Not tested at production.
Copyright © 2017–2018, Texas Instruments Incorporated
5
TPS2595
ZHCSHV0C –JUNE 2017–REVISED APRIL 2018
www.ti.com.cn
7.4 Thermal Information
TPS2595x
(1)
THERMAL METRIC
DSG (WSON)
UNIT
8 PINS
65.6
73.3
28.3
2
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
ψJB
28.4
9.8
RθJC(bot)
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6
Copyright © 2017–2018, Texas Instruments Incorporated
TPS2595
www.ti.com.cn
ZHCSHV0C –JUNE 2017–REVISED APRIL 2018
7.5 Electrical Characteristics
(Test conditions unless otherwise noted) –40°C ≤ TJ ≤ 125°C, VIN = 12 V for TPS25954x/7x, VIN = 5 V for TPS25953x, VIN
=
3.3 V for TPS25952x, VEN = 5 V (= 0 V for TPS2595x3 only) , RILM = 487 Ω , CdVdT = Open, OUT = Open. All voltages
referenced to GND.
PARAMETER
INPUT SUPPLY (IN)
TEST CONDITIONS
MIN
TYP
MAX UNIT
TPS2595x0/1/5
TPS2595x3
V
EN ≥ VUVLO
EN ≤ VOVLO
IQ
IN quiescent current
175
250
µA
V
V
IN ≤ 5 V
0.04
0.45
45
µA
µA
µA
V
TPS2595x0/1/5
VEN < 0.5V
ISD
IN shutdown current
5 V < VIN ≤ 18 V
2
65
TPS2595x3
VEN > 2 V
VIN Rising
VIN Falling
VIN Rising
VIN Falling
TPS2595x5
2.7
2.58
2.44
2.33
2.8
2.9
TPS2595x5
2.68
2.54
2.43
2.78
2.64
2.53
V
IN Undervoltage Protection
Threshold
VUVP
TPS2595x0/1/3
TPS2595x0/1/3
V
V
OUTPUT VOLTAGE CLAMP (OUT)
TPS25952x
TPS25953x
TPS25954x
TPS25952x
3.65
5.5
3.87
5.7
4.1
5.9
V
V
VOVC
Overvoltage clamp threshold(1)
VIN Rising, ROUT = 10 kΩ
VIN ≥ VOVC, IOUT = 10 mA
13.3
3.4
13.7
3.6
14.3
3.8
V
V
VCLAMP
Output voltage while clamping(1) TPS25953x
5.2
5.45
5.7
V
TPS25954x
13 13.55
14.1
V
IOUT = 4 A
5
µs
µs
tOVC
Output clamp response time(1)
TPS25952x/3x/4x
IOUT = 100 mA
10
OUTPUT CURRENT LIMIT AND MONITOR (ILM)
Current monitor gain as
measured on ILM pin
IOUT = 4 A
254
276
276
299 µA/A
304 µA/A
GIMON
IOUT = 1 A
249
(IILM / IOUT
)
RILM = 487 Ω
3.87
1.09
0.46
4.17
1.17
0.49
0
4.42
1.24
0.52
A
A
A
A
RILM = 1780 Ω
RILM = 4420 Ω(3)
ILIMIT
IOUT Current limit(2)
RILM = Open (Single Point Failure Test IEC 62368-1)
IOUT Circuit Breaker Threshold
during RILM Short condition
RILM = Short to GND (Single Point Failure Test IEC 62368-
1)
ICB
3
A
tLIM
tSC
Current limit response time(2)
Short circuit response time(4)
IOUT > ILIMIT + 20% to IOUT ≤ ILIMIT
IOUT > ISC to IOUT ≤ ILIMIT
250
5
µs
µs
ON-RESISTANCE (IN - OUT)
TJ = 25°C
VIN = 4 V to 18 V TJ = –40°C to 85°C
TJ = –40°C to 125°C
34
36
37
47
53
40
51
58
mΩ
mΩ
mΩ
mΩ
mΩ
mΩ
RON
ON state resistance
TJ = 25°C
VIN = 2.7 V to 4 V TJ = –40°C to 85°C
TJ = –40°C to 125°C
(1) Refer to Fig 49
(2) Refer to Fig 50
(3) Guaranteed by design and characterization. Not tested at production.
(4) Refer to Fig 52
Copyright © 2017–2018, Texas Instruments Incorporated
7
TPS2595
ZHCSHV0C –JUNE 2017–REVISED APRIL 2018
www.ti.com.cn
Electrical Characteristics (continued)
(Test conditions unless otherwise noted) –40°C ≤ TJ ≤ 125°C, VIN = 12 V for TPS25954x/7x, VIN = 5 V for TPS25953x, VIN
3.3 V for TPS25952x, VEN = 5 V (= 0 V for TPS2595x3 only) , RILM = 487 Ω , CdVdT = Open, OUT = Open. All voltages
referenced to GND.
=
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
ENABLE / UNDERVOLTAGE LOCKOUT (EN/UVLO) - TPS2595x0/1/5
IEN
EN/UVLO pin leakage current
Undervoltage lockout threshold
–0.1
1.13
1.03
0.1
1.27
1.17
µA
VUVLO(R)
VUVLO(F)
VEN rising
VEN falling
1.2
1.1
V
V
ENABLE / OVERVOLTAGE LOCKOUT (EN/OVLO) - TPS2595x3
IEN
EN/OVLO pin leakage current
–0.1
1.13
1.03
0.1
1.27
1.17
µA
V
VOVLO(R)
VOVLO(F)
VEN rising
VEN falling
1.2
1.1
Overvoltage lockout threshold
V
Overvoltage lockout response
time
tOVLO
VEN > VOVLO to FLT ↓
3
µs
FAULT INDICATION (FLT ) - TPS2595x0/1/3
RFLTB
IFLTB
FLT pin resistance
FLT ↓
12
Ω
FLT pin leakage current
VEN = 2 V, VFLTB = 0 V to 6 V
–0.1
0.1
µA
QUICK OUTPUT DISCHARGE (QOD) - TPS2595x5
RQOD
QOD effective resistance
IN connected to EN, OUT connected to QOD, EN↓ to 1V
19
Ω
OVERTEMPERATURE PROTECTION (TSD)
TSD
Thermal shutdown
TJ Rising
TJ Falling
157
5
°C
°C
TSDHYS
Thermal shutdown hysteresis
Thermal Shutdown Auto-Retry
Interval
Device Enabled and TJ < TSD -
tTSD,RST
TPS2595x1/3/5
TSDHYS
93
ms
7.6 Switching Characteristics
Typical Values are taken at TJ = 25°C unless specifically noted otherwise. ROUT = 100 Ω, COUT = 1 µF
PARAMETER
VIN
3.3 V
5 V
CdVdt = Open
16.3
21.9
38.2
147
CdVdt = 3300pF
10.0
UNIT
SRON
tD,ON
tR
Output Rising slew rate
11.6
V/ms
µs
12 V
3.3 V
5 V
12.4
254
Turn on delay
Rise time
149
289
12 V
3.3 V
5 V
153
335
157
259
179
349
µs
12 V
3.3 V
5 V
248
763
11.6
11.3
11.0
11.6
tD,OFF
Turn off delay
11.5
µs
12 V
11.4
8
版权 © 2017–2018, Texas Instruments Incorporated
TPS2595
www.ti.com.cn
ZHCSHV0C –JUNE 2017–REVISED APRIL 2018
VEN/UVLO
EN/UVLO
UVLO
0
tON
tD,OFF
90%
VIN
SRON
OUT
10%
0 V
tR
tD,ON
tF
Time
图 1. TPS2595x0, TPS2595x1, TPS2595x5 Switching Times
VEN/UVLO
EN/OVLO
OVLO
0
tON
tD,OFF
90%
VIN
SRON
OUT
10%
0 V
tR
tD,ON
tF
Time
图 2. TPS2595x3 Switching Times
版权 © 2017–2018, Texas Instruments Incorporated
9
TPS2595
ZHCSHV0C –JUNE 2017–REVISED APRIL 2018
www.ti.com.cn
7.7 Typical Characteristics
60
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
2.7 V
3.3 V
5 V
12 V
18 V
50
40
30
20
2.7 V
3.3 V
5 V
12 V
18 V
-0.1
-50
-25
0
25
50
75
100
125
150
-50
-25
0
25
50
75
100
125
Temperature (èC)
Temperature (èC)
D008
D002
IOUT = 0.5A , Different Input Voltages
图 3. On-resistance vs Temperature
TPS2595x0/1/5, EN=GND, OUT=Open, Different Input Voltages
图 4. Shutdown Current vs Temperature
2.82
2.8
2.56
2.54
2.52
2.5
2.78
2.76
2.74
2.72
2.7
2.48
Rising
Falling
2.46
2.44
2.42
2.4
2.68
2.66
2.64
Rising
Falling
-50
-25
0
25
50
75
100
125
150
-50
-25
0
25
50
75
100
125
150
Temperature (èC)
Temperature (èC)
D004
D005
TPS2595x5
TPS2595x0/1/3
图 5. UVP Threshold vs Temperature
图 6. UVP Threshold vs Temperature
1.22
1.2
1.22
1.2
Rising
Rising
1.18
1.16
1.14
1.12
1.1
1.18
1.16
1.14
1.12
1.1
2.7 V
5 V
18 V
2.7 V
5 V
2.7 V
5 V
18 V
2.7 V
5 V
18 V
18 V
Falling
Falling
-25
1.08
-50
1.08
0
25
50
75
100
125
150
-50
-25
0
25
50
75
100
125
150
Temperature (èC)
Temperature (èC)
D006
D007
TPS2595x0/1/5, Different Input Voltages
图 7. UVLO Threshold vs Temperature
TPS259573, Different Input Voltages
图 8. OVLO Threshold vs Temperature
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Typical Characteristics (接下页)
210
13.7
13.65
13.6
200
190
180
170
160
150
13.55
13.5
10 mA
1 A
3 A
13.45
13.4
13.35
13.3
13.25
13.2
-40 èC
25 èC
85 èC
105 èC
125 èC
140
13.15
0
5
10
15
20
-50
-25
0
25
50
75
100
125
150
Input Voltage (V)
Temperature (èC)
D003
D009
TPS25954x, Different Output Load Currents
图 10. OVC Threshold vs Temperature
图 9. Quiescent Current vs Input Voltage
5.55
5.5
3.7
3.6
3.5
3.4
3.3
3.2
3.1
3
5.45
5.4
10 mA
1 A
3 A
5.35
5.3
5.25
5.2
5.15
5.1
10 mA
1 A
3 A
5.05
-50
-25
0
25
50
75
100
125
150
-50
-25
0
25
50
75
100
125
150
Temperature (èC)
Temperature (èC)
D010
D011
TPS25953x, Different Output Load Currents
TPS25952x, Different Output Load Currents
图 12. OVC Threshold vs Temperature
图 11. OVC Threshold vs Temperature
10
6
5.5
5
4420 W
1780 W
1020 W
681 W
487 W
4.5
4
3.5
3
1
2.5
2
1.5
1
0.21
0.5
100
1000
10000
-50
0
50
100
150
RILM (W)
Temperature (èC)
D012
D013
VIN = 12V, Different RILM values
图 13. Output Current Limit (ILIMIT) vs RILM
图 14. Output Current Limit (ILIMIT) vs Temperature
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Typical Characteristics (接下页)
6
3
2
487 W
681 W
1020 W
1780 W
4420 W
5.5
5
4.5
4
1
3.5
3
0
2.5
2
-1
-2
-3
1.5
1
-40 èC
25 èC
85 èC
125 èC
0.5
0
1
2
3
4
5
0
1
2
3
4
5
VDS (V)
Output Current Limit (A)
D023
D027
Different RILM values
VIN = 5 V
图 15. Output Current Limit vs VDS
图 16. Output Current Limit Accuracy vs Output Current
Limit
4
3
4
3
4420 W
1780 W
1020 W
681 W
487 W
4420 W
1780 W
1020 W
681 W
487 W
2
2
1
1
0
0
-1
-2
-3
-1
-2
-3
-50
0
50
100
150
-50
0
50
100
150
Temperature (èC)
Temperature (èC)
D028
D029
VIN = 3.3 V, Different RILM values
VIN = 5 V, Different RILM values
图 17. Output Current Limit Accuracy vs Temperature
图 18. Output Current Limit Accuracy vs Temperature
281
4
3
4420 W
1780 W
1020 W
681 W
487 W
280
279
278
277
276
275
274
2
1
0
0.5 A
1 A
2 A
3 A
4 A
-1
-2
-3
-50
0
50
100
150
-50
-25
0
25
50
75
100
125
150
Temperature (èC)
Temperature (èC)
D030
D020
VIN = 12 V, Different RILM values
Different Output Load Currents
图 19. Output Current Limit Accuracy vs Temperature
图 20. Load Current Monitor Gain vs Temperature
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Typical Characteristics (接下页)
20
900
800
700
600
500
400
300
200
100
0
Maximum
Typical
Minimum
Open
3300 pF
4700 pF
6800 pF
15
10
5
0
-5
-10
-15
0
1
2
3
4
5
0
5
10
15
20
IOUT (A)
Input Voltage (V)
D031
D022
Normalized to reference value of GIMON = 276uA/A
Different CdVdt values
图 22. Turn on Delay vs Input Voltage
Open
图 21. Load Current Monitor Gain Accuracy vs Load Current
40
1800
1600
1400
1200
1000
800
Open
3300 pF
4700 pF
6800 pF
3300 pF
4700 pF
6800 pF
35
30
25
20
15
10
5
600
400
200
0
0
2.5
Different CdVdt values
图 23. ON Slew Rate vs Input Voltage
5
7.5
10
12.5
2.5
5
7.5
10
12.5
Input Voltage (V)
Input Voltage (V)
D024
D025
Different CdVdt values
图 24. Rise Time vs Input Voltage
12
11
10
9
10000
1000
100
10
-40 èC
25 èC
85 èC
125 èC
8
Open
1
3300 pF
4700 pF
6800 pF
7
6
0.1
2.5
Different CdVdt values
图 25. Turn OFF Delay vs Input Voltage
5
7.5
10
12.5
1
10
100
Input Voltage (V)
Power Dissipation (W)
D026
D001
图 26. Thermal Shutdown Time vs Power Dissipation
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Typical Characteristics (接下页)
98
2.7 V
3.3 V
5 V
12 V
18 V
96
94
92
90
88
86
-50
-25
0
25
50
75
100
125
150
Temperature (èC)
D019
TPS2595x1/3/5, Different Input Voltages
图 27. Thermal Shutdown Auto-Retry Interval vs Temperature
VIN = 12 V, COUT = 10 µF, RILM = 487 Ω, VEN = 5 V
VIN = 12 V, COUT = 10 µF, RILM = 487 Ω, VEN = 5 V
图 28. Output Voltage Ramp and Inrush Current at Start Up,
图 29. Output Voltage Ramp and Inrush Current at Start Up,
CdVdT = Open
CdVdT = 22 nF
VIN = 12 V, COUT = 1 µF, RILM = 487 Ω, ROUT = 100 Ω
图 31. Turn OFF Delay
VIN = 12 V, COUT = 1 µF, RILM = 487 Ω, ROUT = 100 Ω
图 30. Turn ON Delay
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Typical Characteristics (接下页)
VIN = 12 V, COUT = 1 µF, RILM = 487 Ω, ROUT varied from 12 Ω to
2 Ω to 12 Ω
VIN = 12 V, COUT = 1 µF, RILM = 487 Ω, ROUT varied from 12 Ω to
2 Ω to 12 Ω
图 33. TPS2595x0 Overcurrent Response
图 32. TPS2595x1, TPS2595x3, TPS2595x5 OverCurrent
Response
VIN = 12 V, COUT = 1 µF, RILM = 487 Ω
VIN = 12 V, COUT = 1 µF, RILM = 487 Ω
图 34. Output Hot Short to GND Response
图 35. Output Hot Short to GND Response (Zoomed In)
VIN = 12 V, COUT = 1 µF, RILM = 487 Ω
VIN = 12 V, COUT = 1 µF, RILM = 487 Ω
图 36. Wake Up With Output Short to GND
图 37. Wake Up With Output Short to GND (Zoomed In)
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Typical Characteristics (接下页)
VIN = 12 V, COUT = 1 µF, RILM = 487 Ω, FLT = 3.3 V through 10
kΩ
VIN = 12 V, COUT = 1 µF, RILM = 487 Ω, IOUT stepped from 4 A to
4.8 A
图 39. Hot Plug Response
图 38. Output Load Transient Response
VIN stepped from 12 V to 18 V, COUT = 1 µF, RILM = 487 Ω, FLT =
3.3 V through 10 kΩ, ROUT = 100 Ω
VIN stepped from 12 V to 18 V, COUT = 1 µF, RILM = 487 Ω, FLT =
3.3 V through 10 kΩ, ROUT = 100 Ω
图 40. TPS259573 Overvoltage Lockout Response
图 41. TPS259573 Overvoltage Lockout FLT Response
VIN stepped from 3 V to 6 V, COUT = 1 µF, RILM = 487 Ω, FLT= 3.3
V through 10 kΩ, ROUT = 10 Ω
VIN stepped from 5 V to 8 V, COUT = 1 µF, RILM = 487 Ω, FLT =
3.3 V through 10 kΩ, ROUT = 10 Ω
图 42. TPS25952x Overvoltage Clamp Response
图 43. TPS25953x Overvoltage Clamp Response
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Typical Characteristics (接下页)
VIN Stepped from 12 V to 15 V, COUT = 1 µF, RILM = 487 Ω, FLT =
3.3 V through 10 kΩ, ROUT = 20 Ω
VIN = 5 V, COUT = 1 µF, RILM = 487 Ω
图 45. TPS2595x5 Quick Output Discharge, EN stepped from
图 44. TPS25954x Overvoltage Clamp Response
5 V to 0 V
VIN
VOUT
EN
VIN = 5 V, COUT = 1 µF, RILM = 487 Ω
图 46. TPS2595x5 Quick Output Discharge, EN stepped from 5 V to 1 V
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8 Detailed Description
8.1 Overview
The TPS2595xx devices are integrated eFuse that are used to manage load voltage and load current. The
device provides various factory programmed settings and user manageable settings, which allow device
configuration for handling different transient and steady state supply and load fault conditions, thereby protecting
the input supply and the downstream circuits connected to the device. The device also uses an in-built thermal
shutdown mechanism to protect itself during these fault events.
8.2 Functional Block Diagram
3
4
5
7
IN
IN
OUT
ILM
+
Current
Limit &
Monitor
Charge
Pump
œ
OVC(4)
Driver
UVP
+
EN/UVLO(1)
2
Control
Logic
1
6
8
dVdt
œ
UVLO(3)
FLT (2)
Over Temperature
Protection
GND
(1) For TPS2595x3, this pin is EN/OVLO
(2) For TPS2595x5, this pin is QOD
(3) For TPS2595x3, this voltage is OVLO
(4) This block is not available in the TPS25957x
8.3 Feature Description
8.3.1 Undervoltage Protection (UVP) and Undervoltage Lockout (UVLO)
All the TPS2595xx devices constantly monitor the input supply to ensure that the load is powered up only when
the voltage is at a sufficient level. During the start-up condition, the device waits for the input supply to rise above
a fixed threshold VUVP before it proceeds to turn ON the FET. Similarly, during the ON condition, if the input
supply falls below the UVP threshold, the FET is turned OFF. The UVP rising and falling thresholds are slightly
different, thereby providing some hysteresis and ensuring stable operation around the threshold voltage.
The TPS2595x0, TPS2595x1, TPS2595x5 devices provide an user programmable UVLO mechanism to ensure
that the load is powered up only when the voltage is at a sufficient level. This can be achieved by dividing the
input supply and feeding it to the EN/UVLO pin. Whenever the voltage at the EN/UVLO pin falls below a
threshold VUVLO, the device turns OFF the FET. The FET is turned ON again when the voltage rises above the
threshold. The rising and falling thresholds on this pin are slightly different, thereby providing some hysteresis
and ensuring stable operation around the threshold voltage.
The user must choose the resistor divider values appropriately to map the desired input undervoltage level to the
UVLO threshold of the part. See 图 47.
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Feature Description (接下页)
VIN
R1
R2
EN
图 47. Undervoltage Lockout
VUVLO ì R1+ R2
(
)
VSUPPLY
=
R2
(1)
8.3.2 Overvoltage Protection
The TPS2595xx devices provide 2 ways to handle an input overvoltage condition.
8.3.2.1 Overvoltage Lockout (OVLO)
The TPS259573 device provides an user programmable OVLO mechanism to ensure that the supply to the load
is cut off if the input supply voltage exceeds a certain level. This can be achieved by dividing the input supply
and feeding it to the EN/OVLO pin. Whenever the voltage at the EN/OVLO pin rises above a threshold VOVLO, the
device turns OFF the FET. When the voltage at the EN/OVLO pin falls below the threshold, the FET is turned
ON again.
The user should choose the resistor divider values appropriately to map the desired input overvoltage level to the
OVLO threshold of the part.
VIN
R1
EN
R2
图 48. Overvoltage Lockout
8.3.2.2 Overvoltage Clamp (OVC)
The TPS25952x, TPS25953x, TPS25954x devices provide a mechanism to clamp the output voltage to a
predefined level quickly if the input voltage crosses a certain threshold. This ensures the load is not exposed to
high voltages on any overvoltage at the input supply, and lowers the dependency on external protection devices
(such as TVS/Zener diodes) in this condition. Once the input supply voltage rises above the OVC threshold
voltage VOVC, the device responds by clamping the voltage to VCLAMP within a very short response time tOVC. As
long as an overvoltage condition is present on the input, the output voltage will be clamped to VCLAMP. When the
input drops below the output clamp threshold VOVC, the clamp releases the output voltage. See 图 49.
During the overvoltage clamp condition, there could be significant heat dissipation in the internal FET depending
on the VIN - VOUT voltage drop and the current through the FET leading to a thermal shutdown if the condition
persists for an extended period of time. In this case, the device would either stay latched-off or start a auto retry
cycle as explained in the Overtemperature Protection (OTP) section.
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Feature Description (接下页)
VUVLO
EN
0
Input
Overvoltage
Event
Auto-Restart
with Input
Overvoltage
Input
Overvoltage
Removed
IN
VOVC
0
tOVC
VCLAMP
OUT
FLT
0
VFLT
tTSD,RST
0
TSD
TSDHYS
TJ
TJ
Time
图 49. TPS2595xx Overvoltage Clamp Response (Auto-Retry)
Multiple device options are offered with different clamping voltage thresholds. See the Device Comparison Table
for list of available voltage clamp options.
8.3.3 Inrush Current, Overcurrent and Short Circuit Protection
The TPS2595xx devices incorporates three levels of protection against overcurrent:
•
•
•
Adjustable slew rate for inrush current control (dVdt).
Active current limiting (ILIMIT) for overcurrent protection.
A fast short circuit limit (ISC) to protect against hard short circuits.
8.3.3.1 Slew Rate and Inrush Current Control (dVdt)
The inrush current during turn on is directly proportional to the load capacitance and rising slew rate. 公式 2 can
be used to find the slew rate SRON required to limit the inrush current IINRUSH for a given load capacitance COUT
.
IINRUSH mA
(
)
V
≈
’
SR ON
=
∆
«
÷
◊
ms
COUT mF
(2)
For loads requiring a slower rising slew rate, a capacitance can be added to the dVdt pin to adjust the rising slew
rate and lower the inrush current during turn on. The required CdVdt capacitance to produce a given slew rate can
be calculated using 公式 3.
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Feature Description (接下页)
42000
C dVdt pF =
(
)
V
≈
’
SR ON ∆
÷
◊
ms
«
(3)
8.3.3.2 Active Current Limiting
The load current is monitored during start-up and normal operation. When the load current exceeds the current
limit trip point ILIMIT programmed by RILM resistor, the device regulates the current to the set limit ILIMIT within tLIM
.
The device exits current limiting when the load current falls below limit. 公式 4 can be used to find the RILM value
for a desired current limit.
2000
RILM
=
I
- 0.04
LIMIT
(4)
In the current limiting state, the output voltage drops resulting in increased power dissipation in the internal FET
leading to a thermal shutdown if the condition persists for an extended period of time. In this case, the device
either stays latched-off or starts an auto retry cycle as explained in the Overtemperature Protection (OTP)
section.
Soft Short on VOUT
Auto Retry
Into Short
Auto Retry
(Short Removed)
IOUT
ILIMIT
0
VIN
OUT
FLT
0
tLIM
VFLTB
tTSD,RST
tTSD,RST
0
TSD
TSDHYS
TJ
TJ
Time
图 50. TPS2595x1, TPS2595x3, TPS2595x5 Overcurrent Response (Auto-Retry)
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Feature Description (接下页)
VUVLO
EN
0
Soft Short on VOUT
Short
Removed
Manual Restart
(Device Re-enabled)
ILIMIT
IOUT
0
VIN
OUT
FLT
0
tLIM
VFLTS
0
TSD
TSDHYS
TJ
TJ
Time
图 51. TPS2595x0 Overcurrent Response (Latch-Off)
8.3.3.3 Short Circuit Protection
The current through the device increases very rapidly during a transient short circuit event. The short circuit
threshold ISC is adjusted based on the selected current limit. When a short circuit is detected, the device quickly
limits the current to ILIMIT. The device stops limiting the current once the load current falls below the programmed
ILIMIT threshold. See 图 52.
The output voltage drops in the current limiting state, resulting in increased power dissipation in the internal FET
and leads to a thermal shutdown if the condition persists for an extended period of time. In this case, the device
either stays latched-off or starts an auto retry cycle as explained in the Overtemperature Protection (OTP)
section.
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Feature Description (接下页)
VEN/UVLO
EN
0
Hard Short on VOUT
Short Removed
IOUT
ILIM
0
VIN
OUT
0
tSC
VFLTB
FLT
0
TJ
TJ
Time
图 52. TPS2595xx Short Circuit Response
8.3.4 Overtemperature Protection (OTP)
Thermal shutdown occurs when the junction temperature TJ exceeds TSD. When the TPS2595x0 detects a
thermal overload, it shuts down and remains latched off until the device is re-enabled or power cycled. When the
TPS2595x1, TPS2595x3, TPS2595x5 devices detects a thermal overload, it remains off until the TJ decreases by
TSDHYS and then waits for an additional delay of tTSD,RST after which it automatically retries to turn on if it is still
enabled. See 表 1.
表 1. TPS2595xx Thermal Shutdown
Device
Enter TSD
Exit TSD
TJ < TSD and Device Power Cycled or re-
enabled using EN/UVLO pin
TPS2595x0 (Latch-off)
TJ ≥ TSD
TPS2595x1, TPS2595x3, TPS2595x5 (Auto-
retry)
TJ < TSD – TSDHYS and tTSD,RST Timer
Expired
TJ ≥ TSD
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8.3.5 Fault Indication (FLT )
表 2 summarizes the protection response to various fault conditions.
表 2. TPS2595x0, TPS2595x1, TPS2595x3 Fault Summary
EVENT / FAULT
PROTECTION RESPONSE
FLT INDICATION
Overtemperature
Shutdown
Yes
Output Voltage Clamp (OVC)
(TPS25952x,TPS25953x,TPS25954x only)
Overvoltage
Overvoltage
No
Shutdown (OVLO)
(TPS259573 only)
Yes
Undervoltage
Overcurrent
Short circuit
ILM pin open
ILM pin short
Shutdown (UVP or UVLO)
Current Limiting
No
No
Current Limiting
No
No
Shutdown
Shutdown If IOUT > ICB
Yes If IOUT > ICB
When the TPS2595x0, TPS2595x1, TPS2595x3 devices are turned off as a result of a fault as described in the
table above, the FLT pin is pulled low.
All faults will be cleared if the device loses power or if it is re-enabled using the EN/UVLO (or EN/OVLO) pin.
8.3.6 Quick Output Discharge (QOD)
Some applications require the output capacitor to be discharged quickly when the eFuse is turned off. This
prevents any unpredictable behavior from the downstream devices as the capacitor discharges slowly. The
TPS2595x5 device provides a Quick Output Discharge feature that can be enabled by connecting OUT pin to
QOD pin. An internal FET provides a fast discharge path for the output capacitor resulting in the OUT voltage
falling to 0 V in a short time. The FET initially operates in saturation region and provides a constant current
discharge. After the FET enters linear region, it offers a discharge path similar to a resistor.
It is possible to model this as a simple equivalent resistance, which would discharge a given capacitor charged to
a given voltage in the same time as the overall discharge circuit. This parameter is specified as the effective
QOD resistance RQOD for the device. It takes a time equivalent to 5 time constants (τ = R × C) to discharge a
capacitor by 99.3%. For example, with an effective QOD resistance of 19 Ω, the time taken to discharge a 100-
µF capacitor from 5 V to 35 mV can be calculated as in 公式 5.
tDischarge = 5 × 19 Ω × 100 µF = 9.5 ms
(5)
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8.4 Device Functional Modes
The features of the device depend on the operating mode.
8.4.1 Enable and Fault Pin Functional Mode 1: Single Device, Self-Controlled
In this mode of operation, the device is enabled by the VIN voltage without the need of an external processor to
drive the ENABLE pin. The FLT pin is optionally monitored by an external host. See 图 53.
TPS2595
VIN
VFLT
IN
R1
RFLT
EN
FLT
GPIO
R2
Copyright © 2017, Texas Instruments Incorporated
图 53. Single Device, Self-Controlled
8.4.2 Enable and Fault Pin Functional Mode 2: Single Device, Host-Controlled
In this mode of operation, the device enable pin is driven by an external host. The pin can be driven directly from
a GPIO without the need for any glue logic. The FLT pin is optionally monitored by the host. See 图 54.
TPS2595
VIN
VFLT
IN
RFLT
FLT
Copyright © 2017, Texas Instruments Incorporated
GPIO
GPIO
EN
图 54. Single Device, Host-Controlled
8.4.3 Enable and Fault Pin Functional Mode 2: Multiple Devices, Self-Controlled
In this mode of operation, the devices are self-controlled (no host present). The EN and FLT pins are shorted
together, and connected with up to three total devices as shown in 图 55. In this configuration, when any one of
the TPS2595xx devices detects a fault, it automatically disables the other TPS2595xx devices in the system.
注
This configuration is only applicable to the Active High Enable variants TPS2595x0,
TPS2595x1, TPS2595x5.
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Device Functional Modes (接下页)
TPS2595
VIN
R1
R2
FLT
EN
EN
TPS2595
FLT
EN
FLT
TPS2595
Copyright © 2017, Texas Instruments Incorporated
图 55. Multiple Devices, Self-Controlled
VOUT1
VOUT2
VOUT1
VOUT2
EN
IIN
EN
IIN
图 56. TPS259541 Self-controlled Mode Response with
Overload Fault on OUT1 Followed by Auto-retry with
Persistent Fault
图 57. TPS259541 Self-controlled Mode Response with
Overload on OUT1 Followed by Recovery with Fault
Removed
26
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TPS2595
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ZHCSHV0C –JUNE 2017–REVISED APRIL 2018
9 Application and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The TPS2595xx device is an integrated eFuse that is typically used for hot-swap and power rail protection
applications. The device operates from 2.7 V to 18 V with programmable current limit and undervoltage
protection. The device aids in controlling the in-rush current and provides precise current limiting during overload
conditions for systems such as set-top box, DTVs, gaming consoles, SSDs, HDDs, and smart meters. The
device also provides robust protection for multiple faults on the sub-system rail.
The following design procedure can be used to select the supporting component values based on the application
requirement. Additionally, a spreadsheet design tool TPS2595xx Design Calculation Tool is available.
9.2 Typical Application
3.3 V
VIN = 2.7 to 18 V
IN
OUT
VOUT
(1)
CIN
0.1 µF
34 mꢀ
COUT
1 µF
R1
1 MΩ
R3
10 kΩ
FLT
ILM
EN/UVLO
dVdt
ADC
TPS259541
GND
R2
387 kΩ
CdVDt
3.3 nF
RILM
546 Ω
Copyright © 2017, Texas Instruments Incorporated
(1) CIN is optional and 0.1 µF is recommended to suppress transients due to the inductance of PCB routing or from input
wiring.
图 58. Typical Application Schematic: Simple e-Fuse for Set-Top Boxes
9.2.1 Design Requirements
表 3 lists the TPS25954x design requirements.
表 3. Design Parameters
DESIGN PARAMETER
Input voltage , VIN
EXAMPLE VALUE
12 V
Undervoltage lockout set point, VUV
Overvoltage protection set point , VOV
Load at start-up, RL(SU)
4.3 V
Default: VOVC = 13.7 V
4 Ω
3.7 A
1 µF
85°C
Current limit, ILIMIT
Load capacitance, COUT
Maximum ambient temperatures, TA
版权 © 2017–2018, Texas Instruments Incorporated
27
TPS2595
ZHCSHV0C –JUNE 2017–REVISED APRIL 2018
www.ti.com.cn
9.2.2 Detailed Design Procedure
The designer must know the following:
•
•
•
•
•
Normal input operation voltage
Maximum output capacitance
Maximum current Limit
Load during start-up
Maximum ambient temperature of operation
This design procedure seeks to control the junction temperature of device under both static and transient
conditions by proper selection of output ramp-up time and associated support components. The designer can
adjust this procedure to fit the application and design criteria.
9.2.2.1 Programming the Current-Limit Threshold: RILM Selection
The RILM resistor at the ILM pin sets the over load current limit, this can be set using 公式 6.
2000
RILM
=
I LIMIT - 0.04
(6)
For ILIMIT = 3.7 A, from 公式 6, RILM is 546 Ω, choose closest standard value resistor with 1% tolerance.
9.2.2.2 Undervoltage Lockout Set Point
The undervoltage lockout (UVLO) trip point is adjusted using the external voltage divider network of R1 and R2 as
connected between IN, EN/UVLO and GND pins of the device. The values required for setting the undervoltage
are calculated solving 公式 7.
R1+ R2
VUV
=
ì VUVLO(R)
R2
(7)
Where VUVLO(R) is UVLO rising threshold (1.2 V). Because R1 and R2 leak the current from input supply VIN,
these resistors must be selected based on the acceptable leakage current from input power supply VIN.
The current drawn by R1 and R2 from the power supply is IR12 = VIN / (R1 + R2).
However, leakage currents due to external active components connected to the resistor string can add error to
these calculations. So, the resistor string current, IR12 must be chosen to be 20 times greater than the leakage
current expected.
To set the UVLO at VUVR = 4.3 V, select R2 = 387 kΩ, and R1 = 1 MΩ.
9.2.2.3 Setting Output Voltage Ramp Time (TdVdT
)
For a successful design, the junction temperature of device must be kept below the absolute maximum rating
during both dynamic (start-up) and steady state conditions. Dynamic power stresses often are an order of
magnitude greater than the static stresses, so it is important to determine the right start-up time and in-rush
current limit required with system capacitance to avoid thermal shutdown during start-up with and without load.
The required ramp-up capacitor CdVdT is calculated considering the two possible cases (see Case 1: Start-Up
Without Load. Only Output Capacitance COUT Draws Current and Case 2: Start-Up With Load. Output
Capacitance COUT and Load Draw Current ).
9.2.2.3.1 Case 1: Start-Up Without Load. Only Output Capacitance COUT Draws Current
During start-up, as the output capacitor charges, the voltage drop as well as the power dissipated across the
internal FET decreases. The average power dissipated in the device during start-up is calculated using 公式 9.
For TPS2592xx device, the inrush current is determined as shown in 公式 8.
VIN
IINRUSH = COUT
ì
TdVdT
(8)
Power dissipation during start-up is shown in 公式 9.
28
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TPS2595
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ZHCSHV0C –JUNE 2017–REVISED APRIL 2018
PD(INRUSH) = 0.5 ì V ì IINRUSH
IN
(9)
公式 9 assumes that load does not draw any current until the output voltage has reached its final value.
9.2.2.3.2 Case 2: Start-Up With Load. Output Capacitance COUT and Load Draw Current
When the load draws current during the turnon sequence, there is additional power dissipated. Considering a
resistive load during start-up RL(SU), load current ramps up proportionally with increase in output voltage during
TdVdT time. 公式 10 to 公式 13 show the average power dissipation in the internal FET during charging time due
to resistive load.
V2
1
≈ ’
IN
PD(LOAD)
=
ì
∆ ÷
6
« ◊
RL(SU)
(10)
(11)
(12)
Total power dissipated in the device during start-up is 公式 11.
PD(STARTUP) = PD(INRUSH) + PD(LOAD)
Total current during start-up is given by 公式 12.
ISTARTUP = IINRUSH +IL (t)
If ISTARTUP > ILIMIT, the device limits the current to ILIMIT and the current-limited charging time is determined by 公
式 13.
»
…
…
…
…
ÿ
Ÿ
Ÿ
Ÿ
Ÿ
⁄
≈
∆
∆
∆
’
÷
÷
÷
ILIMIT
IINRUSH
TdvdT(Current-Limited) = COUT ìRL(SU)
ì
-1+LN
V
IINRUSH
IN
ILIMIT
-
∆
«
÷
◊
RL(SU)
(13)
The power dissipation, with and without load, for selected start-up time must not exceed the shutdown limits as
shown in 图 59.
10000
-40 èC
25 èC
85 èC
125 èC
1000
100
10
1
0.1
1
10
100
Power Dissipation (W)
D001
图 59. Thermal Shutdown Limit Plot
For the design example under discussion, select ramp-up capacitor CdVdt = OPEN. The default slew rate for CdVdt
= OPEN is 38.2 mV/µs. With slew rate of 38.2 mV/µs, the ramp-up time TdVdt for 12 V input is 248 µs.
The inrush current drawn by the load capacitance COUT during ramp-up using 公式 14.
1ꢀF × 38.2 mV
I INRUSH
=
= 38.2 mA
ꢀs
(14)
(15)
The inrush power dissipation is calculated using 公式 15.
P
= 0.5 ì 12 ì 38.2 m = 229.2 mW
D(INRUSH)
For 229.2 mW of power loss, the thermal shutdown time of the device must not be less than the ramp-up time
TdVdt to avoid the false trip at the maximum operating temperature. 图 59 shows the thermal shutdown limit at TA
= 85°C, for 229.2 mW of power, the shutdown time is infinite. Therefore, it is safe to use 248 µs as the start-up
time without any load on the output.
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The additional power dissipation when a 4 Ω load is present during start-up is calculated using 公式 10.
12 x 12
P
=
= 6 W
D(LOAD)
6 ´ 4
(16)
(17)
The total device power dissipation during start-up is given in 公式 17.
PD(STARTUP) = 6 + 229.2 m = 6.229 W
The 图 59 shows TA = 85°C and the thermal shutdown time for 6.229 W is more than 10 ms, which is well within
the acceptable limits to not use an external capacitor CdVdt with a start-up load of 4 Ω.
When COUT is large, there is a need to decrease the power dissipation during start-up. This can be done by
increasing the value of the CdVdt capacitor.
9.2.3 Support Component Selection: CIN
CIN is a bypass capacitor to help control transient voltages, unit emissions, and local supply noise. Where
acceptable, a value in the range from 0.001 μF to 0.1 μF is recommended for CIN.
9.2.4 Application Curves
VIN
VIN
VOUT
VOUT
EN
IIN
EN
IIN
图 61. Output Ramp with 4 Ω Load at Start-up
图 60. Output Ramp without Any Load
9.2.5 Controlled Power Down (Quick Output Discharge) using TPS2595x5
When the TPS2595x5 device is disabled, the output voltage is left floating and the power-down profile is entirely
dictated by the load. In some applications, this can lead to undesired activity because the load is not powered
down to a defined state. Controlled output discharge can ensure the load is completely turned off and is not in an
undefined operational state. The QOD pin in the TPS2595x5 device can be connected to the OUT pin to facilitate
the Quick Output Discharge function, as shown in 图 62. When the TPS2595x5 device is disabled, the QOD pin
is pulled low and provides a quick discharge path for the output capacitor. The output voltage discharge rate is
dictated by the output capacitor COUT, the total discharge path resistance (internal plus external), and the load.
30
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TPS2595
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ZHCSHV0C –JUNE 2017–REVISED APRIL 2018
VOUT
VIN = 5 V
IN
OUT
CIN
0.1 µF
34 mꢀ
COUT
100 µF
RLOAD
1000 Ω
RQODEXT
QOD
ILM
from µC
EN/UVLO
dVdt
TPS2595x5
GND
RILM
CdVDt
487 Ω
3.3 nF
Copyright © 2017, Texas Instruments Incorporated
图 62. Circuit Implementation with Quick Output Discharge Function using TPS2595x5
VIN
VIN
VOUT
VOUT
EN
EN
图 63. Output Voltage Discharge using TPS259535 without
QOD [VIN = 5 V, EN = H → L, COUT = 100 µF, RLOAD = 1000
Ω, RQODEXT = OPEN]
图 64. Output Voltage Discharge using TPS259535 with
QOD [VIN = 5 V, EN = H → L, COUT = 100 µF, RLOAD = 1000
Ω, RQODEXT = Short]
9.2.6 Overvoltage Lockout using TPS259573
The TPS259573 device incorporates a circuit to protect the system during overvoltage conditions. A resistor
divider connected from the supply to the EN/OVLO pin to GND (as shown in 图 65) programs the overvoltage
threshold. A voltage more than VOVLO on the EN/OVLO pin turns off the internal FET and protects the
downstream load. 图 66 shows overvoltage cut-off at the input voltage of 15 V.
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ZHCSHV0C –JUNE 2017–REVISED APRIL 2018
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3.3 V
VOUT
VIN = 2.7 to 18 V
IN
OUT
CIN
0.1 µF
34 mꢀ
R3
10 kΩ
COUT
1 µF
RLOAD
100 Ω
R1
1 MΩ
FLT
ILM
EN/OVLO
dVdt
TPS259573
GND
R2
86.9 kΩ
CdVDt
3.3 nF
RILM
487 Ω
Copyright © 2017, Texas Instruments Incorporated
图 65. Circuit Implementation for Overvoltage Lockout using TPS259573
图 66. Overvoltage Lockout Response using TPS259573
32
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TPS2595
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ZHCSHV0C –JUNE 2017–REVISED APRIL 2018
10 Power Supply Recommendations
The TPS2595xx devices are designed for a supply voltage range of 2.7 V ≤ VIN ≤ 18 V. An input ceramic bypass
capacitor higher than 0.1 μF is recommended if the input supply is located more than a few inches from the
device. The power supply must be rated higher than the set current limit to avoid voltage droops during
overcurrent and short-circuit conditions.
10.1 Transient Protection
In the case of a short circuit and overload current limit when the device interrupts current flow, the input
inductance generates a positive voltage spike on the input, and the output inductance generates a negative
voltage spike on the output. The peak amplitude of voltage spikes (transients) is dependent on the value of
inductance in series to the input or output of the device. Such transients can exceed the absolute maximum
ratings of the device if steps are not taken to address the issue. Typical methods for addressing transients
include:
•
•
•
•
Minimize lead length and inductance into and out of the device.
Use a large PCB GND plane.
Use a Schottky diode across the output to absorb negative spikes.
Use a low-value ceramic capacitor CIN = 0.001 μF to 0.1 μF to absorb the energy and dampen the transients.
The approximate value of input capacitance can be estimated with 公式 18:
L(IN
)
VSPIKE Absolute = V IN + I(LOAD) ì
(
)
(
)
C(IN
)
where
•
•
•
•
V(IN) is the nominal supply voltage
I(LOAD) is the load current
L(IN) equals the effective inductance seen looking into the source
C(IN) is the capacitance present at the input
(18)
Some applications may require the addition of a Transient Voltage Suppressor (TVS) to prevent transients from
exceeding the absolute maximum ratings of the device.
The circuit implementation with optional protection components (a ceramic capacitor, TVS and Schottky diode) is
shown in 图 67.
3.3 V
VOUT
VIN = 2.7 to 18 V
IN
OUT
CIN
0.1 µF
34 mꢀ
R3
10 kΩ
COUT
1 µF
RLOAD
100 Ω
R1
1 MΩ
FLT
ILM
EN/UVLO
dVdt
TPS2595xx
GND
R2
86.9 kΩ
CdVDt
3.3 nF
RILM
487 Ω
Copyright © 2017, Texas Instruments Incorporated
图 67. Circuit Implementation with Optional Protection Components
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33
TPS2595
ZHCSHV0C –JUNE 2017–REVISED APRIL 2018
www.ti.com.cn
10.2 Output Short-Circuit Measurements
It is difficult to obtain repeatable and similar short-circuit testing results. The following contribute to variation in
results:
•
•
•
•
•
•
•
Source bypassing
Input leads
Circuit layout
Component selection
Output shorting method
Relative location of the short
Instrumentation
The actual short exhibits a certain degree of randomness because it microscopically bounces and arcs. Ensure
that configuration and methods are used to obtain realistic results. Do not expect to see waveforms exactly like
those in this data sheet because every setup is different.
11 Layout
11.1 Layout Guidelines
•
For all applications, a ceramic decoupling capacitor of 0.01 µF or greater is recommended between the IN
terminal and GND terminal. For hot-plug applications, where input power-path inductance is negligible, this
capacitor can be eliminated or minimized.
•
The optimal placement of the decoupling capacitor is closest to the IN and GND terminals of the device. Care
must be taken to minimize the loop area formed by the bypass-capacitor connection, the IN terminal, and the
GND terminal of the IC. See 图 68 for a PCB layout example.
•
•
•
High current-carrying power-path connections must be as short as possible and must be sized to carry at
least twice the full-load current.
The GND terminal must be tied to the PCB ground plane at the terminal of the IC. The PCB ground must be a
copper plane or island on the board.
Locate the following support components close to their connection pins:
–
–
–
RILM
CdVdT
Resistors for the EN/UVLO (or EN/OVLO) pin
Connect the other end of the component to the GND pin of the device with shortest trace length. The trace
routing for the RILM and CdVdT components to the device must be as short as possible to reduce parasitic
effects on the current limit and soft start timing. These traces must not have any coupling to switching signals
on the board.
•
•
Protection devices such as TVS, snubbers, capacitors, or diodes must be placed physically close to the
device they are intended to protect. These protection devices must be routed with short traces to reduce
inductance. For example, a protection Schottky diode is recommended to address negative transients due to
switching of inductive loads, and it must be physically close to the OUT pins.
Obtaining acceptable performance with alternate layout schemes is possible; Layout Example has been
shown to produce good results and is intended as a guideline.
34
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TPS2595
www.ti.com.cn
ZHCSHV0C –JUNE 2017–REVISED APRIL 2018
11.2 Layout Example
Top Layer
Bottom Layer Ground Plane
Via to Bottom Ground Plane
Power Ground
dVdt
EN/UVLO
IN
1
2
3
4
8
7
6
5
GND
ILM
Bottom
Ground
Layer
GND
FLT
VIN
VOUT
IN
OUT
*
*
High
Frequency
Bypass
Capacitor
Power Ground
(1) Optional: Needed only to suppress the transients caused by inductive load switching
图 68. TPS2595xx Layout
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12 器件和文档支持
12.1 文档支持
12.1.1 相关文档
请参阅如下相关文档：
TPS2595EVM 电子保险丝评估板
TPS2595xx 设计计算工具
12.1.2 相关链接
下表列出了快速访问链接。类别包括技术文档、支持和社区资源、工具和软件，以及立即购买的快速链接。
表 4. 相关链接
器件
产品文件夹
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立即订购
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TPS259520
TPS259521
TPS259530
TPS259531
TPS259533
TPS259540
TPS259541
TPS259570
TPS259571
TPS259573
TPS259525
TPS259535
12.2 接收文档更新通知
如需接收文档更新通知，请访问 www.ti.com.cn 网站上的器件产品文件夹。单击右上角的通知我 进行注册，即可每
周接收产品信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
12.3 社区资源
下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，
并且不一定反映 TI 的观点；请参阅 TI 的 《使用条款》。
TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在
e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。
设计支持
TI 参考设计支持 可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。
12.4 商标
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.5 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
12.6 术语表
SLYZ022 — TI 术语表。
这份术语表列出并解释术语、缩写和定义。
36
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TPS2595
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ZHCSHV0C –JUNE 2017–REVISED APRIL 2018
13 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且
不会对此文档进行修订。如需获取此数据表的浏览器版本，请参阅左侧的导航栏。
版权 © 2017–2018, Texas Instruments Incorporated
37
PACKAGE OPTION ADDENDUM
www.ti.com
7-Apr-2023
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS259520DSGR
TPS259520DSGT
TPS259521DSGR
TPS259521DSGT
TPS259525DSGR
TPS259525DSGT
TPS259530DSGR
TPS259530DSGT
TPS259531DSGR
TPS259531DSGT
TPS259533DSGR
TPS259533DSGT
TPS259535DSGR
TPS259535DSGT
TPS259540DSGR
TPS259540DSGT
TPS259541DSGR
TPS259541DSGT
TPS259570DSGR
TPS259570DSGT
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
DSG
DSG
DSG
DSG
DSG
DSG
DSG
DSG
DSG
DSG
DSG
DSG
DSG
DSG
DSG
DSG
DSG
DSG
DSG
DSG
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-1-260C-UNLIM
Level-2-260C-1 YEAR
Level-1-260C-UNLIM
Level-2-260C-1 YEAR
Level-1-260C-UNLIM
Level-2-260C-1 YEAR
Level-1-260C-UNLIM
Level-2-260C-1 YEAR
Level-1-260C-UNLIM
Level-2-260C-1 YEAR
Level-1-260C-UNLIM
Level-2-260C-1 YEAR
Level-1-260C-UNLIM
Level-2-260C-1 YEAR
Level-1-260C-UNLIM
Level-2-260C-1 YEAR
Level-1-260C-UNLIM
Level-2-260C-1 YEAR
Level-1-260C-UNLIM
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
ES20
ES20
ES21
ES21
ES25
ES25
ES30
ES30
ES31
ES31
ES33
ES33
ES35
ES35
ES40
ES40
ES41
ES41
ES70
ES70
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
250
RoHS & Green
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
7-Apr-2023
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS259571DSGR
TPS259571DSGT
TPS259573DSGR
TPS259573DSGT
ACTIVE
ACTIVE
ACTIVE
ACTIVE
WSON
WSON
WSON
WSON
DSG
DSG
DSG
DSG
8
8
8
8
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-1-260C-UNLIM
Level-2-260C-1 YEAR
Level-1-260C-UNLIM
-40 to 125
-40 to 125
-40 to 125
-40 to 125
ES71
ES71
ES73
ES73
Samples
Samples
Samples
Samples
NIPDAU
NIPDAU
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
7-Apr-2023
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Nov-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS259520DSGR
TPS259520DSGT
TPS259521DSGR
TPS259521DSGT
TPS259525DSGR
TPS259525DSGT
TPS259530DSGR
TPS259530DSGT
TPS259531DSGR
TPS259531DSGT
TPS259533DSGR
TPS259533DSGT
TPS259535DSGR
TPS259535DSGT
TPS259540DSGR
TPS259540DSGT
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
DSG
DSG
DSG
DSG
DSG
DSG
DSG
DSG
DSG
DSG
DSG
DSG
DSG
DSG
DSG
DSG
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
3000
250
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
1.15
1.15
1.15
1.15
1.15
1.15
1.15
1.15
1.15
1.15
1.15
1.15
1.15
1.15
1.15
1.15
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
3000
250
3000
250
3000
250
3000
250
3000
250
3000
250
3000
250
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Nov-2022
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS259541DSGR
TPS259541DSGT
TPS259570DSGR
TPS259570DSGT
TPS259571DSGR
TPS259571DSGT
TPS259573DSGR
TPS259573DSGT
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
DSG
DSG
DSG
DSG
DSG
DSG
DSG
DSG
8
8
8
8
8
8
8
8
3000
250
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
1.15
1.15
1.15
1.15
1.15
1.15
1.15
1.15
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
3000
250
3000
250
3000
250
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Nov-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPS259520DSGR
TPS259520DSGT
TPS259521DSGR
TPS259521DSGT
TPS259525DSGR
TPS259525DSGT
TPS259530DSGR
TPS259530DSGT
TPS259531DSGR
TPS259531DSGT
TPS259533DSGR
TPS259533DSGT
TPS259535DSGR
TPS259535DSGT
TPS259540DSGR
TPS259540DSGT
TPS259541DSGR
TPS259541DSGT
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
DSG
DSG
DSG
DSG
DSG
DSG
DSG
DSG
DSG
DSG
DSG
DSG
DSG
DSG
DSG
DSG
DSG
DSG
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
3000
250
210.0
210.0
210.0
210.0
210.0
210.0
210.0
210.0
210.0
210.0
210.0
210.0
210.0
210.0
210.0
210.0
210.0
210.0
185.0
185.0
185.0
185.0
185.0
185.0
185.0
185.0
185.0
185.0
185.0
185.0
185.0
185.0
185.0
185.0
185.0
185.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
3000
250
3000
250
3000
250
3000
250
3000
250
3000
250
3000
250
3000
250
Pack Materials-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Nov-2022
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPS259570DSGR
TPS259570DSGT
TPS259571DSGR
TPS259571DSGT
TPS259573DSGR
TPS259573DSGT
WSON
WSON
WSON
WSON
WSON
WSON
DSG
DSG
DSG
DSG
DSG
DSG
8
8
8
8
8
8
3000
250
210.0
210.0
210.0
210.0
210.0
210.0
185.0
185.0
185.0
185.0
185.0
185.0
35.0
35.0
35.0
35.0
35.0
35.0
3000
250
3000
250
Pack Materials-Page 4
GENERIC PACKAGE VIEW
DSG 8
2 x 2, 0.5 mm pitch
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224783/A
www.ti.com
PACKAGE OUTLINE
DSG0008A
WSON - 0.8 mm max height
SCALE 5.500
PLASTIC SMALL OUTLINE - NO LEAD
2.1
1.9
B
A
0.32
0.18
PIN 1 INDEX AREA
2.1
1.9
0.4
0.2
ALTERNATIVE TERMINAL SHAPE
TYPICAL
0.8
0.7
C
SEATING PLANE
0.05
0.00
SIDE WALL
0.08 C
METAL THICKNESS
DIM A
OPTION 1
0.1
OPTION 2
0.2
EXPOSED
THERMAL PAD
(DIM A) TYP
0.9 0.1
5
4
6X 0.5
2X
1.5
9
1.6 0.1
8
1
0.32
0.18
PIN 1 ID
(45 X 0.25)
8X
0.4
0.2
8X
0.1
C A B
C
0.05
4218900/E 08/2022
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
DSG0008A
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(0.9)
(
0.2) VIA
8X (0.5)
TYP
1
8
8X (0.25)
(0.55)
SYMM
9
(1.6)
6X (0.5)
5
4
SYMM
(1.9)
(R0.05) TYP
LAND PATTERN EXAMPLE
SCALE:20X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4218900/E 08/2022
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
DSG0008A
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
8X (0.5)
METAL
8
SYMM
1
8X (0.25)
(0.45)
SYMM
9
(0.7)
6X (0.5)
5
4
(R0.05) TYP
(0.9)
(1.9)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 9:
87% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:25X
4218900/E 08/2022
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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